Display panel and display device

Abstract

The present disclosure relates to the field of display technology, and proposes a display panel and a display device. The display panel includes: a substrate, a lead-out line, a detection unit, and a first power access line. The substrate includes a first fan-out area, a bending area, an integrated area, and a second fan-out area located in a first frame area; the orthographic projection of the lead-out line on the substrate substrate is located in the bending area, and the lead-out line is connected to the first fan-out line located in the first fan-out area; the orthographic projection of the detection unit on the substrate substrate is located in the integrated area, and the detection unit is connected to the lead-out line; the first power access line includes a first extension part, a second extension part, and a third extension part, and the first extension part is connected between the second extension part and the third extension part; in the first direction, the orthographic projection of the lead-out line on the substrate substrate is located between the orthographic projection of the second extension part on the substrate substrate and the orthographic projection of the third extension part on the substrate substrate. The display panel can improve the problem of sudden change in resistance of the data line.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the related art, the border area of ​​the display panel is provided with a power access line, which is used to provide a power signal to the display panel. In the related art, the power access line is connected to the power line in the display area through multiple access ports. However, the data fan-out line in the border area needs to avoid the access port of the power access line, which leads to a sudden change in the length of adjacent data lines in the display panel, and finally causes the split screen mura of the display panel.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] According to one aspect of the present disclosure, a display panel is provided, comprising: a base substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of first fan-out lines, a plurality of lead-out lines, a detection unit, and a first power supply access line. The substrate includes a display area and a first frame area, the first frame area is connected to one side of the display area in the second direction, the first frame area includes a first fan-out area, a bending area, an integrated area, and a second fan-out area, the bending area is connected to the side of the first fan-out area away from the display area, the integrated area is connected to the side of the bending area away from the first fan-out area, and the second fan-out area is connected to the side of the integrated area away from the bending area; the orthographic projections of a plurality of sub-pixels on the substrate are located in the display area; the orthographic projections of a plurality of data lines on the substrate are located in the display area, and the data lines are used to provide data signals to the sub-pixels; the orthographic projections of a plurality of first fan-out lines on the substrate are located in the first fan-out area, the first fan-out lines are arranged corresponding to the data lines, and the first fan-out lines are connected to the corresponding data lines; the orthographic projections of a plurality of lead-out lines on the substrate are located in the bending area, the lead-out lines are arranged corresponding to the first fan-out lines, and the lead-out lines are connected to the corresponding the first fan-out line; the detection unit's orthographic projection on the substrate is located in the integrated area, and the detection unit is connected to the lead-out line; a first power access line is used to provide a first power signal to the sub-pixel, and the first power access line includes a first extension part, a second extension part, and a third extension part, and the first extension part is connected between the second extension part and the third extension part; wherein the orthographic projection of the first extension part on the substrate extends along the first direction and is located in the second fan-out area, the orthographic projection of the second extension part on the substrate extends along the second direction and is at least partially located in the bending area, the orthographic projection of the third extension part on the substrate extends along the second direction and is at least partially located in the bending area, and the first direction and the second direction intersect; in the first direction, the orthographic projection of the lead-out line on the substrate is located between the orthographic projection of the second extension part on the substrate and the orthographic projection of the third extension part on the substrate.

[0005] In an exemplary embodiment of the present disclosure, the first power access line also includes a fourth extension portion connected to the first extension portion, and the orthographic projection of the fourth extension portion on the substrate extends along the second direction and is at least partially located in the bending area; in the first direction, the orthographic projection of the fourth extension portion on the substrate is located between the orthographic projection of the second extension portion on the substrate and the orthographic projection of the third extension portion on the substrate; in the first direction, the orthographic projection of part of the lead-out line on the substrate is located between the orthographic projection of the second extension portion on the substrate and the orthographic projection of the fourth extension portion on the substrate, and the orthographic projection of another part of the lead-out line on the substrate is located between the orthographic projection of the third extension portion on the substrate and the orthographic projection of the fourth extension portion on the substrate.

[0006] In an exemplary embodiment of the present disclosure, the plurality of lead lines include a first lead line, a second lead line, a third lead line, and a fourth lead line that are adjacent in sequence in the first direction; an orthographic projection of the second lead line on the substrate and an orthographic projection of the third lead line on the substrate are located on two adjacent sides of an orthographic projection of the fourth extension portion on the substrate; the orthographic projection of the first lead line on the substrate is located on a side where the orthographic projection of the second lead line on the substrate is away from the orthographic projection of the fourth extension portion on the substrate, and the orthographic projection of the fourth lead line on the substrate is located on a side where the orthographic projection of the third lead line on the substrate is away from the orthographic projection of the fourth extension portion on the substrate; the length of the orthographic projection of the first fan-out line connected to the second lead line on the substrate is greater than the length of the orthographic projection of the first fan-out line connected to the first lead line on the substrate, and the length of the orthographic projection of the first fan-out line connected to the third lead line on the substrate is greater than the length of the orthographic projection of the first fan-out line connected to the fourth lead line on the substrate.

[0007] In an exemplary embodiment of the present disclosure, an orthographic projection of the first fan-out line connected to the second lead-out line on the substrate and an orthographic projection of the first fan-out line connected to the third lead-out line on the substrate are symmetrical along a separation line.

[0008] In an exemplary embodiment of the present disclosure, the length of the orthographic projection of the first fan-out line connected to the second lead-out line on the substrate is L1, the length of the orthographic projection of the first fan-out line connected to the third lead-out line on the substrate is L2, and (L1-L2) / L2 is greater than or equal to 0 and less than or equal to 5%.

[0009] In an exemplary embodiment of the present disclosure, the first border area includes a first side edge and a second side edge arranged opposite to each other in the first direction, and the plurality of lead lines include a fifth lead line and a sixth lead line; among the lead lines, the orthographic projection of the fifth lead line on the substrate is closest to the first side edge, and the orthographic projection of the sixth lead line on the substrate is closest to the second side edge; the distance between the orthographic projection of the fourth extension portion on the substrate and the orthographic projection of the fifth lead line on the substrate in the first direction is equal to the distance between the orthographic projection of the fourth extension portion on the substrate and the orthographic projection of the sixth lead line on the substrate in the first direction.

[0010] In an exemplary embodiment of the present disclosure, the substrate further includes a third fan-out area and a binding area, the third fan-out area is connected between the bending area and the integrated area, and the binding area is connected to a side of the second fan-out area away from the display area; the display panel further includes: a third fan-out line, a second fan-out line, a driving circuit, and a binding pin, the orthographic projection of the third fan-out line on the substrate is located in the third fan-out area, and the third fan-out line is connected between the lead line and the detection unit; the orthographic projection of the second fan-out line on the substrate is located in the second fan-out area, and the second fan-out line is connected to the third fan-out line; the driving circuit is at least used to provide the data signal to the data line; the orthographic projection of the binding pin on the substrate is located in the binding area, and the binding pin is connected between the second fan-out line and the driving circuit.

[0011] In an exemplary embodiment of the present disclosure, an orthographic projection of at least part of the third fan-out line on the substrate extends linearly along the second direction.

[0012] In an exemplary embodiment of the present disclosure, a size of the second fan-out area in the second direction is greater than a size of the third fan-out area in the second direction.

[0013] In an exemplary embodiment of the present disclosure, the size of the second fan-out area in the second direction is L3, the size of the third fan-out area in the second direction is L4, and L3 / L4 is greater than or equal to 5 and less than or equal to 9.

[0014] In an exemplary embodiment of the present disclosure, the orthographic projections of the plurality of data lines on the substrate are spaced apart along the first direction and extend along the second direction, and the plurality of data lines include a first data line and a second data line; the display area further includes a fourth fan-out area, and the display panel further includes: a plurality of first data connection lines and a plurality of second data connection lines, the plurality of first data connection lines are located in the fourth fan-out area, the orthographic projections of the first data connection lines on the substrate are spaced apart along the second direction and extend along the first direction, the first data connection lines are connected between the corresponding first data lines and the first fan-out lines, and the orthographic projections of the first data connection lines on the substrate overlap with the orthographic projections of at least part of the second data lines on the substrate; a plurality of second data connection lines are located in the fourth fan-out area, the orthographic projections of the second data connection lines on the substrate are spaced apart along the first direction and extend along the second direction, and the second data connection lines are connected between the first data connection lines and the first fan-out lines.

[0015] In an exemplary embodiment of the present disclosure, the display area includes a third side and a fourth side that are arranged opposite to each other in the first direction; the orthographic projection of the first data line on the base substrate is located on a side where the orthographic projection of the second data line on the base substrate is close to the third side or the fourth side.

[0016] In an exemplary embodiment of the present disclosure, the first border area includes a first side edge and a second side edge arranged opposite to each other in the first direction; in the first fan-out line close to the first side edge, the orthographic projection of at least part of the structure of the first fan-out line on the substrate is located on a side of the orthographic projection of the lead line connected to it on the substrate substrate close to the first side edge; in the first fan-out line close to the second side edge, the orthographic projection of at least part of the structure of the first fan-out line on the substrate substrate is located on a side of the orthographic projection of the lead line connected to it on the substrate substrate close to the second side edge.

[0017] In an exemplary embodiment of the present disclosure, the second extension portion and the lead line are located in the same conductive layer at a portion where the orthographic projection on the base substrate is located in the bending zone; the third extension portion and the lead line are located in the same conductive layer at a portion where the orthographic projection on the base substrate is located in the bending zone; and the fourth extension portion and the lead line are located in the same conductive layer.

[0018] In an exemplary embodiment of the present disclosure, the display panel also includes: a power line, a first power connection line, the orthographic projection of the power line on the substrate is located in the display area and extends along the second direction, and the power line is used to provide the first power signal to the sub-pixel; the orthographic projection of the first power connection line on the substrate is located in the first fan-out area, the orthographic projection of the first power connection line on the substrate extends along the first direction, and the first power connection line connects multiple power lines; the first power access line is connected to the first power connection line through the second extension portion, the third extension portion, and the fourth extension portion.

[0019] In an exemplary embodiment of the present disclosure, the plurality of second fan-out lines include: a plurality of first sub-fan-out lines and a plurality of second sub-fan-out lines, wherein the first sub-fan-out lines are arranged corresponding to the second data lines, and the first sub-fan-out lines are connected to the second data lines corresponding thereto; the second sub-fan-out lines are arranged correspondingly to the second data connection lines, and the second sub-fan-out lines are connected to the second data connection lines corresponding thereto; the display panel further includes: a third data connection line, wherein the orthographic projection of the third data connection line on the substrate is located in the second fan-out area, the third data connection line includes a fifth extension portion and a sixth extension portion, the orthographic projection of the fifth extension portion on the substrate extends along the first direction, the orthographic projection of the sixth extension portion on the substrate extends along the second direction, the fifth extension portion is connected to the second sub-fan-out line, and the sixth extension portion is connected between the binding pin and the fifth extension portion; wherein the orthographic projection of the fifth extension portion on the substrate intersects with the orthographic projection of at least part of the first sub-fan-out lines on the substrate; the arrangement order of the binding pins in the first direction is the same as the arrangement order of the data lines connected thereto in the first direction.

[0020] In an exemplary embodiment of the present disclosure, the third data link line further includes a seventh extension portion, the seventh extension portion is connected between the fifth extension portion and the second sub-fan-out line, and an orthographic projection of the seventh extension portion on the base substrate extends along the second direction.

[0021] In an exemplary embodiment of the present disclosure, the plurality of third data connection lines include a plurality of first sub-data connection lines and a plurality of second sub-data connection lines, the first sub-data connection lines and the second sub-data connection lines are located in different conductive layers; and the orthographic projections of the first sub-data connection lines on the substrate and the orthographic projections of the second sub-data connection lines on the substrate are alternately distributed in sequence in the second direction.

[0022] In an exemplary embodiment of the present disclosure, the display panel further includes: a first gate layer, a second gate layer, a first source-drain layer, a second source-drain layer, and a third source-drain layer, wherein the first gate layer is located on one side of the substrate; the second gate layer is located on a side of the substrate away from the first gate layer; wherein part of the second fan-out line is located on the first gate layer, part of the second fan-out line is located on the second gate layer, and the positive projection of the second fan-out line located on the first gate layer on the substrate and the positive projection of the second fan-out line located on the second gate layer on the substrate are alternately distributed in sequence in the first direction; the first source-drain layer is located on a side of the second gate layer away from the substrate, the first source-drain layer includes a shielding portion, and the shielding portion is connected to a stable voltage source; the second source-drain layer is located on a side of the first source-drain layer away from the substrate, and the first sub-data connection line is located on the second source-drain layer; the third source-drain layer is located on a side of the second source-drain layer away from the substrate, and the second sub-data connection line is located on the third source-drain layer; wherein the shielding portion shields between the second fan-out line and the third data connection line.

[0023] In an exemplary embodiment of the present disclosure, the orthographic projection of the third data connection line on the substrate is located on a side of the orthographic projection of the first extension portion on the substrate away from the orthographic projection of the detection unit on the substrate; and the shielding portion is connected to the first extension portion.

[0024] In an exemplary embodiment of the present disclosure, the display panel further includes: a first gate layer and a second gate layer, the first gate layer being located on one side of the base substrate; the second gate layer being located on a side of the base substrate facing away from the first gate layer; part of the first fan-out lines being located in the first gate layer, part of the first fan-out lines being located in the second gate layer, and an orthographic projection of the first fan-out lines located in the first gate layer on the base substrate and an orthographic projection of the first fan-out lines located in the second gate layer on the base substrate are alternately distributed in sequence in the first direction; part of the third fan-out lines being located in the first gate layer, part of the third fan-out lines being located in the second gate layer, and an orthographic projection of the third fan-out lines located in the first gate layer on the base substrate and an orthographic projection of the third fan-out lines located in the second gate layer on the base substrate are alternately distributed in sequence in the first direction.

[0025] In an exemplary embodiment of the present disclosure, the first sub-data connection line is connected to the second fan-out line located at the first gate layer, and the second sub-data connection line is connected to the second fan-out line located at the second gate layer.

[0026] According to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0027] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0029] Figure 1 A schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0030] Figure 2 It is a structural schematic diagram of a pixel driving circuit in an exemplary embodiment of a display panel disclosed in the present invention;

[0031] Figure 3 A partial enlarged view of a first border area in an exemplary embodiment of the display panel disclosed herein;

[0032] Figure 4 It is a schematic structural diagram of the first border area in another exemplary embodiment of the display panel disclosed in the present invention;

[0033] Figure 5 for Figure 4 The structural diagram of each signal line in the figure;

[0034] Figure 6 for Figure 4 A schematic diagram of the structure of the first power supply access line and the second power supply access line;

[0035] Figure 7 for Figure 4 A partial enlarged view of the first fan-out area;

[0036] Figure 8 for Figure 4 Schematic diagram of the structure of the middle bending zone;

[0037] Fig. 9 for Figure 4 A partial enlarged view of the second fan-out area and the binding area;

[0038] Fig.10 for Fig. 9 The structural layout of the first gate layer;

[0039] Fig.11 for Fig. 9 The structural layout of the second gate layer;

[0040] Fig.12 for Fig. 9 The structural layout of the first source and drain layer in the middle;

[0041] Fig.13 for Fig. 9 The structural layout of the second source and drain layer;

[0042] Fig.14 for Fig. 9 The structural layout of the third source and drain layer;

[0043] Fig.15 for Fig. 9 A cross-sectional view along the dotted line CC;

[0044] Fig.16 for Figure 6 A structural layout of a first power supply access line and a second power supply access line;

[0045] Fig.17 for Fig.16 The structural layout of the first source and drain layer;

[0046] Fig.18 for Fig.16 The structural layout of the second source and drain layer;

[0047] Fig.19 for Fig.16 The structural layout of the third source and drain layer;

[0048] Fig. 20 The figure is a diagram showing the resistance variation of the data lead wires at different positions of the display panel of the present invention. DETAILED DESCRIPTION

[0049] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0050] The terms "a", "an", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to indicate an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0051] like Figure 1, which is a schematic diagram of the structure of an exemplary embodiment of the display panel of the present disclosure. The display panel also includes a substrate, a sub-pixel PIX, a plurality of data lines Da, a first data connection line Fa1, and a second data connection line Fa2. The substrate may include a display area AA, and a fourth fan-out area Fot4 located in the display area AA.

[0052] The orthographic projection of the sub-pixel PIX on the substrate is located in the display area AA, and the sub-pixel PIX may include a pixel driving circuit and a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. Figure 2 FIG. 1 is a schematic diagram of a pixel driving circuit in an exemplary embodiment of a display panel of the present disclosure. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. Among them, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the second gate driving signal terminal G2; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to the node N; the first electrode of the second transistor T2 is connected to the node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the second electrode of the seventh transistor T7, the gate is connected to the enable signal terminal EM, the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2; the second electrode of the first transistor T1 is connected to the node N, the first electrode is connected to the first initial signal terminal Vinit1, and the gate is connected to the first reset signal terminal Re1; the first electrode of the capacitor C is connected to the node N, and the second electrode is connected to the first power supply terminal VDD; the first electrode of the eighth transistor T8 is connected to the third initial signal line Vinit3, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the second reset signal terminal Re2. The pixel driving circuit can be connected to a light-emitting unit OLED to drive the light-emitting unit OLED to emit light, and the light-emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS. Among them, the first transistor T1 and the second transistor T2 can be N-type transistors; the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type transistors.

[0053] The pixel driving circuit driving method may include a reset phase, a data writing phase, and a light-emitting phase. In the reset phase, the first reset signal terminal Re1 outputs a high-level signal, the second reset signal terminal Re2 outputs a low-level signal, the first transistor T1 and the eighth transistor T8 are turned on, the first initial signal terminal Vinit1 inputs the first initial signal to the node N, and the third initial signal terminal Vinit3 inputs the third initial signal to the first electrode of the driving transistor T3. In the data writing phase, the first gate driving signal terminal G1 outputs a high-level signal, the second gate driving signal terminal G2 outputs a low-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and the data signal terminal Da outputs a data signal to write a compensation voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3. Light-emitting phase: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C. The output current of the driving transistor in the pixel driving circuit of the present invention is I=(μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. Wherein, I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.

[0054] In this exemplary embodiment, Figure 1As shown, the orthogonal projection of the data line Da on the substrate is located in the display area AA, and the data line Da is used to provide a data signal to the sub-pixel PIX connected thereto. The pixel driving circuit in the sub-pixel PIX can provide a driving current to the light-emitting unit under the control of the data signal, thereby controlling the gray scale of the sub-pixel. The orthogonal projection of the data line Da on the substrate can be distributed along the first direction X at intervals and extend along the second direction Y. The first direction X and the second direction Y can intersect. For example, the first direction X can be a row direction, and the second direction Y can be a column direction. The plurality of data lines Da may include a first data line Da1 and a second data line Da2. The display area AA includes a third side AA3 and a fourth side AA4 that are arranged opposite to each other in the first direction X. The orthogonal projection of the first data line Da1 on the substrate is located on a side of the orthogonal projection of the second data line Da2 on the substrate that is close to the third side AA3 or the fourth side AA4. The orthographic projections of the first data connection lines Fa1 on the base substrate are distributed along the second direction Y at intervals and extend along the first direction X. The first data connection lines Fa1 are connected to the first data lines Da1, and at least part of the orthographic projections of the first data connection lines Fa1 on the base substrate overlap with at least part of the orthographic projections of the second data lines Da2 on the base substrate. The orthographic projections of the second data connection lines Fa2 on the base substrate are distributed along the first direction X at intervals and extend along the second direction Y. The second data connection lines Fa2 are connected to the first data connection lines Fa1. In this exemplary embodiment, the fourth fan-out area Fot4 is set in the display area AA, so that the narrow frame design of the display panel can be realized.

[0055] In this exemplary embodiment, Figure 1 As shown, the dividing line XX divides the display area AA into two display areas distributed in the first direction X, and the dividing line XX can be located at the midline position of the display area AA in the first direction X. The first data line Da1 on the side away from the dividing line XX can be connected to the second data connection line Fa2 on the side close to the dividing line XX through the first data connection line Fa1. It should be understood that in other exemplary embodiments, the first data connection line Fa1 and the second data connection line Fa2 can also be arranged in other ways. For example, the first data line Da1 on the side close to the dividing line XX is connected to the second data connection line Fa2 on the side close to the dividing line XX through the first data connection line Fa1; for another example, the length of the first data connection line Fa1 can also gradually increase or decrease from top to bottom.

[0056] like Figure 1 As shown, the base substrate may further include a first frame area B1. The first frame area B1 is connected to one side of the display area AA in the second direction Y. Figure 3The figure shows a partial enlarged view of the first border area B1 in an exemplary embodiment of the display panel of the present disclosure. The first border area B1 may include a first fan-out area Fot1, a bending area Ben, a second fan-out area Fot2, an integrated area Bdc, a third fan-out area Fot3, and a binding area COF. The bending area Ben is connected to the side of the first fan-out area Fot1 away from the display area AA, the second fan-out area Fot2 is connected to the side of the bending area Ben away from the first fan-out area Fot1, the integrated area Bdc is connected to the side of the second fan-out area Fot2 away from the bending area Ben, the third fan-out area Fot3 is connected to the side of the integrated area Bdc away from the second fan-out area Fot2, and the binding area COF is located on the side of the third fan-out area Fot3 away from the integrated area Bdc.

[0057] like Figure 3 As shown, the display panel may also include: a plurality of first fan-out lines Ftl1, a plurality of lead-out lines Flx, a plurality of second fan-out lines Ftl2, a detection unit CT, a plurality of third fan-out lines Ftl3, a first power access line VDD, and a plurality of binding pins Pad. The orthographic projections of the plurality of first fan-out lines Ftl1 on the substrate are located in the first fan-out area Fot1, the first fan-out lines Ftl1 are arranged corresponding to the data lines Da, and the first fan-out lines Ftl1 are connected to the corresponding data lines. Among them, the first fan-out line Ftl1 can be connected to the first data line Da1 through the second data connection line Fa2, or directly connected to the second data line Da2. The orthographic projections of the plurality of lead-out lines Flx on the substrate are located in the bending area Ben, the lead-out lines Flx are arranged corresponding to the first fan-out lines Ftl1, and the lead-out lines Flx are connected to the corresponding first fan-out lines Ftl1. The second fan-out line Ftl2 is arranged correspondingly to the lead-out line Flx, and the second fan-out line Ftl2 is connected to the corresponding lead-out line Flx. Figure 1 As shown, since at least part of the orthographic projection of the first data connection line Fa1 on the substrate substrate intersects with the orthographic projection of the second data line Da2 on the substrate substrate, this setting makes the data lead lines formed by the second data connection line Fa2 and the second data line Da2 have different arrangement orders in the first direction X, resulting in incompatibility with conventional integrated circuits. In this exemplary embodiment, it is necessary to change the order of the lead lines Flx in the second fan-out area Fot2 so that the arrangement order of the second fan-out line Ftl2 and the data line Da in the first direction X at the end entering the integrated area Bdc is the same. The partial structure of the orthographic projection of the first power access line VDD on the substrate substrate can be located in the second fan-out area Fot2. The first power access line VDD can be used to provide a first power signal to the sub-pixel. The first power signal can be a high-level power signal. For example, the first power access line VDD can be used to provide a pixel driving circuit with a first power signal. Figure 2The first power supply terminal in the substrate. The positive projection of the detection unit CT on the substrate is located in the integrated area Bdc, and the detection unit CT is connected to the second fan-out line Ftl2. The detection unit CT can be connected to the data line Da through the second fan-out line Ftl2, and the detection unit CT can perform functional detection on the data line Da and the display panel. For example, the detection unit CT can detect whether the data line is short-circuited or open-circuited. For another example, the detection unit CT can perform pure color display detection on the display panel. The positive projection of the third fan-out line Ftl3 on the substrate can be located in the third fan-out area Fot, the third fan-out line Ftl3 can be set corresponding to the second fan-out line Ftl2, and the third fan-out line Ftl3 can be connected to the corresponding second fan-out line Ftl2. The positive projection of the binding pin Pad on the substrate is located in the binding area COF, and the binding pin Pad is correspondingly connected to the third fan-out line Ftl3. The binding pin Pad can be used to bind the drive circuit, and the drive circuit can be used to provide a data signal to the data line Da.

[0058] like Figure 3 As shown, the first power access line VDD may include a plurality of access terminals VDD2, the orthographic projection of the access terminal VDD2 on the substrate extends along the second direction Y, and the orthographic projection of the access terminal VDD2 on the substrate is at least partially located in the bending area Ben. In this exemplary embodiment, the portion of the access terminal VDD2 whose orthographic projection on the substrate is located in the bending area Ben may be located in the same conductive layer as the lead-out line Flx. Therefore, when the first fan-out line Ftl1 is introduced into the bending area Ben, it is necessary to avoid the access terminal VDD2. Figure 3 As shown, the extension length of the first fan-out line Ftl1 on both sides of the access terminal VDD2 will change suddenly, which will cause a sudden change in the resistance of the data line itself, and in severe cases, it will cause split screen mura. In addition, Figure 3 In the illustrated embodiment, the size of the second fan-out region Fot2 in the second direction is relatively small, which is not conducive to reordering the data pin-out lines.

[0059] Based on this, the present exemplary embodiment provides another display panel, such as Figure 4 As shown, it is a schematic diagram of the structure of the first border area in another exemplary embodiment of the display panel disclosed in the present invention. In this exemplary embodiment, the first border area may include a first fan-out area Fot1, a bending area Ben, an integrated area Bdc, and a second fan-out area Fot2, wherein the bending area Ben is connected to a side of the first fan-out area Fot1 away from the display area, the integrated area Bdc is connected to a side of the bending area Ben away from the first fan-out area Fot1, and the second fan-out area Fot2 is connected to a side of the integrated area Bdc away from the bending area Ben. Figure 5 As shown, Figure 4The structural schematic diagram of each signal line in the display panel, the display panel may also include a plurality of first fan-out lines Ftl1, a plurality of lead-out lines Flx, a detection unit CT, and a first power access line VDD. The orthographic projections of the plurality of first fan-out lines Ftl1 on the substrate are located in the first fan-out area Fot1, the first fan-out line Ftl1 is arranged corresponding to the data line Da, and the first fan-out line Ftl1 is connected to the corresponding data line Da, wherein the first fan-out line Ftl1 may be connected to the first data line Da1 through the second data connection line Fa2, or directly connected to the second data line Da2. The orthographic projections of the plurality of lead-out lines Flx on the substrate are located in the bending area Ben, the lead-out lines Flx are arranged corresponding to the first fan-out lines Ftl1, and the lead-out lines Flx are connected to the corresponding first fan-out lines Ftl1; the orthographic projection of the detection unit CT on the substrate is located in the integrated area Bdc, and the detection unit CT is connected to the lead-out lines Flx. As shown Figure 6 As shown, Figure 4 Schematic diagram of the structure of the first power access line and the second power access line in FIG. The first power access line VDD can be used to provide a first power signal to the sub-pixels in the display panel. For example, the first power access line VDD can be used to provide Figure 2 The first power supply terminal in. The first power access line VDD may include a first extension part VDD1, a second extension part VDD2, and a third extension part VDD3. The first extension part VDD1 is connected between the second extension part VDD2 and the third extension part VDD3; wherein the orthographic projection of the first extension part VDD1 on the substrate extends along the first direction X and is located in the second fan-out area Fot2, the orthographic projection of the second extension part VDD2 on the substrate extends along the second direction Y and is at least partially located in the bending area Ben, and the orthographic projection of the third extension part VDD3 on the substrate extends along the second direction Y and is at least partially located in the bending area Ben. In the first direction X, the orthographic projection of the lead-out line Flx on the substrate is located between the orthographic projection of the second extension part VDD2 on the substrate and the orthographic projection of the third extension part VDD3 on the substrate.

[0060] In this exemplary embodiment, the orthographic projections of all lead wires Flx on the base substrate are located between the orthographic projections of the second extension portion VDD2 on the base substrate and the orthographic projections of the third extension portion VDD3 on the base substrate. The first fan-out wire Ftl1 connected to the lead wire Flx does not need to avoid the second extension portion VDD2 and the third extension portion VDD3. Therefore, the first fan-out wire Ftl1 distributed in the first direction X will not have a problem of sudden length change.

[0061] like Figure 4 ,5 As shown in , 6, the first power access line VDD may also include a fourth extension part VDD4 connected to the first extension part VDD1, the orthographic projection of the fourth extension part VDD4 on the substrate extends along the second direction Y and is at least partially located in the bending area Ben; in the first direction X, the orthographic projection of the fourth extension part VDD4 on the substrate is located between the orthographic projection of the second extension part VDD2 on the substrate and the orthographic projection of the third extension part VDD3 on the substrate. In the first direction X, the orthographic projection of part of the lead-out line Flx on the substrate is located between the orthographic projection of the second extension part VDD2 on the substrate and the orthographic projection of the fourth extension part VDD4 on the substrate, and the orthographic projection of part of the lead-out line Flx on the substrate is located between the orthographic projection of the third extension part VDD3 on the substrate and the orthographic projection of the fourth extension part VDD4 on the substrate. Among them, the multiple lead wires Flx include a first lead wire Flx1, a second lead wire Flx2, a third lead wire Flx3, and a fourth lead wire Flx4 that are adjacent to each other in sequence in the first direction X; the orthographic projection of the second lead wire Flx2 on the substrate and the orthographic projection of the third lead wire Flx3 on the substrate are located on two adjacent sides of the orthographic projection of the fourth extension portion VDD4 on the substrate; the orthographic projection of the first lead wire Flx1 on the substrate is located on a side where the orthographic projection of the second lead wire Flx2 on the substrate is away from the orthographic projection of the fourth extension portion VDD4 on the substrate, and the orthographic projection of the fourth lead wire Flx4 on the substrate is located on a side where the orthographic projection of the third lead wire Flx3 on the substrate is away from the orthographic projection of the fourth extension portion VDD4 on the substrate. The length of the orthographic projection of the first fan-out line Ftl1 connected to the second lead line Flx2 on the substrate is greater than the length of the orthographic projection of the first fan-out line Ftl1 connected to the first lead line Flx1 on the substrate, and the length of the orthographic projection of the first fan-out line Ftl1 connected to the third lead line Flx3 on the substrate is greater than the length of the orthographic projection of the first fan-out line Ftl1 connected to the fourth lead line Flx4 on the substrate. The orthographic projection of the first fan-out line Ftl1 connected to the second lead line Flx2 on the substrate and the orthographic projection of the first fan-out line Ftl1 connected to the third lead line Flx3 on the substrate can be symmetrical along a dividing line XX. This setting can also ensure that the first fan-out line Flt1 will not have a sudden change in length at both sides of the fourth extension portion VDD4.

[0062] like Figure 4 ,5 6, the first frame area B1 may include a first side B11 and a second side B12 that are arranged opposite to each other in the first direction X, and the plurality of lead lines Flx include a fifth lead line Flx5 and a sixth lead line Flx6; among the lead lines Flx, the orthographic projection of the fifth lead line Flx5 on the substrate is closest to the first side B11, and the orthographic projection of the sixth lead line Flx6 on the substrate is closest to the second side B12; the distance between the orthographic projection of the fourth extension portion VDD4 on the substrate and the orthographic projection of the fifth lead line Flx on the substrate in the first direction X may be equal to the distance between the orthographic projection of the fourth extension portion VDD4 on the substrate and the orthographic projection of the sixth lead line Flx6 on the substrate in the first direction X. The orthographic projections of the lead lines Flx on the substrate may be distributed at equal intervals along the first direction X. That is, the separation line XX may be located at the midline position of the region where the lead lines Flx are located in the first direction X.

[0063] It should be understood that in other exemplary embodiments, the orthographic projection of the first fan-out line Ftl1 connected to the second lead line Flx2 on the substrate and the orthographic projection of the first fan-out line Ftl1 connected to the third lead line Flx3 on the substrate may also be arranged asymmetrically. As long as the orthographic projection of the first fan-out line Ftl1 connected to the second lead line Flx2 on the substrate and the orthographic projection of the first fan-out line Ftl1 connected to the third lead line Flx3 on the substrate are the same or close in length, the problem of no sudden change in the length of the first fan-out line Ftl1 can be solved. In this exemplary embodiment, the length of the orthographic projection of the first fan-out line Ftl1 connected to the second lead line Flx on the substrate is L1, the length of the orthographic projection of the first fan-out line Ftl1 connected to the third lead line Flx on the substrate is L2, (L1-L2) / L2 is greater than or equal to 0 and less than or equal to 5%, for example, (L1-L2) / L2 can be equal to 0, 0.5%, 1%, 2%, 3%, 4%, 5%, etc. In addition, it should be noted that in other exemplary embodiments, the fourth extension portion VDD4 may not be provided in the present application.

[0064] like Figure 4 , 5As shown in Figure 6, in this exemplary embodiment, the substrate further includes a third fan-out area Fot3 and a binding area COF, the third fan-out area Fot3 is connected between the bending area Ben and the integrated area Bdc, and the binding area COF is connected to a side of the second fan-out area Fot2 away from the display area. The display panel also includes: a plurality of third fan-out lines Ftl3, a plurality of second fan-out lines Ftl2, a driving circuit (not shown in the figure), and a binding pin Pad. The orthographic projection of the third fan-out line Ftl3 on the substrate is located in the third fan-out area Fot3, and the third fan-out line Ftl3 is connected between the lead line Flx and the detection unit CT; the orthographic projection of the second fan-out line Ftl2 on the substrate is located in the second fan-out area Fot2, and the second fan-out line Ftl2 is connected to the third fan-out line Ftl3; the driving circuit is at least used to provide the data signal to the data line; the orthographic projection of the binding pin Pad on the substrate is located in the binding area COF, and the binding pin Pad is connected between the second fan-out line Ftl2 and the driving circuit.

[0065] like Figure 4 , 5 As shown in Figures 6 and 7, the present application can change the order of the data lines in the second fan-out area Fot2 so that the arrangement order of the binding pins Pad is the same as the arrangement order of the data lines in the display area, so that the display panel can match the conventional drive circuit. In addition, the present application sets the integrated area Bdc where the detection unit CT is located between the bending area Ben and the second fan-out area Fot2, so that the positive projection of the third fan-out line Ftl3 on the substrate can extend in a straight line along the second direction Y. This setting can greatly compress the size of the third fan-out area Fot3 in the second direction Y, thereby leaving enough space for changing the order for the second fan-out area Fot2. It should be understood that in other exemplary embodiments, a small portion of the third fan-out lines Ftl3 located on both sides of the first direction X can also extend obliquely to the middle position.

[0066] like Figure 4 , 5 , 6, in this exemplary embodiment, the size of the second fan-out area Fot2 in the second direction Y may be greater than the size of the third fan-out area Fot3 in the second direction Y. For example, the size of the second fan-out area Fot2 in the second direction Y is L3, the size of the third fan-out area Fot3 in the second direction Y is L4, L3 / L4 may be greater than or equal to 5 and less than or equal to 9, for example, L3 / L4 may be equal to 5, 6, 7, 8, 9, etc.

[0067] like Figure 4 , 5As shown in Figure 6, in the first fan-out line Ftl1 close to the first side B11, the orthographic projection of at least part of the structure of the first fan-out line Ftl1 on the substrate substrate is located on the side of the orthographic projection of the lead line Flx connected thereto on the substrate substrate close to the first side B11. The first fan-out line Ftl1 close to the first side B11 refers to: the first fan-out line Ftl1 whose orthographic projection on the substrate substrate is closer to the first side B11 than the distance from the second side B12. In this exemplary embodiment, in the first fan-out line Ftl1 close to the first side B11, the orthographic projection of the first fan-out line Ftl1 on the substrate substrate may extend obliquely toward the side away from the first side B11. It should be understood that in other exemplary embodiments, the orthographic projection of the first fan-out line Ftl1 on the substrate substrate may also first extend along the first direction X to the side away from the first side B11, and then extend along the second direction Y to the bending area Ben. In the first fan-out line Ftl1 near the second side, the orthographic projection of at least part of the structure of the first fan-out line Ftl1 on the substrate substrate is located on the side of the orthographic projection of the lead line Flx connected thereto on the substrate substrate near the second side B12. Similarly, the first fan-out line Ftl1 near the second side B12 refers to: the first fan-out line Ftl1 whose orthographic projection on the substrate substrate is farther from the first side B11 than from the second side B12. In this exemplary embodiment, in the first fan-out line Ftl1 near the second side B12, the orthographic projection of the first fan-out line Ftl1 on the substrate substrate may extend obliquely toward the side away from the second side B12. It should be understood that in other exemplary embodiments, the orthographic projection of the first fan-out line Ftl1 on the substrate substrate may also first extend along the first direction X toward the side away from the second side B12, and then extend along the second direction Y toward the bending area Ben.

[0068] In this exemplary embodiment, the display panel further includes: a power line (not shown), the orthographic projection of the power line on the substrate is located in the display area and extends along the second direction Y, and the power line is used to provide the first power signal to the sub-pixel. For example, the power line can be used to provide Figure 2 The first power supply terminal in. Figure 4 , 5As shown in , 6, the display panel in the present application may also include a first power connection line VDDx, the orthographic projection of the first power connection line VDDx on the substrate may be located in the first fan-out area Fot1, the orthographic projection of the first power connection line VDDx on the substrate extends along the first direction X, and the first power connection line VDDx connects multiple power lines; the first power access line VDD may be connected to the first power connection line VDDx through the second extension portion VDD2, the third extension portion VDD3, and the fourth extension portion VDD4.

[0069] like Figure 4 , 5 As shown in , 6, the display panel may further include a second power access line VSS and a second power connection line VSSx, the orthographic projection of the second power connection line VSSx on the substrate is located in the first fan-out area Fot1, and the orthographic projection of the second power access line VSS on the substrate is at least partially located in the bending area Ben and the second fan-out area Fot2. The second power connection line VSSx may be connected to the cathode ring in the display panel, or the second power connection line VSSx may form a partial structure of the cathode ring, the second power access line VSS may be used to provide a second power signal to the second power connection line VSSx, and the second power signal may be a low-level power signal, for example, the second power access line VSS may increase Figure 2 The second power supply terminal in.

[0070] In this exemplary embodiment, the display panel can bend a portion of the structure of the bending area Ben in the first frame area away from the display area to the non-display surface of the display panel through the bending area Ben.

[0071] In this exemplary embodiment, the display panel may include a substrate, a first active layer, a first insulating layer, a first gate layer, a buffer layer, a second active layer, a second insulating layer, a second gate layer, a dielectric layer, a third gate layer, a passivation layer, a first flat layer, a first source-drain layer, a second flat layer, a second source-drain layer, a third flat layer, and a third source-drain layer, which are sequentially stacked. Part of the structure of the first active layer can be used to form a channel region of a P-type transistor in a pixel driving circuit, part of the structure of the first gate layer can be used to form a gate of a P-type transistor in a pixel driving circuit and a first electrode of a capacitor, part of the structure of the second gate layer can be used to form a bottom gate of an N-type transistor in a pixel driving circuit and a second electrode of a capacitor, part of the structure of the third gate layer can be used to form a top gate of an N-type transistor in a pixel driving circuit, part of the structure of the first source-drain layer can be used to form a bridge connecting a transistor and a signal terminal, part of the structure of the second source-drain layer can be used to form a part of a power line, and part of the structure of the third source-drain layer can be used to form a data line and a part of a power line. The first insulating layer and the second insulating layer may be a single-layer structure or a multi-layer structure. The materials of the first insulating layer and the second insulating layer may be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the buffer layer may include at least one of a silicon oxide layer and a silicon nitride layer; the dielectric layer may be a silicon nitride layer; the passivation layer may be a silicon oxide layer; the materials of the first flat layer, the second flat layer, and the third flat layer may be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The substrate may be a flexible substrate or a rigid substrate. The substrate may be made of polyimide (PI), polyethylene terephthalate (PET), etc. The materials of the first gate layer and the second gate layer may be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy, or a molybdenum / titanium alloy or a laminate, etc. The materials of the first source-drain layer, the second source-drain layer, and the third source-drain layer may include metal materials, for example, one of molybdenum, aluminum, copper, titanium, niobium, or alloys, or molybdenum / titanium alloys or stacks, or titanium / aluminum / titanium stacks. The square resistance of the first source-drain layer, the second source-drain layer, and the third source-drain layer may be smaller than the square resistance of the first gate layer, the second gate layer, and the third gate layer. The first active layer may be formed of polysilicon material, and the second active layer may be formed of indium gallium zinc oxide.

[0072] It should be understood that in other exemplary embodiments, the pixel driving circuit in the display panel may have other structures, for example, the pixel driving circuit may not include the eighth transistor, and for another example, the first transistor and the second transistor may be P-type transistors. Accordingly, the display panel may also have other architectures, for example, when the pixel driving circuit includes only one type of transistor, the display panel may not include the third gate layer and the second active layer. In addition, the display panel may also only have the first source-drain layer and the second source-drain layer, and the data line may be located at the second source-drain layer.

[0073] like Figure 7 As shown, Figure 4 Partially enlarged view of the first fan-out area in FIG. Among them, the plurality of first fan-out lines Ftl1 may include a plurality of first sub-fan-out lines Ftl1x and a plurality of second sub-fan-out lines Ftl1y, wherein the first sub-fan-out lines Ftl1x may be located in the first gate layer of the display panel, and the second sub-fan-out lines Ftl1y may be located in the second gate layer of the display panel. The orthographic projections of the plurality of first sub-fan-out lines Ftl1x and the plurality of second sub-fan-out lines Ftl1y on the substrate may be alternately distributed in sequence along the first direction X. This arrangement may improve the integration of the first fan-out lines Ftl1.

[0074] Similarly, part of the second fan-out line Ftl2 is located in the first gate layer, part of the second fan-out line Ftl2 is located in the second gate layer, and the orthographic projection of the second fan-out line Ftl2 located in the first gate layer on the substrate and the orthographic projection of the second fan-out line Ftl2 located in the second gate layer on the substrate are alternately distributed in sequence in the first direction X; part of the third fan-out line Ftl3 is located in the first gate layer, part of the third fan-out line Ftl3 is located in the second gate layer, and the orthographic projection of the third fan-out line Ftl3 located in the first gate layer on the substrate and the orthographic projection of the third fan-out line Ftl3 located in the second gate layer on the substrate are alternately distributed in sequence in the first direction X; part of the binding pin Pad is located in the first gate layer, part of the binding pin Pad is located in the second gate layer, and the orthographic projection of the binding pin Pad located in the first gate layer on the substrate and the orthographic projection of the binding pin Pad located in the second gate layer on the substrate are alternately distributed in sequence in the first direction X.

[0075] like Figure 8 As shown, Figure 4Schematic diagram of the structure of the bending area in the middle. The orthographic projection on the substrate substrate of the second extension portion VDD2, the portion of the third extension portion VDD3, the portion of the fourth extension portion VDD4, the portion of the orthographic projection on the substrate substrate located in the bending area Ben, and the orthographic projection on the substrate substrate located in the bending area Ben do not overlap with the orthographic projection of the lead line Flx on the substrate substrate. On the one hand, this arrangement can make the portion of the second extension portion VDD2, the portion of the third extension portion VDD3, the portion of the fourth extension portion VDD4, the portion of the orthographic projection on the substrate substrate located in the bending area Ben, located in the same conductive layer as the lead line Flx. For example, the portion of the second extension VDD2 whose orthogonal projection on the substrate is located in the bending area Ben, the portion of the third extension VDD3 whose orthogonal projection on the substrate is located in the bending area Ben, the portion of the fourth extension VDD4 whose orthogonal projection on the substrate is located in the bending area Ben, and the lead line Flx can be located in the first source and drain layer. On the other hand, this arrangement can reduce the parasitic capacitance between the data line and the power line. It should be understood that in other exemplary embodiments, the portion of the second extension VDD2 whose orthogonal projection on the substrate is located in the bending area Ben, the portion of the third extension VDD3 whose orthogonal projection on the substrate is located in the bending area Ben, the portion of the fourth extension VDD4 whose orthogonal projection on the substrate is located in the bending area Ben, and the lead line Flx can also be located in different conductive layers.

[0076] like Figure 9-14 As shown, Fig. 9 for Figure 4 A partial enlarged view of the second fan-out area and the binding area. Fig.10 for Fig. 9 The structural layout of the first gate layer in Fig.11 for Fig. 9 The structural layout of the second gate layer in Fig.12 for Fig. 9 The structural layout of the first source and drain layer. Fig.13 for Fig. 9 The structural layout of the second source and drain layer, Fig.14 for Fig. 9 Structural layout of the third source and drain layer.

[0077] like Figure 9-14 As shown, the plurality of second fan-out lines Ftl2 may include: a plurality of first sub-fan-out lines Ftl21, a plurality of second sub-fan-out lines Ftl22, the first sub-fan-out lines Ftl21 and the Figure 1 The first sub-fan-out line Ftl21 is connected between the second data line Da2 and the binding pin Pad. Figure 1 The second data connection line Fa2 is arranged correspondingly, and the second sub-fan-out line Ftl22 is connected to the second data connection line Fa2 corresponding thereto. The display panel may also include: a third data connection line Fa3, the orthographic projection of the third data connection line Fa3 on the substrate is located in the second fan-out area Fot2, part of the third data connection line Fa3 may be located in the second source and drain layer of the display panel, and part of the third data connection line Fa3 may be located in the third source and drain layer of the display panel. The third data connection line Fa3 may include a fifth extension portion Fa35 and a sixth extension portion Fa36, the orthographic projection of the fifth extension portion Fa35 on the substrate extends along the first direction X, the orthographic projection of the sixth extension portion Fa36 on the substrate extends along the second direction Y, the fifth extension portion Fa35 connects the second sub-fan-out line Ftl22, and the sixth extension portion Fa36 may be connected between the binding pin Pad and the fifth extension portion Fa35. The orthographic projection of the fifth extension portion Fa35 on the substrate intersects with the orthographic projection of at least part of the first sub-fan-out line Ftl21 on the substrate. In this exemplary embodiment, the second fan-out line Ftl2 is reordered through the third data connection line Fa3, so that the arrangement order of the binding pins Pad in the first direction X is the same as the arrangement order of the data lines connected thereto in the first direction X. The sixth extension portion Fa36 can be connected to the binding pin Pad through the first bridge portion 41, wherein the sixth extension portion Fa36 is connected to the first bridge portion 41 through a via hole, and the first bridge portion 41 is connected to the binding pin Pad through a via hole. Fig. 9 The black squares in the middle indicate the positions of the via holes. The first bridge portion 41 may be located at the first source-drain layer of the display panel.

[0078] like Figure 4 As shown, in this exemplary embodiment, the orthographic projection of the third data connection line Fa3 on the base substrate is located on a side where the orthographic projection of the first extension portion VDD1 on the base substrate is away from the orthographic projection of the detection unit CT on the base substrate.

[0079] like Figure 9-14As shown, the third data connection line Fa3 also includes a seventh extension portion Fa37, the seventh extension portion Fa37 is connected between the fifth extension portion Fa35 and the second sub-fan-out line Ftl22, and the orthographic projection of the seventh extension portion Fa37 on the substrate extends along the second direction Y. The seventh extension portion Fa37 can be connected to the second sub-fan-out line Ftl22 through the second bridge portion 42, wherein the seventh extension portion Fa37 can be connected to the second sub-fan-out line Ftl22 through a via, and the second bridge portion 42 is connected to the second sub-fan-out line Ftl22 through a via. The second bridge portion 42 can be located in the first source and drain layer of the display panel. It should be noted that in other exemplary embodiments, the fifth extension portion Fa35 and the second sub-fan-out line Ftl22 can also be directly connected. That is, the third data connection line Fa3 may not include the seventh extension portion Fa37.

[0080] like Figure 9-14 As shown, the plurality of third data connection lines Fa3 may include a plurality of first sub-data connection lines Fa31 and a plurality of second sub-data connection lines Fa32, the first sub-data connection lines Fa31 may be located in the second source-drain layer, and the second sub-data connection lines Fa32 may be located in the third source-drain layer. The orthographic projection of the first sub-data connection lines Fa31 on the substrate and the orthographic projection of the second sub-data connection lines Fa32 on the substrate are alternately distributed in the second direction Y. This arrangement may improve the integration of the third data connection lines Fa3. It should be understood that in other exemplary embodiments, the third data connection lines Fa3 may be located in the same conductive layer, and the first sub-data connection lines Fa31 and the plurality of second sub-data connection lines Fa32 may also be located in other conductive layers, respectively. For example, the first sub-data connection lines Fa31 and the second sub-data connection lines Fa32 may also be located in the first source-drain layer and the second source-drain layer, respectively.

[0081] like Figure 9-14 As shown, the display panel may further include a shielding portion 43, and the shielding portion 43 may be connected to a stable voltage source, for example, the shielding portion 43 may be connected to the first extension portion VDD1. The shielding portion 43 may be located between the conductive layer where the second fan-out line Ftl2 is located and the conductive layer where the third data connection line Fa3 is located, for example, the shielding portion 43 may be located in the first source-drain layer. The shielding portion 43 may shield between the second fan-out line Ftl2 and the third data connection line Fa3, thereby reducing interference between different data signals.

[0082] like Figure 9-14As shown, the first sub-data connection line Fa31 located in the second source-drain layer can be connected to the second fan-out line Ftl2 located in the first gate layer, and the second sub-data connection line Fa32 located in the third source-drain layer can be connected to the second fan-out line Ftl2 located in the second gate layer. This setting can make the length of the connection vias between different third data connection lines Fa3 and the second fan-out line Ftl2 similar, thereby reducing the resistance difference between different data leads. Wherein, the data lead includes a data line, and a fan-out line and a lead connected to the data line.

[0083] like Figure 9-14 As shown, the display panel may further include a plurality of simulated bridge portions 44, the simulated bridge portions 44 may be connected to the binding pins Pad connected to the first sub-fan-out line Ftl21 through vias, and the simulated bridge portions 44 may simulate the conductive effect of the first bridge portion 41 to reduce the resistance difference between different data leads. In addition, the simulated bridge portions 44 may also simulate the parasitic capacitance, light shielding and other characteristics of the first bridge portion 41 to improve the uniformity of the structure at different positions of the display panel, thereby improving the uniformity of the display of the display panel.

[0084] like Fig.15 As shown, Fig. 9 A cross-sectional view along the dotted line CC in FIG. In which, the substrate 90, the first insulating layer 91, the first gate layer, the buffer layer 92, the second insulating layer 93, the second gate layer, the dielectric layer 94, the passivation layer 95, the first planar layer 96, the first source-drain layer, the second planar layer 97, the second source-drain layer, the third planar layer 98, and the third source-drain layer are sequentially stacked.

[0085] like Figure 16-19 As shown, Fig.16 for Figure 6 The structural layout of the first power supply access line and the second power supply access line, Fig.17 for Fig.16 The structural layout of the first source and drain layer in the figure. Fig.18 for Fig.16 The structural layout of the second source and drain layer in the figure. Fig.19 for Fig.16 Structural layout of the third source and drain layer.

[0086] The first extension portion VDD1 is located in the second source-drain layer and the third source-drain layer. The first power access line VDD and the second power access line VSS are located in the bending area Ben and are only arranged in the second source-drain layer. The first power connection line VDDx and the second power connection line VSSx can be arranged in the first source-drain layer. It should be understood that in other exemplary embodiments, the first power connection line VDDx and the second power connection line VSSx can also be located in any one or more layers of the first source-drain layer, the second source-drain layer, and the third source-drain layer.

[0087] like Fig. 20 , which is a resistance variation diagram of the data lead-out line at different positions of the display panel of the present disclosure. The horizontal axis represents different positions of the display panel in the first direction X, Fig. 20 The middle dotted line DD represents the center line position of the display panel in the first direction. The ordinate represents the resistance of the data lead. E1 represents Figure 3 The resistance variation diagram of the data line lead wire at different positions of the display panel in the embodiment shown, E2 represents Figure 4 The resistance variation diagram of the data line lead wire at different positions of the display panel in the embodiment shown. Fig. 20 It can be seen that Figure 3 In the embodiment shown, there is a sudden change in resistance of the data line. Figure 3 The illustrated embodiment can improve this mutation problem.

[0088] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a display device such as a mobile phone, a tablet computer, a television, etc.

[0089] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered merely as exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0090] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel comprises: A substrate, comprising a display area and a first frame area, wherein the first frame area is connected to one side of the display area in a second direction, the first frame area comprises a first fan-out area, a bending area, an integrated area, and a second fan-out area, the bending area is connected to a side of the first fan-out area away from the display area, the integrated area is connected to a side of the bending area away from the first fan-out area, and the second fan-out area is connected to a side of the integrated area away from the bending area; A plurality of sub-pixels, the orthographic projections of which on the base substrate are located in the display area; A plurality of data lines, the orthographic projections of which on the base substrate are located in the display area, and the data lines are used to provide data signals to the sub-pixels; A plurality of first fan-out lines, whose orthographic projections on the substrate are located in the first fan-out area, the first fan-out lines are arranged corresponding to the data lines, and the first fan-out lines are connected to the corresponding data lines; A plurality of lead-out lines, the orthographic projections of which on the substrate are located in the bending region, the lead-out lines are arranged corresponding to the first fan-out lines, and the lead-out lines are connected to the first fan-out lines corresponding thereto; A detection unit, wherein the orthographic projection of the detection unit on the substrate is located in the integrated area, and the detection unit is connected to the lead-out line; A first power access line, used to provide a first power signal to the sub-pixel, the first power access line comprising a first extension portion, a second extension portion, and a third extension portion, the first extension portion being connected between the second extension portion and the third extension portion; The orthographic projection of the first extension portion on the substrate extends along the first direction and is located in the second fan-out area, the orthographic projection of the second extension portion on the substrate extends along the second direction and is at least partially located in the bending area, the orthographic projection of the third extension portion on the substrate extends along the second direction and is at least partially located in the bending area, and the first direction and the second direction intersect; In the first direction, an orthographic projection of the lead-out line on the base substrate is located between an orthographic projection of the second extension portion on the base substrate and an orthographic projection of the third extension portion on the base substrate.

2. The display panel according to claim 1, wherein: The first power supply access line further includes a fourth extension portion connected to the first extension portion, the orthographic projection of the fourth extension portion on the base substrate extending along the second direction and at least partially located in the bending area; In the first direction, the orthographic projection of the fourth extension portion on the base substrate is located between the orthographic projection of the second extension portion on the base substrate and the orthographic projection of the third extension portion on the base substrate; In the first direction, the orthographic projection of part of the lead wires on the substrate is located between the orthographic projection of the second extension part on the substrate and the orthographic projection of the fourth extension part on the substrate, and the orthographic projection of another part of the lead wires on the substrate is located between the orthographic projection of the third extension part on the substrate and the orthographic projection of the fourth extension part on the substrate.

3. The display panel according to claim 2, wherein: The plurality of lead wires include a first lead wire, a second lead wire, a third lead wire, and a fourth lead wire that are sequentially adjacent to each other in the first direction; The orthographic projection of the second lead line on the base substrate and the orthographic projection of the third lead line on the base substrate are located on two adjacent sides of the orthographic projection of the fourth extension portion on the base substrate; The orthographic projection of the first lead line on the substrate is located on a side where the orthographic projection of the second lead line on the substrate is away from the orthographic projection of the fourth extension on the substrate, and the orthographic projection of the fourth lead line on the substrate is located on a side where the orthographic projection of the third lead line on the substrate is away from the orthographic projection of the fourth extension on the substrate; The length of the orthographic projection of the first fan-out line connected to the second lead-out line on the substrate is greater than the length of the orthographic projection of the first fan-out line connected to the first lead-out line on the substrate, and the length of the orthographic projection of the first fan-out line connected to the third lead-out line on the substrate is greater than the length of the orthographic projection of the first fan-out line connected to the fourth lead-out line on the substrate.

4. The display panel according to claim 3, wherein: An orthographic projection of the first fan-out line connected to the second lead-out line on the substrate and an orthographic projection of the first fan-out line connected to the third lead-out line on the substrate are symmetrical along a separation line.

5. The display panel according to claim 3, wherein: The length of the orthographic projection of the first fan-out line connected to the second lead line on the base substrate is L1, the length of the orthographic projection of the first fan-out line connected to the third lead line on the base substrate is L2, and (L1-L2) / L2 is greater than or equal to 0 and less than or equal to 5%.

6. The display panel according to claim 2, wherein: The first border area includes a first side edge and a second side edge that are arranged opposite to each other in the first direction, and the plurality of lead lines include a fifth lead line and a sixth lead line; Among the lead wires, the orthographic projection of the fifth lead wire on the base substrate is closest to the first side, and the orthographic projection of the sixth lead wire on the base substrate is closest to the second side; The distance between the orthographic projection of the fourth extension portion on the substrate and the orthographic projection of the fifth lead line on the substrate in the first direction is equal to the distance between the orthographic projection of the fourth extension portion on the substrate and the orthographic projection of the sixth lead line on the substrate in the first direction.

7. The display panel according to claim 1, wherein: The base substrate further includes a third fan-out area and a binding area, wherein the third fan-out area is connected between the bending area and the integrated area, and the binding area is connected to a side of the second fan-out area away from the display area; The display panel further includes: A third fan-out line, the orthographic projection of which on the substrate is located in the third fan-out area, and the third fan-out line is connected between the lead-out line and the detection unit; A second fan-out line, the orthographic projection of which on the substrate is located in the second fan-out area, and the second fan-out line is connected to the third fan-out line; a driving circuit, the driving circuit being at least used to provide the data signal to the data line; A binding pin, whose orthographic projection on the substrate is located in the binding area, and the binding pin is connected between the second fan-out line and the driving circuit.

8. The display panel according to claim 7, wherein: An orthographic projection of at least part of the third fan-out line on the substrate extends linearly along the second direction.

9. The display panel according to claim 7, wherein: A size of the second fan-out area in the second direction is greater than a size of the third fan-out area in the second direction.

10. The display panel according to claim 9, wherein: A size of the second fan-out area in the second direction is L3, a size of the third fan-out area in the second direction is L4, and L3 / L4 is greater than or equal to 5 and less than or equal to 9.

11. The display panel according to claim 7, wherein: The orthographic projections of the plurality of data lines on the substrate are spaced apart along the first direction and extend along the second direction, and the plurality of data lines include a first data line and a second data line; The display area further includes a fourth fan-out area, and the display panel further includes: a plurality of first data connection lines, located in the fourth fan-out region, wherein the orthographic projections of the first data connection lines on the substrate are spaced apart along the second direction and extend along the first direction, the first data connection lines are connected between the corresponding first data lines and the first fan-out lines, and the orthographic projections of the first data connection lines on the substrate overlap with at least a portion of the orthographic projections of the second data lines on the substrate; A plurality of second data connection lines are located in the fourth fan-out area, the orthographic projections of the second data connection lines on the substrate are spaced apart along the first direction and extend along the second direction, and the second data connection lines are connected between the first data connection lines and the first fan-out lines.

12. The display panel according to claim 11, wherein: The display area includes a third side and a fourth side that are arranged opposite to each other in the first direction; The orthographic projection of the first data line on the base substrate is located on a side of the orthographic projection of the second data line on the base substrate close to the third side or the fourth side.

13. The display panel according to claim 1, wherein: The first border area includes a first side edge and a second side edge that are arranged opposite to each other in the first direction; In the first fan-out line close to the first side, an orthographic projection of at least a portion of the structure of the first fan-out line on the base substrate is located on a side of an orthographic projection of the lead-out line connected thereto on the base substrate close to the first side; In the first fan-out line close to the second side, an orthographic projection of at least part of the structure of the first fan-out line on the base substrate is located on a side of an orthographic projection of the lead-out line connected thereto on the base substrate close to the second side.

14. The display panel according to claim 2, wherein: The second extension portion and the lead wire are located in the same conductive layer, where the orthographic projection on the base substrate is located in the bending area; The third extension portion and the lead wire are located in the same conductive layer at a portion where the orthographic projection on the base substrate is located in the bending area; The portion of the fourth extension portion whose orthographic projection on the base substrate is located in the bending region and the lead-out line are located in the same conductive layer.

15. The display panel according to claim 2, wherein: The display panel further includes: a power line, the orthographic projection of which on the base substrate is located in the display area and extends along the second direction, the power line being used to provide the first power signal to the sub-pixel; A first power connection line, whose orthographic projection on the substrate is located in the first fan-out area, the orthographic projection of the first power connection line on the substrate extends along the first direction, and the first power connection line connects a plurality of the power lines; The first power supply incoming line is connected to the first power supply connecting line through the second extending portion, the third extending portion, and the fourth extending portion.

16. The display panel according to claim 11, wherein: The plurality of second fan-out lines include: a plurality of first sub-fan-out lines, wherein the first sub-fan-out lines are arranged corresponding to the second data lines, and the first sub-fan-out lines are connected to the corresponding second data lines; a plurality of second sub-fan-out lines, wherein the second sub-fan-out lines and the second data connection lines are arranged correspondingly, and the second sub-fan-out lines are connected to the second data connection lines corresponding thereto; The display panel further includes: a third data connection line, the orthographic projection on the substrate is located in the second fan-out area, the third data connection line comprises a fifth extension portion and a sixth extension portion, the orthographic projection of the fifth extension portion on the substrate extends along the first direction, the orthographic projection of the sixth extension portion on the substrate extends along the second direction, the fifth extension portion is connected to the second sub-fan-out line, and the sixth extension portion is connected between the binding pin and the fifth extension portion; Wherein, the orthographic projection of the fifth extension portion on the substrate intersects with the orthographic projection of at least part of the first sub-fan-out line on the substrate; The arrangement order of the binding pins in the first direction is the same as the arrangement order of the data lines connected thereto in the first direction.

17. The display panel according to claim 16, wherein: The third data connection line further includes a seventh extension portion, the seventh extension portion is connected between the fifth extension portion and the second sub-fan-out line, and an orthographic projection of the seventh extension portion on the base substrate extends along the second direction.

18. The display panel according to claim 16, wherein: The plurality of third data connection lines include a plurality of first sub-data connection lines and a plurality of second sub-data connection lines, and the first sub-data connection lines and the second sub-data connection lines are located in different conductive layers; The orthographic projections of the first sub-data connection lines on the base substrate and the orthographic projections of the second sub-data connection lines on the base substrate are alternately distributed in sequence in the second direction.

19. The display panel according to claim 18, wherein: The display panel further includes: A first gate layer, located on one side of the substrate; A second gate layer is located on a side of the substrate away from the first gate layer; Part of the second fan-out lines are located in the first gate layer, and part of the second fan-out lines are located in the second gate layer, and the orthographic projections of the second fan-out lines located in the first gate layer on the substrate and the orthographic projections of the second fan-out lines located in the second gate layer on the substrate are alternately distributed in the first direction; A first source-drain layer is located on a side of the second gate layer away from the substrate, the first source-drain layer comprises a shielding portion, and the shielding portion is connected to a stable voltage source; A second source-drain layer is located on a side of the first source-drain layer away from the base substrate, and the first sub-data connection line is located on the second source-drain layer; A third source-drain layer is located on a side of the second source-drain layer away from the substrate, and the second sub-data connection line is located on the third source-drain layer; Wherein, the shielding part shields between the second fan-out line and the third data connection line.

20. The display panel according to claim 19, wherein: The orthographic projection of the third data connection line on the base substrate is located on a side where the orthographic projection of the first extension portion on the base substrate is away from the orthographic projection of the detection unit on the base substrate; The shielding portion is connected to the first extending portion.

21. The display panel according to claim 7, wherein: The display panel further includes: A first gate layer, located on one side of the substrate; A second gate layer is located on a side of the substrate away from the first gate layer; Part of the first fan-out lines are located in the first gate layer, and part of the first fan-out lines are located in the second gate layer, and the orthographic projections of the first fan-out lines located in the first gate layer on the substrate and the orthographic projections of the first fan-out lines located in the second gate layer on the substrate are alternately distributed in sequence in the first direction; Part of the third fan-out lines is located in the first gate layer, and part of the third fan-out lines is located in the second gate layer, and the orthographic projection of the third fan-out lines located in the first gate layer on the substrate and the orthographic projection of the third fan-out lines located in the second gate layer on the substrate are alternately distributed in the first direction.

22. The display panel according to claim 19, wherein: The first sub-data connection line is connected to the second fan-out line located in the first gate layer, and the second sub-data connection line is connected to the second fan-out line located in the second gate layer.

23. A display device, wherein: The display device comprises the display panel according to any one of claims 1-22.

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