Light-emitting diode chip with reduced step fracture possibility and preparation method thereof

Abstract

The present disclosure provides a light-emitting diode chip and a preparation method thereof that reduce the possibility of step fracture, and belongs to the field of light-emitting diode manufacturing technology. In the light-emitting diode chip, in the direction from the surface of the n-type layer to the p-type layer, the maximum distance between the side wall of the step and the side wall of the epitaxial wafer is gradually reduced. The longitudinal section of the side wall of the step is a curve, and the curve includes a first arc segment close to the p-type layer and a second arc segment away from the p-type layer. One end of the first arc segment is connected to and tangent to one end of the second arc segment. The center of the circle corresponding to the first arc segment is located inside the epitaxial wafer, and the center of the circle corresponding to the second arc segment is located outside the epitaxial wafer. To avoid stress concentration, the step is relatively flat near the connection position between the p-type layer and the n-type layer and the connection area is larger. The connection strength is large and the tolerance to the force in the vertical direction is high, which can reduce the possibility of fracture.

Description

Technical Field

[0001] The present disclosure relates to the technical field of light emitting diode manufacturing, and in particular to a light emitting diode chip with reduced possibility of step fracture and a manufacturing method thereof. Background Art

[0002] Light-emitting diodes are an important light source device, widely used in outdoor lighting and automobile taillights. Light-emitting diode chips are the basic structure used to prepare light-emitting diodes.

[0003] The light-emitting diode chip includes an epitaxial wafer, an n-electrode and a p-electrode. The epitaxial wafer includes a substrate and an n-type layer, a light-emitting layer and a p-type layer stacked in sequence on the substrate. The surface of the p-type layer has a step extending to the n-type layer. The n-electrode is connected to the surface of the n-type layer exposed by the step, and the p-electrode is connected to the surface of the p-type layer.

[0004] The sidewalls of the step extending from the p-type layer to the surface of the n-type layer are usually perpendicular to the surface of the n-type layer, resulting in a weak connection at the junction of the sidewall of the step and the surface of the n-type layer. The LED chip is prone to breakage at the junction of the sidewall of the step and the surface of the n-type layer, affecting the reliability of the LED chip. Summary of the Invention

[0005] The present disclosure provides a light-emitting diode chip and a method for manufacturing the same that reduces the possibility of step fracture, thereby reducing the possibility of the light-emitting diode chip fracture at the interface between the sidewall of the step and the surface of the n-type layer, thereby improving the reliability of the light-emitting diode chip. The technical solution is as follows:

[0006] The present disclosure provides a light-emitting diode chip with reduced step fracture potential, the light-emitting diode chip comprising an epitaxial wafer, an n-electrode, and a p-electrode. The epitaxial wafer comprises a substrate and an n-type layer, a light-emitting layer, and a p-type layer sequentially stacked on the substrate. The surface of the p-type layer has a step extending to the n-type layer. The n-electrode is connected to the surface of the n-type layer exposed by the step, and the p-electrode is connected to the surface of the p-type layer.

[0007] In the direction from the surface of the n-type layer to the p-type layer, the maximum distance between the side wall of the step and the side wall of the epitaxial wafer gradually decreases, and the longitudinal section of the side wall of the step is a curve, the curve including a first arc-shaped line segment close to the p-type layer and a second arc-shaped line segment away from the p-type layer, one end of the first arc-shaped line segment is connected to and tangent to one end of the second arc-shaped line segment, the center of a circle corresponding to the first arc-shaped line segment is located inside the epitaxial wafer, and the center of a circle corresponding to the second arc-shaped line segment is located outside the epitaxial wafer.

[0008] Optionally, a radius corresponding to the second arc-shaped line segment is greater than a radius corresponding to the first arc-shaped line segment, and a length of the second arc-shaped line segment is greater than a length of the first arc-shaped line segment.

[0009] Optionally, the projection of the epitaxial wafer on the surface of the substrate is a rectangle, the projection of the side wall of the step on the surface of the substrate is an arc, and both ends of the arc are tangent to two adjacent sides of the rectangle.

[0010] Optionally, the smaller the distance between the side wall of the step and the p-electrode, the larger the radius and length corresponding to the first arc-shaped line segment and the radius and length corresponding to the second arc-shaped line segment.

[0011] The present disclosure provides a method for preparing a light-emitting diode chip with reduced possibility of step fracture. The method for preparing a light-emitting diode chip with reduced possibility of step fracture includes:

[0012] providing a substrate;

[0013] sequentially growing an n-type layer, a light-emitting layer, and a p-type layer on the substrate to obtain an epitaxial wafer;

[0014] A step is formed extending from the p-type layer to the n-type layer, wherein the maximum distance between the sidewall of the step and the sidewall of the epitaxial wafer gradually decreases in a direction from the surface of the n-type layer toward the p-type layer, and the longitudinal cross-section of the sidewall of the step is a curve, wherein the curve includes a first arc segment close to the p-type layer and a second arc segment away from the p-type layer, wherein one end of the first arc segment is connected to and tangent to one end of the second arc segment, the center of a circle corresponding to the first arc segment is located within the epitaxial wafer, and the center of a circle corresponding to the second arc segment is located outside the epitaxial wafer;

[0015] forming a p-electrode on a surface of the p-type layer;

[0016] An n-electrode is formed on a surface of the n-type layer exposed by the step.

[0017] Optionally, the step of preparing the step extending from the p-type layer to the n-type layer includes:

[0018] coating a photoresist on the surface of the p-type layer;

[0019] sequentially exposing and developing the photoresist to form a pattern on the photoresist and forming a first arc-shaped region and a second arc-shaped region connected to each other on a sidewall of the photoresist;

[0020] A step extending to the n-type layer is etched in the p-type layer.

[0021] Optionally, the step of preparing the step extending from the p-type layer to the n-type layer further includes:

[0022] After developing the photoresist, the photoresist is baked before etching the p-type layer to form a step extending to the n-type layer.

[0023] Optionally, the photoresist is baked at a temperature of 120 to 130 degrees Celsius for 20 to 30 minutes.

[0024] Optionally, etching a step extending from the p-type layer to the n-type layer includes:

[0025] Etching for a first time using a first gas at a power of 300-500W;

[0026] Etching with a second gas for a second time period at a power of 300-800 W, wherein the second time period is greater than the first time period;

[0027] The step is obtained by etching with a third gas for a third time under a power of 100-200 W, wherein the third time is shorter than the first time.

[0028] Optionally, the first gas and the second gas both include chlorine and bromine chloride, the third gas includes argon, the flow rate of the first gas is greater than the flow rate of the second gas, and the flow rate of the third gas is less than the flow rate of the second gas.

[0029] The technical solutions provided by the embodiments of the present disclosure have the following beneficial effects:

[0030] In a light-emitting diode chip, the maximum distance between the sidewall of a step and the sidewall of an epitaxial wafer gradually decreases in a direction from the surface of the n-type layer toward the p-type layer, and the longitudinal cross-section of the step sidewall is curved. This can increase the connection strength between the step and the n-type layer, reduce the possibility of the step breaking at the junction with the n-type layer, and improve the reliability of the light-emitting diode chip. It also ensures sufficient space on the n-type layer for the n-electrode. The longitudinal cross-section of the step sidewall is curved, and the curve includes a first arc segment close to the p-type layer and a second arc segment away from the p-type layer. One end of the first arc segment is connected to and tangent to one end of the second arc segment. The center of the circle corresponding to the first arc segment is located inside the epitaxial wafer, and the center of the circle corresponding to the second arc segment is located outside the epitaxial wafer. There is a connection and transition between the first arc segment and the second arc segment, and the curvature change directions of the first arc segment and the second arc segment are different, which can effectively avoid stress concentration and reduce the possibility of the light-emitting diode chip breaking due to stress concentration at the step; and the setting of the center of the first arc segment and the center of the second arc segment can also make the step relatively flat and the connection area larger near the connection position between the p-type layer and the n-type layer, the connection strength is large, and the tolerance to the vertical force is high, which can reduce the possibility of breakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0032] Figure 1 This is a schematic structural diagram of a light-emitting diode chip that reduces the possibility of step fractures, provided by an embodiment of the present disclosure;

[0033] Figure 2 is a side view of a step provided by an embodiment of the present disclosure;

[0034] Figure 3 is a top view of a step provided by an embodiment of the present disclosure;

[0035] Figure 4 A schematic structural diagram of another light-emitting diode chip with reduced step fracture potential provided by an embodiment of the present disclosure;

[0036] Figure 5 This is a flow chart of a light-emitting diode chip with reduced step fracture potential and a method for manufacturing the same, provided by an embodiment of the present disclosure;

[0037] Figure 6 This is a flow chart of another light-emitting diode chip and its preparation method that reduces the possibility of step fracture provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0039] Figure 1 This is a schematic diagram of the structure of a light-emitting diode chip that reduces the possibility of step fracture provided by an embodiment of the present disclosure. Figure 1 It can be seen that the embodiment of the present disclosure provides a light-emitting diode chip with reduced possibility of step fracture. The light-emitting diode chip with reduced possibility of step fracture includes an epitaxial wafer 1, an n-electrode 2 and a p-electrode 3. The epitaxial wafer 1 includes a substrate 11 and an n-type layer 12, a light-emitting layer 13 and a p-type layer 14 stacked in sequence on the substrate 11. The surface of the p-type layer 14 has a step 10 extending to the n-type layer 12. The n-electrode 2 is connected to the surface of the n-type layer 12 exposed by the step 10, and the p-electrode 3 is connected to the surface of the p-type layer 14.

[0040] Figure 2 is a side view of the steps provided in the embodiment of the present disclosure, with reference to Figure 2 It can be seen that in the direction from the surface of the n-type layer 12 to the p-type layer 14 , the maximum distance between the side wall of the step 10 and the side wall of the epitaxial wafer 1 gradually decreases, and the longitudinal section of the side wall of the step 10 is a curve, which includes a first arc segment 101 close to the p-type layer 14 and a second arc segment 102 away from the p-type layer 14 . One end of the first arc segment 101 is connected to and tangent to one end of the second arc segment 102 . The center of the circle corresponding to the first arc segment 101 is located inside the epitaxial wafer 1 , and the center of the circle corresponding to the second arc segment 102 is located outside the epitaxial wafer 1 .

[0041] In the light-emitting diode chip, the maximum distance between the sidewalls of step 10 and the sidewalls of epitaxial wafer 1 gradually decreases in the direction from the surface of n-type layer 12 toward p-type layer 14. The longitudinal cross-section of the sidewalls of step 10 is curved. This strengthens the connection between step 10 and n-type layer 12, reduces the likelihood of step 10 breaking at the interface with n-type layer 12, and improves the reliability of the light-emitting diode chip. It also ensures sufficient space on n-type layer 12 for n-electrode 2. The longitudinal cross-section of the sidewalls of step 10 is curved, and the curve includes a first arcuate segment 101 proximal to p-type layer 14 and a second arcuate segment 102 distal to p-type layer 14. One end of first arcuate segment 101 is connected to and tangent to one end of second arcuate segment 102. The center of the circle corresponding to first arcuate segment 101 is located within epitaxial wafer 1, while the center of the circle corresponding to second arcuate segment 102 is located outside epitaxial wafer 1. There is a connection and transition between the first arc segment 101 and the second arc segment 102, and the curvature change directions of the first arc segment 101 and the second arc segment 102 are different, which can effectively avoid stress concentration and reduce the possibility of the light-emitting diode chip breaking due to stress concentration at the step 10; and the setting of the center of the first arc segment 101 and the center of the second arc segment 102 can also make the step 10 relatively flat and with a larger connection area near the connection position between the p-type layer 14 and the n-type layer 12, so that the connection strength is high and the tolerance to vertical forces is high, which can reduce the possibility of breakage.

[0042] It should be noted that the side wall of the epitaxial wafer 1 provided in the present disclosure is the side wall of the epitaxial wafer 1 that is farthest from the step 10. Figure 1 The side wall farthest from the step 10 is marked as 1a.

[0043] refer to Figure 2 It can be seen that the radius corresponding to the second arc segment 102 is greater than the radius corresponding to the first arc segment 101 , and the length of the second arc segment 102 is greater than the length of the first arc segment 101 .

[0044] The first arc segment 101 and the second arc segment 102 adopt the above structure, which can ensure that the step 10 can withstand greater stress and further reduce the possibility of the light emitting diode chip being broken at the step 10.

[0045] Optionally, the smaller the distance between the sidewall of the step 10 and the p-electrode 3 , the larger the radius and length corresponding to the first arc segment 101 and the radius and length corresponding to the second arc segment 102 .

[0046] In an implementation method provided in the present disclosure, the smaller the distance between the side wall of the step 10 and the p-electrode 3, the larger the radius and length of the first arc segment 101 and the second arc segment 102 corresponding to the side wall of this part of the step 10, which can reduce the stress concentration of the step 10 near the p-electrode 3, reduce the possibility of fracture near the p-electrode 3, and improve the reliability of the light-emitting diode chip.

[0047] It should be noted that the step 10 is located relatively close to the p-electrode 3. Since the fabrication of the p-electrode 3 itself generates a certain amount of stress, the slopes of the first and second curved segments 101, 102 corresponding to the sidewalls of the step 10 are made steeper near the p-electrode 3. This effectively reduces the possibility of the LED chip breaking or separating near the p-electrode 3. The radius and length of the first curved segment 101 are the radius of the circle on which the first curved segment 101 is located and the length of the first curved segment 101 itself, respectively. The surface of the substrate 11 is the largest surface of the substrate 11 where the n-type layer 12 is laminated.

[0048] Figure 3 is a top view of the steps provided in the embodiment of the present disclosure, with reference to Figure 3 It can be seen that the projection of the epitaxial wafer 1 on the surface of the substrate 11 is a rectangle, the projection of the side wall of the step 10 on the surface of the substrate 11 is an arc 103, and both ends of the arc 103 are tangent to the two adjacent sides of the rectangle.

[0049] The projection of the step 10 on the surface of the substrate 11 is set as an arc 103, and the two ends of the arc 103 are tangent to the two adjacent sides of the rectangle. This can reduce the stress concentration between the step 10 and the epitaxial wafer 1, thereby reducing the possibility of step fracture caused by stress concentration and improving the reliability of the resulting light-emitting diode chip.

[0050] refer to Figure 3 It can be seen that in one implementation provided by the present disclosure, the orthographic projection arc 103 of the step 10 on the surface of the substrate 11 can be divided into a first portion 1031, a second portion 1032, and a third portion 1033. The first portion 1031, the second portion 1032, and the third portion 1033 each have a corresponding first arc segment 101 and a second arc segment 102. The radii of the first arc segment 101 and the second arc segment 102 corresponding to the first portion 1031, the second portion 1032, and the third portion 1033 can decrease successively. The reliability of the resulting light-emitting diode chip can be effectively increased.

[0051] Figure 4 The structural diagram of another light-emitting diode chip with reduced step fracture possibility provided by the embodiment of the present disclosure is shown in FIG. Figure 4It can be seen that in another implementation provided by the present disclosure, a light-emitting diode chip with reduced step fracture potential includes an epitaxial wafer 1, an n-electrode 2, and a p-electrode 3. The epitaxial wafer 1 may include a substrate 111 and a buffer layer 15 grown on the substrate 11, an undoped GaN layer 16, an n-type layer 12, a light-emitting layer 13, an AlGaN electron blocking layer 17, a p-type layer 14, and a p-type contact layer 18. The surface of the p-type layer 14 has a step 10 extending to the n-type layer 12. The n-electrode 2 is connected to the surface of the n-type layer 12 exposed by the step 10, and the p-electrode 3 is connected to the surface of the p-type layer 14.

[0052] In the direction from the surface of the n-type layer 12 to the p-type layer 14 , the maximum distance between the sidewall of the step 10 and the sidewall of the epitaxial wafer 1 gradually decreases, and the longitudinal cross-section of the sidewall of the step 10 is a curve. The curve includes a first arc segment 101 close to the p-type layer 14 and a second arc segment 102 away from the p-type layer 14 . One end of the first arc segment 101 is connected to and tangent to one end of the second arc segment 102 . The center of the circle corresponding to the first arc segment 101 is located inside the epitaxial wafer 1 , and the center of the circle corresponding to the second arc segment 102 is located outside the epitaxial wafer 1 .

[0053] It should be noted that Figure 4 The steps 10 shown in FIG. Figure 1 The structure of the step 10 shown in FIG is the same as that in FIG, and will not be described again here.

[0054] Optionally, the substrate 11 may be a sapphire substrate 11, which is easy to manufacture and obtain.

[0055] For example, the buffer layer 15 may be an AlN buffer layer 15 , which can ensure the crystal quality of the epitaxial thin film grown on the low-temperature buffer layer 15 .

[0056] Optionally, the buffer layer 15 may have a thickness of 10 to 30 nm, which can reduce the lattice mismatch between the n-type layer 12 and the substrate 11 and ensure the crystal quality of the epitaxial layer.

[0057] For example, the thickness of the non-doped GaN layer 16 may be 1 to 3.5 μm. The quality of the light emitting diode epitaxial wafer 1 obtained at this time is relatively good.

[0058] In an implementation provided by the present disclosure, the thickness of the undoped GaN layer 16 may also be 1 μm, which is not limited by the present disclosure.

[0059] Optionally, the doping element of the n-type layer 12 may be Si, and the doping concentration of the Si element may be 1×10 18 ~1×10 19 cm -3 The overall quality of the n-type layer 12 is good.

[0060] For example, the thickness of the n-type layer 12 may be 2-3 μm. The obtained n-type layer 12 has good overall quality.

[0061] In an implementation provided by the present disclosure, the thickness of the n-type layer 12 may be 2 μm, which is not limited by the present disclosure.

[0062] Optionally, the Al composition in the AlGaN electron blocking layer 17 may be 0.15-0.25, which has a better electron blocking effect.

[0063] Optionally, the p-type layer 14 may be doped with Mg, and the thickness of the p-type layer 14 may be Figure 1 The structure is the same as shown in , and will not be repeated here.

[0064] By way of example, the thickness of the p-type contact layer 18 may be 15 nm.

[0065] Exemplarily, both the n-electrode 2 and the p-electrode 3 can be prepared by including at least one of Gr, Ni, Al, Au and Pt materials.

[0066] It should be noted that Figure 4 The chip structure shown in Figure 1 The chip structure shown in FIG is more detailed. The resulting chip has improved quality and luminous efficiency. The n-type layer 12, p-type layer 14, and light-emitting layer 13 provided in this disclosure are primarily made of gallium nitride. In other implementations provided in this disclosure, the n-type layer 12, p-type layer 14, and light-emitting layer 13 may also be made of aluminum gallium nitride.

[0067] Figure 5 This is a flow chart of a light-emitting diode chip and a method for manufacturing the same, provided by an embodiment of the present disclosure, which reduces the possibility of step fracture. Figure 5 It can be seen that the embodiment of the present disclosure provides a method for preparing a light-emitting diode chip with reduced possibility of step fracture. The method for preparing a light-emitting diode chip with reduced possibility of step fracture includes:

[0068] S101: providing a substrate.

[0069] S102: Growing an n-type layer, a light-emitting layer, and a p-type layer in sequence on the substrate to obtain an epitaxial wafer.

[0070] S103: Prepare a step extending from the p-type layer to the n-type layer, in the direction from the surface of the n-type layer to the p-type layer, the maximum distance between the side wall of the step and the side wall of the epitaxial wafer gradually decreases, and the longitudinal section of the side wall of the step is a curve, the curve includes a first arc segment close to the p-type layer and a second arc segment away from the p-type layer, one end of the first arc segment is connected to and tangent to one end of the second arc segment, the center of the circle corresponding to the first arc segment is located inside the epitaxial wafer, and the center of the circle corresponding to the second arc segment is located outside the epitaxial wafer.

[0071] S104: forming a p-electrode on the surface of the p-type layer.

[0072] S105: forming an n-electrode on the surface of the n-type layer exposed by the step.

[0073] In a light-emitting diode chip, the maximum distance between the sidewall of a step and the sidewall of an epitaxial wafer gradually decreases in a direction from the surface of the n-type layer toward the p-type layer, and the longitudinal cross-section of the step sidewall is curved. This can increase the connection strength between the step and the n-type layer, reduce the possibility of the step breaking at the junction with the n-type layer, and improve the reliability of the light-emitting diode chip. It also ensures sufficient space on the n-type layer for the n-electrode. The longitudinal cross-section of the step sidewall is curved, and the curve includes a first arc segment close to the p-type layer and a second arc segment away from the p-type layer. One end of the first arc segment is connected to and tangent to one end of the second arc segment. The center of the circle corresponding to the first arc segment is located inside the epitaxial wafer, and the center of the circle corresponding to the second arc segment is located outside the epitaxial wafer. There is a connection and transition between the first arc segment and the second arc segment, and the curvature change directions of the first arc segment and the second arc segment are different, which can effectively avoid stress concentration and reduce the possibility of the light-emitting diode chip breaking due to stress concentration at the step; and the setting of the center of the first arc segment and the center of the second arc segment can also make the step relatively flat and the connection area larger near the connection position between the p-type layer and the n-type layer, the connection strength is large, and the tolerance to the vertical force is high, which can reduce the possibility of breakage.

[0074] The light emitting diode chip obtained after executing step S105 can be referred to Figures 1 to 3 The structure of the light-emitting diode chip shown in .

[0075] Optionally, in step S103 , preparing a step extending from the p-type layer to the n-type layer includes:

[0076] The p-type layer is coated with photoresist; the photoresist is sequentially exposed and developed to form a pattern on the photoresist and to form a first arc-shaped area and a second arc-shaped area connected to the sidewall of the photoresist; and a step extending to the n-type layer is etched in the p-type layer.

[0077] After coating the p-type layer with photoresist, a pattern can be formed on the photoresist through exposure and development processes, and the sidewalls of the photoresist can be formed into a first curved area and a second curved area connected to each other, so as to form a step with a certain slope in the subsequent etching process.

[0078] It should be noted that the first arc-shaped region and the second arc-shaped region correspond to the first arc-shaped line segment and the second arc-shaped line segment of the step obtained by etching, respectively.

[0079] Exposing the photoresist includes: using a curved laser to irradiate the photoresist to form a first arc-shaped area and a second arc-shaped area on the photoresist.

[0080] Controlling the laser during the exposure phase of the photoresist to change the shape of the photoresist can ensure that the shape of the obtained photoresist is more accurate, which is conducive to ensuring that the shape quality of the obtained step is better.

[0081] It should be noted that the photoresist has a certain shape. When the gas etches the epitaxial wafer, it will transfer the shape on the photoresist to the epitaxial wafer to form a step of the corresponding shape. In the present disclosure, if it is necessary to set the sidewalls of different parts of the photoresist to different shapes or slopes, this can be done by adjusting the laser angle of exposure for each part of the photoresist.

[0082] In this disclosure, it is necessary to form Figure 2 The shape corresponding to the middle step and the different slopes of the first, second, and third parts can be achieved by controlling the intensity of the curved laser in each part. In one implementation provided by the present disclosure, the intensities of the curved laser corresponding to the three parts can be 20W per second, 10W per second, and 5W per second, respectively.

[0083] In other implementations provided by the present disclosure, the pattern and shape of the photoresist finally obtained can also be controlled by controlling the coating step of the photoresist or controlling the development area of ​​the photoresist.

[0084] Optionally, preparing a step extending from the p-type layer to the n-type layer further includes:

[0085] After developing the photoresist, the photoresist is baked before etching the p-type layer to form a step extending to the n-type layer.

[0086] After development and before etching the p-type layer, the photoresist is baked to soften the photoresist to ensure a smoother surface, which is beneficial to improving the shape of the obtained photoresist and ensuring better quality of the final step.

[0087] Optionally, the photoresist is baked at a temperature of 120 to 130 degrees Celsius for 20 to 30 minutes.

[0088] Baking the photoresist under the above conditions can ensure that the obtained photoresist has good quality while effectively controlling the preparation cost of the photoresist.

[0089] Exemplarily, etching a step extending from the p-type layer to the n-type layer includes:

[0090] Etching is performed for a first time using a first gas at a power of 300-500W; etching is performed for a second time using a second gas at a power of 300-800W, and the second time is greater than the first time; etching is performed for a third time using a third gas at a power of 100-200W to obtain a step, and the third time is less than the first time.

[0091] The steps of etching the steps from the p-type layer are divided into a first stage, a second stage, and a third stage corresponding to the first, second, and third durations respectively, and the second duration is longer than the first duration, and the third duration is shorter than the first duration. This ensures that after the initial form of the steps is stably etched from the p-type layer with a relatively high power, a higher power is used to etch a longer and larger second portion of the steps, and finally a lower power third gas is used to etch the steps in the last stage. This ensures the connection quality and strength between the steps and the n-type layer, and ensures a stable transition between the steps and the n-type layer.

[0092] Optionally, the first gas and the second gas both include chlorine and bromine chloride, the third gas includes argon, the flow rate of the first gas is greater than the flow rate of the second gas, and the flow rate of the third gas is less than the flow rate of the second gas.

[0093] The composition and flow rates of the first, second, and third gases within the above ranges can ensure the etching efficiency and size of the step between the n-type layer and the p-type layer, while also ensuring a stable transition between the step and the n-type layer. This also avoids excessively increasing the production cost of the LED chip.

[0094] For example, the flow rates of chlorine and bromine chloride in the first gas can be 30-60 sccm and 10-30 sccm, respectively, and the flow rates of chlorine and bromine chloride in the second gas can be 20-40 sccm and 20-40 sccm, respectively. This ensures the quality of the resulting steps while effectively controlling the production cost of the LED chip.

[0095] In other implementations provided by the present disclosure, the first gas and the second gas may both include chlorine, and the third gas may include argon, and the present disclosure does not impose any limitation on this.

[0096] Figure 6 This is another light-emitting diode chip and its manufacturing method flow chart for reducing the possibility of step fracture provided by the embodiment of the present disclosure. Figure 6 It can be seen that the light-emitting diode chip and its manufacturing method for reducing the possibility of step fracture may include:

[0097] S201: providing a substrate.

[0098] The substrate can be a sapphire substrate, which is easy to implement and manufacture.

[0099] Optionally, step S201 may further include: treating the surface of the substrate for growing the epitaxial layer in a hydrogen atmosphere for 5 to 6 minutes.

[0100] For example, when processing the surface of the substrate for growing the epitaxial layer, the temperature of the reaction chamber may be 1000-1100° C., and the pressure of the reaction chamber may be 200-500 Torr.

[0101] S202: growing a buffer layer on the substrate.

[0102] The buffer layer may be an AlN buffer layer. The AlN layer may be obtained by magnetron sputtering.

[0103] For example, the deposition temperature of the AlN layer may be 400-800° C., the sputtering power may be 3000-5000 W, and the pressure may be 2-20 mtorr. The quality of the obtained AlN layer is good.

[0104] S203: growing a non-doped GaN layer on the buffer layer.

[0105] The thickness of the undoped GaN layer may be 0.5 to 3 μm.

[0106] For example, the growth temperature of the undoped GaN layer may be 1000-1100° C., and the growth pressure may be controlled at 100-300 Torr. The quality of the undoped GaN layer obtained is good.

[0107] S204: growing an n-type layer on the non-doped GaN layer.

[0108] Optionally, the n-type layer may be an n-type layer, the growth temperature of the n-type layer may be 1000-1100° C., and the growth pressure of the n-type layer may be 100-300 Torr.

[0109] Optionally, the thickness of the n-type layer may be 0.5-3 μm.

[0110] S205: growing a multi-quantum well layer on the n-type layer.

[0111] It should be noted that the growth conditions, growth method and structure of the multi-quantum well layer in step S205 are similar to those in step S206. Figure 5 The growth conditions, growth method and structure of the multi-quantum well layer in step S103 are the same as those in step S104. Detailed description will not be given here.

[0112] S206: growing an AlGaN electron blocking layer on the multi-quantum well layer.

[0113] The AlGaN electron blocking layer can be grown at a temperature of 800-1000°C and a pressure of 100-300 Torr. The AlGaN electron blocking layer grown under these conditions has good quality, which is beneficial for improving the luminous efficiency of the light-emitting diode.

[0114] S207: growing a p-type layer on the AlGaN electron blocking layer.

[0115] Optionally, the growth pressure of the p-type layer may be 200-600 Torr, and the growth temperature of the p-type layer may be 800-1000°C.

[0116] S208: growing a p-type contact layer on the p-type layer.

[0117] Optionally, the growth pressure of the p-type contact layer may be 100-300 Torr, and the growth temperature of the p-type contact layer may be 800-1000°C.

[0118] S209: preparing a step on the p-type contact layer extending to the n-type layer.

[0119] Step S209 can refer to Figure 5 The step S103 shown in FIG is omitted for brevity.

[0120] S210: preparing a p-electrode on the p-type layer, and preparing an n-electrode on the surface of the n-type layer exposed by the step.

[0121] Both the p-electrode and the n-electrode can be obtained by evaporation or sputtering.

[0122] It should be noted that Figure 6 The method for preparing the light emitting diode epitaxial wafer shown in Figure 5 The light-emitting diode preparation method shown in provides a more detailed growth method of light-emitting diode epitaxial wafers.

[0123] The structure of the light emitting diode epitaxial wafer after executing step S208 can be seen in Figure 4 .

[0124] It should be noted that in the embodiments of the present disclosure, a Veeco K465ior C4or RBMOCVD (Metal Organic Chemical Vapor Deposition) device is used to realize the growth method of the light-emitting diode. High-purity H2 (hydrogen) or high-purity N2 (nitrogen) or a mixture of high-purity H2 and high-purity N2 is used as the carrier gas, high-purity NH3 is used as the N source, trimethylgallium (TMGa) and triethylgallium (TEGa) are used as the gallium source, trimethylindium (TMIn) is used as the indium source, silane (SiH4) is used as the N-type dopant, trimethylaluminum (TMAl) is used as the aluminum source, and bis(cyclopentadienyl)magnesium (CP2Mg) is used as the P-type dopant.

[0125] The above description does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not intended to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments with equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure are still within the scope of the technical solution of the present disclosure.

Claims

1. A light-emitting diode chip with reduced step fracture potential, the light-emitting diode chip comprising an epitaxial wafer, an n-electrode, and a p-electrode, the epitaxial wafer comprising a substrate and an n-type layer, a light-emitting layer, and a p-type layer sequentially stacked on the substrate, the surface of the p-type layer having a step extending to the n-type layer, the n-electrode being electrically connected to the surface of the n-type layer exposed by the step, and the p-electrode being electrically connected to the surface of the p-type layer, characterized in that: In the direction from the surface of the n-type layer to the p-type layer, the maximum distance between the side wall of the step and the side wall of the epitaxial wafer gradually decreases, and the longitudinal section of the side wall of the step is a curve, the curve including a first arc-shaped line segment close to the p-type layer and a second arc-shaped line segment away from the p-type layer, one end of the first arc-shaped line segment is connected to and tangent to one end of the second arc-shaped line segment, the center of a circle corresponding to the first arc-shaped line segment is located inside the epitaxial wafer, and the center of a circle corresponding to the second arc-shaped line segment is located outside the epitaxial wafer.

2. The light-emitting diode chip with reduced step fracture potential according to claim 1, characterized in that: The radius corresponding to the second arc segment is greater than the radius corresponding to the first arc segment, and the length of the second arc segment is greater than the length of the first arc segment.

3. The light-emitting diode chip with reduced step fracture possibility according to claim 1 or 2, characterized in that: The projection of the epitaxial wafer on the surface of the substrate is a rectangle, the projection of the side wall of the step on the surface of the substrate is an arc, and both ends of the arc are tangent to two adjacent sides of the rectangle.

4. The light-emitting diode chip with reduced step fracture possibility according to claim 3, characterized in that: The smaller the distance between the sidewall of the step and the p-electrode, the larger the radius and length corresponding to the first arc-shaped line segment and the radius and length corresponding to the second arc-shaped line segment.

5. A method for preparing a light-emitting diode chip with reduced possibility of step fracture, characterized in that: The method for preparing a light-emitting diode chip with reduced possibility of step fracture comprises: providing a substrate; sequentially growing an n-type layer, a light-emitting layer, and a p-type layer on the substrate to obtain an epitaxial wafer; A step is formed extending from the p-type layer to the n-type layer, wherein the maximum distance between the sidewall of the step and the sidewall of the epitaxial wafer gradually decreases in a direction from the surface of the n-type layer toward the p-type layer, and the longitudinal cross-section of the sidewall of the step is a curve, wherein the curve includes a first arc segment close to the p-type layer and a second arc segment away from the p-type layer, wherein one end of the first arc segment is connected to and tangent to one end of the second arc segment, the center of a circle corresponding to the first arc segment is located within the epitaxial wafer, and the center of a circle corresponding to the second arc segment is located outside the epitaxial wafer; forming a p-electrode on a surface of the p-type layer; An n-electrode is formed on a surface of the n-type layer exposed by the step.

6. The method for preparing a light-emitting diode chip with reduced step fracture potential according to claim 5, characterized in that: The step of preparing the step extending from the p-type layer to the n-type layer comprises: coating a photoresist on the surface of the p-type layer; sequentially exposing and developing the photoresist to form a pattern on the photoresist and forming a first arc-shaped region and a second arc-shaped region connected to each other on a sidewall of the photoresist; A step extending to the n-type layer is etched in the p-type layer.

7. The method for preparing a light-emitting diode chip with reduced step fracture potential according to claim 6, characterized in that: The step of preparing the step extending from the p-type layer to the n-type layer further includes: After developing the photoresist, the photoresist is baked before etching the p-type layer to form a step extending to the n-type layer.

8. The method for preparing a light-emitting diode chip with reduced step fracture potential according to claim 7, characterized in that: The photoresist is baked at a temperature of 120 to 130 degrees Celsius for 20 to 30 minutes.

9. The method for preparing a light emitting diode chip with reduced step fracture potential according to any one of claims 6 to 8, characterized in that: The step of etching the p-type layer to form a step extending to the n-type layer comprises: Etching for a first time using a first gas at a power of 300-500W; Etching with a second gas for a second time period at a power of 300-800 W, wherein the second time period is greater than the first time period; The step is obtained by etching with a third gas for a third time under a power of 100-200 W, wherein the third time is shorter than the first time.

10. The method for preparing a light emitting diode chip with reduced step fracture potential according to claim 9, characterized in that: The first gas and the second gas both include chlorine and bromine chloride, the third gas includes argon, the flow rate of the first gas is greater than the flow rate of the second gas, and the flow rate of the third gas is less than the flow rate of the second gas.

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