An iron domain wall stress deformation memory and a preparation method thereof

Abstract

The application discloses a ferroelastic domain wall stress deformation memory and a preparation method thereof. The memory comprises a substrate, a ferroelectric layer and an electrode layer. The memory utilizes the clamping stress generated by the lattice mismatch between the ferroelectric layer and the substrate to make the ferroelastic domain wall in the ferroelectric layer generate stress deformation, thereby forming a "0" and "1" switch, realizing fast and stable storage and reading of data. The preparation method of the memory provided by the application utilizes a semiconductor preparation process to prepare the ferroelectric layer and the electrode layer on the (001) surface of the substrate by adopting a pulse laser deposition method. The method is simple in process, high in precision, effectively guarantees the yield of products, and can realize large-scale industrial production of the memory.

Description

TECHNICAL FIELD

[0001] The application relates to a micro memory, in particular to a ferroelectric domain wall stress deformation memory and a preparation method thereof, and belongs to the information storage field. BACKGROUND

[0002] Memory is an important part of electronic systems. The rapid development of information technology has increased the demand for high-density, high-speed, low-power non-volatile memory, which has forced people to seek alternative disruptive technologies. Ferroelectric memory is a new type of non-volatile memory with great application prospects. According to the structure of the storage unit of the device, it can be roughly divided into two categories: 1T / 1C and 1T (T represents a transistor, and C represents a capacitor). Both have the advantages of fast information reading speed and non-volatility, but the former has a small storage density and destructive readout, and the latter has poor data retention. The new scientific field of "domain wall nanoelectronics" regards the conductive ferroelectric domain wall (the interface between different polarization regions in ferroelectric materials) as a new way of information storage, that is, through the "introduction" and "removal" of the conductive ferroelectric domain wall in the storage unit to generate readable and writable data states, and the concept of ferroelectric domain wall memory is born. Compared with the current commercial non-volatile ferroelectric memory based on the flip of ferroelectric domains (regions with consistent polarization orientation), the ferroelectric domain wall memory has the characteristic of non-destructive readout. Compared with the ferromagnetic domain wall, the size of the ferroelectric domain wall is usually one to two orders of magnitude smaller, so the ferroelectric domain wall memory has higher storage density, higher read-write speed and lower energy consumption than the ferromagnetic domain wall memory. Compared with electronic devices based on the interface of heterogeneous materials, the position and size of the conductive ferroelectric domain wall can be controlled by an external field, so the design of the ferroelectric domain wall memory device is more flexible.

[0003] The conductive ferroelectric domain wall is the core of the ferroelectric domain wall memory, and the conductivity, stability without external field and mobility under external field of the conductive ferroelectric domain wall are the basic conditions for the application of the ferroelectric domain wall memory. The better the conductivity of the conductive ferroelectric domain wall is, the higher the on-off ratio of the electric conductance of the storage unit when the domain wall is "introduced" and "removed" is, and the data is easier to be read; the better the stability of the conductive ferroelectric domain wall without external field is, the smaller the fluctuation of the stored data is, and the higher the retention is; the better the mobility under external field is, the easier the data writing / erasing is, and the lower the power consumption is. The strong charged ferroelectric domain wall in the ferroelectric body, i.e. the domain wall formed in the "head-to-head" or "tail-to-tail" direction of the polarization direction, exhibits high conductivity due to the aggregation of the electric charge, and is often used for the development of the ferroelectric domain wall memory. However, the formation of the strong charged ferroelectric domain wall in the conventional ferroelectric body (such as BiFeO3) requires a high formation energy, and is difficult to exist stably. The strong charged ferroelectric domain wall in the unconventional ferroelectric body (such as the hexagonal hydrohausmannite ferroelectric body) exhibits good conductivity and stability, but the domain wall is almost immovable due to the topological protection. It can be seen that the development of the ferroelectric domain wall with good mobility, excellent conductivity and stability has important significance for promoting the development of the ferroelectric domain wall memory. SUMMARY

[0004] In view of the problems in the prior art, a first object of the present application is to provide a ferroelastic domain wall stress deformation memory based on the clamping stress generated by the lattice mismatch between the ferroelectric layer and the substrate, so that the ferroelastic domain wall in the ferroelectric layer produces stress deformation, thereby forming "0" and "1" switches to realize the storage and reading of data. The memory has the advantages of high stability, large information storage density and low power consumption, and has a wide application in the field of mobile storage.

[0005] A second object of the present application is to provide a preparation method of the ferroelastic domain wall stress deformation memory, which has simple process, high precision and effectively guarantees the yield of the product, and can realize the large-scale industrial production of the above-mentioned memory.

[0006] To achieve the above technical purposes, the application provides a ferroelastic domain wall stress deformation memory, which comprises a substrate, a ferroelectric layer and an electrode layer; when the lattice constant of the ferroelectric layer is 0.389 nm<=a=b<=0.392 nm and c is 0.414-0.416 nm, the lattice constant of the substrate is 0.389 nm<=a=b<=0.391 nm and c is 0.413-0.415 nm; when the lattice constant of the ferroelectric layer is 0.393 nm<=a=b<=0.396 nm and c is 0.410-0.419 nm, the lattice constant of the substrate is 0.389 nm<=a=b<=0.391 nm and c is 0.413-0.415 nm; when the lattice constant of the ferroelectric layer is a is 0.199-0.201 nm, b is 0.184-0.189 nm and c is 0.216-0.218 nm, the lattice constant of the substrate is a is 0.199-0.20 nm, b is 0.185-0.186 nm and c is 0.216-0.217 nm.

[0007] The application utilizes the lattice mismatch between the substrate and the ferroelectric layer to induce clamping stress, so that the ferroelastic domain wall in the ferroelectric layer is deformed to present a bending shape, and further, the ferroelectric domain wall will produce different shrinkage or expansion deformation under the action of an applied electric field, thereby forming a "0" and "1" switch to realize information storage and reading.

[0008] As a preferred scheme, the ferroelectric layer contains a ferroelastic domain wall.

[0009] As a preferred scheme, the electrode layer is a single electrode layer or a double electrode layer; the double electrode layer comprises a bottom electrode layer and a top electrode layer.

[0010] As a preferred scheme, when the electrode layer is a single electrode layer, the substrate, the ferroelectric layer and the electrode layer are stacked from bottom to top, and the electrode layer is spaced and parallelly distributed on the upper surface of the ferroelectric layer at both ends.

[0011] As a preferred scheme, when the electrode layer is a double electrode layer, the substrate, the bottom electrode layer, the ferroelectric layer and the top electrode layer are stacked from bottom to top.

[0012] As a preferred scheme, the stress deformation range of the ferroelastic domain wall under an applied electric field is-0.01-0.32%, and the applied electric field does not exceed the c-domain coercive electric field value. If the stress deformation exceeds the range or the external electric field strength exceeds the coercive electric field strength, the ferroelastic domain wall will disappear, and the original c-a-c domain structure will change into a single c domain.

[0013] As a preferred scheme, the substrate is one of SrTiO3, DyScO3, GdScO3 and LaAlO3.

[0014] As a preferred embodiment, the ferroelectric layer is one of lead titanate, lead zirconate titanate, and barium titanate.

[0015] As a preferred embodiment, the single electrode layer material is at least one of Au, Pt, and Ag.

[0016] As a preferred embodiment, the top electrode layer material is at least one of Au, Pt, and Ag.

[0017] As a preferred embodiment, the bottom electrode layer material is at least one of SrRuO3, Pt, and LiNbO3.

[0018] As a preferred embodiment, when the ferroelectric layer is lead titanate, its lattice constants are a = b = 0.39045 nm and c = 0.41524 nm, and the corresponding substrate lattice constant ranges are 0.38917 nm ≤ a = b ≤ 0.39006 nm and 0.41387 nm ≤ c ≤ 0.41483 nm.

[0019] As a preferred embodiment, when the ferroelectric layer is lead zirconate titanate, its lattice constants a = b = 0.395 nm and c = 0.413 nm, and the corresponding substrate lattice constant ranges are 0.39370 nm ≤ a = b ≤ 0.39461 nm and 0.41164 nm ≤ c ≤ 0.41259 nm.

[0020] As a preferred embodiment, when the ferroelectric layer is barium titanate, its lattice constants are a = 0.2 nm, b = 0.186 nm, and c = 0.217 nm. The corresponding lattice constant ranges of the substrate are 0.19934 nm ≤ a ≤ 0.19980 nm, 0.18539 nm ≤ b ≤ 0.18581 nm, and 0.21629 nm ≤ c ≤ 0.21678 nm.

[0021] This invention calculates the lattice constant of the substrate by using the compressive strain range of the ferroelastic domain walls and the lattice constant of the ferroelectric layer. The calculation formula is as follows:

[0022]

[0023] In the formula: a represents the compressive strain caused by lattice mismatch, which is dimensionless; s denoted as , where is the lattice constant of the substrate, with dimensions in nm; a f is the lattice constant of the ferroelectric layer, with dimensions in nm.

[0024] This invention also provides a method for fabricating a ferroelastic domain wall stress deformation memory, comprising the following steps:

[0025] 1) after the silver paste is solidified on the (001) surface of the substrate, a ferroelectric layer and an electrode layer are prepared in sequence by using the pulse laser deposition method, and thus the memory is obtained;

[0026] 2) after the silver paste is solidified on the (001) surface of the substrate, a bottom electrode layer, a ferroelectric layer and a top electrode layer are prepared in sequence by using the pulse laser deposition method, and thus the memory is obtained.

[0027] Before the pulse laser deposition treatment is performed, the silver paste is solidified on the (001) surface of the substrate, and the purpose of solidifying the silver paste is to fix the substrate and prevent the substrate from falling off in the subsequent work. In the preparation process, the substrate is completely inverted, and if the silver paste is not completely solidified in advance, the substrate will have the risk of falling into the deposition cavity.

[0028] As a preferred scheme, the solidification temperature of the silver paste is 70-90℃.

[0029] As a preferred scheme, the thickness of the ferroelectric layer is 100-150nm.

[0030] As a preferred scheme, the conditions of the pulse laser deposition method are as follows: the constant oxygen partial pressure is 150-250mTorr, the deposition temperature is 550-650℃, and the laser energy density is 250-350mJ.

[0031] Further, the application also provides a detailed preparation method of the memory, comprising the following steps: 1) the substrate is cleaned by using anhydrous ethanol, and then the cleaned substrate is adhered to the (001) surface of the substrate by using liquid silver paste, and placed on a heating table until the silver paste is solidified; 2) the room temperature is adjusted to 23-26℃, the sample chamber and the epitaxial chamber of the molecular laser are vacuumized, and the laser is preheated; 3) after the laser is preheated, nitrogen is filled into the sample chamber and the epitaxial chamber under reduced pressure, the substrate and the target material are placed in the chambers, and then the chambers are vacuumized again, and the temperature is uniformly increased to the reaction temperature; 4) when the molecular laser reaches the reaction temperature, oxygen is introduced, the laser is turned on to start the deposition, and after the deposition is completed, the oxygen is turned off, and the temperature is uniformly decreased to room temperature, and thus the memory is obtained.

[0032] As a preferred scheme, the uniform heating rate is 40-60℃ / min, and the uniform cooling rate is selected to be 20-30℃ / min.

[0033] As a preferred scheme, the reaction temperature is 600℃.

[0034] As a preferred scheme, the conditions of the laser deposition are as follows: the wavelength of the output laser is 248nm, the pulse width is 20nm, the working gas is KeF, the laser energy density is 300mJ, the laser frequency is 10Hz, and the focusing mirror position is 10cm.

[0035] The main mechanism of the memory of the present application is that strain will be generated in the heteroepitaxial film with mismatch degree, and the strain is different with the mismatch degree. Generally, if the mismatch degree is zero, that is, the lattice of the epitaxial film is completely matched with the substrate, no strain will be generated in the epitaxial film; if the mismatch degree is not zero, the lattice constant of the film is different from that of the substrate, in order to maintain the coherent growth relationship between the film atoms and the substrate atoms, the epitaxial film will generate tensile (or compressive) strain in the vertical interface and parallel interface direction. The thickness of the substrate is often much larger than the thickness of the film, so the strain is only concentrated in the film, and the strain of the substrate can be ignored. Therefore, the substrate with different lattice constants will exert different epitaxial strains in the film, which will generate a force between the interface of the substrate and the film, so as to make the lattice size of the film and the substrate match. This force is called clamping stress, which will make the ferroelectric domain wall at the interface of the film and the substrate bend, and free charges will accumulate near the bent ferroelectric domain wall, so that the bent ferroelectric domain wall has good metal conductivity. When an electric field is applied to the ferroelectric domain wall, the deformation state of the ferroelectric domain wall will change, and stretching or contraction in the in-plane direction or out-of-plane direction will be generated, thereby forming "0" and "1" switches to realize data storage and reading. This storage mode determines that the memory has lower power consumption, and the bending of the ferroelectric domain wall generated by the lattice mismatch is more stable, and the data retention is also higher, effectively avoiding the crosstalk problem of adjacent storage units, further improving the information storage density.

[0036] Compared with the prior art, the technical scheme of the present application has the following beneficial technical effects:

[0037] 1) The memory provided by the present application utilizes the clamping stress generated between the ferroelectric layer and the substrate due to the lattice mismatch to make the ferroelectric domain wall in the ferroelectric layer deform under stress, thereby forming "0" and "1" switches to realize data storage and reading. The memory not only has good stability, but also has excellent conductivity, and can realize fast and stable storage and reading of data.

[0038] 2) In the technical scheme provided by the present application, the electrodes of the storage unit are connected / disconnected by the stretching / contraction of the ferroelectric domain wall, thereby obtaining high / low conductive states. The switching ratio of the memory obtained by the technical scheme provided by the present application is greater than 100, and the size of the information storage unit is about 4 nm.

[0039] 3) In the technical scheme provided by the present application, the ferroelectric layer and the electrode layer are prepared on the (001) surface of the substrate by using the pulse laser deposition method. The method is simple in process, high in precision, and can effectively ensure the yield of the product, so that large-scale industrial production of the above-mentioned memory can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1(a) and (d) are structural schematic diagrams of ferroelectric domain wall memory; (b-c) are in-plane expansion and contraction schematic diagrams of curved ferroelastic domain wall in ferroelectric domain wall memory; (e-f) are out-of-plane expansion and contraction schematic diagrams of curved ferroelastic domain wall in ferroelectric domain wall memory.

[0041] Figure 2 is an in-plane expansion and contraction schematic diagram of curved ferroelastic domain wall in lead zirconate titanate ferroelectric thin film.

[0042] Figure 3 (a) is a table of length change of curved ferroelastic domain wall in lead zirconate titanate ferroelectric thin film under cyclic voltage (unit: nm); (b) is an evolution process schematic diagram of curved ferroelastic domain wall in lead zirconate titanate ferroelectric thin film under cyclic voltage.

[0043] Figure 4 is an out-of-plane expansion and contraction schematic diagram of curved ferroelastic domain wall in lead titanate ferroelectric thin film.

[0044] Figure 5 is a structural schematic diagram of ferroelastic domain wall in lead titanate ferroelectric thin film under tensile stress.

[0045] Figure 6 is a domain structure schematic diagram of lead titanate ferroelectric thin film when the compressive strain is -0.33%.

[0046] Figure 7 is a domain structure schematic diagram of lead titanate ferroelectric thin film when the voltage is greater than the c-domain coercive voltage thereof. DETAILED DESCRIPTION

[0047] In order to make the purpose, advantages and basic flow of the present application clearer, the present application will be described in detail below in combination with examples, comparative examples and drawings.

[0048] Example 1

[0049] Au / Pb(Zr 0.2 Ti 0.8 )O3 / SrTiO3-based ferroelectric domain wall memory, the structure is shown in (a). Figure 1

[0050] From top to bottom, they are Au electrode layer, Pb(Zr 0.2 Ti 0.8 )O3 ferroelectric thin film layer, SrTiO3 substrate layer. The lattice constant of the selected (001)-SrTiO3 substrate is a=b=0.39370 nm, c=0.41164 nm. First, use anhydrous ethanol to clean, then use liquid silver paste to stick to the surface of the cleaned iron sheet, and place it on the heating table at 80°C until the silver paste solidifies; then on the (001)-SrTiO3 single crystal substrate, a (001)-Pb(Zr 0.2 Ti​0.8 )O3 thin film, the experimental process: the air conditioner is adjusted to room temperature 25 degrees, the two molecular pumps of the sample chamber and the epitaxial chamber are operated at full speed (820 and 1500 respectively), vacuumizing, laser preheating for 8 minutes, filling nitrogen to adjust the pressure reducing valve to 0.5 atmosphere, vacuumizing after putting the target material, putting the substrate, the heating rate is selected to be 50 degrees per minute; the cooling rate is selected to be 25 degrees per minute, after reaching the set temperature (600℃), oxygen is opened, the laser is started to deposit, after the deposition time is over, oxygen is closed, and the temperature is cooled to 30℃; the experimental parameters: constant oxygen partial pressure (100mTorr), temperature (600℃), the laser is a Compex Pro 205 type excimer laser produced by the United States Coherent company, the output laser wavelength is 248nm, the pulse width is 20nm, the working gas is KeF, the laser energy density is (300mJ), the laser frequency is (10Hz), and the focusing mirror position is (10cm); the Au probe (diameter 10nm) of the conductive atomic force microscope (C-AFM) is selected as the top electrode, and finally the Au / Pb(Zr 0.2 Ti 0.8 )O3 / SrTiO3 structure ferroelectric domain wall memory. The bending ferroelastic domain wall in the Pb(Zr 0.2 Ti 0.8 )O3 ferroelectric thin film is stretched along the in-plane direction to realize data storage, and the schematic diagram of the principle is shown in Figure 1 (b-c). Since the lattice constant of SrTiO3 is a=b=0.39370nm, c=0.41164nm, and the lattice constant of Pb(Zr 0.2 Ti 0.8 )O3 is a=b=0.395nm, c=0.413nm, the Pb(Zr 0.2 Ti 0.8 )O3 ferroelectric thin film is subjected to compressive strain, and the bending ferroelastic domain wall is obtained in the (001)-PZT thin film. The bending ferroelastic domain wall is shortened along the in-plane under the action of an electric field of-5V and-6V (the voltage does not exceed the coercive voltage of the Pb(Zr 0.2 Ti 0.8 )O3 ferroelectric thin film), and is shortened along the in-plane under the action of an electric field of 3V and 4V (the voltage does not exceed the coercive voltage of the Pb(Zr 0.2 Ti 0.8 )O3 ferroelectric thin film), as shown in Figure 2 . In the ferroelectric domain wall memory, the resistance between the two electrodes containing the bending ferroelastic domain wall exhibits distinguishable high and low values, which are used to store data "0" and "1", and the information storage density of a single storage unit is 125bit / μm 2 . By comparing with Pb(Zr 0.2 Ti 0.8)O3 ferroelectric thin film, the bending ferroelastic domain wall can be stretched and contracted at a smaller coercive voltage, and then the data storage is realized. It can be seen that the power consumption of the memory is lower. After a certain state of the ferroelectric domain wall memory is left for more than 72 hours, the domain structure of the region is scanned again with the same parameters, and it is found that the domain structure has no change, and the ferroelastic domain can be stably contracted under the cyclic voltage, as shown in Figure 3 , it can be seen that the memory has good data retention.

[0051] Example 2

[0052] Au / PbTiO3 / SrRuO3 / SrTiO3-based ferroelectric domain wall memory, as shown in Figure 1 (d). From top to bottom, they are Au top electrode layer, PbTiO3 ferroelectric thin film layer, SrRuO3 bottom electrode layer, and SrTiO3 substrate layer. The lattice constant of the selected (001)-SrTiO3 substrate is a=b=0.38936 nm, c=0.41408 nm. First, use anhydrous ethanol to clean, then use liquid silver paste to stick to the surface of the cleaned iron sheet, and place it on the 80°C heating table until the silver paste solidifies; on the (001)-SrTiO3 single crystal substrate, use pulsed laser deposition method to prepare SrRuO3 with a thickness of 19 nm; then on the (001)-SrTiO3 single crystal substrate, use pulsed laser deposition method to prepare (001)-PTO thin film with a thickness of 145 nm, the experimental process: adjust the air conditioner to room temperature 25 degrees, run the two molecular pumps in the sample chamber and epitaxial chamber at full speed (820 and 1500 respectively), vacuumize, preheat the laser for 8 minutes, fill nitrogen to adjust the pressure valve to 0.5 atmosphere, vacuumize after putting in the target material, put in the substrate, select the heating rate of 50 degrees per minute; the cooling rate is selected to be 25 degrees per minute, and the oxygen is opened after reaching the set temperature (600°C); start deposition by opening the laser, and after the deposition time is over, close the oxygen and cool to 30°C; experimental parameters: constant oxygen partial pressure (200 mTorr), temperature (600°C), laser is Compex Pro 205 type excimer laser produced by American Coherent company, output laser wavelength is 248 nm, pulse width is 20 nm, working gas is KeF, laser energy density (300 mJ), laser frequency (10 Hz), focusing mirror position (10 cm); finally, use conductive atomic force microscope (C-AFM) Au probe (diameter 10 nm) as the top electrode, and finally get Au / PbTiO3 / SrRuO3 / SrTiO3 structure ferroelectric domain wall memory. The bending ferroelastic domain wall in the PbTiO3 ferroelectric thin film is stretched and contracted in the out-of-plane direction to realize data storage, and the schematic diagram of the principle is as shown in Figure 1(e-f) shown. Since the lattice constant of SrTiO3 is a = b = 0.38936 nm, c = 0.41408 nm, and the lattice constant of PbTiO3 is a = b = 0.39045 nm, c = 0.41524 nm, the PbTiO3 ferroelectric thin film is subjected to compressive strain, and a curved ferroelastic domain wall is obtained in the PbTiO3 ferroelectric thin film, as shown in Figure 4 Fig. 2 (black arrows in the figure represent the polarization direction). When a loading electric field (voltage does not exceed the coercive voltage of PbTiO3) is applied, the curved ferroelastic domain wall undergoes expansion and contraction movement in the out-of-plane direction, as shown in Figure 4 Fig. 3 (black arrows in the figure represent the polarization direction), the resistance between the Au and SrRuO3 electrodes shows distinguishable high and low values with the expansion and contraction of the domain wall, which is used to store data "0" and "1", and the information storage density of a single storage unit is 125 bit / μm 2 . And the domain structure in a certain state is continuously evolved in time, and it is found that the domain structure does not change at all, which shows that the a domain state after applying an electric field can exist stably, and it is stable in energy, and the data can be stored for a long time.

[0053] Comparative Example 1

[0054] The Au / PbTiO3 / SrRuO3 / SrTiO3-based ferroelectric domain wall memory has the same structure and preparation process as Example 2. The difference lies in that there is a 0.8° bevel angle on the surface of the (001)-SrTiO3 single crystal substrate, so that the PbTiO3 ferroelectric thin film is subjected to tensile strain. The ferroelastic domain wall in the PbTiO3 ferroelectric thin film does not bend, as shown in Figure 5 Fig. 4 (black arrows in the figure represent the polarization direction), the conductivity is poor, and the "0" and "1" of the ferroelectric domain wall memory containing the domain wall are not easy to distinguish, and the data cannot be stably stored and read.

[0055] Comparative Example 2

[0056] The Au / PbTiO3 / SrRuO3 / SrTiO3-based ferroelectric domain wall memory has the same structure and preparation process as Example 2. The difference lies in that the PbTiO3 ferroelectric thin film is subjected to a compressive strain of -0.33%, and the domain structure is as shown in Figure 6 Fig. 5 (black arrows in the figure represent the polarization direction). It can be seen that when the compressive strain is -0.33%, the domain wall completely disappears, and the conductivity is poor, and the ferroelectric domain wall memory under this strain cannot write data "0" and "1".

[0057] Comparative Example 3

[0058] Au / PbTiO3 / SrRuO3 / SrTiO3-based ferroelectric domain wall memory with the same structure and fabrication process as in Example 2. The PbTiO3 ferroelectric film was subjected to a compressive strain of -0.28%. The difference is that when the applied electric field exceeds the coercive field of PbTiO3, the region has no curved ferroelastic domain wall, no obvious electrical conductivity, and the ferroelectric domain wall memory fails, with the domain structure as shown in Figure 7 ​

Claims

1. A ferroelastic domain wall stress deformation memory, characterized in that: Includes a substrate, a ferroelectric layer, and an electrode layer; When the lattice constant of the ferroelectric layer is 0.389nm≤a=b≤0.392nm and c is 0.414~0.416nm, the lattice constant of the substrate is 0.389nm≤a=b≤0.391nm and c is 0.413~0.415nm. When the lattice constant of the ferroelectric layer is 0.393 nm ≤ a = b ≤ 0.396 nm and c is 0.410~0.419 nm, the lattice constant of the substrate is 0.389 nm ≤ a = b ≤ 0.391 nm and c is 0.413~0.415 nm. The ferroelectric layer contains ferroelastic domain walls; the stress deformation range of the ferroelastic domain walls under an applied electric field is -0.01 to -0.32%, and the applied electric field does not exceed the coercive electric field value of the c-domain; The substrate is one of SrTiO3, DyScO3, GdScO3 and LaAlO3; The ferroelectric layer is one of lead titanate, lead zirconate titanate, and barium titanate.

2. The ferroelastic domain wall stress deformation memory according to claim 1, characterized in that: The electrode layer is a single electrode layer or a double electrode layer; the double electrode layer includes a bottom electrode layer and a top electrode layer.

3. The ferroelastic domain wall stress deformation memory according to claim 2, characterized in that: When the electrode layer is a single electrode layer, the substrate, ferroelectric layer and electrode layer are stacked sequentially from bottom to top, and the electrode layers are distributed parallel to each other at both ends of the upper surface of the ferroelectric layer.

4. A ferroelastic domain wall stress deformation memory according to claim 2, characterized in that: When the electrode layer is a dual electrode layer, the substrate, bottom electrode layer, ferroelectric layer and top electrode layer are stacked sequentially from bottom to top.

5. A ferroelastic domain wall stress deformation memory according to claim 2, characterized in that: The single electrode layer material is at least one of Au, Pt, and Ag; The top electrode layer material is at least one of Au, Pt, and Ag; The bottom electrode layer material is at least one of SrRuO3, Pt and LiNbO3.

6. A method for fabricating a ferroelastic domain wall stress deformation memory according to any one of claims 1 to 5, characterized in that: Including method A or method B: Method A: After solidifying silver paste on the (001) surface of the substrate, a ferroelectric layer and an electrode layer are prepared sequentially using pulsed laser deposition to obtain the desired result; Method B: After solidifying silver paste on the substrate (001) surface, the bottom electrode layer, ferroelectric layer and top electrode layer are prepared sequentially by pulsed laser deposition.

7. The method for fabricating a ferroelastic domain wall stress deformation memory according to claim 6, characterized in that: The solidification temperature of the silver paste is 70~90℃; the thickness of the ferroelectric layer is 100~150nm.

8. The method for fabricating a ferroelastic domain wall stress deformation memory according to claim 6, characterized in that: The conditions for the pulsed laser deposition method are: constant oxygen partial pressure of 150~250 mTorr, deposition temperature of 550~650℃, and laser energy density of 250~350 mJ.

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