Repair circuit of electrical connection structure and control method thereof

Abstract

The present disclosure provides a repair circuit of an electrical connection structure and a control method thereof. The repair circuit of the electrical connection structure comprises an electrical connection module, M first data terminals, M second data terminals, a first control circuit module and a second control circuit module. Each first data terminal is connected to a first end of at least two electrical connection structures in one-to-one correspondence through at least two first switch units, and at least one electrical connection structure connects at least two first data terminals. Each second data terminal is connected to a second end of at least two electrical connection structures in one-to-one correspondence through at least two second switch units, and at least one electrical connection structure connects at least two second data terminals. Thus, at least two electrical connection structures are provided between each first data terminal and the corresponding second data terminal to enable data transmission, mutual backup between the electrical connection structures is achieved, and the reliability of data transmission is ensured.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a repair circuit for an electrical connection structure and a control method thereof. Background Technology

[0002] With the continuous development of integrated circuits, as semiconductor processes and devices have progressed to the nanometer level, it has become increasingly difficult to further improve integration density by reducing feature size. Three-dimensional stacked memory devices have emerged as another possible way to improve integration density. In stacked memory devices, the semiconductor chips in each layer are typically electrically connected via through-silicon vias (TSVs). TSVs are prone to failure during manufacturing and bonding, and TSV failures inevitably affect communication between chips. To ensure normal communication between semiconductor chips, spare TSVs are usually provided so that signal transmission can continue even if some TSVs are damaged.

[0003] The semiconductor chips in the aforementioned stacked memory devices cannot transmit data bidirectionally through through-silicon vias (TSVs), which limits the performance of the stacked memory devices and makes them prone to short circuits that cause the spare TSVs to fail. In addition, the excessive number of spare TSVs results in design redundancy and affects the structural compactness of the semiconductor chips. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a repair circuit for an electrical connection structure and a control method thereof.

[0006] According to a first aspect of the present disclosure, a repair circuit for an electrical connection structure is provided, comprising:

[0007] An electrical connection module, including the 1st, 2nd, ..., Nth electrical connection structures, where N is a positive integer greater than or equal to 3;

[0008] M first data terminals are located on the first side of the electrical connection module. Each first data terminal is connected to the first terminal of at least two electrical connection structures through at least two first switch units. At least one of the electrical connection structures is connected to at least two first data terminals.

[0009] M second data terminals are located on the second side of the electrical connection module and correspond one-to-one with the M first data terminals. Each second data terminal is connected one-to-one with the second terminal of at least two electrical connection structures through at least two second switch units, and corresponds to the connection relationship between the M first data terminals and the electrical connection structures. At least one of the electrical connection structures is connected to at least two second data terminals, where M is a positive integer greater than or equal to 2 and less than N.

[0010] A first control circuit is used to control each of the first switch units to be turned on or off according to the voltage change of the first terminal of each of the electrical connection structures. When one of the first switch units connected to the same first data terminal is turned on, the other first switch units connected to the first data terminal are turned off.

[0011] The second control circuit is used to control each of the second switch units to be turned on or off according to the voltage change at the second terminal of each of the electrical connection structures. When one of the second switch units connected to the same second data terminal is turned on, the other second switch units connected to the second data terminal are turned off.

[0012] In some embodiments of this disclosure, two adjacent first data terminals are respectively connected to at least one of the same electrical connection structures via the first switching unit;

[0013] Two adjacent second data terminals are respectively connected to at least one of the same electrical connection structures via the second switching unit.

[0014] In some embodiments of this disclosure, the first first data terminal is connected to the first terminal of the first, ..., R electrical connection structures respectively through R first switch units;

[0015] The i-th first data terminal is connected to the first terminal of the i-th, ..., (i+R-1)-th electrical connection structure through R first switch units respectively;

[0016] The first second data terminal is connected to the second terminal of the first, ..., R electrical connection structures respectively through R second switch units;

[0017] The j-th second data terminal is connected to the second terminal of the j-th, ..., (j+R-1)-th electrical connection structure through R second switch units respectively;

[0018] Where i is a positive integer greater than or equal to 2, j is a positive integer greater than or equal to 2, and R is a positive integer greater than or equal to 2.

[0019] In some embodiments of this disclosure, the first control circuit is configured to control the on or off of each of the first switching units connected to each of the first data terminals;

[0020] For each of the first data terminals, the first control circuit is used to control the first switch unit corresponding to the electrical connection structure with the earlier serial number and in normal working state among the unoccupied electrical connection structures connected to it to be turned on.

[0021] The second control circuit is configured to control the on or off state of each of the second switch units connected to each of the second data terminals;

[0022] Specifically, for each of the second data terminals, the second control circuit is used to control the second switch unit corresponding to the electrical connection structure with the earlier serial number and in normal working state among the unoccupied electrical connection structures connected to it to be turned on.

[0023] In some embodiments of this disclosure, the first control circuit includes N discharge circuits and N first detection circuits. The first terminals of the N first detection circuits and the N discharge circuits are respectively connected to the first terminals of the N electrical connection structures one by one. The second terminal of each first detection circuit is connected to each of the first switching units of the corresponding electrical connection structure.

[0024] The second control circuit includes N discharge circuits and N second detection circuits. The first terminals of the N second detection circuits and the N discharge circuits are respectively connected to the second terminals of the N electrical connection structures. The second terminal of each second detection circuit is connected to each of the second switching units of the corresponding electrical connection structure.

[0025] The charging circuit is used to charge the corresponding electrical connection structure to a first voltage level, and the discharging circuit is used to discharge the corresponding electrical connection structure to a second voltage level.

[0026] The first detection circuit is used to generate a first control signal based on the voltage level change at the first terminal of the connected electrical connection structure. The first control signal is output from the second terminal of the first detection circuit and is used to control the conduction or deactivation of each of the first switching units corresponding to the electrical connection structure.

[0027] The second detection circuit is used to generate a second control signal based on the voltage level change at the second terminal of the connected electrical connection structure. The second control signal is output from the second terminal of the second detection circuit and is used to control the conduction or shutdown of each of the second switching units corresponding to the electrical connection structure.

[0028] In some embodiments of this disclosure, the first control circuit includes a plurality of first sub-control units connected one-to-one with each of the first switch units, and the first sub-control units are used to control the conduction and closing of the first switch units connected thereto;

[0029] Each first data terminal corresponds to R first sub-control units.

[0030] For the first data terminal,

[0031] The first first control unit corresponding to the first first data terminal is used to control the first first switch unit connected to it to turn on or off according to the first control signal of the first first detection circuit.

[0032] The m1th first sub-control unit corresponding to the first first data terminal is used to control the first switch unit connected to it to turn on or off according to the first control signal of the m1th first detection circuit and the output signal of the (m1-1)th first sub-control unit corresponding to it.

[0033] For the m2th first data terminal

[0034] The first sub-control unit corresponding to the m2th first data terminal is used to control the first first switch unit connected to it to turn on or off according to the first control signal of the m2th first detection circuit and the output signal of the first sub-control unit corresponding to the (m2-1)th first data terminal.

[0035] The m1th first sub-control unit corresponding to the m2th first data terminal is used to control the first switch unit connected to it to turn on or off according to the first control signal of the (m2+m1-1)th first detection circuit, the output signal of the (m1-1)th first sub-control unit corresponding to it, and the output signal of the (m1-1)th first sub-control unit corresponding to the (m2-1)th first data terminal.

[0036] The second control circuit includes a plurality of second sub-control units connected in a one-to-one correspondence with each of the second switch units. The second sub-control units are used to control the conduction and closing of the second switch units connected to them.

[0037] Each second data terminal corresponds to R second sub-control units.

[0038] For the first second data terminal,

[0039] The first second control unit corresponding to the first second data terminal is used to control the second switch unit connected to it to turn on or off according to the second control signal of the first second detection circuit;

[0040] The m1th second sub-control unit corresponding to the first second data terminal is used to control the second switch unit connected to it to turn on or off according to the second control signal of the m1th second detection circuit and the output signal of the (m1-1)th second sub-control unit.

[0041] For the m2th second data terminal

[0042] The first second sub-control unit corresponding to the m2th second data terminal is used to control the second switch unit connected thereto to turn on or off according to the second control signal of the m2th second detection circuit and the output signal of the first second sub-control unit corresponding to the (m2-1)th second data terminal.

[0043] The m1th second sub-control unit corresponding to the m2th second data terminal is used to control the second switch unit connected thereto to turn on or off according to the second control signal of the (m2+m1-1)th second detection circuit, the output signal of the (m1-1)th second sub-control unit, and the output signal of the (m1-1)th second sub-control unit of the (m2-1)th second data terminal.

[0044] Where m1 is a positive integer greater than or equal to 2 and less than or equal to R, and m2 is a positive integer greater than or equal to 2 and less than or equal to M.

[0045] In some embodiments of this disclosure, for the first first data terminal,

[0046] The first first data terminal corresponds to the first first control unit, which includes a first node. The input terminal of the first node is connected to the output terminal of the first detection circuit, and the output terminal of the first node serves as the control terminal of the corresponding first switch unit.

[0047] When m1 is less than R, the m1th first sub-control unit corresponding to the first first data terminal includes a first AND gate and a first OR gate. The input terminal of the first AND gate is connected to the inverted signal of the output terminal of the first node and the output terminal of the m1th first detection circuit, respectively. The output terminal of the first AND gate is connected to the control terminal of the corresponding first switch unit. The input terminal of the first OR gate is connected to the output terminal of the first node and the output terminal of the first AND gate, respectively. The output terminal of the first OR gate serves as the output terminal of the m1th first sub-control unit.

[0048] The Rth first sub-control unit corresponding to the first first data terminal includes a second AND gate and a second OR gate. The input terminal of the second AND gate is connected to the inverted signal of the output terminal of the first OR gate and the output terminal of the Rth first detection circuit. The output terminal of the second AND gate is connected to the control terminal corresponding to the first switch unit. The input terminal of the second OR gate is connected to the output terminal of the first OR gate and the output terminal of the second AND gate. The output terminal of the second OR gate serves as the output terminal of the Rth first sub-control unit corresponding to the first first data terminal and is connected to the Rth first sub-control unit corresponding to the second first data terminal.

[0049] When m2 is less than M, for the m2th first data terminal,

[0050] The first sub-control unit corresponding to the m2th first data terminal includes a third AND gate. The input terminal of the third AND gate is connected to the output terminal of the m2th first detection circuit and the output terminal of the first sub-control unit corresponding to the (m2-1)th first data terminal. The output terminal of the third AND gate serves as the output terminal of the first sub-control unit corresponding to the m2th first data terminal and is connected to the control terminal of the corresponding first switch unit and the corresponding second first sub-control unit.

[0051] When m1 is less than R, the m1th first sub-control unit corresponding to the m2th first data terminal includes a fourth AND gate and a third OR gate. The input terminal of the fourth AND gate is connected to the output terminal of the (m2+m1-1)th first detection circuit, the inverted signal of the output terminal of the corresponding (m1-1)th first sub-control unit, and the output terminal of the m1th first sub-control unit corresponding to the (m2-1)th first data terminal. The output terminal of the fourth AND gate is connected to the control terminal of the corresponding first switch unit and the third OR gate. The input terminal of the third OR gate is connected to the output terminal of the corresponding (m1-1)th first sub-control unit and the output terminal of the fourth AND gate. The output terminal of the third OR gate serves as the output terminal of the m1th first sub-control unit corresponding to the m2th first data terminal and is connected to the corresponding m1+1th first sub-control unit.

[0052] The Rth first sub-control unit corresponding to the m2th first data terminal includes a fifth AND gate and a fourth OR gate. The input of the fifth AND gate is connected to the output of the (R+m1-1)th first detection circuit, the inverted signal of the output of the corresponding (R-1)th first sub-control unit, and the output of the Rth first sub-control unit of the (m2-1)th first data terminal. The output of the fifth AND gate is connected to the control terminal of the corresponding first switch unit and the fourth OR gate. The input of the fourth OR gate is connected to the output of the corresponding (R-1)th first sub-control unit and the output of the fifth AND gate. The output of the fourth OR gate serves as the output of the Rth first sub-control unit corresponding to the m2th first data terminal and is connected to the Rth first sub-control unit of the m2+1th first data terminal.

[0053] For the Mth first data terminal

[0054] The first sub-control unit corresponding to the Mth first data terminal includes a sixth AND gate. The input terminal of the sixth AND gate is connected to the output terminal of the Mth first detection circuit and the first sub-control unit corresponding to the (M-1)th first data terminal. The output terminal of the sixth AND gate serves as the output terminal of the first sub-control unit corresponding to the Mth first data terminal and is connected to the control terminal of the corresponding first switch unit and the corresponding second sub-control unit.

[0055] When m1 is less than R, the m1th first sub-control unit corresponding to the Mth first data terminal includes a seventh AND gate and a fifth OR gate. The input of the seventh AND gate is connected to the output of the (M+m1-1)th first detection circuit, the inverted signal of the output of the (m1-1)th first sub-control unit, and the m1th first sub-control unit corresponding to the (M-1)th first data terminal. The output of the seventh AND gate is connected to the control terminal of the corresponding first switch unit and the fifth OR gate. The input of the fifth OR gate is connected to the output of the (m1-1)th first sub-control unit and the output of the seventh AND gate. The output of the fifth OR gate serves as the output of the m1th first sub-control unit corresponding to the Mth first data terminal and is connected to the (m1+1)th first sub-control unit.

[0056] The first first control unit corresponding to the Mth first data terminal includes an eighth AND gate. The input terminal of the eighth AND gate is connected to the output terminal of the (R+M-1)th first detection circuit, the inverted signal of the output terminal of the corresponding R-1th control unit, and the output terminal of the Rth first control unit of the M-1th first data terminal. The output terminal of the eighth AND gate is connected to the control terminal of the corresponding first switch unit.

[0057] For each of the second data terminals, the R second sub-control units corresponding to the second data terminal have the same structure as the R first sub-control units corresponding to the first data terminal.

[0058] In some embodiments of this disclosure, when the Mth first data terminal is connected to the Mth second data terminal through the N'th electrical connection structure, if N' is less than N, the first sub-control unit and the second sub-control unit corresponding to the N'+1 to Nth electrical connection structures respectively turn off their respective connected first switch unit and second switch unit.

[0059] In some embodiments of this disclosure, the first detection circuit includes a first flip-flop and a first inverter. The input terminal of the first inverter serves as the first terminal of the first detection circuit and is connected to the first terminal of the corresponding electrical connection structure. The output terminal of the first inverter is connected to the clock input terminal of the first flip-flop. The output terminal of the first flip-flop serves as the second terminal of the first detection circuit and is connected to each first switching unit and each first sub-control unit.

[0060] The second detection circuit includes a second flip-flop and a second inverter. The input terminal of the second inverter serves as the first terminal of the second detection circuit and is connected to the second terminal of the corresponding electrical connection structure. The output terminal of the second inverter is connected to the clock input terminal of the second flip-flop. The output terminal of the second flip-flop serves as the second terminal of the second detection circuit and is connected to each second switching unit and each second sub-control unit.

[0061] In some embodiments of this disclosure, the first trigger is a rising edge trigger and outputs a high-level signal in response to a rising edge signal;

[0062] The second flip-flop is a rising edge flip-flop and outputs a high-level signal in response to a rising edge signal.

[0063] In some embodiments of this disclosure, the first switching unit is turned on in response to a high-level signal output by the corresponding first sub-control unit;

[0064] The second switching unit is turned on in response to the high-level signal output by the corresponding first sub-control unit.

[0065] In some embodiments of this disclosure, the first detection circuit further includes a first transistor, the first terminal of the first transistor is connected to the input terminal of the first inverter, the second terminal of the first transistor is grounded, and the gate of the first transistor is connected to the inverted signal of the power-on signal.

[0066] The second detection circuit further includes a second transistor, the first terminal of which is connected to the input terminal of the second inverter, the second terminal of which is grounded, and the gate of which is connected to the inverted signal of the power-on signal.

[0067] In some embodiments of this disclosure, the reset terminal of the first trigger is connected to a power-on signal, and the first trigger is used to reset its output terminal when it does not receive a power-on signal at its reset terminal;

[0068] The reset terminal of the second flip-flop is connected to a power-on signal, and the second flip-flop is used to reset its output terminal when it does not receive a power-on signal at its reset terminal.

[0069] In some embodiments of this disclosure, the electrical connection structure is a through-silicon via (TSV) structure, the M first data terminals and the first control circuit are disposed in a first semiconductor chip, and the M second data terminals and the second control circuit are disposed in a second semiconductor chip.

[0070] A second aspect of this disclosure provides a control method for a repair circuit of an electrical connection structure. The repair circuit includes an electrical connection module, which comprises N electrical connection structures. A first side of the electrical connection module has M first data terminals, and a second side of the electrical connection module has M second data terminals. Each first data terminal is connected to the first terminals of at least two of the electrical connection structures, and each second data terminal is connected to the second terminals of at least two of the electrical connection structures. N is a positive integer greater than or equal to 3, and M is a positive integer greater than or equal to 2 and less than N. The control method includes:

[0071] Detect the voltage changes at the first and second terminals of each of the aforementioned electrical connection structures;

[0072] The electrical connection structure is controlled to be connected or disconnected from the corresponding first data terminal based on the voltage change at the first terminal of each electrical connection structure, and the electrical connection structure is controlled to be connected or disconnected from the corresponding second data terminal based on the voltage change at the second terminal of each electrical connection structure, so that the electrical connection structure is selectively connected to the first data terminal or disconnected from all the first data terminals, and the electrical connection structure is selectively connected to the second data terminal or disconnected from all the second data terminals.

[0073] When the two ends of the electrical connection structure are respectively connected to a first data terminal and a second data terminal, the control data signal is transmitted from the connected first data terminal to the second data terminal, or the control data signal is transmitted from the connected second data terminal to the first data terminal.

[0074] In some embodiments of this disclosure, detecting the voltage change at the first and second terminals of each of the electrical connection structures includes:

[0075] The charging circuit sets the first and second terminals of the electrical connection structure to a first voltage level.

[0076] The first and second terminals of the electrical connection structure are set to a second voltage level by a discharge circuit.

[0077] Controlling the connection or disconnection of the electrical connection structure with its corresponding first data terminal based on the voltage change at the first terminal of each electrical connection structure, and controlling the connection or disconnection of the electrical connection structure with its corresponding second data terminal based on the voltage change at the second terminal of each electrical connection structure, including:

[0078] In response to a change in voltage at the first terminal of the electrical connection structure from the first voltage level to the second voltage level, the first detection circuit controls the electrical connection structure to selectively connect to the first data terminal.

[0079] In response to a change in voltage at the second terminal of the electrical connection structure from the first voltage level to the second voltage level, the second detection circuit controls the electrical connection structure to selectively connect to the second data terminal.

[0080] In some embodiments of this disclosure, the first data terminal, the electrical connection structure, and the second data terminal are connected by a control circuit to form a data transmission path. The control circuit sequentially controls the connection of each data transmission path according to the sequence number of the electrical connection structure corresponding to the data transmission path.

[0081] In the repair circuit for the electrical connection structure provided in this embodiment, both the first data terminal and the second data terminal are connected to the electrical connection structure in the electrical connection module through switching units. When the voltage change at both ends of the electrical connection structure meets the requirements (i.e., the electrical connection structure is normal), the first control circuit and the second control circuit will control the switching units at both ends of the electrical connection structure to open, thereby enabling the first data terminal and the second data terminal to conduct. Therefore, after conduction, data signals can be transmitted from the first data terminal to the second data terminal, and vice versa, thus achieving bidirectional data transmission and improving the performance of electrical devices, such as semiconductor devices, in the repair circuit using this electrical connection structure. In addition, since switching units are provided at both ends of the electrical connection structure, when some of the electrical connection structures are short-circuited, the first and second switching units on both sides of the electrical connection structure cannot conduct, so the current will not affect the other electrical connection structures, thereby ensuring data transmission performance.

[0082] In the M first data terminals and M second data terminals, each first data terminal is connected to the first end of at least two electrical connection structures through at least two first switching units, and each second data terminal is connected to the second end of at least two electrical connection structures through at least two second switching units. This ensures that each first data terminal and its corresponding second data terminal have at least two electrical connection structures capable of data transmission, achieving redundancy between electrical connection structures and guaranteeing the reliability of data transmission. At least one electrical connection structure simultaneously connects to at least two first data terminals and at least one electrical connection structure simultaneously connects to at least two second data terminals, allowing the same electrical connection structure to be used for data transmission between different first and second data terminals. When a first switching unit connected to a first data terminal is turned on, it controls the other first switching units connected to the first data terminal to be turned off; when a second switching unit connected to the same second data terminal is turned on, it controls the other second switching units connected to the second data terminal to be turned off. This achieves mutual redundancy of electrical connection structures between different data terminals, reducing design redundancy in connection structures, improving the compactness of the semiconductor structure of the repair circuit using this electrical connection structure, and ensuring the independence between data transmission paths.

[0083] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0084] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0085] Figure 1 This diagram illustrates a circuit structure in the related art.

[0086] Figure 2 A schematic diagram of the structure of a repair circuit illustrating an electrical connection structure according to an exemplary embodiment of the present disclosure is shown.

[0087] Figure 3 A circuit diagram showing a repair circuit for an electrical connection structure illustrated in an exemplary embodiment of this disclosure;

[0088] Figure 4 A circuit diagram illustrating a repair circuit for an electrical connection structure shown in another exemplary embodiment of this disclosure;

[0089] Figure 5This diagram illustrates the structure of the control circuit, electrical connection structure, and switching unit in a repair circuit for an electrical connection structure according to an exemplary embodiment of the present disclosure.

[0090] Figure 6 This diagram shows the timing sequence of the operation of a repair circuit for an electrical connection structure illustrated in an exemplary embodiment of the present disclosure.

[0091] Figure 7 A flowchart illustrating a control method for a repair circuit of an electrical connection structure is provided in an exemplary embodiment of this disclosure.

[0092] In the diagram: 10', Electrical connection module; 11', Electrical connection structure; 20', First control circuit; 30', Second control circuit; 40', First switching unit; 50', Second switching unit;

[0093] 10. Electrical connection module; 11. Electrical connection structure; 20. First control circuit; 21. Discharge circuit; 211. Third transistor; 22. First detection circuit; 221. First trigger; 222. First inverter; 223. First transistor; 224. Third inverter; 30. Second control circuit; 31. Charging circuit; 311. Fourth transistor; 32. Second detection circuit; 321. Second trigger; 322. Second inverter; 323. Second transistor; 324. Fourth inverter; 40. First switching unit; 41. nMOS transistor; 42. pMOS transistor; 50. Second switching unit; 60. First data terminal; 70. Second data terminal; 80. First sub-control unit; 90. Second sub-control unit. Detailed Implementation

[0094] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0095] This article mainly uses a stacked semiconductor device as an example. The repair circuit and control method for the electrical connection structure provided in the embodiments of this disclosure can be understood to be suitable for other devices with the same problem.

[0096] Multilayer semiconductor devices comprise multiple layers of semiconductor chips stacked together, electrically connected via structures such as through-silicon vias (TSVs). Because TSVs require a physical connection, they need to be tested after the multilayer semiconductor device is powered on to ensure proper signal transmission. However, to enable testing, the test circuitry for TSVs typically includes unidirectional gates such as inverters, making bidirectional data transmission between chips difficult and thus affecting the performance of the multilayer semiconductor device.

[0097] Therefore, a circuit structure is proposed in related technologies, such as Figure 1 As shown, the circuit structure includes an electrical connection module 10', a first control circuit 20', and a second control circuit 30'. The electrical connection module 10' includes two electrical connection structures 11', each with a first switch unit 40' and a second switch unit 50' at its two ends. The first control circuit 20' controls the first switch unit 40' to be turned on or off based on voltage changes at the first end (e.g., the left end) of the electrical connection structure 11'. The second control circuit 30' controls the second switch unit 50' to be turned on or off based on voltage changes at the second end (e.g., the right end) of the electrical connection structure 11'.

[0098] In the circuit structure described above, when both the first switching unit 40' and the second switching unit 50' are in the ON state, data can be transmitted from the first switching unit 40' to the second switching unit 50' and vice versa, thus achieving bidirectional data transmission. Furthermore, since the first ends of each electrical connection structure 11' are isolated through their respective first switching units 40', and the second ends of each electrical connection structure 11' are isolated through their respective second switching units 50', the failure of one electrical connection structure 11' (e.g., a short circuit) can prevent it from affecting other electrical connection structures, ensuring the reliability of the circuit structure.

[0099] However, in the above circuit structure, a spare electrical connection structure 11 is set for each electrical connection structure 11'. Although it can realize the detection of electrical connection structure and the modification of faulty electrical connection results, it requires double or even several times more electrical connection results, resulting in an excessive number of electrical connection structures, causing design redundancy and affecting the structural compactness of semiconductor chips.

[0100] Based on this, an exemplary embodiment of this disclosure provides a repair circuit for an electrical connection structure. In this repair circuit, at least two first data terminals are respectively connected to the same electrical connection structure through corresponding first switching units, and at least two second data terminals are respectively connected to the same electrical connection structure through corresponding second switching units. This allows the same electrical connection structure to be used for data transmission between different first data terminals and second data terminals. When a first switching unit connected to the same first data terminal is turned on, other first switching units connected to that first data terminal are turned off, and the electrical connection structure connected to the other first switching units can serve as a backup for other first data terminals. When a second switching unit connected to the same second data terminal is turned on, other second switching units connected to the second data terminal are turned off, and the electrical connection structure connected to the other second switching units can serve as a backup for other second data terminals. This reduces the design redundancy of the connection structure, improves the compactness of the semiconductor structure of the repair circuit using this electrical connection structure, and ensures the independence between data transmission paths.

[0101] like Figure 2 As shown, an exemplary embodiment of this disclosure provides a repair circuit for an electrical connection structure. This repair circuit includes an electrical connection module 10, M first data terminals 60, M second data terminals 70, a first control circuit 20, and a second control circuit 30. The electrical connection module 10 includes the 1st, 2nd, ..., Nth electrical connection structures 11, where N is a positive integer greater than or equal to 3. Figure 3 For example, the electrical connection module 10 includes four electrical connection structures 11, namely TSV1, TSV2, TSV3 and TSV4, to be used as follows: Figure 4 For example, the electrical connection module 10 includes six electrical connection structures 11, namely TSV1, TSV2, TSV3, TSV4, TSV5 and TSV6.

[0102] M first data terminals 60 are located on the first side of the electrical connection module 10 (e.g., the left side of the electrical connection module 10), and M second data terminals 70 are located on the second side of the electrical connection module 10 (e.g., the right side of the electrical connection module 10). For example, the electrical connection module 10 is used to realize the connection between chips, such as to realize the connection between chip Die0 and chip Die1. Then, the first data terminals 60 and the first control circuit 20 are disposed on chip Die0, and the second data terminals 70 and the second control circuit 20 are disposed on chip Die1.

[0103] like Figure 2As shown, each first data terminal 60 is connected one-to-one with the first terminal of at least two electrical connection structures 11 through at least two first switch units 40. That is, the first data terminal 60 is connected to the first terminal of at least two electrical connection structures 11, and a first switch unit 40 is provided between the first data terminal 60 and each electrical connection structure 11, where M is a positive integer greater than or equal to 2 and less than N. Continuing with... Figure 3 For example, in Figure 3 In the illustrated embodiment, the repair circuit of the electrical connection structure includes two first data terminals 60, IO1 and IO2. These two first data terminals 60 are respectively connected one-to-one to the first terminals of three electrical connection structures 11 via three first electrical switch units 40. Specifically, the first data terminal IO1 is connected to the first terminals of the three electrical connection structures 11 via the three first switch units 40; that is, the first data terminal IO1 is connected to the first terminal of TSV1 via first switch unit S41, to the first terminal of TSV2 via first switch unit S42, and to the first terminal of TSV3 via first switch unit S43. Similarly, the first data terminal IO2 is connected to the first terminals of the three electrical connection structures 11 via the three first switch units 40; that is, IO2 is connected to the first terminal of TSV2 via first switch unit S44, to the first terminal of TSV3 via first switch unit S45, and to the first terminal of TSV4 via first switch unit S46.

[0104] At least one electrical connection structure 11 connects to at least two first data terminals 60, meaning that at least one electrical connection structure 11 simultaneously connects to at least two first data terminals 60. For example, as... Figure 3 As shown, the first data terminal IO1 and the first data terminal IO2 are respectively connected to TSV2 through different first switch units 40, and the first data terminal IO1 and the first data terminal IO2 are respectively connected to TSV3 through different first switch units 40.

[0105] like Figure 2 As shown, M second data terminals 70 are located on the second side of the electrical connection module 10, corresponding one-to-one with M first data terminals 70. That is, each second data terminal 70 corresponds to a first data terminal 60, so as to form a data transmission path between the corresponding first data terminal 60 and the second data terminal 70. Figure 3 In the embodiment shown, the repair circuit of the electrical connection structure includes two second data terminals 70, IO1' and IO2', wherein the second data terminal IO1' corresponds to the first data terminal IO1, and the second data terminal IO2' corresponds to the first data terminal IO2.

[0106] Each second data terminal 70 is connected one-to-one with the second terminal of at least two electrical connection structures 11 through at least two second switching units 50, and corresponds one-to-one with the connection relationship between the M first data terminals 60 and the electrical connection structures 11, for example, as Figure 3 As shown, the second data terminal IO1' is connected to the second terminal of TSV1 through the second switch unit S51, to the second terminal of TSV2 through the second switch unit S52, and to the second terminal of TSV3 through the second switch unit S53. The second data terminal IO2' is connected to the second terminals of the three electrical connection structures 11 through the three second switch units 50, that is, the second data terminal IO2' is connected to the second terminal of TSV2 through the second switch unit S54, to the second terminal of TSV3 through the second switch unit S55, and to the second terminal of TSV4 through the second switch unit S56.

[0107] At least one electrical connection structure 11 connects to at least two second data terminals 70, meaning that at least one electrical connection structure 11 simultaneously connects to at least two second data terminals 70. For example, as... Figure 3 As shown, the second data terminal IO1' and the second data terminal IO2' are respectively connected to TSV2 through the second switch unit 50, and the second data terminal IO1' and the second data terminal IO2' are respectively connected to TSV3 through the second switch unit 50.

[0108] The first control circuit 20 is used to control each first switch unit 40 to be turned on or off according to the voltage change at the first terminal of each electrical connection structure 11. When one first switch unit 40 connected to the same first data terminal 60 is turned on, it controls the other first switch units 40 connected to the first data terminal 60 to be turned off, and so on. Figure 3 For example, if the first control circuit 20 controls the first switch unit S42 corresponding to the first data terminal IO1 in TSV2 to be turned on, then the first switch units S41 and S43 connected to the first data terminal IO1 are turned off. If the first control circuit 20 controls the first switch unit S45 corresponding to the first data terminal IO2 in TSV3 to be turned on, then the first switch units S44 and S46 connected to the first data terminal IO2 are turned off.

[0109] The second control circuit 30 is used to control each second switching unit 50 to be turned on or off according to the voltage change at the second terminal of each electrical connection structure 11, and when one second switching unit 50 connected to the same second data terminal 70 is turned on, it controls the other second switching units 50 connected to the second data terminal 70 to be turned off. (Reference) Figure 3If the second control circuit 30 controls the second switch unit S52 corresponding to the second data terminal IO1' in TSV2 to be turned on, then the second switch units S51 and S52 connected to the second data terminal IO1' are turned off. If the second control circuit 30 controls the second switch unit S55 corresponding to the second data terminal IO2' in TSV3 to be turned on, then the second switch units S54 and S56 connected to the second data terminal IO2' are turned off.

[0110] In this embodiment, both the first data terminal 60 and the second data terminal 70 are connected to the electrical connection structure 11 in the electrical connection module 10 through a switching unit. The switching unit is a bidirectional switching device. When the voltage change at both ends of the electrical connection structure 11 meets the requirements (i.e., the electrical connection structure is normal), the first control circuit 20 and the second control circuit 30 will control the switching unit at both ends of the electrical connection structure 11 to open, so as to realize the bidirectional conduction of the first data terminal 60 and the second data terminal 70. Therefore, after conduction, the data signal can be transmitted from the first data terminal 60 to the second data terminal 70, and from the second data terminal 70 to the first data terminal 60, thereby realizing bidirectional data transmission and improving the performance of electrical devices, such as semiconductor devices, in the repair circuit using this electrical connection structure. Furthermore, since both ends of the electrical connection structure 11 are equipped with switching units, when some of the electrical connection structures 11 are short-circuited, the voltage across the electrical connection structure 11 will not change (i.e., the voltage across the electrical connection structure 11 does not meet the change requirement). Under the control of the first control circuit 20 and the second control circuit 30, the first switching unit 40 and the second switching unit 50 on both sides of the electrical connection structure 11 cannot be turned on. Therefore, the current will not affect the other electrical connection structures 11, thereby ensuring data transmission performance.

[0111] In the M first data terminals 60 and M second data terminals 70, each first data terminal 60 is connected to the first end of at least two electrical connection structures 11 through at least two first switching units 40, and each second data terminal 70 is connected to the second end of at least two electrical connection structures 11 through at least two second switching units 50. This ensures that each first data terminal 60 and its corresponding second data terminal 70 have at least two electrical connection structures 11 that can transmit data, realize the redundancy between electrical connection structures 11, and ensure the reliability of data transmission. At least one electrical connection structure 11 connects at least two first data terminals 60 and at least one electrical connection structure 11 connects at least two second data terminals 70, thereby enabling the same electrical connection structure 11 to be used for data transmission between different first data terminals 60 and second data terminals 70. When a first switching unit 40 connected to the same first data terminal 60 is turned on, other first switching units 40 connected to the first data terminal 60 are turned off. When a second switching unit 50 connected to the same second data terminal 70 is turned on, other second switching units 50 connected to the second data terminal 70 are turned off. This achieves sequential backup between electrical connection structures 11, which reduces the design redundancy of electrical connection structures 11, improves the compactness of the semiconductor structure of the repair circuit using this electrical connection structure, and ensures the independence between data transmission paths.

[0112] For example, the electrical connection structure 11 includes through-silicon vias (TSVs) for establishing electrical connections between two adjacent semiconductor chips, namely a first semiconductor chip and a second semiconductor chip. M first data terminals 60 and a first control circuit 20 are disposed in the first semiconductor chip, and M second data terminals 70 and a second control circuit 30 are disposed in the second semiconductor chip. For example, in a stacked semiconductor device, TSVs are used to establish electrical connections between a substrate semiconductor chip and a core semiconductor chip, or to establish electrical connections between core semiconductor chips.

[0113] In the M first data terminals 60, any two or more first data terminals 60 can be connected to the same electrical connection structure 11. To facilitate circuit pattern layout and ensure the compactness of the repair circuit of the electrical connection structure, adjacent first data terminals 60 are designed to be connected to the same electrical connection structure. In an exemplary embodiment, two adjacent first data terminals 60 are respectively connected to at least one identical electrical connection structure 11 through a first switching unit 40. In some embodiments, such as... Figure 2As shown, in adjacent first data terminals 60, a first switching unit 40 of one first data terminal 60 is connected to a first switching unit 40 of another first data terminal 60 via the same electrical connection structure 11. That is, the two first data terminals 60 share one electrical connection structure 11 through different first switching units. In other embodiments, in adjacent first data terminals 60, multiple first switching units 40 connected to one first data terminal 60 are connected to multiple identical electrical connection structures 11 through multiple first switching units 40 of another first data terminal 60. It can be understood that each first data terminal 60 is connected to an electrical connection structure 11 in a one-to-one correspondence through only one first switching unit 40. Therefore, when multiple first switching units 40 corresponding to one first data terminal 60 are connected to multiple identical electrical connection structures 11 through multiple first switching units 40 corresponding to another first data terminal 60, it means that the two first data terminals 60 share multiple electrical connection structures 11. For each electrical connection structure 11, two first data terminals 60 are connected through two first switching units 40 respectively. For example, as... Figure 3 As shown, the first data terminal IO1 and the first data terminal IO2 are respectively connected to the first terminal of TSV2 through their respective first switch units S42 and S44. Furthermore, the first data terminal IO1 and the first data terminal IO2 are also respectively connected to the first terminal of TSV3 through their respective first switch units S43 and S45, thereby enabling the first data terminal IO1 and the first data terminal IO2 to share TSV2 and TSV3.

[0114] Similarly, any two or more of the M second data terminals 70 can be connected to the same electrical connection structure 11. To facilitate circuit layout and ensure the compactness of the repair circuit of the electrical connection structure, adjacent second data terminals 70 are designed to be connected to the same electrical connection structure 11. In an exemplary embodiment, two adjacent second data terminals 70 are respectively connected to at least one identical electrical connection structure 11 through a second switching unit 50. In some embodiments, such as... Figure 2As shown, in adjacent second data terminals 70, a second switching unit 50 of one second data terminal 70 is connected to a second switching unit 50 of another second data terminal 70 via the same electrical connection structure 11, meaning the two second data terminals 70 share one electrical connection structure 11. In other embodiments, in adjacent second data terminals 70, multiple second switching units 50 of one second data terminal 70 are connected to multiple identical electrical connection structures 11 via multiple second switching units 50 of another second data terminal 70. It can be understood that each second data terminal 70 is connected to an electrical connection structure 11 via only one second switching unit 50. Therefore, when multiple second switching units 50 of one second data terminal 70 are connected to multiple identical electrical connection structures 11 via multiple second switching units 50 of another second data terminal 70, it means that the two second data terminals 70 share multiple electrical connection structures 11, and for each electrical connection structure 11, two second data terminals 70 are connected via two second switching units 50 respectively. For example, as... Figure 3 As shown, the second data terminal IO1' and the second data terminal IO2' are respectively connected to the second terminal of TSV2 through their respective second switch units S52 and S54. Furthermore, the second data terminal IO1' and the second data terminal IO2' are also respectively connected to the second terminal of TSV3 through their respective second switch units S53 and S55, thereby enabling the second data terminal IO1' and the second data terminal IO2' to share TSV2 and TSV3.

[0115] Understandably, in this embodiment, it can be as follows: Figure 3 The two first data terminals 60 shown share one or more electrical connection structures 11, and the two second data terminals 70 share one or more electrical connection structures 11. In other embodiments, multiple first data terminals 60 may share one or more electrical connection structures 11, and multiple second data terminals 70 may share one or more electrical connection structures 11.

[0116] In an exemplary embodiment of this disclosure, the first first data terminal 60 is connected to the first terminals of the first, ..., R electrical connection structures 11 via R first switch units 40; the i-th first data terminal 60 is connected to the first terminals of the i-th, ... (i+R-1)-th electrical connection structures 11 via R first switch units 40; the first second data terminal 70 is connected to the second terminals of the first, ..., R-th electrical connection structures 11 via R second switch units 50; and the j-th second data terminal 70 is connected to the second terminals of the j-th, ..., (j+R-1)-th electrical connection structures 11 via R second switch units 50; wherein i is a positive integer greater than or equal to 2, j is a positive integer greater than or equal to 2, and R is a positive integer greater than or equal to 2. For example, as... Figure 4As shown, the first data terminal 60 is connected to the first terminals of the first, second, and third electrical connection structures 11 via three first switch units 40. The i-th data terminal 60 is connected to the first terminals of the i-th, (i+1), and (i+2)-th electrical connection structures 11 via three first switch units 40. The first second data terminal 70 is connected to the second terminals of the first, second, and third electrical connection structures 11 via three second switch units 50; the j-th second data terminal 70 is connected to the second terminals of the j-th, (j+1), and (j+2)-th electrical connection structures 11 via three second switch units 50. Thus, the second and third electrical connection structures 11 can serve as backups for the first electrical connection structure 11. That is, when the first electrical connection structure 11 fails, the second or third electrical connection structure 11 can be used for signal transmission. The (i+1)th and (i+2)th electrical connection structures 11 can serve as backups for the i-th electrical connection structure 11. When the i-th electrical connection structure 11 fails, the (i+1)th or (i+2)th electrical connection structure 11 can be used for signal transmission.

[0117] For example, such as Figure 4 As shown, the repair circuit for the electrical connection structure includes four first data terminals 60, namely first data terminals IO1, IO2, IO3 and IO4. The repair circuit for the electrical connection structure also includes six electrical connection structures 11, namely TSV1, TSV2, TSV3, TSV4, TSV5 and TSV6. Among them, the first data terminal IO1 is connected to the first terminals of TSV1, TSV2 and TSV3 through three first switching units 40, the first data terminal IO2 is connected to the first terminals of TSV2, TSV3 and TSV4 through three first switching units 40, the first data terminal IO3 is connected to the first terminals of TSV3, TSV4 and TSV5 through three first switching units 40, and the first data terminal IO4 is connected to the first terminals of TSV4, TSV5 and TSV6 through three first switching units 40. The repair circuit for the electrical connection structure also includes four second data terminals 70, namely second data terminals IO1', IO2', IO3' and IO4'. Second data terminal IO1' is connected to the second terminals of TSV1, TSV2 and TSV3 through three second switch units 50, second data terminal IO2' is connected to the second terminals of TSV2, TSV3 and TSV4 through three second switch units 50, second data terminal IO3' is connected to the second terminals of TSV3, TSV4 and TSV5 through three second switch units 50, and second data terminal IO4' is connected to the second terminals of TSV4, TSV5 and TSV6 through three second switch units 50.

[0118] In this embodiment, when TSV1, TSV2, TSV3, and TSV4 are all normal, the first data terminal IO1 can transmit signals with the second data terminal IO1' via TSV1, the first data terminal IO2 can transmit signals with the second data terminal IO2' via TSV2, the first data terminal IO3 can transmit signals with the second data terminal IO3' via TSV3, and the first data terminal IO4 can transmit signals with the second data terminal IO4' via TSV4. However, when TSV2 fails, the first data terminal IO1 can transmit signals with the second data terminal IO1' via TSV1, the first data terminal IO2 can transmit signals with the second data terminal IO2' via TSV3, the first data terminal IO3 can transmit signals with the second data terminal IO3' via TSV4, and the first data terminal IO4 can transmit signals with the second data terminal IO4' via TSV5. When both TSV2 and TSV3 fail, the first data terminal IO1 can transmit signals to the second data terminal IO1' through TSV1, the first data terminal IO2 can transmit signals to the second data terminal IO2' through TSV4, the first data terminal IO3 can transmit signals to the second data terminal IO3' through TSV5, and the first data terminal IO4 can transmit signals to the second data terminal IO4' through TSV6.

[0119] For ease of control, the first control circuit 20 can set conduction priorities for each first switch unit 40 and each second switch unit 50. A higher conduction priority means the unit is turned on more quickly. In one embodiment, the first control circuit 20 is configured to control the on / off state of each first switch unit 40 connected to each first data terminal 60; wherein, for each first data terminal 60, the first control circuit 20 controls the first switch unit 40 corresponding to the first-numbered and normally functioning electrical connection structure 11 connected to it to be turned on. For example, as... Figure 4 As shown, the first data terminal IO1 is connected to TSV1, TSV2, and TSV3 through the first switch unit S41, the first switch unit S42, and the first switch unit S43, respectively. If the first data terminal IO1 is already connected to TSV1, that is, the first switch unit S41 is connected, then the first switch unit S42 and the first switch unit S43 connected to TSV2 and TSV3 are controlled to be turned off.

[0120] Similarly, the second control circuit 30 is configured to control the on / off state of each second switch unit 50 connected to each second data terminal 70; wherein, for each second data terminal 70, the second control circuit 30 controls the second switch unit 50 corresponding to the first-numbered and normally functioning electrical connection structure 11 connected to it to be turned on. For example, as Figure 4As shown, the second data terminal IO1' is connected to TSV1, TSV2, and TSV3 through the second switch unit S51, the second switch unit S52, and the second switch unit S53, respectively. If the second data terminal IO1' is already connected to TSV1, that is, the second switch unit S51 is connected, then the second switch unit S52 and the second switch unit S53 connected to TSV2 and TSV3 are controlled to be turned off.

[0121] For example, Figure 4 The specific switch control and conduction data terminals of the repair circuit for the electrical connection structure shown are as follows:

[0122] When TSV1 to TSV4 are all normal (TSV5 and TSV6 can be normal or faulty), the data connection status is as follows:

[0123] IO1-TSV1-IO1', IO2-TSV2-IO2', IO3-TSV3-IO3', IO4-TSV4-IO4';

[0124] When TSV1 fails and other TSVs are functioning normally, the data connection status is as follows:

[0125] IO1-TSV2-IO1', IO2-TSV3-IO2', IO3-TSV4-IO3', IO4-TSV5-IO4';

[0126] When TSV2 fails and other TSVs are functioning normally, the data connection status is as follows:

[0127] IO1-TSV1-IO1', IO2-TSV3-IO2', IO3-TSV4-IO3', IO4-TSV5-IO4';

[0128] When TSV3 fails and other TSVs are functioning normally, the data connection status is as follows:

[0129] IO1-TSV1-IO1', IO2-TSV2-IO2', IO3-TSV4-IO3', IO4-TSV5-IO4';

[0130] When TSV4 fails and other TSVs are normal, the data connection status is as follows:

[0131] IO1-TSV1-IO1', IO2-TSV2-IO2', IO3-TSV3-IO3', IO4-TSV5-IO4';

[0132] When TSV1-2 fails and other TSVs are normal, the data connection status is as follows:

[0133] IO1-TSV3-IO1', IO2-TSV4-IO2', IO3-TSV5-IO3', IO4-TSV6-IO4';

[0134] When TSV1 and 3 fail, and other TSVs are normal, the data connection status is as follows:

[0135] IO1-TSV2-IO1', IO2-TSV4-IO2', IO3-TSV5-IO3', IO4-TSV6-IO4';

[0136] When TSV1 and 4 fail, and other TSVs are normal, the data connection status is as follows:

[0137] IO1-TSV2-IO1', IO2-TSV3-IO2', IO3-TSV5-IO3', IO4-TSV6-IO4';

[0138] When TSV1 and 5 are faulty, and other TSVs are normal, the data connection status is as follows:

[0139] IO1-TSV2-IO1', IO2-TSV3-IO2', IO3-TSV4-IO3', IO4-TSV6-IO4';

[0140] When TSV1 and 6 are faulty, and other TSVs are normal, the data connection status is as follows:

[0141] IO1-TSV2-IO1', IO2-TSV3-IO2', IO3-TSV4-IO3', IO4-TSV5-IO4';

[0142] When TSV2 and TSV3 fail, and other TSVs are normal, the data connection status is as follows:

[0143] IO1-TSV1-IO1', IO2-TSV4-IO2', IO3-TSV5-IO3', IO4-TSV6-IO4';

[0144] When TSV2 and TSV4 fail, and other TSVs are normal, the data connection status is as follows:

[0145] IO1-TSV1-IO1', IO2-TSV3-IO2', IO3-TSV5-IO3', IO4-TSV6-IO4';

[0146] When TSV2 and TSV5 fail, and other TSVs are normal, the data connection status is as follows:

[0147] IO1-TSV1-IO1', IO2-TSV3-IO2', IO3-TSV4-IO3', IO4-TSV6-IO4';

[0148] When TSV2 and TSV6 fail, and other TSVs are normal, the data connection status is as follows:

[0149] IO1-TSV1-IO1', IO2-TSV3-IO2', IO3-TSV4-IO3', IO4-TSV5-IO4';

[0150] When TSV3 and TSV4 fail, and other TSVs are normal, the data connection status is as follows:

[0151] IO1-TSV1-IO1', IO2-TSV2-IO2', IO3-TSV5-IO3', IO4-TSV6-IO4';

[0152] When TSV3 and TSV5 fail, and other TSVs are normal, the data connection status is as follows:

[0153] IO1-TSV1-IO1', IO2-TSV2-IO2', IO3-TSV4-IO3', IO4-TSV6-IO4';

[0154] When TSV3 and TSV6 fail, and other TSVs are normal, the data connection status is as follows:

[0155] IO1-TSV1-IO1', IO2-TSV2-IO2', IO3-TSV4-IO3', IO4-TSV5-IO4';

[0156] When TSV4 and TSV5 fail, and other TSVs are normal, the data connection status is as follows:

[0157] IO1-TSV1-IO1', IO2-TSV2-IO2', IO3-TSV3-IO3', IO4-TSV6-IO4';

[0158] When TSV4 and TSV6 fail, and other TSVs are normal, the data connection status is as follows:

[0159] IO1-TSV1-IO1', IO2-TSV2-IO2', IO3-TSV3-IO3', IO4-TSV5-IO4'.

[0160] With the circuit design described above, only two electrical connection structures 11 are added so that each electrical connection structure 11 can correspond to two spare electrical connection structures 11 (each electrical connection structure 11 is reserved sequentially). This allows each pair of data terminals (the first data terminal and the corresponding second data terminal) to have three available electrical connection structures 11 to realize data transmission, thereby further ensuring the reliability of signal transmission. Furthermore, it does not add too many extra electrical connection structures 11, ensuring the simplicity of the electrical connection structure repair circuit.

[0161] In one exemplary embodiment of this disclosure, such as Figure 3 As shown, the first control circuit 20 includes N discharge circuits 21 and N first detection circuits 22. The first terminals of the N first detection circuits 22 and the N discharge circuits 21 are respectively connected to the first terminals of the N electrical connection structures 11. The second terminal of each first detection circuit 22 is connected to the first switching unit 40 of the corresponding electrical connection structure 11. (Continue to refer to...) Figure 3 The second control circuit 30 includes N charging circuits 31 and N second detection circuits 32. The first ends of the N second detection circuits 32 and the N charging circuits 31 are respectively connected to the second ends of the N electrical connection structures 11. The second end of each second detection circuit 32 is connected to each second switch unit 50 of the corresponding electrical connection structure 11.

[0162] The discharge circuit 21 is used to discharge the electrical connection structure 11, and the charging circuit 31 is used to charge the electrical connection structure 11. The first detection circuit 22 generates a first control signal based on the voltage level change at the first terminal of the connected electrical connection structure 11. The first control signal is output from the second terminal of the first detection circuit 22 and is used to control the conduction or shutdown of each first switch unit 40 of the corresponding electrical connection structure 11. That is, after the discharge circuit 21 and the charging circuit 31 complete the charging and discharging of the electrical connection structure 11, if the voltage on the left side of the electrical connection structure 11 changes, it indicates that the electrical connection structure 11 is normal. If the voltage on the left side of the electrical connection structure 11 does not change, it indicates that the electrical connection structure 11 has malfunctioned, such as a short circuit or open circuit.

[0163] The second detection circuit 32 generates a second control signal based on the voltage level change at the second terminal of the connected electrical connection structure 11. The second control signal is output from the second terminal of the second detection circuit 32 and is used to control the conduction or shutdown of each second switch unit 50 of the corresponding electrical connection structure 11. That is, after the discharge circuit 21 and the charging circuit 31 complete the charging and discharging of the electrical connection structure 11, if the voltage on the right side of the electrical connection structure 11 changes, it indicates that the electrical connection structure 11 is normal. If the voltage on the right side of the electrical connection structure 11 does not change, it indicates that the electrical connection structure 11 has malfunctioned, such as a short circuit or open circuit.

[0164] In an exemplary embodiment of this disclosure, the first control circuit 20 further includes a first sub-control unit 80 connected to each of the first switch units 40 in a one-to-one correspondence, the first sub-control unit 80 being used to control the on and off states of the first switch units 40 connected thereto. The second control circuit 30 further includes a second sub-control unit 90 connected to each of the second switch units 50 in a one-to-one correspondence, the second sub-control unit 90 being used to control the on and off states of the second switch units 40 connected thereto.

[0165] For example, multiple electrical connection structures 11 are provided between two semiconductor chips. Each electrical connection structure 11 has a corresponding discharge circuit 21 and a first detection circuit 22 in one semiconductor chip, and a corresponding charging circuit 31 and a second detection circuit 32 in the other semiconductor chip. The discharge circuit 21 and the charging circuit 31 charge and discharge the corresponding electrical connection structure 11. Each first detection circuit 22 and each second detection circuit 32 detects the voltage change at both ends of the corresponding electrical connection structure 11 and controls each first sub-control unit 80 and each second sub-control unit 90, thereby controlling the conduction and shutdown of each first switch unit 40 and each second switch unit 50.

[0166] Each first data terminal 60 corresponds to R first sub-control units 80.

[0167] Specifically, for the first data terminal, the corresponding first sub-control units 80 are configured as follows:

[0168] The first first data terminal 60, corresponding to the first first control unit 80, is used to control the conduction or deactivation of the first first switch unit 40 connected thereto, according to the first control signal of the first first detection circuit 22. For example, as... Figure 3 As shown, the first sub-control unit 80 corresponding to the first data terminal IO1 is the first node A. The first node A is connected to the output terminal of the first detection circuit 22 and the control terminal of the first switching unit S41. The first node A can also be replaced by the result of a buffer circuit / AND gate, etc., which is not limited here.

[0169] The m1th first sub-control unit 80 corresponding to the first first data terminal is used to control the first switching unit 40 connected to it to turn on or off according to the first control signal of the m1th first detection circuit 22 and the output signal of the (m1-1)th first sub-control unit 80 corresponding to it. For example, Figure 3 As shown, the second first sub-control unit 80 corresponding to the first data terminal IO1 is the first sub-control unit C1. The input terminal of the first sub-control unit C1 is connected to the first node A and the first detection circuit 22 of the current level (connected to TSV2). The output terminal of the first sub-control unit C1 is connected to the control terminal of the first switching unit S42.

[0170] For the m2th first data terminal, the corresponding first sub-control units 80 are configured as follows:

[0171] The first sub-control unit 80 corresponding to the m2th first data terminal 60 is used to control the conduction or deactivation of the first first switch unit 40 connected thereto, based on the first control signal of the m2th first detection circuit 22 and the output signal of the first sub-control unit 80 corresponding to the (m2-1)th first data terminal 60. For example, as Figure 3 As shown, the first sub-control unit 80 corresponding to the first data terminal IO2 is the first sub-control unit C2. The input terminal of the first sub-control unit C2 is connected to the first detection circuit 22 of the current stage (connected to TSV2) and the first node A. The output terminal of the first sub-control unit C2 is connected to the first switch unit S44.

[0172] The m1-th first sub-control unit 80 corresponding to the m2-th first data terminal 60 is used to control the conduction or deactivation of the first switching unit 40 connected thereto based on the first control signal of the (m2+m1-1)-th first detection circuit 22, the output signal of the (m1-1)-th first sub-control unit 80 corresponding thereto, and the output signal of the (m1-1)-th first sub-control unit 80 corresponding to the (m2-1)-th first data terminal 60. For example, as Figure 3 As shown, the second first sub-control unit 80 corresponding to the first data terminal IO2 is the first sub-control unit C4. The input terminal of the first sub-control unit C4 is connected to the first detection circuit 22, the first sub-control unit C2 and the first sub-control unit C1 of the current stage (connected to TSV3). The output terminal of the first sub-control unit C4 is connected to the first switch unit S45.

[0173] Similarly, each second data terminal 70 corresponds to R second sub-control units 90.

[0174] For the first second data terminal, the corresponding second sub-control units 90 are configured as follows:

[0175] The first second control unit 90 corresponding to the first second data terminal 70 is used to control the conduction or deactivation of the second switching unit 50 connected thereto according to the second control signal of the first second detection circuit 32. For example, as... Figure 3 As shown, the first second sub-control unit 90 corresponding to the second data terminal IO1' is the second node B. The second node B is connected to the output terminal of the second detection circuit 32 and the control terminal of the second switch unit S51. The second node B can also be replaced by a buffer circuit / AND gate, etc., which is not limited here.

[0176] The m1th second sub-control unit 90 corresponding to the first second data terminal 70 is used to control the conduction or deactivation of the second switching unit 50 connected thereto according to the second control signal of the m1th second detection circuit 32 and the output signal of the (m1-1)th second sub-control unit 90. For example, Figure 3 As shown, the second second sub-control unit 90 corresponding to the second data terminal IO1' is the second sub-control unit C1'. The input terminal of the second sub-control unit C1' is connected to the second node B and the second detection circuit 32 of the current level (connected to TSV2). The output terminal of the second sub-control unit C1' is connected to the control terminal of the second switching unit S52.

[0177] For the m2th second data terminal, the corresponding second sub-control units 90 are configured as follows:

[0178] The first second sub-control unit 90 corresponding to the m2th second data terminal 70 is used to control the conduction or deactivation of the second switching unit 50 connected thereto, based on the second control signal of the m2th second detection circuit 32 and the output signal of the first second sub-control unit 90 corresponding to the (m2-1)th second data terminal 70. For example, as Figure 3 As shown, the first second sub-control unit 90 corresponding to the second data terminal IO2' is the second sub-control unit C2'. The input terminal of the second sub-control unit C2' is connected to the second detection circuit 32 of the current stage (connected to TSV2) and the second node B. The output terminal of the second sub-control unit C2' is connected to the second switch unit S54.

[0179] The m1th second sub-control unit 90 corresponding to the m2th second data terminal 70 is used to control the conduction or deactivation of the second switch unit 50 connected to it based on the second control signal of the (m2+m1-1)th second detection circuit 32, the output signal of the (m1-1)th second sub-control unit 90, and the output signal of the (m1-1)th second sub-control unit 90 of the (m2-1)th second data terminal 70. Here, m1 is a positive integer greater than or equal to 2 and less than or equal to n1, and m2 is a positive integer greater than or equal to 2 and less than or equal to M. For example, as... Figure 3 As shown, the second second sub-control unit 80 corresponding to the second data terminal IO2' is the second sub-control unit C4'. The input terminal of the second sub-control unit C4' is connected to the second detection circuit 32, the second sub-control unit C2' and the second sub-control unit C1' of the current stage (connected to TSV3). The output terminal of the second sub-control unit C4' is connected to the second switch unit S55.

[0180] The first sub-control unit 80 and the second sub-control unit 90 can use AND gates, OR gates, or other logic circuits to control the first switching unit 40 and the second switching unit 50. For example, for the first first data terminal, the first first sub-control unit 80 corresponding to the first first data terminal includes a first node. The input terminal of the first node is connected to the output terminal of the first first detection circuit 22, and the output terminal of the first node serves as the control terminal of the corresponding first switching unit 40. For example, as... Figure 3 As shown, the first sub-control unit 80 includes a first node A.

[0181] When m1 is less than R, the m1th first sub-control unit 80 corresponding to the first first data terminal 60 includes a first AND gate and a first OR gate. The input terminal of the first AND gate is connected to the inverted signal of the output terminal of the first node and the output terminal of the m1th first detection circuit 22, respectively. The output terminal of the first AND gate is connected to the control terminal of the corresponding first switching unit 40. The input terminal of the first OR gate is connected to the output terminal of the first node and the output terminal of the first AND gate, respectively. The output terminal of the first OR gate serves as the output terminal of the m1th first sub-control unit 80. For example, as shown... Figure 3 As shown, the m1th first sub-control unit 80 corresponding to the first first data terminal IO1 includes the first sub-control unit C1. For example... Figure 4 As shown, the m1th first sub-control unit 80 corresponding to the first first data terminal IO1 includes the first sub-control unit C6.

[0182] The Rth first sub-control unit 80 corresponding to the first first data terminal 60 includes a second AND gate and a second OR gate. The input of the second AND gate is connected to the inverted signal of the output of the first OR gate and the output of the Rth first detection circuit 22, respectively. The output of the second AND gate is connected to the control terminal corresponding to the first switching unit 40. The input of the second OR gate is connected to the output of the first OR gate and the output of the second AND gate, respectively. The output of the second OR gate serves as the output of the Rth first sub-control unit 80 corresponding to the first first data terminal 60, and is connected to the Rth first sub-control unit 80 corresponding to the second first data terminal 60. Figure 3 As shown, the Rth first sub-control unit 80 corresponding to the first first data terminal 60 includes the first sub-control unit C3, as follows: Figure 4 As shown, the Rth first sub-control unit 80 corresponding to the first first data terminal 60 includes the first sub-control unit C8.

[0183] When m2 is less than M, for the m2th first data terminal 60, the first first sub-control unit 80 corresponding to the m2th first data terminal 60 includes a third AND gate. The input of the third AND gate is connected to the output of the m2th first detection circuit 22 and the output of the first first sub-control unit 80 corresponding to the (m2-1)th first data terminal 60, respectively. The output of the third AND gate serves as the output of the first first sub-control unit 80 corresponding to the m2th first data terminal 60, and is connected to the control terminal of the corresponding first switch unit 40 and the corresponding second first sub-control unit 80, respectively. Figure 4 As shown, the first sub-control unit 80 corresponding to the m2th first data terminal 60 includes first sub-control units C7 and C10.

[0184] When m1 is less than R, the m1st first sub-control unit 80 corresponding to the m2th first data terminal 60 includes a fourth AND gate and a third OR gate. The input of the fourth AND gate is connected to the output of the (m2+m1-1)th first detection circuit 22, the inverted signal of the output of the corresponding (m1-1)th first sub-control unit 80, and the output of the m1st first sub-control unit 80 corresponding to the (m2-1)th first data terminal 60. The output of the fourth AND gate is connected to the control terminal of the corresponding first switch unit 40 and the third OR gate. The input of the third OR gate is connected to the output of the corresponding (m1-1)th first sub-control unit 80 and the output of the fourth AND gate. The output of the third OR gate serves as the output of the m1st first sub-control unit 80 corresponding to the m2th first data terminal 60 and is connected to the corresponding m1+1th first sub-control unit 80. Figure 4 As shown, the first sub-control unit 80 corresponding to the m2th first data terminal 60 includes a first sub-control unit C9 and a first sub-control unit C12.

[0185] The Rth first sub-control unit 80 corresponding to the m2th first data terminal 60 includes a fifth AND gate and a fourth OR gate. The input of the fifth AND gate is connected to the output of the (R+m1-1)th first detection circuit 22, the inverted signal of the output of the corresponding (R-1)th first sub-control unit 80, and the output of the Rth first sub-control unit 80 of the (m2-1)th first data terminal 60. The output of the fifth AND gate is connected to the control terminal of the corresponding first switch unit 40 and the fourth OR gate. The input of the fourth OR gate is connected to the output of the (R-1)th first sub-control unit 80 and the output of the fifth AND gate. The output of the fourth OR gate serves as the output of the Rth first sub-control unit 80 corresponding to the m2th first data terminal 60, and is connected to the Rth first sub-control unit 80 of the m2+1th first data terminal 60. Figure 4 As shown, the Rth first sub-control unit 80 corresponding to the m2th first data terminal 60 includes a first sub-control unit C11 and a first sub-control unit C14.

[0186] For the Mth first data terminal 60, the first first sub-control unit 80 corresponding to the Mth first data terminal 60 includes a sixth AND gate. The input terminal of the sixth AND gate is connected to the output terminal of the Mth first detection circuit 22 and the first first sub-control unit 80 corresponding to the (M-1)th first data terminal 60, respectively. The output terminal of the sixth AND gate serves as the output terminal of the first first sub-control unit 80 corresponding to the Mth first data terminal 60, and is connected to the control terminal of the corresponding first switching unit 40 and the corresponding second first sub-control unit 80, respectively. Figure 3 As shown, the first sub-control unit 80 corresponding to the Mth first data terminal 60 includes the first sub-control unit C2. For example... Figure 4 As shown, the first sub-control unit 80 corresponding to the Mth first data terminal 60 includes the first sub-control unit C13.

[0187] When m1 is less than R, the m1th first sub-control unit 80 corresponding to the Mth first data terminal 60 includes a seventh AND gate and a fifth OR gate. The input of the seventh AND gate is connected to the output of the (M+m1-1)th first detection circuit 22, the inverted signal of the output of the corresponding (m1-1)th first sub-control unit 80, and the m1th first sub-control unit 80 corresponding to the (M-1)th first data terminal 60. The output of the seventh AND gate is connected to the control terminal of the corresponding first switch unit 40 and the fifth OR gate. The input of the fifth OR gate is connected to the output of the corresponding (m1-1)th first sub-control unit 80 and the output of the seventh AND gate. The output of the fifth OR gate serves as the output of the m1th first sub-control unit 80 corresponding to the Mth first data terminal 60 and is connected to the corresponding m1+1th first sub-control unit 80. Figure 3 As shown, the m1th first sub-control unit 80 corresponding to the Mth first data terminal 60 includes the first sub-control unit C4, as follows: Figure 4 As shown, the first sub-control unit 80 corresponding to the Mth first data terminal 60 includes the first sub-control unit C15.

[0188] The first first data terminal 60 corresponds to the Rth first sub-control unit 80, which includes an eighth AND gate. The input of the eighth AND gate is connected to the output of the (R+M-1)th first detection circuit 22, the inverted signal of the output of the corresponding (R-1)th first sub-control unit 80, and the output of the Rth first sub-control unit 80 of the (M-1)th first data terminal 60. The output of the eighth AND gate is connected to the control terminal of the corresponding first switching unit 40. Figure 3 As shown, the Rth first sub-control unit 80 corresponding to the Mth first data terminal 60 includes the first sub-control unit C5, as follows: Figure 4 As shown, the Rth first sub-control unit 80 corresponding to the Mth first data terminal 60 includes a first sub-control unit C16.

[0189] For each second data terminal 70, the R second sub-control units 90 corresponding to the second data terminal 70 and the R first sub-control units 80 corresponding to the first data terminal 60 corresponding to the second data terminal 70 have the same structure, which will not be described again here.

[0190] In an exemplary embodiment of this disclosure, when the Mth first data terminal 60 is connected to the Mth second data terminal 70 through the N'th electrical connection structure 11, if N' is less than N, the first sub-control units 80 and the second sub-control units 90 corresponding to the N'+1 to Nth electrical connection structures 11 respectively turn off their respective connected first switch units 40 and second switch units 50. That is, when the number of normal electrical connection structures 11 exceeds the number of first data terminals 60 and second data terminals 70 that need to transmit data, the first sub-control unit can turn off the first switch unit 40 corresponding to the normal and unused electrical connection structure 11, and the second sub-control unit can turn off the second switch unit 50 corresponding to the normal and unused electrical connection structure 11, thereby freeing up the excess normal electrical connection structures 11 for the transmission of other signals. For example, as Figure 4 As shown, if the four first data terminals IO1 / IO2 / IO3 / IO4 are connected to the four second data terminals IO1' / IO2' / IO3' / IO4' respectively through the first four electrical connection structures TSV1 / TSV2 / TSV3 / TSV4, then the first sub-control units corresponding to the fifth and sixth electrical connection structures TSV5 and TSV6 will turn off their respective connected first switch units 40, and the second sub-control units corresponding to the fifth and sixth electrical connection structures TSV5 and TSV6 will turn off their respective connected second switch units 50.

[0191] The following is combined Figure 3 and Figure 4 The specific structures of the first sub-control unit 80 and the second sub-control unit 90 are described in detail. For example... Figure 3As shown, for TSV2, the first sub-control unit C1 corresponding to the first data terminal IO1 includes an AND gate ANDG1 and an OR gate ORG1. The input of AND gate ANDG1 is connected to the inverted output of the first detection circuit 22 corresponding to TSV1 and the output of the first detection circuit 22 corresponding to TSV2. The output of AND gate ANDG1 is connected to the control terminal of the first switching unit 40. The input of OR gate ORG1 is connected to the output of the first detection circuit 22 corresponding to TSV1 and the output of AND gate ANDG1. The first sub-control unit C2 corresponding to the first data terminal IO2 includes an AND gate ANDG2. The input of AND gate ANDG2 is connected to the output of the first detection circuit 22 corresponding to TSV1 and the output of the first detection circuit 22 corresponding to TSV2. The structures of the second sub-control unit C1' corresponding to the second data terminal IO1' and the second sub-control unit C2' corresponding to the second data terminal IO2' are similar to those of the first sub-control units C1 and C2, respectively, and will not be described in detail here.

[0192] Continue to refer to Figure 3 For TSV3, the first sub-control unit C3 corresponding to the first data terminal IO1 includes an AND gate ANDG3 and an OR gate ORG2. The input of AND gate ANDG3 is connected to the inverted output of OR gate ORG1 and the output of the first detection circuit 22 corresponding to TSV3. The output of AND gate ANDG3 is connected to the control terminal of the first switching unit 40. The input of OR gate ORG2 is connected to the output of OR gate ORG1 and the output of AND gate ANDG3. The first sub-control unit C4 corresponding to the first data terminal IO2 includes an AND gate ANDG4 and an OR gate ORG3. The input of AND gate ANDG4 is connected to the output of OR gate ORG1, the inverted output of AND gate ANDG2 and the output of the first detection circuit 22 corresponding to TSV3. The output of AND gate ANDG4 is connected to the control terminal of the first switching unit 40. The input of OR gate ORG3 is connected to the output of AND gate ANDG4 and the output of AND gate ANDG2. The structures of the second sub-control unit C3' corresponding to the second data terminal IO1' and the second sub-control unit C4' corresponding to the second data terminal IO2' are similar to those of the first sub-control units C3 and C4, respectively, and will not be described in detail here.

[0193] For TSV4, the first sub-control unit C5 corresponding to the first data terminal IO2 includes an AND gate ANDG5. The input of AND gate ANDG5 is connected to the output of OR gate ORG2, the inverted output of OR gate ORG3, and the output of the first detection circuit 22 corresponding to TSV4. The output of AND gate ANDG5 is connected to the control terminal of the first switching unit 40. The structure of the second sub-control unit C5' corresponding to the second data terminal IO2' is similar to that of the first sub-control unit C5, and will not be described again here.

[0194] In another embodiment, such as Figure 4 As shown, for TSV2, the first sub-control unit C6 corresponding to the first data terminal IO1 includes an AND gate ANDG6 and an OR gate ORG4. The input of AND gate ANDG6 is connected to the inverted output of the first detection circuit 22 corresponding to TSV1 and the output of the first detection circuit corresponding to TSV2. The output of AND gate ANDG6 is connected to the control terminal of the first switching unit 40. The input of OR gate ORG4 is connected to the output of AND gate ANDG6 and the output of the first detection circuit 22 corresponding to TSV1. The first sub-control unit C7 corresponding to the first data terminal IO2 includes an AND gate ANDG7. The input of AND gate ANDG7 is connected to the output of the first detection circuit 22 corresponding to TSV1 and the output of the first detection circuit 22 corresponding to TSV2. The output of AND gate ANDG7 is connected to the control terminal of the first switching unit 40. The structures of the second sub-control unit C6' corresponding to the second data terminal IO1' and the second sub-control unit C7' corresponding to the second data terminal IO2' are similar to those of the first sub-control units C6 and C7, respectively, and will not be described in detail here.

[0195] For TSV3, the first sub-control unit C8 corresponding to the first data terminal IO1 includes an AND gate ANDG8 and an OR gate ORG5. The input of AND gate ANDG8 is connected to the inverted output of OR gate ORG4 and the output of the first detection circuit 22 corresponding to TSV3. The output of AND gate ANDG8 is connected to the control terminal of the first switching unit 40. The input of OR gate ORG5 is connected to the output of AND gate ANDG8 and the output of OR gate ORG4. The first sub-control unit C9 corresponding to the first data terminal IO2 includes an AND gate ANDG9 and an OR gate ORG6. The input of AND gate ANDG9 is connected to the output of OR gate ORG4, the inverted output of AND gate ANDG7 and the output of the first detection circuit 22 corresponding to TSV3. The output of AND gate ANDG9 is connected to the control terminal of the first switching unit 40. The input of OR gate ORG6 is connected to the output of AND gate ANDG9 and the output of AND gate ANDG7. The first sub-control unit C10, corresponding to the first data terminal IO3, includes an AND gate ANDG10. The input of AND gate ANDG10 is connected to the output of AND gate ANDG7 and the output of the first detection circuit 22 corresponding to TSV3. The output of AND gate ANDG10 is connected to the control terminal of the first switching unit 40. The structures of the second sub-control unit C8', corresponding to the second data terminal IO1', the second sub-control unit C9', corresponding to the second data terminal IO2', and the second sub-control unit C10', corresponding to the second data terminal IO3', are similar to those of the first sub-control units C8, 9, and 10, respectively, and will not be described in detail here.

[0196] For TSV4, the first sub-control unit C11 corresponding to the first data terminal IO2 includes an AND gate ANDG11 and an OR gate ORG7. The input of AND gate ANDG11 is connected to the output of OR gate ORG5, the inverted output of OR gate ORG6, and the output of the first detection circuit 22 corresponding to TSV4. The output of AND gate ANDG11 is connected to the control terminal of the first switching unit 40. The input of OR gate ORG7 is connected to the output of AND gate ANDG11 and the output of OR gate ORG6. The first sub-control unit C12 corresponding to the first data terminal IO3 includes an AND gate ANDG12 and an OR gate ORG8. The input of AND gate ANDG12 is connected to the output of OR gate ORG6, the inverted output of AND gate ANDG10, and the output of the first detection circuit 22 corresponding to TSV4. The output of AND gate ANDG12 is connected to the control terminal of the first switching unit 40. The input of OR gate ORG8 is connected to the output of AND gate ANDG12 and the output of AND gate ANDG10. The first sub-control unit C13, corresponding to the first data terminal IO4, includes an AND gate ANDG13. The input of AND gate ANDG13 is connected to the output of AND gate ANDG10 and the output of the first detection circuit 22 corresponding to TSV4. The output of AND gate ANDG13 is connected to the control terminal of the first switching unit 40. The structures of the second sub-control units C11', C12', and C13', corresponding to the second data terminal IO2', IO3', and IO4', are similar to those of the first sub-control units C11, C12, and C13, respectively, and will not be described in detail here.

[0197] For TSV5, the first sub-control unit C14 corresponding to the first data terminal IO3 includes an AND gate ANDG14 and an OR gate ORG9. The input of AND gate ANDG14 is connected to the output of OR gate ORG7, the inverted output of OR gate ORG8, and the output of the first detection circuit corresponding to TSV5. The output of AND gate ANDG14 is connected to the control terminal of the first switching unit 40. The input of OR gate ORG9 is connected to the output of AND gate ANDG14 and the output of OR gate ORG8. The first sub-control unit C15 corresponding to the first data terminal IO4 includes an AND gate ANDG15 and an OR gate ORG10. The input of AND gate ANDG15 is connected to the output of OR gate ORG8, the inverted output of AND gate ANDG13, and the output of the first detection circuit 22 corresponding to TSV5. The output of AND gate ANDG15 is connected to the control terminal of the first switching unit 40. The input of OR gate ORG10 is connected to the output of AND gate ANDG15 and the output of AND gate ANDG13. The structures of the second sub-control unit C14' corresponding to the second data terminal IO3' and the second sub-control unit C15' corresponding to the second data terminal IO4' are similar to those of the first sub-control units C14 and C15, respectively, and will not be described in detail here.

[0198] For TSV6, the first control unit C16 corresponding to the first data terminal IO4 includes an AND gate ANDG16. The input of AND gate ANDG16 is connected to the output of OR gate ORG9, the inverted output of OR gate ORG10, and the output of the first detection circuit 22 corresponding to TSV6. The output of AND gate ANDG16 is connected to the control terminal of the first switching unit 40.

[0199] For example, the first switching unit 40 is configured to turn on in response to a high-level signal output by the corresponding first sub-control unit 80, and turn off when a low-level signal is received. For instance, the first switching unit 40 is a CMOS transmission gate; if a low level is output to the first switching unit 40, the first switching unit 40 is turned off, and if a high level is output to the first switching unit 40, the first switching unit 40 is turned on. In other embodiments, the first switching unit 40 may also be configured to turn on when the control terminal receives a low level and turn off when a high level is received; this disclosure does not limit this. The configuration of the second switching unit 50 is similar to that of the first switching unit 40, and will not be described again here.

[0200] In some embodiments, such as Figure 5 As shown, the first control signal can be output through the first flip-flop 221. For example, the first flip-flop 221 is a rising-edge flip-flop. During charging and discharging, when the voltage on the first side of the electrical connection structure 11 changes, a rising-edge signal is generated at the clock terminal of the first flip-flop 221, thereby causing the first flip-flop 221 to output a high-level first control signal. For example, as shown... Figure 5As shown, the first detection circuit 22 includes a first flip-flop 221 and a first inverter 222. The input terminal D of the first flip-flop 221 is connected to the power supply VDD. The input terminal of the first inverter 222 serves as the first terminal of the first detection circuit 22 and is connected to the first terminal of the corresponding electrical connection structure 11. The output terminal of the first inverter 222 is connected to the clock input terminal Clk of the first flip-flop 221. The output terminal of the first flip-flop 221 serves as the second terminal of the first detection circuit 22 and is connected to each first switching unit 40. In the first electrical connection structure, the output terminal Q of the first flip-flop 221 is connected to the control terminal of the first switching unit 40. In the n1th electrical connection structure, the output terminal of the first flip-flop 221 is connected to each first sub-control unit 80. When the electrical connection structure 11 is charging, its first terminal is at a high level, which, after passing through the first inverter 222, forms a low level at the clock input terminal Clk of the first flip-flop 221. When the electrical connection structure 11 discharges, its first terminal changes from a high level to a low level. After passing through the first inverter 222, a high level is formed at the clock input terminal Clk of the first flip-flop 221. Thus, a rising edge signal is detected at the clock input terminal Clk of the first flip-flop 221, and the output terminal Q of the first flip-flop 221 outputs a high level. Of course, in other embodiments, the first flip-flop 221 can also be a falling edge flip-flop or other types of flip-flops, and this disclosure does not limit this.

[0201] Similarly, such as Figure 5 As shown, the second detection circuit 32 includes a second flip-flop 321 and a second inverter 322. The input terminal of the second inverter 322 serves as the first terminal of the second detection circuit 32 and is connected to the second terminal of the corresponding electrical connection structure 11. The output terminal of the second inverter 322 is connected to the clock input terminal of the second flip-flop 321. The output terminal of the second flip-flop 321 serves as the second terminal of the second detection circuit 32 and is connected to each second switching unit 50 and each second sub-control unit 90. In the first electrical connection structure, the output terminal of the second flip-flop is connected to the control terminal of the second switching unit 50. In the n2nd electrical connection structure, the output terminal of the second flip-flop 321 is connected to each second sub-control unit. The operation of the second flip-flop 321 is similar to that of the first flip-flop 221. For details, please refer to the previous description of the first flip-flop 221, which will not be repeated here.

[0202] In an exemplary embodiment of this disclosure, such as Figure 5As shown, the first detection circuit 22 includes a first transistor 223. The input terminal of the first inverter 222 is connected to the first terminal of the first transistor 223, the second terminal of the first transistor 223 is grounded, and the gate of the first transistor 223 is connected to the inverse signal of the power-on signal. The first transistor 223 is configured such that when its gate input is high, its first and second terminals are turned on; when its gate input is low, its first and second terminals are turned off. Since the gate of the first transistor 223 is connected to the inverse signal of the power-on signal, when not powered on, the gate input of the first transistor 223 is high, causing the first and second terminals of the first transistor 223 to be turned on. Thus, the input terminal of the first inverter 222 is grounded, and the output of the first inverter 222 to the clock input terminal Clk of the first flip-flop 221 is high, i.e., the clock input terminal Clk of the first flip-flop 221 is set to "1". This ensures that before power-on, no rising edge will be generated at the clock input terminal Clk of the first flip-flop 221, that is, no high level will be output, thereby ensuring the reliability of the repair circuit of this electrical connection structure.

[0203] In one embodiment, such as Figure 5 As shown, the first detection circuit 22 also includes a third inverter 224 connected end-to-end with the first transistor 223. That is, the input terminal of the third inverter 224 is connected to the output terminal of the first inverter 222, and the output terminal of the third inverter 224 is connected to the input terminal of the first inverter 222. The two form a latch to ensure the reliability of the signal at the clock input terminal Clk of the first flip-flop 221.

[0204] Similarly, such as Figure 5 As shown, the second detection circuit 32 includes a second transistor 323. The input terminal of the second inverter 322 is connected to the first terminal of the second transistor 323, the second terminal of the second transistor 323 is grounded, and the gate of the second transistor 323 is connected to the inverted signal of the electrical signal. The second transistor 323 functions similarly to the first transistor 223. Of course, it is understandable that the second detection circuit 32 may also include a fourth inverter 324 connected end-to-end with the second transistor 323. For details, please refer to the previous description of the first transistor 223, which will not be repeated here.

[0205] In an exemplary embodiment of this disclosure, such as Figure 5As shown, the reset terminal RN of the first flip-flop 221 is connected to the inverted signal of the power-on signal. The first flip-flop 221 is used to reset its output terminal Q when it does not receive the power-on signal at its reset terminal. When the first detection circuit 22 determines that the electrical connection structure 11 is normal, it will output a high level. When the power is off, the reset terminal of the first flip-flop 221 will no longer receive the power-on signal. At this time, the output terminal Q of the first flip-flop 221 is reset, so that the output terminal Q of the first flip-flop 221 outputs a low level, thereby controlling the corresponding first switch unit 40 to disconnect, so as to ensure the effectiveness of the next power-on detection.

[0206] Similarly, such as Figure 5 As shown, the reset terminal of the second flip-flop 321 is connected to the inverse signal of the power-on signal. The second flip-flop 321 is used to reset its output terminal when it does not receive the power-on signal, so as to control the corresponding second switch units 50 to open. The operation of the reset terminal of the second flip-flop 321 is similar to that of the reset terminal of the first flip-flop 221. For details, please refer to the previous description and it will not be repeated here.

[0207] In an exemplary embodiment of this disclosure, such as Figure 5 As shown, the charging circuit 31 includes a pull-up driver for pulling the electrical connection structure 11 to a first voltage level according to the charging drive signal PDRV. Exemplarily, the pull-up driver includes a fourth transistor 311, the gate of which is connected to the charging drive signal PDRV, the first terminal of which is connected to a power supply, and the second terminal of which is connected to the second terminal of the electrical connection structure 11. The fourth transistor 311 is configured such that when its gate input is high, its first and second terminals are off, and when its gate input is low, its first and second terminals are on.

[0208] like Figure 5 As shown, the discharge circuit 21 includes a pull-down driver for pulling down the electrical connection structure 11 to a second voltage level according to the discharge drive signal NDRV. Exemplarily, the pull-down driver includes a third transistor 211, the gate of which is connected to the discharge drive signal NDRV, the first terminal of which is grounded, and the second terminal of which is connected to the first terminal of the electrical connection structure 1. The third transistor 211 is configured such that when its gate input is high, its first and second terminals are turned on, and when its gate input is low, its first and second terminals are turned off.

[0209] The following is combined Figure 6 The timing diagram shown illustrates the specific operation of the first detection circuit 22, such as... Figure 6As shown, before point A (power-on), the power-on signal is low, the reset terminal RN of the first flip-flop 221 is high, and the output of the first flip-flop 221 is "0". The inverted signal of the power-on signal... When the clock signal is high, the first transistor 223 is turned on, grounding the input of the first inverter 222. The first inverter 222 outputs a high level to the clock input Clk of the first flip-flop 221, thus setting the clock input Clk to "1". After power-on (after point A), the power-on signal is high, the reset terminal RN of the first flip-flop 221 is low, and the first transistor 223 is off. When the charging drive signal PDRV outputs a low level (i.e., point B), the fourth transistor 311 is turned on, charging the electrical connection structure 11. Simultaneously, the input of the first inverter 222 is high, and the first inverter 222 outputs a low level to the clock input Clk of the first flip-flop 221, thus setting the clock input Clk to "0". At point C, the charging drive signal PDRV output changes from low to high, causing the fourth transistor 311 to turn off. When the discharge drive signal NDRV outputs a high level (i.e., point D), the third transistor 211 turns on, thereby discharging the electrical connection structure 11. The input terminal of the first inverter 222 becomes low, and the output of the first inverter 222 to the clock input terminal Clk of the first flip-flop 221 changes from low to high, thus generating a rising edge at the clock input terminal Clk, and the first flip-flop 221 outputs a high level (TSV on). The operation of the second detection circuit 32 is similar to that of the first detection circuit 22, and will not be described again here.

[0210] An exemplary embodiment of this disclosure also provides a control method for a repair circuit of an electrical connection structure. This control method can be applied to the control of the repair circuit of the aforementioned electrical connection structure, such as... Figure 7 As shown, the control methods include:

[0211] S100, Detect the voltage change at the first and second terminals of each electrical connection structure;

[0212] S200: Control the electrical connection structure to be connected or disconnected from the corresponding first data terminal according to the voltage change of the first terminal of each electrical connection structure, and control the electrical connection structure to be connected or disconnected from the corresponding second data terminal according to the voltage change of the second terminal of each electrical connection structure, so that the electrical connection structure is selectively connected to the first data terminal or disconnected from all the first data terminals, and selectively connected to the second data terminal or disconnected from all the second data terminals.

[0213] When the two ends of the electrical connection structure are respectively connected to a first data terminal and a second data terminal, the control data signal is transmitted from the connected first data terminal to the second data terminal, or the control data signal is transmitted from the connected second data terminal to the first data terminal.

[0214] In this embodiment, the electrical connection structure can be controlled to be switched on or off with the first data terminal and the second data terminal respectively based on the voltage changes at both ends of the electrical connection structure. Therefore, after being switched on, the data signal can be transmitted from the first data terminal to the second data terminal, and vice versa, thereby realizing bidirectional data transmission. This improves the performance of electrical devices, such as semiconductor devices, in the repair circuit using this electrical connection structure. When some of the electrical connection structures are short-circuited, both ends are disconnected to isolate them from other electrical connection structures, so the current will not affect other electrical connection structures, thus ensuring data transmission performance. In addition, the electrical connection structure is selectively switched on with the first data terminal and selectively switched on with the second data terminal, realizing mutual redundancy between the electrical connection structures while ensuring the independence between data transmission paths.

[0215] In one embodiment, detecting voltage changes at the first and second terminals of each of the electrical connection structures includes:

[0216] The charging circuit sets the first and second terminals of the electrical connection structure to a first voltage level.

[0217] The first and second terminals of the electrical connection structure are set to a second voltage level by a discharge circuit.

[0218] Controlling the connection or disconnection of the electrical connection structure with its corresponding first data terminal based on the voltage change at the first terminal of each electrical connection structure, and controlling the connection or disconnection of the electrical connection structure with its corresponding second data terminal based on the voltage change at the second terminal of each electrical connection structure, including:

[0219] In response to the voltage at the first terminal of the electrical connection structure changing from a first voltage level to a second voltage level, the first detection circuit controls the electrical connection structure to selectively connect to the first data terminal.

[0220] In response to the voltage at the second terminal of the electrical connection structure changing from the first voltage level to the second voltage level, the second detection circuit controls the electrical connection structure to selectively connect to the second data terminal.

[0221] In this embodiment, the process of charging and discharging the electrical connection structure through the charging circuit and the discharging circuit, as well as the process of controlling the electrical connection structure to selectively connect to the first data terminal through the first detection circuit and the process of controlling the electrical connection structure to selectively connect to the second data terminal through the second detection circuit, can be referred to the relevant description in the previous description of the electrical connection structure repair circuit, and will not be repeated here.

[0222] The first data terminal, the electrical connection structure, and the second data terminal are connected by a control circuit to form a data transmission path. The control circuit sequentially controls the connection of each data transmission path according to the sequence number of the electrical connection structure corresponding to the data transmission path, and transmits data signals in each data transmission path. This facilitates the selection of the data transmission path and ensures the reliability of data signal transmission. For example, the repair circuit for the electrical connection structure has first data terminals IO1 to IO4, electrical connection structures TSV1 to TSV5, and second data terminals IO1' to IO4'. If the first, second, third, and fifth electrical connection structures are normal, and the fourth electrical connection structure is faulty, then the first data terminal IO1, electrical connection structure TSV1, and second data terminal IO1' are connected through the control circuit to form data transmission path 1; the first data terminal IO2, electrical connection structure TSV2, and second data terminal IO2' are connected through the control circuit to form data transmission path 2; the first data terminal IO3, electrical connection structure TSV3, and second data terminal IO3' are connected through the control circuit to form data transmission path 3; and the first data terminal IO4, electrical connection structure TSV5, and second data terminal IO4' are connected through the control circuit to form data transmission path 4. The control circuit controls the connection of each data transmission path sequentially according to the sequence number of the electrical connection structure corresponding to the data transmission path, that is, sequentially connects data transmission path 1, data transmission path 2, data transmission path 3, and data transmission path 4, thereby transmitting data signals in the connected data transmission paths.

[0223] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0224] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0225] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0226] In this disclosure, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase “comprising…” does not exclude the presence of additional identical elements in the article or device that includes said element.

[0227] Although preferred embodiments of the present disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0228] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, the intent of this disclosure also includes these modifications and variations.

Claims

1. A repair circuit with an electrical connection structure, characterized in that, include: An electrical connection module, including the 1st, 2nd, ..., Nth electrical connection structures, where N is a positive integer greater than or equal to 3; M first data terminals are located on the first side of the electrical connection module. Each first data terminal is connected to the first terminal of at least two electrical connection structures through at least two first switch units. At least one of the electrical connection structures is connected to at least two first data terminals. M second data terminals are located on the second side of the electrical connection module and correspond one-to-one with the M first data terminals. Each second data terminal is connected one-to-one with the second terminal of at least two electrical connection structures through at least two second switch units, and corresponds to the connection relationship between the M first data terminals and the electrical connection structures. At least one of the electrical connection structures is connected to at least two second data terminals, where M is a positive integer greater than or equal to 2 and less than N. A first control circuit is used to control each of the first switch units to be turned on or off according to the voltage change of the first terminal of each of the electrical connection structures. When one of the first switch units connected to the same first data terminal is turned on, the other first switch units connected to the first data terminal are turned off. The second control circuit is used to control each second switch unit to be turned on or off according to the voltage change of the second terminal of each electrical connection structure. When one of the second switch units connected to the same second data terminal is turned on, the other second switch units connected to the second data terminal are turned off. Two adjacent first data terminals are respectively connected to at least one of the same electrical connection structures via the first switching unit; Two adjacent second data terminals are respectively connected to at least one of the same electrical connection structures via the second switching unit; The first control circuit is configured to control the on or off of each of the first switch units connected to each of the first data terminals; For each of the first data terminals, the first control circuit is used to control the first switch unit corresponding to the electrical connection structure with the earlier serial number and in normal working state among the unoccupied electrical connection structures connected to it to be turned on. The second control circuit is configured to control the on or off state of each of the second switch units connected to each of the second data terminals; Specifically, for each of the second data terminals, the second control circuit is used to control the second switch unit corresponding to the electrical connection structure with the earlier serial number and in normal working state among the unoccupied electrical connection structures connected to it to be turned on.

2. The repair circuit for the electrical connection structure according to claim 1, characterized in that, The first data terminal is connected to the first terminal of the first, ..., R electrical connection structures respectively through R first switch units; The i-th first data terminal is connected to the first terminal of the i-th, ..., (i+R-1)-th electrical connection structure through R first switch units respectively; The first second data terminal is connected to the second terminal of the first, ..., R electrical connection structures respectively through R second switch units; The j-th second data terminal is connected to the second terminal of the j-th, ..., (j+R-1)-th electrical connection structure through R second switch units respectively; Where i is a positive integer greater than or equal to 2, j is a positive integer greater than or equal to 2, and R is a positive integer greater than or equal to 2.

3. The repair circuit for the electrical connection structure according to claim 2, characterized in that, The first control circuit includes N discharge circuits and N first detection circuits. The first terminals of the N first detection circuits and the N discharge circuits are respectively connected to the first terminals of the N electrical connection structures. The second terminal of each first detection circuit is connected to each of the first switching units of the corresponding electrical connection structure. The second control circuit includes N charging circuits and N second detection circuits. The first terminals of the N second detection circuits and the N charging circuits are respectively connected to the second terminals of the N electrical connection structures. The second terminal of each second detection circuit is connected to each of the second switching units of the corresponding electrical connection structure. The charging circuit is used to charge the corresponding electrical connection structure to a first voltage level, and the discharging circuit is used to discharge the corresponding electrical connection structure to a second voltage level. The first detection circuit is used to generate a first control signal based on the voltage level change at the first terminal of the connected electrical connection structure. The first control signal is output from the second terminal of the first detection circuit and is used to control the conduction or deactivation of each of the first switching units corresponding to the electrical connection structure. The second detection circuit is used to generate a second control signal based on the voltage level change at the second terminal of the connected electrical connection structure. The second control signal is output from the second terminal of the second detection circuit and is used to control the conduction or shutdown of each of the second switching units corresponding to the electrical connection structure.

4. The repair circuit for the electrical connection structure according to claim 3, characterized in that, The first control circuit includes a plurality of first sub-control units that are connected one-to-one with each of the first switch units. The first sub-control units are used to control the conduction and closing of the first switch units connected to them. Each first data terminal corresponds to R first sub-control units. For the first data terminal, The first first control unit corresponding to the first first data terminal is used to control the first first switch unit connected to it to turn on or off according to the first control signal of the first first detection circuit. The m1th first sub-control unit corresponding to the first first data terminal is used to control the first switch unit connected to it to turn on or off according to the first control signal of the m1th first detection circuit and the output signal of the (m1-1)th first sub-control unit corresponding to it. For the m2th first data terminal The first sub-control unit corresponding to the m2th first data terminal is used to control the first first switch unit connected to it to turn on or off according to the first control signal of the m2th first detection circuit and the output signal of the first sub-control unit corresponding to the (m2-1)th first data terminal. The m1th first sub-control unit corresponding to the m2th first data terminal is used to control the first switch unit connected to it to turn on or off according to the first control signal of the (m2+m1-1)th first detection circuit, the output signal of the (m1-1)th first sub-control unit corresponding to it, and the output signal of the (m1-1)th first sub-control unit corresponding to the (m2-1)th first data terminal. The second control circuit includes a plurality of second sub-control units connected in a one-to-one correspondence with each of the second switch units. The second sub-control units are used to control the conduction and closing of the second switch units connected to them. Each second data terminal corresponds to R second sub-control units. For the first second data terminal, The first second control unit corresponding to the first second data terminal is used to control the second switch unit connected to it to turn on or off according to the second control signal of the first second detection circuit; The m1th second sub-control unit corresponding to the first second data terminal is used to control the second switch unit connected to it to turn on or off according to the second control signal of the m1th second detection circuit and the output signal of the (m1-1)th second sub-control unit. For the m2th second data terminal The first second sub-control unit corresponding to the m2th second data terminal is used to control the second switch unit connected to it to turn on or off according to the second control signal of the m2th second detection circuit and the output signal of the first second sub-control unit corresponding to the (m2-1)th second data terminal. The m1th second sub-control unit corresponding to the m2th second data terminal is used to control the second switch unit connected to it to turn on or off according to the second control signal of the (m2+m1-1)th second detection circuit, the output signal of the (m1-1)th second sub-control unit, and the output signal of the (m1-1)th second sub-control unit of the (m2-1)th second data terminal. Where m1 is a positive integer greater than or equal to 2 and less than or equal to R, and m2 is a positive integer greater than or equal to 2 and less than or equal to M.

5. The repair circuit for the electrical connection structure according to claim 4, characterized in that, For the first data terminal, The first first data terminal corresponds to the first first sub-control unit, which includes a first node. The input terminal of the first node is connected to the output terminal of the first first detection circuit, and the output terminal of the first node serves as the control terminal of the corresponding first switch unit. When m1 is less than R, the m1th first sub-control unit corresponding to the first first data terminal includes a first AND gate and a first OR gate. The input terminal of the first AND gate is connected to the inverted signal of the output terminal of the first node and the output terminal of the m1th first detection circuit, respectively. The output terminal of the first AND gate is connected to the control terminal of the corresponding first switch unit. The input terminal of the first OR gate is connected to the output terminal of the first node and the output terminal of the first AND gate, respectively. The output terminal of the first OR gate serves as the output terminal of the m1th first sub-control unit. The Rth first sub-control unit corresponding to the first first data terminal includes a second AND gate and a second OR gate. The input terminal of the second AND gate is connected to the inverted signal of the output terminal of the first OR gate and the output terminal of the Rth first detection circuit, respectively. The output terminal of the second AND gate is connected to the control terminal corresponding to the first switch unit. The input terminal of the second OR gate is connected to the output terminal of the first OR gate and the output terminal of the second AND gate, respectively. The output terminal of the second OR gate serves as the output terminal of the Rth first sub-control unit corresponding to the first first data terminal and is connected to the Rth first sub-control unit corresponding to the second first data terminal. When m2 is less than M, for the m2th first data terminal, The first sub-control unit corresponding to the m2th first data terminal includes a third AND gate. The input terminal of the third AND gate is connected to the output terminal of the m2th first detection circuit and the output terminal of the first sub-control unit corresponding to the (m2-1)th first data terminal. The output terminal of the third AND gate serves as the output terminal of the first sub-control unit corresponding to the m2th first data terminal and is connected to the control terminal of the corresponding first switch unit and the corresponding second sub-control unit. When m1 is less than R, the m1th first sub-control unit corresponding to the m2th first data terminal includes a fourth AND gate and a third OR gate. The input terminal of the fourth AND gate is connected to the output terminal of the (m2+m1-1)th first detection circuit, the inverted signal of the output terminal of the corresponding (m1-1)th first sub-control unit, and the output terminal of the m1th first sub-control unit corresponding to the (m2-1)th first data terminal. The output terminal of the fourth AND gate is connected to the control terminal of the corresponding first switch unit and the third OR gate. The input terminal of the third OR gate is connected to the output terminal of the corresponding (m1-1)th first sub-control unit and the output terminal of the fourth AND gate. The output terminal of the third OR gate serves as the output terminal of the m1th first sub-control unit corresponding to the m2th first data terminal and is connected to the corresponding m1+1th first sub-control unit. The Rth first sub-control unit corresponding to the m2th first data terminal includes a fifth AND gate and a fourth OR gate. The input of the fifth AND gate is connected to the output of the (R+m1-1)th first detection circuit, the inverted signal of the output of the corresponding (R-1)th first sub-control unit, and the output of the Rth first sub-control unit of the (m2-1)th first data terminal. The output of the fifth AND gate is connected to the control terminal of the corresponding first switch unit and the fourth OR gate. The input of the fourth OR gate is connected to the output of the corresponding (R-1)th first sub-control unit and the output of the fifth AND gate. The output of the fourth OR gate serves as the output of the Rth first sub-control unit corresponding to the m2th first data terminal and is connected to the Rth first sub-control unit of the m2+1th first data terminal. For the Mth first data terminal The first sub-control unit corresponding to the Mth first data terminal includes a sixth AND gate. The input terminal of the sixth AND gate is connected to the output terminal of the Mth first detection circuit and the first sub-control unit corresponding to the (M-1)th first data terminal. The output terminal of the sixth AND gate serves as the output terminal of the first sub-control unit corresponding to the Mth first data terminal and is connected to the control terminal of the corresponding first switch unit and the corresponding second sub-control unit. When m1 is less than R, the m1th first sub-control unit corresponding to the Mth first data terminal includes a seventh AND gate and a fifth OR gate. The input of the seventh AND gate is connected to the output of the (M+m1-1)th first detection circuit, the inverted signal of the output of the (m1-1)th first sub-control unit, and the m1th first sub-control unit corresponding to the (M-1)th first data terminal. The output of the seventh AND gate is connected to the control terminal of the corresponding first switch unit and the fifth OR gate. The input of the fifth OR gate is connected to the output of the (m1-1)th first sub-control unit and the output of the seventh AND gate. The output of the fifth OR gate serves as the output of the m1th first sub-control unit corresponding to the Mth first data terminal and is connected to the (m1+1)th first sub-control unit. The first control unit corresponding to the Mth first data terminal includes an eighth AND gate. The input terminal of the eighth AND gate is connected to the output terminal of the (R+M-1)th first detection circuit, the inverted signal of the output terminal of the corresponding R-1th first control unit, and the output terminal of the Rth first control unit of the M-1th first data terminal. The output terminal of the eighth AND gate is connected to the control terminal of the corresponding first switch unit. For each of the second data terminals, the R second sub-control units corresponding to the second data terminal have the same structure as the R first sub-control units corresponding to the first data terminal.

6. The repair circuit for the electrical connection structure according to claim 4, characterized in that, When the Mth first data terminal is connected to the Mth second data terminal through the N'th electrical connection structure, if N' is less than N, the first sub-control unit and the second sub-control unit corresponding to the N'+1 to Nth electrical connection structures respectively turn off their respective connected first switch unit and second switch unit.

7. The repair circuit for the electrical connection structure according to claim 4, characterized in that, The first detection circuit includes a first flip-flop and a first inverter. The input terminal of the first inverter serves as the first terminal of the first detection circuit and is connected to the first terminal of the corresponding electrical connection structure. The output terminal of the first inverter is connected to the clock input terminal of the first flip-flop. The output terminal of the first flip-flop serves as the second terminal of the first detection circuit and is connected to each first switching unit and each first sub-control unit. The second detection circuit includes a second flip-flop and a second inverter. The input terminal of the second inverter serves as the first terminal of the second detection circuit and is connected to the second terminal of the corresponding electrical connection structure. The output terminal of the second inverter is connected to the clock input terminal of the second flip-flop. The output terminal of the second flip-flop serves as the second terminal of the second detection circuit and is connected to each second switching unit and each second sub-control unit.

8. The repair circuit for the electrical connection structure according to claim 7, characterized in that, The first flip-flop is a rising edge flip-flop and outputs a high-level signal in response to a rising edge signal; The second flip-flop is a rising edge flip-flop and outputs a high-level signal in response to a rising edge signal.

9. The repair circuit for the electrical connection structure according to claim 7, characterized in that, The first switching unit is turned on in response to the high-level signal output by the corresponding first sub-control unit; The second switching unit is turned on in response to the high-level signal output by the corresponding first sub-control unit.

10. The repair circuit for the electrical connection structure according to claim 7, characterized in that, The first detection circuit further includes a first transistor, the first terminal of the first transistor is connected to the input terminal of the first inverter, the second terminal of the first transistor is grounded, and the gate of the first transistor is connected to the inverted signal of the power-on signal. The second detection circuit further includes a second transistor, the first terminal of which is connected to the input terminal of the second inverter, the second terminal of which is grounded, and the gate of which is connected to the inverted signal of the power-on signal.

11. The repair circuit for the electrical connection structure according to claim 7, characterized in that, The reset terminal of the first flip-flop is connected to a power-on signal, and the first flip-flop is used to reset its output terminal when it receives a power-on signal at its reset terminal; The reset terminal of the second flip-flop is connected to a power-on signal, and the second flip-flop is used to reset its output terminal when it receives a power-on signal at its reset terminal.

12. The repair circuit for the electrical connection structure according to any one of claims 1 to 2, characterized in that, The electrical connection structure is a through-silicon via (TSV) structure. The M first data terminals and the first control circuit are disposed in the first semiconductor chip, and the M second data terminals and the second control circuit are disposed in the second semiconductor chip.

13. A repair circuit with an electrical connection structure, characterized in that, include: An electrical connection module, including the 1st, 2nd, ..., Nth electrical connection structures, where N is a positive integer greater than or equal to 3; M first data terminals are located on the first side of the electrical connection module. Each first data terminal is connected to the first terminal of at least two electrical connection structures through at least two first switch units. At least one of the electrical connection structures is connected to at least two first data terminals. M second data terminals are located on the second side of the electrical connection module and correspond one-to-one with the M first data terminals. Each second data terminal is connected one-to-one with the second terminal of at least two electrical connection structures through at least two second switch units, and corresponds to the connection relationship between the M first data terminals and the electrical connection structures. At least one of the electrical connection structures is connected to at least two second data terminals, where M is a positive integer greater than or equal to 2 and less than N. A first control circuit is used to control each of the first switch units to be turned on or off according to the voltage change of the first terminal of each of the electrical connection structures. When one of the first switch units connected to the same first data terminal is turned on, the other first switch units connected to the first data terminal are turned off. The second control circuit is used to control each second switch unit to be turned on or off according to the voltage change of the second terminal of each electrical connection structure. When one of the second switch units connected to the same second data terminal is turned on, the other second switch units connected to the second data terminal are turned off. Two adjacent first data terminals are respectively connected to at least one of the same electrical connection structures via the first switching unit; Two adjacent second data terminals are respectively connected to at least one of the same electrical connection structures via the second switching unit; The first data terminal is connected to the first terminal of the first, ..., R electrical connection structures respectively through R first switch units; The i-th first data terminal is connected to the first terminal of the i-th, ..., (i+R-1)-th electrical connection structure through R first switch units respectively; The first second data terminal is connected to the second terminal of the first, ..., R electrical connection structures respectively through R second switch units; The j-th second data terminal is connected to the second terminal of the j-th, ..., (j+R-1)-th electrical connection structure through R second switch units respectively; Where i is a positive integer greater than or equal to 2, j is a positive integer greater than or equal to 2, and R is a positive integer greater than or equal to 2; The first control circuit includes N discharge circuits and N first detection circuits. The first terminals of the N first detection circuits and the N discharge circuits are respectively connected to the first terminals of the N electrical connection structures. The second terminal of each first detection circuit is connected to each of the first switching units of the corresponding electrical connection structure. The second control circuit includes N charging circuits and N second detection circuits. The first terminals of the N second detection circuits and the N charging circuits are respectively connected to the second terminals of the N electrical connection structures. The second terminal of each second detection circuit is connected to each of the second switching units of the corresponding electrical connection structure. The charging circuit is used to charge the corresponding electrical connection structure to a first voltage level, and the discharging circuit is used to discharge the corresponding electrical connection structure to a second voltage level. The first detection circuit is used to generate a first control signal based on the voltage level change at the first terminal of the connected electrical connection structure. The first control signal is output from the second terminal of the first detection circuit and is used to control the conduction or deactivation of each of the first switching units corresponding to the electrical connection structure. The second detection circuit is used to generate a second control signal based on the voltage level change at the second terminal of the connected electrical connection structure. The second control signal is output from the second terminal of the second detection circuit and is used to control the conduction or shutdown of each of the second switching units corresponding to the electrical connection structure.

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