Undervoltage lockout circuit

Abstract

Embodiments of the present disclosure provide an under-voltage lockout circuit, which comprises a voltage sampling circuit, a comparison circuit, and a hysteresis control circuit. The voltage sampling circuit samples a voltage under test and provides a sampled voltage to the comparison circuit via a first node. The sampled voltage is obtained by dividing the voltage under test with at least two transistors. The comparison circuit compares the sampled voltage with a reference voltage from a reference voltage terminal and generates an under-voltage lockout indication signal based on the comparison result. An active level of the under-voltage lockout indication signal is used to indicate that a circuit using the voltage under test enters an under-voltage lockout state. The hysteresis control circuit causes the under-voltage lockout indication signal to flip from an inactive level to the active level when the voltage under test rises to a first preset voltage value, and causes the under-voltage lockout indication signal to flip from the active level to the inactive level when the voltage under test falls from the first preset voltage value to a second preset voltage value. The first preset voltage value is higher than the second preset voltage value.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to undervoltage lockout circuits. Background Technology

[0002] To provide a stable and reliable power supply to application systems, power management chips can be used. These chips include an undervoltage lockout (UVLO) circuit. The UVLO circuit outputs an undervoltage lockout signal to control the power management chip. When the power supply voltage to the chip falls below a preset value, the chip stops operating and enters a locked state. Until the power supply voltage is sufficient to drive the chip to operate stably, the internal control signals of the power management chip are locked, preventing it from activating.

[0003] During the startup process of a power management chip, its power supply voltage steadily rises. Once it reaches its turn-on voltage, the power management chip begins operation. However, internal circuitry or the load may pull the power supply voltage below the turn-on voltage, causing the chip to malfunction. In this case, the undervoltage lockout circuit must also lock the internal control signal of the power management chip to prevent it from activating.

[0004] In power management chips, stable power supply voltage is paramount. Therefore, undervoltage lockout circuits need to be integrated within the power management chip to improve power supply reliability and safety. For other integrated circuits, undervoltage lockout circuits are equally important for improving circuit reliability and stability. Summary of the Invention

[0005] The embodiments described herein provide an undervoltage lockout circuit.

[0006] According to a first aspect of this disclosure, an undervoltage lockout circuit is provided. The undervoltage lockout circuit includes a voltage sampling circuit, a comparator circuit, and a hysteresis control circuit. The voltage sampling circuit is configured to sample a voltage to be measured from a voltage to be measured terminal and provide the sampled voltage to the comparator circuit via a first node. The sampled voltage is obtained by dividing the voltage to be measured using at least two transistors. The comparator circuit is configured to compare the sampled voltage with a reference voltage from a reference voltage terminal, generate an undervoltage lockout indication signal based on the comparison result, and output the undervoltage lockout indication signal from its output terminal. The active level of the undervoltage lockout indication signal is used to indicate that the circuit using the voltage to be measured has entered an undervoltage lockout state. The hysteresis control circuit is configured to flip the undervoltage lockout indication signal from an inactive level to an active level when the voltage to be measured rises to a first preset voltage value, and to flip the undervoltage lockout indication signal from an active level to an inactive level when the voltage to be measured falls from the first preset voltage value to a second preset voltage value. The first preset voltage value is higher than the second preset voltage value.

[0007] In some embodiments of this disclosure, the voltage sampling circuit includes a first transistor and a second transistor. The control electrode of the first transistor is coupled to its second electrode. The first electrode of the first transistor is coupled to the voltage being measured. The control electrode and the second electrode of the second transistor are coupled to a second voltage terminal. The first electrode of the second transistor is coupled to the second electrode of the first transistor and a first node.

[0008] In some embodiments of this disclosure, the voltage sampling circuit includes a first transistor to a fifth transistor. The control electrode of the first transistor is coupled to the second electrode of the third transistor and the first electrode of the fourth transistor. The first electrode of the first transistor is coupled to the voltage being measured. The second electrode of the first transistor is coupled to the second electrode of the fourth transistor. The control electrode and the second electrode of the second transistor are coupled to a second voltage terminal.

[0009] The first terminal of the second transistor is coupled to the second terminal and the first node of the first transistor. The control terminal and the first terminal of the third transistor are coupled to the first terminal of the first transistor. The control terminal of the fourth transistor is provided with an inverted enable signal. The enable signal is used to enable the undervoltage lockout circuit. The control terminal of the fifth transistor is provided with an inverted enable signal. The first terminal of the fifth transistor is coupled to the second voltage terminal. The second terminal of the fifth transistor is coupled to the first terminal of the second transistor.

[0010] In some embodiments of this disclosure, the voltage sampling circuit further includes a capacitor. A first terminal of the capacitor is coupled to a first node. A second terminal of the capacitor is coupled to a second voltage terminal.

[0011] In some embodiments of this disclosure, the hysteresis control circuit includes a sixth transistor. The control electrode of the sixth transistor is coupled to an output terminal. The first electrode of the sixth transistor is coupled to a first node. The second electrode of the sixth transistor is coupled to a second voltage terminal.

[0012] In some embodiments of this disclosure, the comparator circuit includes: a seventh transistor through an eleventh transistor. The control electrode of the seventh transistor is coupled to a reference voltage terminal. The first electrode of the seventh transistor is coupled to the first electrode of the tenth transistor and the second electrode of the eleventh transistor. The second electrode of the seventh transistor is coupled to the control electrode and the second electrode of the eighth transistor. The first electrode of the eighth transistor is coupled to the first electrode of the ninth transistor and a first voltage terminal. The control electrode of the ninth transistor is coupled to the control electrode of the eighth transistor. The second electrode of the ninth transistor is coupled to the second electrode of the tenth transistor. The control electrode of the tenth transistor is coupled to a first node. The control electrode of the eleventh transistor is coupled to a bias voltage terminal. The first electrode of the eleventh transistor is coupled to a second voltage terminal.

[0013] In some embodiments of this disclosure, the comparison circuit further includes a twelfth transistor and a thirteenth transistor. The control electrode of the twelfth transistor is coupled to the second electrode of the ninth transistor. The first electrode of the twelfth transistor is coupled to a first voltage terminal. The second electrode of the twelfth transistor is coupled to the second electrode of the thirteenth transistor. The control electrode of the thirteenth transistor is coupled to a bias voltage terminal. The first electrode of the thirteenth transistor is coupled to a second voltage terminal.

[0014] In some embodiments of this disclosure, the comparison circuit further includes fourteenth to seventeenth transistors. The control terminal of the fourteenth transistor is coupled to the second terminal of the twelfth transistor. The first terminal of the fourteenth transistor is coupled to a first voltage terminal. The second terminal of the fourteenth transistor is coupled to the second terminal of the fifteenth transistor. The control terminal of the fifteenth transistor is coupled to the second terminal of the twelfth transistor. The first terminal of the fifteenth transistor is coupled to a second voltage terminal. The control terminal of the sixteenth transistor is coupled to the second terminal of the fourteenth transistor. The first terminal of the sixteenth transistor is coupled to the first voltage terminal. The second terminal of the sixteenth transistor is coupled to the second terminal of the seventeenth transistor. The control terminal of the seventeenth transistor is coupled to the second terminal of the fourteenth transistor. The first terminal of the seventeenth transistor is coupled to a second voltage terminal.

[0015] In some embodiments of this disclosure, the undervoltage lockout circuit further includes a bias voltage generating circuit. The bias voltage generating circuit includes transistors eighteen through thirty-first and a resistor. The control terminal of transistor eighteen is coupled to a second voltage terminal. The first terminal of transistor eighteen is coupled to a third voltage terminal. The second terminal of transistor eighteen is coupled to the first terminal of transistor nineteen. The control terminal of transistor nineteen is coupled to a second voltage terminal. The second terminal of transistor nineteen is coupled to the first terminal of transistor twentieth. The control terminal of transistor twentieth is coupled to a second voltage terminal. The second terminal of transistor twentieth is coupled to the first terminal of transistor twentieth. The control terminal of transistor twentieth is coupled to a second voltage terminal. The second terminal of transistor twentieth is coupled to the control terminal of transistor twentieth and the second terminal of transistor twentieth. The first terminal of transistor twentieth is coupled to the first terminal of transistor twentieth. The second terminal of transistor twentieth is coupled to the control terminal of transistor twentieth and the second terminal of transistor twentieth. The control terminal of transistor twentieth is coupled to the second terminal of transistor twentieth. The first terminal of transistor twentieth is coupled to a test voltage terminal. The first terminal of transistor twentieth is coupled to a second voltage terminal. The first terminal of transistor twentieth is coupled to a third voltage terminal. The control and second terminals of transistor 26 are coupled to the second terminal of transistor 27. The first terminal of transistor 26 is coupled to the second terminal of transistor 25. The first terminal of transistor 27 is coupled to the first terminal of a resistor. The second terminal of the resistor is coupled to the second terminal of transistor 28. The control terminal of transistor 28 is coupled to the test voltage terminal. The first terminal of transistor 28 is coupled to the second voltage terminal. The control terminal of transistor 29 is coupled to the control terminal of transistor 25. The first terminal of transistor 29 is coupled to the third voltage terminal. The second terminal of transistor 29 is coupled to the control and second terminals of transistor 30. The first terminal of transistor 30 is coupled to the control and second terminals of transistor 31. The control terminal of transistor 31 is coupled to the bias voltage terminal. The first terminal of transistor 31 is coupled to the second voltage terminal.

[0016] According to a second aspect of this disclosure, an undervoltage lockout circuit is provided. The undervoltage lockout circuit includes: a first transistor to a thirty-first transistor, a capacitor, and a resistor. The control electrode of the first transistor is coupled to the second electrode of the third transistor and the first electrode of the fourth transistor. The first electrode of the first transistor is coupled to a test voltage terminal. The second electrode of the first transistor is coupled to the second electrode of the fourth transistor. The control electrode and the second electrode of the second transistor are coupled to a second voltage terminal. The first electrode of the second transistor is coupled to the second electrode of the first transistor and the control electrode of the tenth transistor. The control electrode and the first electrode of the third transistor are coupled to the first electrode of the first transistor. The control electrode of the fourth transistor is provided with an inverted enable signal. The enable signal is used to enable the undervoltage lockout circuit. The control electrode of the fifth transistor is provided with an inverted enable signal. The first electrode of the fifth transistor is coupled to the second voltage terminal. The second electrode of the fifth transistor is coupled to the first electrode of the second transistor. The first terminal of the capacitor is coupled to the first electrode of the second transistor. The second terminal of the capacitor is coupled to the second voltage terminal. The control electrode of the sixth transistor is coupled to an output terminal. The first electrode of the sixth transistor is coupled to the first electrode of the second transistor. The second electrode of the sixth transistor is coupled to the second voltage terminal. The control electrode of the seventh transistor is coupled to a reference voltage terminal. The first terminal of the seventh transistor is coupled to the first terminal of the tenth transistor and the second terminal of the eleventh transistor. The second terminal of the seventh transistor is coupled to the control terminal and the second terminal of the eighth transistor. The first terminal of the eighth transistor is coupled to the first terminal and the first voltage terminal of the ninth transistor. The control terminal of the ninth transistor is coupled to the control terminal of the eighth transistor. The second terminal of the ninth transistor is coupled to the second terminal of the tenth transistor. The control terminal of the eleventh transistor is coupled to the control terminal of the thirty-first transistor. The first terminal of the eleventh transistor is coupled to the second voltage terminal. The control terminal of the twelfth transistor is coupled to the second terminal of the ninth transistor. The first terminal of the twelfth transistor is coupled to the first voltage terminal. The second terminal of the twelfth transistor is coupled to the second terminal of the thirteenth transistor. The control terminal of the thirteenth transistor is coupled to the control terminal of the thirty-first transistor. The first terminal of the thirteenth transistor is coupled to the second voltage terminal. The control terminal of the fourteenth transistor is coupled to the second terminal of the twelfth transistor. The first terminal of the fourteenth transistor is coupled to the first voltage terminal. The second terminal of the fourteenth transistor is coupled to the second terminal of the fifteenth transistor. The control terminal of the fifteenth transistor is coupled to the second terminal of the twelfth transistor. The first terminal of the fifteenth transistor is coupled to the second voltage terminal. The control terminal of the sixteenth transistor is coupled to the second terminal of the fourteenth transistor. The first terminal of the sixteenth transistor is coupled to the first voltage terminal. The second terminal of the sixteenth transistor is coupled to the second terminal and the output terminal of the seventeenth transistor. The control terminal of the seventeenth transistor is coupled to the second terminal of the fourteenth transistor. The first terminal of the seventeenth transistor is coupled to the second voltage terminal. The control terminal of the eighteenth transistor is coupled to the second voltage terminal. The first terminal of the eighteenth transistor is coupled to the third voltage terminal. The second terminal of the eighteenth transistor is coupled to the first terminal of the nineteenth transistor. The control terminal of the nineteenth transistor is coupled to the second voltage terminal. The second terminal of the nineteenth transistor is coupled to the first terminal of the twentieth transistor.The control terminal of the 20th transistor is coupled to the second voltage terminal. The second terminal of the 20th transistor is coupled to the first terminal of the 21st transistor. The control terminal of the 21st transistor is coupled to the second voltage terminal. The second terminal of the 21st transistor is coupled to the control terminal of the 22nd transistor and the second terminal of the 23rd transistor. The first terminal of the 22nd transistor is coupled to the first terminal of the 23rd transistor. The second terminal of the 22nd transistor is coupled to the control terminal and the second terminal of the 25th transistor. The control terminal of the 23rd transistor is coupled to the control terminals of the 27th and 31st transistors. The first terminal of the 23rd transistor is coupled to the second terminal of the 24th transistor. The control terminal of the 24th transistor is coupled to the test voltage terminal. The first terminal of the 24th transistor is coupled to the second voltage terminal. The first terminal of the 25th transistor is coupled to the third voltage terminal. The control terminal and the second terminal of the 26th transistor are coupled to the second terminal of the 27th transistor. The first terminal of the 26th transistor is coupled to the second terminal of the 25th transistor. The first terminal of the 27th transistor is coupled to the first terminal of a resistor. The second terminal of the resistor is coupled to the second terminal of the 28th transistor. The control terminal of the 28th transistor is coupled to the test voltage terminal. The first terminal of the 28th transistor is coupled to the second voltage terminal. The control terminal of the 29th transistor is coupled to the control terminal of the 25th transistor. The first terminal of the 29th transistor is coupled to the third voltage terminal. The second terminal of the twenty-ninth transistor is coupled to the control terminal and the second terminal of the thirtieth transistor. The first terminal of the thirtieth transistor is coupled to the control terminal and the second terminal of the thirty-first transistor. The first terminal of the thirty-first transistor is coupled to the second voltage terminal. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0018] Figure 1 This is a schematic block diagram of an undervoltage lockout circuit according to an embodiment of the present disclosure;

[0019] Figure 2 This is an exemplary circuit diagram of an undervoltage lockout circuit according to an embodiment of the present disclosure;

[0020] Figure 3 This is another exemplary circuit diagram of an undervoltage lockout circuit according to an embodiment of the present disclosure;

[0021] Figure 4 This is yet another exemplary circuit diagram of an undervoltage lockout circuit according to embodiments of the present disclosure; and

[0022] Figure 5 This is yet another exemplary circuit diagram of an undervoltage lockout circuit according to an embodiment of the present disclosure.

[0023] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0025] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0026] In all embodiments of this disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current directions between the source and drain (emitter and collector) of N-type and P-type transistors are opposite, the controlled middle terminal of the transistor is referred to as the control terminal, and the remaining two terminals of the transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0027] In traditional undervoltage lockout circuits, a resistor is used to divide the power supply voltage of the power management chip to obtain a sample voltage. Then, a voltage comparator compares the sample voltage with the power management chip's internal reference voltage to determine if the power supply voltage is normal. If the power supply voltage is abnormal, the undervoltage lockout circuit needs to lock the power management chip's internal control signal, preventing it from operating (equivalent to shutting down the power management chip). When the power supply voltage returns to normal, the undervoltage lockout circuit needs to restart the power management chip. This type of undervoltage lockout circuit has poor accuracy and consumes a lot of power. Furthermore, the output voltage of the undervoltage lockout circuit is easily affected by interference, causing repeated fluctuations and resulting in the power management chip repeatedly turning on and off.

[0028] Embodiments of this disclosure provide an undervoltage lockout circuit. Figure 1 A schematic block diagram of an undervoltage lockout circuit 100 according to an embodiment of the present disclosure is shown. The undervoltage lockout circuit 100 includes a voltage sampling circuit 110, a comparison circuit 120, and a hysteresis control circuit 130.

[0029] The voltage sampling circuit 110 can be coupled to the comparator circuit 120 and the hysteresis control circuit 130 via the first node N1. The voltage sampling circuit 110 can also be coupled to the voltage under test terminal VCC. The voltage under test terminal VCC can provide the voltage under test VCC externally. In some embodiments of this disclosure, the voltage under test VCC can be used as a power supply voltage in the circuit using the voltage under test VCC (e.g., a power management chip). The voltage sampling circuit 110 can be configured to sample the voltage under test VCC from the voltage under test terminal VCC and provide the sampled voltage to the comparator circuit 120 via the first node N1. Instead of the conventional method of using resistors to divide the voltage under test to obtain the sampled voltage, in the voltage sampling circuit 110, the sampled voltage is obtained by dividing the voltage under test using at least two transistors. In some embodiments of this disclosure, the length L of the at least two transistors is taken to be as large as possible to ensure that the sampled voltage output by the voltage sampling circuit 110 is stable under different process corners.

[0030] Comparator circuit 120 may be coupled to voltage sampling circuit 110 and hysteresis control circuit 130 via first node N1. Comparator circuit 120 may also be coupled to first voltage terminal VS1, reference voltage terminal Vref, and output terminal VO. Comparator circuit 120 may be configured to compare the sampled voltage with a reference voltage Vref from reference voltage terminal Vref, generate an undervoltage lockout indication signal based on the comparison result, and output the undervoltage lockout indication signal from output terminal VO. The active level of the undervoltage lockout indication signal can be used to indicate that a circuit using the voltage under test VCC (e.g., a power management chip) has entered an undervoltage lockout state. The inactive level of the undervoltage lockout indication signal can be used to indicate that a circuit using the voltage under test (e.g., a power management chip) has exited an undervoltage lockout state. In some embodiments of this disclosure, the active level of the undervoltage lockout indication signal may be determined as high or low depending on the architecture of the circuit using the voltage under test.

[0031] Hysteresis control circuit 130 can be coupled to voltage sampling circuit 110 and comparator circuit 120 via first node N1. Hysteresis control circuit 130 can also be coupled to output terminal VO. Hysteresis control circuit 130 can be configured to cause undervoltage lockout indication signal to flip from invalid level to valid level when the measured voltage VCC rises to a first preset voltage value, and to cause undervoltage lockout indication signal to flip from valid level to invalid level when the measured voltage VCC drops from the first preset voltage value to a second preset voltage value. The first preset voltage value is higher than the second preset voltage value. In this way, the circuit using the measured voltage (e.g., power management chip) can have a hysteresis effect when entering and exiting the undervoltage lockout state, avoiding repeated changes in the output voltage of undervoltage lockout circuit 100, which would cause the circuit using the measured voltage (e.g., power management chip) to repeatedly turn on and off.

[0032] In some embodiments of this disclosure, the hysteresis control circuit 130 can change the magnitude of the sampling voltage by altering the voltage division ratio of the voltage under test. Thus, when the voltage under test VCC rises to a first preset voltage value, the sampling voltage reaches the reference voltage value, causing the undervoltage lockout indication signal to flip from an invalid level to an active level. When the voltage under test VCC drops from the first preset voltage value to a second preset voltage value, the sampling voltage falls below the reference voltage value, causing the undervoltage lockout indication signal to flip from an active level to an invalid level. The magnitude of the reference voltage can be determined based on the target value of the voltage under test VCC, the first preset voltage value, the second preset voltage value, and the corresponding voltage division ratio of the voltage under test when the hysteresis control circuit 130 is operating and not operating. Whether the active level of the undervoltage lockout indication signal is high or low can be set according to the circuit it controls.

[0033] Figure 2 An exemplary circuit diagram of an undervoltage lockout circuit 200 according to an embodiment of the present disclosure is shown. Figure 2 In the example, the voltage sampling circuit 110 may include a first transistor M1 and a second transistor M2. The control electrode of the first transistor M1 is coupled to its second electrode. The first electrode of the first transistor M1 is coupled to the voltage terminal VCC to be measured. The control electrode and the second electrode of the second transistor M2 are coupled to a second voltage terminal V2. The first electrode of the second transistor M2 is coupled to the second electrode of the first transistor M1 and a first node N1. The voltage at the first node N1 is the aforementioned sampling voltage, which can be represented by Vcp.

[0034] The comparator circuit 120 may include transistors 7 through 11. The control electrode of transistor 7 M7 is coupled to a reference voltage terminal Vref. The first electrode of transistor 7 M7 is coupled to the first electrode of transistor 10 M10 and the second electrode of transistor 11 M11. The second electrode of transistor 7 M7 is coupled to the control electrode and the second electrode of transistor 8 M8. The first electrode of transistor 8 M8 is coupled to the first electrode of transistor 9 M9 and a first voltage terminal VS1. The control electrode of transistor 9 M9 is coupled to the control electrode of transistor 8 M8. The second electrode of transistor 9 M9 is coupled to the second electrode of transistor 10 M10 and the output terminal VO. The control electrode of transistor 10 M10 is coupled to a first node N1. The control electrode of transistor 11 M11 is coupled to a bias voltage terminal Vb. The first electrode of transistor 11 M11 is coupled to a second voltage terminal V2. Under the control of a bias voltage Vb from the bias voltage terminal Vb, transistor 11 can provide a constant current to transistors 7 and 10 M10.

[0035] The hysteresis control circuit 130 may include a sixth transistor M6. The control electrode of the sixth transistor M6 is coupled to the output terminal VO. The first electrode of the sixth transistor M6 is coupled to the first node N1. The second electrode of the sixth transistor M6 is coupled to the second voltage terminal V2.

[0036] exist Figure 2 In the example, a high-voltage signal is input from the first voltage terminal VS1, and the second voltage terminal V2 is grounded. The sixth transistor M6, the seventh transistor M7, the tenth transistor M10, and the eleventh transistor M11 are N-type transistors. The first transistor M1, the second transistor M2, the eighth transistor M8, and the ninth transistor M9 are P-type transistors. Those skilled in the art will understand that, based on the above inventive concept... Figure 2 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 2 The examples shown have different settings.

[0037] In some embodiments of this disclosure, the voltage to be measured, VCC, is increased from 0V, for example, to 3.3V. The voltage input from the first voltage terminal VS1 is, for example, 1.8V.

[0038] The following is combined with Figure 2 The following example illustrates the operation of the undervoltage lockout circuit 200 according to an embodiment of the present disclosure.

[0039] The first transistor M1 and the second transistor M2 are normally open. The voltage at the first node N1 is the sampled voltage Vcp obtained by dividing the voltage to be measured VCC. The sampled voltage Vcp is provided to the control electrode of the tenth transistor M10 in comparator 220.

[0040] When the sampled voltage Vcp is less than the reference voltage Vref (i.e., the voltage under test VCC is less than the first preset voltage value), comparator 220 outputs a high-level undervoltage lockout indication signal. The sixth transistor M6 is turned on. The sampled voltage Vcp is obtained by dividing the voltage under test VCC by the internal resistances of the first transistor M1, the second transistor M2, and the sixth transistor M6. The high-level undervoltage lockout indication signal causes the circuit using the voltage under test VCC (e.g., a power management chip) to enter an undervoltage lockout state.

[0041] When the sampled voltage Vcp is greater than the reference voltage Vref (i.e., the voltage under test VCC is greater than the second preset voltage value), comparator 220 outputs a low-level undervoltage lockout indication signal. The sixth transistor M6 is turned off. The sampled voltage Vcp is obtained by dividing the voltage under test VCC by the internal resistances of the first transistor M1 and the second transistor M2. The low-level undervoltage lockout indication signal causes the circuit using the voltage under test VCC (e.g., a power management chip) to exit the undervoltage lockout state.

[0042] When the sixth transistor M6 is on, the ratio of the sampled voltage Vcp to the measured voltage VCC is lower than when the sixth transistor M6 is off. Therefore, the first preset voltage value is higher than the second preset voltage value. In one example, the first preset voltage value is 2.7V, and the second preset voltage value is 2.6V. Thus, when the measured voltage VCC rises to 2.7V, the undervoltage lockout indicator signal toggles from high to low, turning off the sixth transistor M6. When the measured voltage VCC drops to 2.6V, the undervoltage lockout indicator signal toggles from low to high, turning on the sixth transistor M6. Therefore, circuits using the measured voltage VCC (e.g., power management chips) may exhibit hysteresis when entering and exiting the undervoltage lockout state.

[0043] In some embodiments of this disclosure, a low-level undervoltage lockout indication signal is required to indicate that a circuit using the voltage under test (VCC) (e.g., a power management chip) has entered an undervoltage lockout state. Figure 3 An exemplary circuit diagram of an undervoltage lockout circuit 300 for this application scenario is shown. Figure 2Based on this, the comparator circuit 320 may further include an inverter circuit 321. The inverter circuit 321 may include a twelfth transistor M12 and a thirteenth transistor M13. The control electrode of the twelfth transistor M12 is coupled to the second electrode of the ninth transistor M9. The first electrode of the twelfth transistor M12 is coupled to a first voltage terminal VS1. The second electrode of the twelfth transistor M12 is coupled to the second electrode of the thirteenth transistor M13 and the output terminal VO. The control electrode of the thirteenth transistor M13 is coupled to a bias voltage terminal Vb. The first electrode of the thirteenth transistor M13 is coupled to a second voltage terminal V2. The voltage at the output terminal VO is the inverted voltage of the voltage Vo1 at the second electrode of the ninth transistor M9.

[0044] and Figure 2 The examples shown are different, in Figure 3 In the example, the sixth transistor M6 is configured as a P-type transistor. Furthermore, the twelfth transistor M12 is a P-type transistor. The thirteenth transistor M13 is an N-type transistor.

[0045] When the sampled voltage Vcp is less than the reference voltage Vref (i.e., the voltage under test VCC is less than the first preset voltage value), voltage Vo1 is at a high level. Therefore, comparator 220 outputs a low-level undervoltage lockout indication signal. The sixth transistor M6 is turned on. The sampled voltage Vcp is obtained by dividing the voltage under test VCC by the internal resistances of the first transistor M1, the second transistor M2, and the sixth transistor M6. The low-level undervoltage lockout indication signal causes the circuit using the voltage under test VCC (e.g., a power management chip) to enter an undervoltage lockout state.

[0046] When the sampled voltage Vcp is greater than the reference voltage Vref (i.e., the voltage under test VCC is greater than the second preset voltage value), voltage Vo1 is at a low level. Therefore, comparator 220 outputs a high-level undervoltage lockout indication signal. The sixth transistor M6 is turned off. The sampled voltage Vcp is obtained by dividing the voltage under test VCC by the internal resistances of the first transistor M1 and the second transistor M2. The high-level undervoltage lockout indication signal causes the circuit using the voltage under test VCC (e.g., the power management chip) to exit the undervoltage lockout state.

[0047] therefore, Figure 3 The undervoltage lockout circuit 300 shown also enables circuits using the voltage under test VCC (e.g., power management chips) to have a hysteresis effect when entering and exiting the undervoltage lockout state.

[0048] Figure 4 Another exemplary circuit diagram of an undervoltage lockout circuit 400 according to an embodiment of the present disclosure is shown. Figure 4In the example, the voltage sampling circuit 410 may include: a first transistor M1 to a fifth transistor M5. The control electrode of the first transistor M1 is coupled to the second electrode of the third transistor M3 and the first electrode of the fourth transistor M4. The first electrode of the first transistor M1 is coupled to the measured voltage terminal VCC. The second electrode of the first transistor M1 is coupled to the second electrode of the fourth transistor M4. The control electrode and the second electrode of the second transistor M2 are coupled to a second voltage terminal V2. The first electrode of the second transistor M2 is coupled to the second electrode of the first transistor M1 and a first node N1. The control electrode and the first electrode of the third transistor M3 are coupled to the first electrode of the first transistor M1. The control electrode of the fourth transistor M4 is provided with an inverted enable signal ENN. The enable signal is used to enable the undervoltage lockout circuit 400. The control electrode of the fifth transistor M5 is provided with an inverted enable signal ENN. The first electrode of the fifth transistor M5 is coupled to the second voltage terminal V2. The second electrode of the fifth transistor M5 is coupled to the first electrode of the second transistor M2.

[0049] When the undervoltage lockout circuit 400 is required to operate, i.e., when the undervoltage lockout circuit 400 is enabled, the enable signal is at a high level. Therefore, the inverted signal ENN of the enable signal is at a low level. The fourth transistor M4 is turned on while the fifth transistor M5 is turned off. When the undervoltage lockout circuit 400 is required to stop operating, the enable signal is at a low level. Therefore, the inverted signal ENN of the enable signal is at a high level. The fourth transistor M4 is turned off while the fifth transistor M5 is turned on. In this way, the voltage of the first node N1 is pulled low to ground, making the sampled voltage 0V. Thus, the undervoltage lockout signal output by the undervoltage lockout circuit 400 remains at a low level.

[0050] exist Figure 4 In the example, the third transistor M3 can be used to remove static electricity. When the voltage to be measured, VCC, is lower than the threshold voltage of the third transistor M3, the third transistor M3 is turned on, and the static electricity on the control electrode of the first transistor M1 can be released to the voltage to be measured, VCC, so as to avoid the static voltage on the control electrode of the first transistor M1 being too high and being mistakenly turned off.

[0051] In addition, Figure 4 In the example, the voltage sampling circuit 410 may further include a capacitor C. A first terminal of the capacitor C is coupled to a first node N1. A second terminal of the capacitor C is coupled to a second voltage terminal V2. The capacitor C can be used to filter glitches on the sampled voltage Vcp.

[0052] exist Figure 3Based on the inverter circuit 321 shown, the inverter circuit 421 may further include: fourteenth transistor M14 to seventeenth transistor M17. The control electrode of the fourteenth transistor M14 is coupled to the second electrode of the twelfth transistor M12. The first electrode of the fourteenth transistor M14 is coupled to the first voltage terminal VS1. The second electrode of the fourteenth transistor M14 is coupled to the second electrode of the fifteenth transistor M15. The control electrode of the fifteenth transistor M15 is coupled to the second electrode of the twelfth transistor M12. The first electrode of the fifteenth transistor M15 is coupled to the second voltage terminal V2. The control electrode of the sixteenth transistor M16 is coupled to the second electrode of the fourteenth transistor M14. The first electrode of the sixteenth transistor M16 is coupled to the first voltage terminal VS1. The second electrode of the sixteenth transistor M16 is coupled to the second electrode of the seventeenth transistor M17. The control electrode of the seventeenth transistor M17 is coupled to the second electrode of the fourteenth transistor M14. The first electrode of the seventeenth transistor M17 is coupled to the second voltage terminal V2.

[0053] exist Figure 4 In the example, transistors M14 (fourteenth) and M15 (fifteenth) can form an inverter. Transistor M16 (sixteenth) and M17 (seventeenth) can form another inverter. Therefore, Figure 4 The output of the inverter circuit 421 shown is Figure 3 The output of the inverting circuit 321 shown is in phase. Transistors fourteen through seventeen, M14 and M17, can be used to enhance the driving force of the undervoltage lockout signal.

[0054] and Figure 3 The example shown is the same, in Figure 4 In the example, the sixth transistor M6 is configured as a P-type transistor. Furthermore, the fourteenth transistor M14 and the sixteenth transistor M16 are P-type transistors. The fifteenth transistor M15 and the seventeenth transistor M17 are N-type transistors.

[0055] Figure 5 Further exemplary circuit diagrams of undervoltage lockout circuit 500 according to embodiments of the present disclosure are shown. Figure 4 Based on the undervoltage lockout circuit 400 shown, the undervoltage lockout circuit 500 may further include a bias voltage generation circuit 540. The bias voltage generation circuit 540 can output a bias voltage Vb from the bias voltage terminal Vb.

[0056] The bias voltage generating circuit 540 may include: eighteenth transistor M18 to thirty-first transistor M31, and resistor R1. The control terminal of the eighteenth transistor M18 is coupled to the second voltage terminal V2. The first terminal of the eighteenth transistor M18 is coupled to the third voltage terminal VS2. The second terminal of the eighteenth transistor M18 is coupled to the first terminal of the nineteenth transistor M19. The control terminal of the nineteenth transistor M19 is coupled to the second voltage terminal V2. The second terminal of the nineteenth transistor M19 is coupled to the first terminal of the twentieth transistor M20. The control terminal of the twentieth transistor M20 is coupled to the second voltage terminal V2. The second terminal of the twentieth transistor M20 is coupled to the first terminal of the twenty-first transistor M21. The control terminal of the twenty-first transistor M21 is coupled to the second voltage terminal V2. The second terminal of the twenty-first transistor M21 is coupled to the control terminal of the twenty-second transistor M22 and the second terminal of the twenty-third transistor M23. The first terminal of the twenty-second transistor M22 is coupled to the first terminal of the twenty-third transistor M23. The second terminal of the twenty-second transistor M22 is coupled to the control terminal and the second terminal of the twenty-fifth transistor M25. The control terminal of transistor M23 (23rd transistor) is coupled to the control terminals of transistors M27 (27th transistor) and M31 (31st transistor). The first terminal of transistor M23 is coupled to the second terminal of transistor M24 (24th transistor). The control terminal of transistor M24 is coupled to the measured voltage terminal VCC. The first terminal of transistor M24 is coupled to the second voltage terminal V2. The first terminal of transistor M25 (25th transistor) is coupled to the third voltage terminal VS2. The control terminal and the second terminal of transistor M26 (26th transistor) are coupled to the second terminal of transistor M27 (27th transistor). The first terminal of transistor M26 is coupled to the second terminal of transistor M25 (25th transistor). The first terminal of transistor M27 (27th transistor) is coupled to the first terminal of resistor R1. The second terminal of resistor R1 is coupled to the second terminal of transistor M28 (28th transistor). The control terminal of transistor M28 (28th transistor) is coupled to the measured voltage terminal VCC. The first terminal of transistor M28 (28th transistor) is coupled to the second voltage terminal V2. The control terminal of transistor M29 (29th transistor) is coupled to the control terminal of transistor M25 (25th transistor). The first terminal of transistor M29 (29th transistor) is coupled to the third voltage terminal VS2. The second terminal of the twenty-ninth transistor M29 is coupled to the control terminal and the second terminal of the thirtieth transistor M30. The first terminal of the thirtieth transistor M30 is coupled to the control terminal and the second terminal of the thirty-first transistor M31. The control terminal of the thirty-first transistor M31 is coupled to the bias voltage terminal Vb. The first terminal of the thirty-first transistor M31 is coupled to the second voltage terminal V2.

[0057] exist Figure 5 In the example, a high-voltage signal is input from the first voltage terminal VS1, the second voltage terminal V2 is grounded, and a high-voltage signal is input from the third voltage terminal VS2. In some embodiments of this disclosure, the third voltage from the third voltage terminal VS2 may be equal to the first voltage from the first voltage terminal VS1.

[0058] Transistors M22 through M24, M27, M28, M30, and M31 are N-type transistors. Transistors M18 through M21, M25, M26, and M29 are P-type transistors. Those skilled in the art will understand that, based on the above inventive concept... Figure 5 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 5 The examples shown have different settings.

[0059] Figure 5 The bias voltage generation circuit 540 shown has a self-starting function. Figure 5 In the example, the threshold voltage of the twenty-fourth transistor M24 is equal to the threshold voltage of the twenty-eighth transistor M28. When the voltage to be measured VCC is less than the threshold voltage of the twenty-fourth transistor M24, both the twenty-fourth transistor M24 and the twenty-eighth transistor M28 are turned off, and the bias voltage generation circuit 540 does not work.

[0060] When the voltage under test VCC rises to the threshold voltage of the 24th transistor M24, the 24th transistor M24 and the 28th transistor M28 turn on. The control electrodes of the 18th transistor M18 to the 21st transistor M21 are grounded, therefore all of them turn on. This pulls up the voltage at the control electrode of the 22nd transistor M22, causing it to turn on. The voltage at the control electrode of the 25th transistor M25 is pulled down to ground via the 22nd transistor M22 and the 24th transistor M24. The 25th transistor M25 and the 29th transistor M29 then turn on. This raises the voltage at the control electrode of the 31st transistor M31 (i.e., the second node N2), thus outputting a bias voltage Vb. The bias voltage Vb turns on the 23rd transistor M23, pulling down the voltage at the control electrode of the 22nd transistor M22 to ground. Thus, after the bias voltage generation circuit 540 starts (outputs bias voltage Vb), the 22nd transistor M22 automatically turns off, completing the self-starting process.

[0061] The bias voltage generation circuit 540 can self-start using the voltage under test VCC. Therefore, it can stop providing a bias voltage Vb to the comparator circuit 420 when the voltage under test VCC is lower than the threshold voltage of the twenty-fourth transistor M24, thereby saving power consumption of the undervoltage lockout circuit 500. After self-starting, the bias voltage generation circuit 540 can provide a stable bias voltage to the comparator 420.

[0062] In summary, the undervoltage lockout circuit according to embodiments of this disclosure can improve the accuracy of undervoltage lockout and reduce power consumption. The undervoltage lockout circuit according to embodiments of this disclosure has a hysteresis design, which can avoid repeated switching on and off of the circuit using the measured voltage VCC.

[0063] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0064] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0065] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0066] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. An under-voltage lockout circuit comprising: The voltage sampling circuit, the comparison circuit, and the hysteresis control circuit, The voltage sampling circuit is configured to sample a to-be-tested voltage from a to-be-tested voltage terminal and provide the sampled voltage to the comparison circuit via a first node, wherein the sampled voltage is obtained by dividing the to-be-tested voltage by using at least two transistors. The comparison circuit is configured to compare the sampled voltage with a reference voltage from a reference voltage terminal, generate an under-voltage lock indication signal based on a comparison result, and output the under-voltage lock indication signal from an output terminal, wherein an effective level of the under-voltage lock indication signal is used to indicate that a circuit using the to-be-tested voltage enters an under-voltage lock state. The hysteresis control circuit is configured to make the under-voltage lock indication signal flip from an invalid level to the effective level when the to-be-tested voltage rises to a first preset voltage value, and make the under-voltage lock indication signal flip from the effective level to the invalid level when the to-be-tested voltage falls from the first preset voltage value to a second preset voltage value, wherein the first preset voltage value is higher than the second preset voltage value; the hysteresis control circuit comprises a sixth transistor, wherein a control pole of the sixth transistor is coupled to the output terminal, a first pole of the sixth transistor is coupled to the first node, and a second pole of the sixth transistor is coupled to a second voltage terminal. The under-voltage lock circuit further comprises a bias voltage generation circuit configured to provide a bias voltage to the comparison circuit from a bias voltage terminal, wherein the bias voltage generation circuit comprises an eighteenth transistor to a thirty-first transistor and a resistor, wherein a control pole of the eighteenth transistor is coupled to the second voltage terminal, a first pole of the eighteenth transistor is coupled to a third voltage terminal, and a second pole of the eighteenth transistor is coupled to a first pole of a nineteenth transistor; a control pole of the nineteenth transistor is coupled to the second voltage terminal, a second pole of the nineteenth transistor is coupled to a first pole of a twentieth transistor; a control pole of the twentieth transistor is coupled to the second voltage terminal, a second pole of the twentieth transistor is coupled to a first pole of a twenty-first transistor; a control pole of the twenty-first transistor is coupled to the second voltage terminal, a second pole of the twenty-first transistor is coupled to a control pole of a twenty-second transistor and a second pole of a twenty-third transistor; a first pole of the twenty-second transistor is coupled to a first pole of the twenty-third transistor, and a second pole of the twenty-second transistor is coupled to a control pole and a second pole of a twenty-fifth transistor; a control pole of the twenty-third transistor is coupled to a control pole of a twenty-seventh transistor and a control pole of the thirty-first transistor, and the first pole of the twenty-third transistor is coupled to a second pole of a twenty-fourth transistor; a control pole of the twenty-fourth transistor is coupled to the to-be-tested voltage terminal, and a first pole of the twenty-fourth transistor is coupled to the second voltage terminal; a first pole of the twenty-fifth transistor is coupled to the third voltage terminal; a control electrode and a second electrode of the twenty-sixth transistor are coupled to a second electrode of the twenty-seventh transistor, a first electrode of the twenty-sixth transistor is coupled to the second electrode of the twenty-fifth transistor; a first electrode of the twenty-seventh transistor is coupled to a first end of the resistor; a second end of the resistor is coupled to a second electrode of the twenty-eighth transistor; a control electrode of the twenty-eighth transistor is coupled to the to-be-measured voltage terminal, a first electrode of the twenty-eighth transistor is coupled to the second voltage terminal; a control electrode of the twenty-ninth transistor is coupled to a control electrode of the twenty-fifth transistor, a first electrode of the twenty-ninth transistor is coupled to the third voltage terminal, a second electrode of the twenty-ninth transistor is coupled to a control electrode and a second electrode of the thirtieth transistor; a first electrode of the thirtieth transistor is coupled to a control electrode and a second electrode of the thirty-first transistor; a control electrode of the thirty-first transistor is coupled to the bias voltage terminal, a first electrode of the thirty-first transistor is coupled to the second voltage terminal.

2. The under voltage lockout circuit of claim 1, wherein, the voltage sampling circuit comprises a first transistor and a second transistor, wherein a control electrode of the first transistor is coupled to a second electrode of the first transistor, a first electrode of the first transistor is coupled to the to-be-measured voltage terminal; a control electrode and a second electrode of the second transistor are coupled to a second voltage terminal, a first electrode of the second transistor is coupled to the second electrode of the first transistor and the first node.

3. The undervoltage lockout circuit of claim 1, wherein, the voltage sampling circuit comprises a first transistor to a fifth transistor, wherein a control electrode of the first transistor is coupled to a second electrode of the third transistor and a first electrode of the fourth transistor, a first electrode of the first transistor is coupled to the to-be-measured voltage terminal, a second electrode of the first transistor is coupled to a second electrode of the fourth transistor; a control electrode and a second electrode of the second transistor are coupled to a second voltage terminal, a first electrode of the second transistor is coupled to the second electrode of the first transistor and the first node; a control electrode and a first electrode of the third transistor are coupled to the first electrode of the first transistor; a control electrode of the fourth transistor is provided with an inverted signal of an enable signal, the enable signal being used for enabling the under-voltage lockout circuit; a control electrode of the fifth transistor is provided with the inverted signal of the enable signal, a first electrode of the fifth transistor is coupled to the second voltage terminal, a second electrode of the fifth transistor is coupled to the first electrode of the second transistor.

4. The undervoltage lockout circuit of claim 2 or 3, wherein, the voltage sampling circuit further comprises a capacitor, wherein a first end of the capacitor is coupled to the first node, a second end of the capacitor is coupled to the second voltage terminal.

5. The undervoltage lockout circuit of claim 1, wherein, the comparison circuit comprises a seventh transistor to an eleventh transistor, wherein a control electrode of the seventh transistor is coupled to the reference voltage terminal, a first electrode of the seventh transistor is coupled to a first electrode of the tenth transistor and a second electrode of the eleventh transistor, a second electrode of the seventh transistor is coupled to a control electrode and a second electrode of the eighth transistor; a first electrode of the eighth transistor is coupled to a first electrode of the ninth transistor and a first voltage terminal; a control electrode of the ninth transistor is coupled to the control electrode of the eighth transistor, a second electrode of the ninth transistor is coupled to a second electrode of the tenth transistor; a control electrode of the tenth transistor is coupled to the first electrode of the ninth transistor, a first electrode of the tenth transistor is coupled to a second electrode of the eleventh transistor; A control electrode of the tenth transistor is coupled to the first node; A control electrode of the eleventh transistor is coupled to a bias voltage terminal, and a first electrode of the eleventh transistor is coupled to a second voltage terminal.

6. The undervoltage lockout circuit of claim 5, wherein, The comparison circuit further includes twelfth and thirteenth transistors, A control electrode of the twelfth transistor is coupled to a second electrode of the ninth transistor, a first electrode of the twelfth transistor is coupled to the first voltage terminal, and a second electrode of the twelfth transistor is coupled to a second electrode of the thirteenth transistor; A control electrode of the thirteenth transistor is coupled to the bias voltage terminal, and a first electrode of the thirteenth transistor is coupled to the second voltage terminal.

7. The undervoltage lockout circuit of claim 6, wherein, The comparison circuit further includes fourteenth to seventeenth transistors; A control electrode of the fourteenth transistor is coupled to the second electrode of the twelfth transistor, a first electrode of the fourteenth transistor is coupled to the first voltage terminal, and a second electrode of the fourteenth transistor is coupled to a second electrode of the fifteenth transistor; A control electrode of the fifteenth transistor is coupled to the second electrode of the twelfth transistor, and a first electrode of the fifteenth transistor is coupled to the second voltage terminal; A control electrode of the sixteenth transistor is coupled to the second electrode of the fourteenth transistor, a first electrode of the sixteenth transistor is coupled to the first voltage terminal, and a second electrode of the sixteenth transistor is coupled to a second electrode of the seventeenth transistor; A control electrode of the seventeenth transistor is coupled to the second electrode of the fourteenth transistor, and a first electrode of the seventeenth transistor is coupled to the second voltage terminal.

8. An under voltage lockout circuit comprising: First to thirty-first transistors, a capacitor, and a resistor, A control electrode of the first transistor is coupled to a second electrode of a third transistor and a first electrode of a fourth transistor, a first electrode of the first transistor is coupled to a voltage to be measured, and a second electrode of the first transistor is coupled to a second electrode of the fourth transistor; A control electrode and a second electrode of the second transistor are coupled to a second voltage terminal, and a first electrode of the second transistor is coupled to the second electrode of the first transistor and a control electrode of a tenth transistor; A control electrode and a first electrode of the third transistor are coupled to the first electrode of the first transistor; A control electrode of the fourth transistor is provided with an inverted signal of an enable signal used for enabling the under-voltage lockout circuit; A control electrode of the fifth transistor is provided with the inverted signal of the enable signal, a first electrode of the fifth transistor is coupled to the second voltage terminal, and a second electrode of the fifth transistor is coupled to the first electrode of the second transistor; A first terminal of the capacitor is coupled to the first electrode of the second transistor, and a second terminal of the capacitor is coupled to the second voltage terminal; A control electrode of the sixth transistor is coupled to an output terminal, a first electrode of the sixth transistor is coupled to the first electrode of the second transistor, and a second electrode of the sixth transistor is coupled to the second voltage terminal; A control electrode of the seventh transistor is coupled to a reference voltage terminal, a first electrode of the seventh transistor is coupled to a first electrode of the tenth transistor and a second electrode of an eleventh transistor, and a second electrode of the seventh transistor is coupled to a control electrode and a second electrode of an eighth transistor; A first electrode of the eighth transistor is coupled with a first electrode of a ninth transistor and a first voltage terminal; A control electrode of the ninth transistor is coupled with the control electrode of the eighth transistor, and a second electrode of the ninth transistor is coupled with a second electrode of the tenth transistor; A control electrode of the eleventh transistor is coupled with a control electrode of the thirty-first transistor, and a first electrode of the eleventh transistor is coupled with a second voltage terminal; A control electrode of the twelfth transistor is coupled with the second electrode of the ninth transistor, a first electrode of the twelfth transistor is coupled with the first voltage terminal, and a second electrode of the twelfth transistor is coupled with a second electrode of the thirteenth transistor; A control electrode of the thirteenth transistor is coupled with the control electrode of the thirty-first transistor, and a first electrode of the thirteenth transistor is coupled with the second voltage terminal; A control electrode of the fourteenth transistor is coupled with the second electrode of the twelfth transistor, a first electrode of the fourteenth transistor is coupled with the first voltage terminal, and a second electrode of the fourteenth transistor is coupled with a second electrode of the fifteenth transistor; A control electrode of the fifteenth transistor is coupled with the second electrode of the twelfth transistor, and a first electrode of the fifteenth transistor is coupled with the second voltage terminal; A control electrode of the sixteenth transistor is coupled with the second electrode of the fourteenth transistor, a first electrode of the sixteenth transistor is coupled with the first voltage terminal, and a second electrode of the sixteenth transistor is coupled with a second electrode of the seventeenth transistor and the output terminal; A control electrode of the seventeenth transistor is coupled with the second electrode of the fourteenth transistor, and a first electrode of the seventeenth transistor is coupled with the second voltage terminal; A control electrode of the eighteenth transistor is coupled with the second voltage terminal, a first electrode of the eighteenth transistor is coupled with a third voltage terminal, and a second electrode of the eighteenth transistor is coupled with a first electrode of the nineteenth transistor; A control electrode of the nineteenth transistor is coupled with the second voltage terminal, and a second electrode of the nineteenth transistor is coupled with a first electrode of the twentieth transistor; A control electrode of the twentieth transistor is coupled with the second voltage terminal, and a second electrode of the twentieth transistor is coupled with a first electrode of the twenty-first transistor; A control electrode of the twenty-first transistor is coupled with the second voltage terminal, and a second electrode of the twenty-first transistor is coupled with a control electrode of the twenty-second transistor and a second electrode of the twenty-third transistor; A first electrode of the twenty-second transistor is coupled with a first electrode of the twenty-third transistor, and a second electrode of the twenty-second transistor is coupled with a control electrode and a second electrode of the twenty-fifth transistor; A control electrode of the twenty-third transistor is coupled with a control electrode of the twenty-seventh transistor and a control electrode of the thirty-first transistor, and the first electrode of the twenty-third transistor is coupled with a second electrode of the twenty-fourth transistor; A control electrode of the twenty-fourth transistor is coupled with the to-be-measured voltage terminal, and a first electrode of the twenty-fourth transistor is coupled with the second voltage terminal; A first electrode of the twenty-fifth transistor is coupled with the third voltage terminal; A control electrode and a second electrode of the twenty-sixth transistor are coupled with the second electrode of the twenty-seventh transistor, and a first electrode of the twenty-sixth transistor is coupled with the second electrode of the twenty-fifth transistor; A first electrode of the twenty-seventh transistor is coupled to a first terminal of the resistor; A second terminal of the resistor is coupled to a second electrode of a twenty-eighth transistor; A control electrode of the twenty-eighth transistor is coupled to the to-be-measured voltage terminal, and a first electrode of the twenty-eighth transistor is coupled to the second voltage terminal; A control electrode of a twenty-ninth transistor is coupled to the control electrode of the twenty-fifth transistor, a first electrode of the twenty-ninth transistor is coupled to the third voltage terminal, and a second electrode of the twenty-ninth transistor is coupled to a control electrode and a second electrode of a thirtieth transistor; A first electrode of the thirtieth transistor is coupled to a control electrode and a second electrode of a thirty-first transistor; A first electrode of the thirty-first transistor is coupled to the second voltage terminal.

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