A delay phase-locked loop circuit and its control method

Abstract

This invention discloses a delay phase-locked loop (PLL) circuit and its control method. The circuit includes: a single-ended to differential converter for converting an externally input reference clock signal; a delay circuit including at least two delay units, wherein the first delay unit has two input channels and two control input ports; the converted reference clock signal is input to a frequency divider counter after being connected to the first input channel; the output of the frequency divider counter is connected to a channel selector, which is connected to the first control input port; when the number of reference clock signal cycles counted by the frequency divider counter reaches a preset value, the channel selector outputs a control signal to the first control input port, enabling the second input channel to conduct, allowing the reference clock to enter the delay circuit and cycle through the second input channel; the feedback clock signal output by the delay circuit is fed back to the basic PLL circuit. The circuit of this invention exhibits high linearity and stability.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and in particular to a delay phase-locked loop circuit and its control method. Background Technology

[0002] Since their invention, phase-locked loops (PLLs) have been widely used in analog and digital systems. The main applications of PLLs are clock data recovery in digital systems and frequency synthesizer communication systems for wireless channel selection. The performance of these systems directly depends on the quality of the clock signal; therefore, improving the signal quality of the PLL is crucial. Among existing PLLs, delay-locked loops (DLLs) are widely used in systems-on-chips and high-precision time-to-digital converters due to their good stability, high integration density, and multi-clock phase output.

[0003] Traditional DLL structures generally use voltage-controlled delay lines (VCDLs) to form delay chains. However, since the tuning characteristics of VCDLs are nonlinear, their gain KVCDL is not constant. This nonlinearity can severely degrade the stability of DLLs. Summary of the Invention

[0004] Therefore, in order to solve the above-mentioned problems in the prior art, this application provides a phase-locked loop circuit with high linearity.

[0005] Therefore, the present invention provides a delay phase-locked loop circuit, comprising:

[0006] A single-ended to differential circuit is used to convert an externally input reference clock signal.

[0007] The delay circuit includes at least two delay units, wherein the first delay unit has two input channels, a first input channel and a second input channel, and two control input ports, a first control input port and a second control input port;

[0008] After the converted reference clock signal is connected to the first input channel, it is input to the frequency divider counter. The output of the frequency divider counter is connected to a channel selector, which is connected to the first control input port. When the number of reference clock signal cycles counted by the frequency divider counter reaches a preset value, the channel selector outputs a control signal to the first control input port, which turns on the second input channel. The reference clock signal then enters the delay circuit and cycles through the second input channel.

[0009] The feedback clock signal output by the delay circuit is fed back to the basic phase-locked loop circuit. The basic phase-locked loop circuit generates a tuning current based on the phase difference between the feedback clock signal and the reference clock signal, which is input to the second control input port to adjust the delay time of the delay unit until the feedback clock signal and the reference clock signal are in phase.

[0010] Furthermore, the basic phase-locked loop circuit includes:

[0011] The frequency and phase detector is configured to compare the phase difference between the feedback clock signal and the reference clock signal;

[0012] A charge pump, connected to a frequency and phase detector, is configured to convert the phase difference between a reference clock signal and a feedback clock signal into a proportional charging and discharging current.

[0013] A loop filter, connected to the charge pump, is configured to filter the current output by the charge pump to generate a control voltage;

[0014] The voltage-to-current conversion circuit, connected to the loop filter, is configured to convert the control voltage into a current signal that is linearly related to it; the current signal is the tuning current.

[0015] Furthermore, the delay unit also includes a first inverter and a second inverter. The input terminal of the first inverter is connected to the non-inverting output terminal of the two input channels, and the input terminal of the second inverter is connected to the inverting output terminal of the two input channels. The output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the input terminal of the first inverter. The output terminals of the first inverter and the second inverter are respectively the non-inverting output terminal and the inverting output terminal of the delay unit.

[0016] Furthermore, the voltage-to-current conversion circuit includes:

[0017] PMOS transistor MP1 and NMOS transistor MN1, both of which have their gates connected to an enable control signal, and their sources are connected to the high-level output terminal and the low-level output terminal of the drive power supply, respectively.

[0018] PMOS transistor MP2 has its source connected to the high-level output terminal of the drive power supply, and its gate and drain are both connected to the drain of PMOS transistor MP1.

[0019] The gate of NMOS transistor MN2 is connected to the control voltage, the drain is connected to the drain of PMOS transistor MP2, and the source is connected to the drain of NMOS transistor MN1.

[0020] PMOS transistor MP3 and NMOS transistor MN3 have their sources connected to the high-level and low-level output terminals of the driving power supply, respectively. The gate of PMOS transistor MP3 is connected to the drain of PMOS transistor MP2 and outputs a positive voltage signal. The gate of NMOS transistor MN3 is connected to the drain of NMOS transistor MN3 and outputs an inverted voltage signal.

[0021] PMOS transistor MP4 and NMOS transistor MN4 have their drains connected to each other, and their gates are connected to the low-level output terminal and the high-level output terminal of the driving power supply, respectively. The source of PMOS transistor MP4 is connected to the drain of PMOS transistor MP3, and the source of NMOS transistor MN4 is connected to the drain of NMOS transistor MN3.

[0022] Furthermore, the delay unit includes:

[0023] PMOS transistors MP5 and MP6 have their gates connected to a positive voltage signal, their sources connected to the high-level output of the drive power supply, and their drains connected to the second control input ports of the first and second input channels, respectively.

[0024] NMOS transistors MN5 and MN6 have their gates connected to an inverted voltage signal, their sources connected to the low-level output of the drive power supply, and their drains connected to the second control input ports of the first and second input channels, respectively.

[0025] Furthermore, the first inverter includes a PMOS transistor MP7 and an NMOS transistor MN7, and the second inverter includes a PMOS transistor MP8 and an NMOS transistor MN8. The sources of both PMOS transistors MP7 and MP8 are connected to the high-level output terminal of the driving power supply, and the sources of both NMOS transistors MN7 and MN8 are connected to the low-level output terminal of the driving power supply. The gates of PMOS transistors MP7 and MN7 are connected as the input terminal of the first inverter, and the drains of PMOS transistors MP7 and MN7 are connected as the output terminal of the first inverter. The gates of PMOS transistors MP8 and MN8 are connected as the input terminal of the second inverter, and the drains of PMOS transistors MP8 and MN8 are connected as the output terminal of the second inverter.

[0026] Furthermore, the delay circuit includes four or more even-numbered delay units, and the signal output by the last delay unit is cross-coupled to the second input channel of the first delay unit.

[0027] According to a second aspect, the present invention also provides a control method for a delay phase-locked loop circuit, for controlling the delay phase-locked loop circuit described in any embodiment of the first aspect, the method comprising the following steps:

[0028] A first level signal is applied to the first control input port of the first delay unit in the delay circuit to control the first input channel of the first delay unit to be turned on;

[0029] When the number of reference clock signal cycles counted by the frequency divider counter reaches a preset value, a second level signal is applied to the first control input port to control the second input channel of the first delay unit to be turned on.

[0030] The technical solution provided by this invention has the following advantages:

[0031] 1. The delay phase-locked loop circuit provided by this invention sets the first delay unit in the delay circuit to have two input channels (in practical applications, all delay units in the delay circuit can be set to have two input channels, but only the first delay unit uses two input channels) and two input control channels. This allows the external reference clock signal to be divided through the first input channel of the first delay unit. After the number of reference clock signal cycles counted by the frequency divider counter reaches the preset frequency division ratio, the second input channel is selected (through the control signal generated by the channel selector connected to the frequency divider counter). This allows the buffer in the first delay unit to cycle through the delay circuit through the second input channel. In other words, this circuit uses multiplexing of low-jitter reference clock signals to enter the entire delay phase-locked loop circuit, which can reduce the noise introduced by the circuit's own input and improve the linearity of the circuit.

[0032] Furthermore, by setting the basic phase-locked loop circuit to adjust the delay time of the delay unit by generating a tuning current that is linearly related to the circuit's operating frequency, the linearity of the delay phase-locked loop circuit can be further improved.

[0033] 2. The delay phase-locked loop circuit provided by the present invention includes a voltage-to-current conversion circuit in the basic phase-locked loop circuit, so that the control voltage is converted into a current signal that is linearly related to it, and thereby controls the delay of the delay unit. This enables the delay phase-locked loop circuit to exhibit a linear relationship between the control voltage and the system operating frequency, with high linearity.

[0034] 3. The delay phase-locked loop circuit provided by the present invention, by setting the delay unit to have two inverters connected end to end to form a mutually feedback coupling form, shapes the signal output by the delay unit, and can improve the quality of the output signal of the delay phase-locked loop circuit. Attached Figure Description

[0035] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of a delay phase-locked loop circuit provided in an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of a voltage-to-current conversion circuit provided in an embodiment of the present invention;

[0038] Figure 3 A schematic diagram of a delay unit provided in an embodiment of the present invention;

[0039] Figure 4 A flowchart of a control method for a delay phase-locked loop circuit provided in an embodiment of the present invention. Detailed Implementation

[0040] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] In the description of this invention, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0042] Example 1

[0043] Figure 1 A schematic diagram of the delay phase-locked loop circuit in one embodiment of this invention is shown. Figure 1 As shown, the delay phase-locked loop circuit includes a single-ended to differential circuit, a delay circuit, a frequency divider counter, a channel selector, and a basic phase-locked loop circuit.

[0044] Among them, such as Figure 1As shown, the delay circuit includes at least two delay units. The first delay unit has two input channels: a first input channel and a second input channel, as well as two control input ports: a first control input port and a second control input port. The externally input reference clock signal, converted from a single-ended to a differential circuit, first enters the first delay unit through the first input channel for buffering and is then output to a frequency divider counter. The frequency divider counter counts the number of periods of the reference clock signal. When the counted number of periods reaches a preset value (i.e., a preset division ratio), it outputs a signal to a channel selector connected to it. The channel selector outputs a control signal to the first control input port of the first delay unit, enabling the second input channel to conduct. The reference clock signal buffered in the first delay unit then enters the entire delay circuit and cycles periodically through the second input channel within the delay circuit (i.e., the clock signal output by the last delay unit in the delay circuit is coupled back to the second input channel of the first delay unit).

[0045] In practical applications, in order to ensure that the delay time interval of each delay unit is the same, each delay unit in the delay circuit can be set as the same differential delay adjustable multiplexer with two input channels and two control input ports, but only the first delay unit uses two input channels.

[0046] Furthermore, to ensure the delay circuit does not lock out, the number of delay units in the delay circuit should be three or more. Based on the differential characteristics of the entire circuit, the number of delay units can be set to an even number, and the output of one stage can be cross-coupled to the input of the next stage to enable the entire delay loop to oscillate. Figure 1 The signal output from the last delay unit is cross-coupled to the first input channel of the first delay unit.

[0047] Among them, such as Figure 1 As shown, the feedback clock signal output by the delay circuit is fed back to the basic phase-locked loop circuit. The basic phase-locked loop circuit generates a tuning current based on the phase difference between the feedback clock signal and the reference clock signal, which is input to the second control input port to adjust the delay time of the delay unit until the feedback clock signal and the reference clock signal are in phase.

[0048] like Figure 1As shown, a basic phase-locked loop (PLL) circuit may include a phase-frequency discriminator, a charge pump, a loop filter, and a voltage-to-current converter. The phase-frequency discriminator is configured to compare the phase difference between a feedback clock signal and a reference clock signal; the charge pump, connected to the phase-frequency discriminator, is configured to convert the phase difference between the reference clock signal and the feedback clock signal into a proportional charging / discharging current; the loop filter, connected to the charge pump, is configured to filter the current output by the charge pump to generate a control voltage; the voltage-to-current converter, connected to the loop filter and with its output connected to each delay unit in the delay circuit, is configured to convert the control voltage into a linearly related current signal; this current signal is the tuning current used to tune the delay time of each delay unit.

[0049] Therefore, the delay phase-locked loop circuit in this embodiment, by setting the first delay unit in the delay circuit to have two input channels (in practical applications, all delay units in the delay circuit can be set to have two input channels, but only the first delay unit uses two input channels) and two input control channels, allows the external reference clock signal to be divided through the first input channel of the first delay unit. After the number of reference clock signal cycles counted by the frequency divider counter reaches the preset frequency division ratio, the second input channel can be selected (through the control signal generated by the channel selector connected to the frequency divider counter). This allows the buffer in the first delay unit to cycle through the delay circuit through the second input channel. In other words, this circuit uses multiplexing of low-jitter reference clock signals to enter the entire delay phase-locked loop circuit, which can reduce the noise introduced by the circuit's own input and improve the linearity of the circuit.

[0050] Furthermore, by setting the basic phase-locked loop circuit to adjust the delay time of the delay unit by generating a tuning current that is linearly related to the circuit's operating frequency, the linearity of the delay phase-locked loop circuit can be further improved.

[0051] Figure 2 A schematic diagram of the voltage-to-current conversion circuit in one embodiment of this invention is shown. Figure 2 As shown, the voltage-to-current conversion circuit may include: a PMOS transistor MP1 and an NMOS transistor MN1, both with their gates connected to the enable control signal EN, and their sources connected to the high-level output terminal VDD and the low-level output terminal VSS of the drive power supply, respectively; a PMOS transistor MP2, with its source connected to the high-level output terminal VDD of the drive power supply, and its gate and drain connected to the drain of the PMOS transistor MP1; and an NMOS transistor MN2, with its gate connected to the control voltage VSS. CTRLThe drain of PMOS transistor MP2 is connected to the drain of PMOS transistor MP3, and the source of NMOS transistor MN1 is connected to the drain of NMOS transistor MN1. The sources of PMOS transistor MP3 and NMOS transistor MN3 are connected to the high-level output terminal VDD and the low-level output terminal VSS of the driving power supply, respectively. The gate of PMOS transistor MP3 is connected to the drain of PMOS transistor MP2 and outputs a positive voltage signal VOP. The gate of NMOS transistor MN3 is connected to the drain of NMOS transistor MN3 and outputs an inverted voltage signal VON. The drains of PMOS transistor MP4 and NMOS transistor MN4 are connected to each other, and their gates are connected to the low-level output terminal VSS and the high-level output terminal VDD of the driving power supply, respectively. The source of PMOS transistor MP4 is connected to the drain of PMOS transistor MP3, and the source of NMOS transistor MN4 is connected to the drain of NMOS transistor MN3.

[0052] like Figure 2 As shown, the voltage-to-current conversion circuit can also include a linear regulator, which is located between the source of NMOS transistor MN2 and the drain of NMOS transistor MN1, so that the current-to-voltage conversion circuit can switch between various linearity configurations.

[0053] In this voltage-to-current conversion circuit, PMOS transistor MP1 and NMOS transistor MN1 are enable control transistors, PMOS transistor MP2 is the load transistor, NMOS transistor MN2 is the input transistor, PMOS transistor MP3 and NMOS transistor MN3 are control voltage output transistors, and PMOS transistor MP4 and NMOS transistor MN4 are used for matching the delay unit. When EN is at the first level (e.g., high level), the control signal V... CTRL The NMOS transistor MN2 is input into the circuit. At this time, NMOS transistor MN2 and the linear regulator form a common-source operational amplifier with source negative feedback. PMOS transistor MP2 is connected as a diode as a load and serves as the replication reference for the current mirror. The current signal completed by the linear conversion of NMOS transistor MN2 is copied to the branches containing PMOS transistors MP3, NMOS transistors MN3, MP4 and MN4, and output to each unit of the delay circuit through the VOP and VON voltage signals. When EN is at the second level (e.g., low level), PMOS transistors MP1 and NMOS transistor MN1 are turned off, and the voltage-to-current conversion circuit does not work, which can reduce the power consumption of the circuit.

[0054] Figure 3 A schematic diagram of the delay unit in one embodiment of this invention is shown. Figure 3As shown, the delay unit may include: PMOS transistors MP5 and MP6, both of which have their gates connected to a positive voltage signal VOP, and their sources connected to the high-level output terminal VDD of the driving power supply, and their drains connected to the second control input ports of the first input channel IN1 and the second input channel IN2, respectively; and NMOS transistors MN5 and MN6, both of which have their gates connected to an inverted voltage signal VON, and their sources connected to the low-level output terminal VSS of the driving power supply, and their drains connected to the second control input ports of the first input channel IN1 and the second input channel IN2, respectively.

[0055] Among them, PMOS transistors MP5, MP6, NMOS transistors MN5 and MN6 are responsible for adjusting the delay of the delay module. IN1 and IN2 are two input channels of the delay unit, both of which are differential input channels. IN1P and IN1N are the non-inverting and inverting input terminals of the IN1 input channel, respectively. IN2P and IN2N are the non-inverting and inverting input terminals of the IN2 input channel, respectively. Signal S is the control signal output by the channel selector, which is connected to the first control input port of the first input channel IN1 and the second input channel IN2.

[0056] like Figure 3 As shown, the delay unit can also be configured to include a first inverter and a second inverter. The input terminal of the first inverter is connected to the non-inverting output terminals of the two input channels, and the input terminal of the second inverter is connected to the inverting output terminals of the two input channels. The output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the input terminal of the first inverter. The output terminals of the first and second inverters are respectively the non-inverting and inverting output terminals of the delay unit. Specifically, as shown... Figure 3 As shown, the first inverter includes a PMOS transistor MP7 and an NMOS transistor MN7, and the second inverter includes a PMOS transistor MP8 and an NMOS transistor MN8. The sources of PMOS transistors MP7 and MP8 are connected to the high-level output terminal VDD of the driving power supply, and the sources of NMOS transistors MN7 and MN8 are connected to the low-level output terminal VSS of the driving power supply. The gates of PMOS transistors MP7 and MN7 are connected as the input terminal of the first inverter, and the drains of PMOS transistors MP7 and MN7 are connected as the output terminal of the first inverter. The gates of PMOS transistors MP8 and MN8 are connected as the input terminal of the second inverter, and the drains of PMOS transistors MP8 and MN8 are connected as the output terminal of the second inverter.

[0057] Example 2

[0058] Figure 4A flowchart illustrating a control method for a delay-locked loop (PLL) circuit in one embodiment of this invention is shown. This control method is used to control the delay-locked loop circuit described in any embodiment of Embodiment 1 above. A detailed description of this delay-locked loop circuit can be found in Embodiment 1 above, and will not be repeated here. Figure 4 As shown, the method includes the following steps:

[0059] S110: Apply a first level signal to the first control input port of the first delay unit in the delay circuit to control the first input channel of the first delay unit to be turned on.

[0060] S120: When the number of reference clock signal cycles counted by the frequency divider counter reaches a preset value, a second level signal is applied to the first control input port to control the second input channel of the first delay unit to be turned on.

[0061] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A delay phase-locked loop circuit, characterized in that, include: A single-ended to differential circuit is used to convert an externally input reference clock signal. The delay circuit includes at least two delay units, wherein the first delay unit has two input channels, a first input channel and a second input channel, and two control input ports, a first control input port and a second control input port; After the converted reference clock signal is connected to the first input channel, it is input to a frequency divider counter. The output of the frequency divider counter is connected to a channel selector, which is connected to the first control input port. When the number of reference clock signal cycles counted by the frequency divider counter reaches a preset value, the channel selector outputs a control signal to the first control input port, which turns on the second input channel. The reference clock signal then enters the delay circuit and cycles through the second input channel. The feedback clock signal output by the delay circuit is fed back to the basic phase-locked loop circuit. The basic phase-locked loop circuit generates a tuning current based on the phase difference between the feedback clock signal and the reference clock signal and inputs it to the second control input port to adjust the delay time of the delay unit until the feedback clock signal and the reference clock signal are in phase.

2. The delay-locked loop circuit according to claim 1, characterized in that, The basic phase-locked loop circuit includes: A frequency and phase detector is configured to compare the phase difference between the feedback clock signal and the reference clock signal; A charge pump, connected to the frequency and phase detector, is configured to convert the phase difference between the reference clock signal and the feedback clock signal into a proportional charging and discharging current. A loop filter, connected to the charge pump, is configured to filter the current output by the charge pump to generate a control voltage; A voltage-to-current conversion circuit, connected to the loop filter, is configured to convert the control voltage into a current signal that is linearly related to it; the current signal is the tuning current.

3. The delay phase-locked loop circuit according to claim 2, characterized in that, The delay unit further includes a first inverter and a second inverter. The input terminal of the first inverter is connected to the non-inverting output terminals of the two input channels, and the input terminal of the second inverter is connected to the inverting output terminals of the two input channels. The output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the input terminal of the first inverter. The output terminals of the first inverter and the second inverter are respectively the non-inverting output terminal and the inverting output terminal of the delay unit.

4. The delay phase-locked loop circuit according to claim 3, characterized in that, The voltage-to-current conversion circuit includes: PMOS transistor MP1 and NMOS transistor MN1, both of which have their gates connected to an enable control signal, and their sources are connected to the high-level output terminal and the low-level output terminal of the drive power supply, respectively. PMOS transistor MP2 has its source connected to the high-level output terminal of the driving power supply, and its gate and drain are both connected to the drain of PMOS transistor MP1. The gate of NMOS transistor MN2 is connected to the control voltage, the drain is connected to the drain of PMOS transistor MP2, and the source is connected to the drain of NMOS transistor MN1. PMOS transistor MP3 and NMOS transistor MN3, the sources of which are connected to the high-level output terminal and the low-level output terminal of the driving power supply, respectively. The gate of PMOS transistor MP3 is connected to the drain of PMOS transistor MP2 and outputs a positive voltage signal. The gate of NMOS transistor MN3 is connected to the drain of NMOS transistor MN3 and outputs an inverted voltage signal. PMOS transistor MP4 and NMOS transistor MN4 are connected at their drains and their gates are connected to the low-level output terminal and the high-level output terminal of the driving power supply, respectively. The source of PMOS transistor MP4 is connected to the drain of PMOS transistor MP3, and the source of NMOS transistor MN4 is connected to the drain of NMOS transistor MN3.

5. The delay phase-locked loop circuit according to claim 4, characterized in that, The delay unit includes: PMOS transistors MP5 and MP6 have their gates connected to the positive voltage signal, their sources connected to the high-level output terminal of the driving power supply, and their drains connected to the second control input ports of the first input channel and the second input channel, respectively. NMOS transistors MN5 and MN6 have their gates connected to the inverted voltage signal, their sources connected to the low-level output of the driving power supply, and their drains connected to the second control input ports of the first input channel and the second input channel, respectively.

6. The delay phase-locked loop circuit according to claim 5, characterized in that, The first inverter includes a PMOS transistor MP7 and an NMOS transistor MN7, and the second inverter includes a PMOS transistor MP8 and an NMOS transistor MN8. The sources of the PMOS transistors MP7 and MP8 are connected to the high-level output terminal of the driving power supply, and the sources of the NMOS transistors MN7 and MN8 are connected to the low-level output terminal of the driving power supply. The gates of the PMOS transistors MP7 and MN7 are connected as the input terminal of the first inverter, and the drains of the PMOS transistors MP7 and MN7 are connected as the output terminal of the first inverter. The gates of the PMOS transistors MP8 and MN8 are connected as the input terminal of the second inverter, and the drains of the PMOS transistors MP8 and MN8 are connected as the output terminal of the second inverter.

7. The delay phase-locked loop circuit according to claim 1, characterized in that, The delay circuit includes four or more even-numbered delay units, and the signal output by the last delay unit is cross-coupled to the second input channel of the first delay unit.

8. A control method for a delay phase-locked loop circuit as described in any one of claims 1-7, characterized in that, Includes the following steps: A first level signal is applied to the first control input port of the first delay unit in the delay circuit to control the first input channel of the first delay unit to be turned on; When the number of reference clock signal cycles counted by the frequency divider counter reaches a preset value, a second level signal is applied to the first control input port to control the second input channel of the first delay unit to be turned on.

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