Low resource overhead companion clock based training method

Abstract

The low resource occupation rate training method based on the accompanying clock relates to the training method of the accompanying clock, solves the problems that in the low frequency application process of the existing detector, for the high density FPGA internal layout wiring, there is a wiring problem, and an additional clock with double pixel clock frequency is needed, and the application proposes that a single shift register is used to generate the write pulse of the effective data and control the write operation address in the word correction stage, the pulse of each word correction only acts in front of the count signal of the output effective write pulse, the repeated writing of two groups of data is avoided, and the resource utilization is reduced. Through the estimation of the tap number, different sampling positions can be set according to the detected tap number, so that the training error condition caused by detecting a single jump edge position is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to a training method of a companion clock, and particularly relates to a low-resource-occupancy training method based on a companion clock. BACKGROUND

[0002] In order to improve the temperature adaptability of the detector serial image data conditioning, the detector outputs a low phase deviation companion clock of the serial image data of different regions to perform synchronization control of serial-to-parallel conversion. The serial data of multiple regions are configured with a companion clock, which occupies more clock resources in the FPGA. If the iserdes resource in the FPGA is used for serial-to-parallel conversion, there may be a routing problem for high-density FPGA internal layout and wiring, and an additional clock with a double-pixel clock frequency is also needed. An existing training method keeps a counter unchanged during word correction, and uses another counter to generate a write pulse of the effective number and control the write address, which consumes two counters.

[0003] The state transition diagram of the existing bit correction is shown in Figure 1 When a new channel training starts, it enters the "find the first jump edge" stage, and after detecting the first jump edge, it enters the "find the first stable sampling eye start position" stage. After experiencing the first jump edge, the data starts to be stable, and then enters the "find the second jump edge" stage. When the second jump edge is detected, if the tap does not meet the specified number, it enters the "find the first stable sampling eye start position" stage, otherwise it enters the "second jump edge found" stage.

[0004] In the "find the first jump edge" stage, the delay number of the current IODELAY subchannle_EYE_CHECK_cnt is assigned to the first jump edge position loc_eye_start. In the "find the second jump edge" stage, the stable length count cnt_stable starts to increase by 1. In the "second jump edge found" stage, when the state of unstable data is detected at the same time:

[0005] loc_eye_end=loc_eye_start+cnt_stable;

[0006] loc_eye_mid=loc_eye_start+cnt_stable / 2;

[0007] loc_eye_mid is the final setting of the sampling position, and loc_eye_end is the detected second jump edge position. SUMMARY

[0008] The present application provides a low-resource-occupancy training method based on a companion clock to solve the problems of routing failure and the need for additional clock with double pixel clock frequency in the low-frequency application of the existing detector.

[0009] The low-resource-occupancy training method based on a companion clock is realized by a low-resource-occupancy training system based on a companion clock, which comprises an IBUFDS, an IODELAY, an IDDR, an mbit shift register, a RAM, five D flip-flops, an inverter INV1, an inverter INV2, and an m / 2bit shift register.

[0010] The differential serial image data data_serailin_p and data_serailin_n output by the detector are converted into single-ended data data_ser by the IBUFDS, delayed by the IODELAY, and sent to the IDDR for double-edge sampling with the same frequency as the FPGA internal clock clk_ser. The two signals after double-edge sampling are signal iddr_q1 and signal iddr_q2. Signal iddr_q1 is sent to the mbit shift register as the rising edge sampling signal data_1 after passing through the D flip-flop D1. Iddr_q2 is output as the falling edge sampling signal data_2 after passing through the D flip-flop D2 and sent to the mbit shift register. At the same time, the falling edge sampling signal data_2 is sent to the m bit shift register as the falling edge sampling delay signal data_2_q after passing through the D flip-flop D3. The shift data shift_data output by the m bit shift register is sent to the RAM across the clock domain after being output by the D flip-flop D4.

[0011] The word correction level control signal bitsip_even with the rising edge of the pulse bitsip high only once enables inversion at the rising edge of each pulse bitsip and is connected to the EN end of the inverter INV1. Bitsip_even controls the mbit shift register to realize different parallel data combinations in the high and low level stages. The parallel data load enable signal load_parallel is generated by the m / 2bit shift register. The data input end D of the m / 2bit shift register is connected to low level 0, the parallel set end s is connected to high level 1, and the parallel set control end l is connected to the control signal bitslip_req. The m / 2bit shift register increases 1 bit of 0 every time it moves.

[0012] When the values in the m / 2 bit shift register are all 0, then the next clock is set to all 1; when the values in the m / 2 bit shift register are all 0, the parallel data load enable signal load_parallel is set to high level, otherwise it is set to low level; the bitsip_even connects the first enable input end of the D flip-flop D5; the second enable input end of the D flip-flop D5 is connected to the low 3 bits of the m / 2 bit shift register, which are the second bit and the zeroth bit after being negated and ANDed with the first bit; the third enable input end of the D flip-flop D5 is the negated control signal bitslip_req through the inverter INV2; the three enable input ends are connected to the EN end of D5 after performing "wire AND" operation;

[0013] The parallel data load enable signal load_parallel output by the m / 2 bit shift register controls the D flip-flop D4, and when load_parallel is high, the D flip-flop D4 is enabled to output.

[0014] The process of bit correction is as follows:

[0015] I. According to the frequency f of the serial image data serial_data , the reference clock frequency f of IODELAY reference , and the maximum tap number n of iodelay tap_max Estimate the maximum tap number n corresponding to the stable region that may be detected data_tap_max ;

[0016]

[0017] II. According to the relative relationship between the frequency f of the serial image data serial_data and the reference clock frequency f of IODELAY reference , determine the number of jump edges that bit correction may detect:

[0018]

[0019] In the formula, t jitter_left is the left jitter time of the parallel data, t jitter_right is the right jitter time of the parallel data;

[0020] Test the delay time t iodelay_ce_delay from the start of the tap value change of IODELAY, i.e. the enable signal ce of IODELAY is valid high, to the start of the change of the received parallel data: set the delay time from the start of the tap value change of IODELAY to the start of the detection of the stability of the parallel data and the duration of the detection process to the same p pixel clock periods: p pixel clock periods need to meet the following conditions:

[0021]

[0022] In the formula, m is the bit width of the parallel data.

[0023] The length t of the stable region of the test serial image data sdata_wending ,Right now:

[0024]

[0025] Once the first transition edge is detected, the relative position of the first transition edge is determined:

[0026] a) When the position of the first detected transition edge is less than the maximum number of taps n of IODELAY tap_max Half of, that is When IODELAY is delayed, the delay direction is an increase in the number of taps;

[0027] b) When the position of the first detected transition edge is greater than or equal to the maximum number of taps n of IODELAY tap_max half of When IODELAY is delayed, the delay direction is a decrease in the number of taps;

[0028] During the in-situ correction phase, when detecting the position of the transition edge, the maximum number of taps traversed is 2n. tap_max :

[0029] a) If no transition edge is detected, the number of taps traversed reaches 2n. tap_max Then stop the bit correction operation; the maximum number of taps that this training method can detect is n. tap_max Then the final sampling position value loc_eye_mid is

[0030] b) When only one transition edge is detected, and the position of that transition edge has exceeded the maximum number of taps n tap_max Half of n and less than n tap_max When the sampling position value loc_eye_mid is half of the position loc_eye_start of the transition edge, the final sampling position value is taken.

[0031] c) When two transition edges are detected, the bit correction operation is stopped, and the number of taps n corresponding to the stable sampling region between the two transition edges is determined. data_tap_check Greater than or equal to And less than n data_tap_max When the sampling position is such that the final sampling position is the average of the two transition edge positions;

[0032] When the number of taps corresponding to the stable sampling region between two transition edges is greater than n data_tap_maxWhen t, the final sampling position takes the value of the second jump edge position minus t sdata_wending .

[0033] The present application has the following beneficial effects:

[0034] 1. The method of the present application uses a companion clock with small phase change relative to serial image data for training, which has good temperature adaptability and does not require dynamic training.

[0035] 2. The method of the present application can set different sampling positions according to the detected tap number by estimating the tap number, thereby avoiding the situation of training error caused by detecting a single jump edge position.

[0036] 3. The method of the present application proposes to use a single shift register to generate an effective data write pulse and control the write operation address in the word correction stage, and the pulse of each word correction only acts in front of the count signal outputting the effective write pulse, thereby avoiding repeated writing of two groups of data and reducing resource usage. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is the state transition diagram of the existing bit correction;

[0038] Figure 2 is a CMOS data training system block diagram of the present application. DETAILED DESCRIPTION

[0039] In combination Figure 2 The present embodiment is a low-resource-consumption training method based on a companion clock, which is implemented by a CMOS data training system. The training system includes a differential-to-single-ended converter (IBUFDS), an input-output delay device (IODELAY), a double-edge sampler (IDDR), an mbit shift register, a RAM, five D flip-flops, an inverter INV1, an inverter INV2, and an m / 2bit shift register.

[0040] The serial image data data_serailin_p and data_serailin_n outputted by the detector in differential form is converted into single-ended data data_ser by IBUFDS, and then is delayed by IODELAY. The delayed signal data_ser_del is inputted into IDDR to be double-edge sampled with the internal clock clk_ser of the FPGA with the same frequency as the serial image data. The two signals after double-edge sampling are signal iddr_q1 and signal iddr_q2. The signal iddr_q1 is inputted into mbit shift register as rising edge sampling signal data_1 after passing through D flip-flop D1. The signal iddr_q2 is outputted as falling edge sampling signal data_2 after passing through D flip-flop D2 and inputted into mbit shift register. At the same time, the falling edge sampling signal data_2 is inputted into m bit shift register as falling edge sampling delay signal data_2_q after passing through D flip-flop D3. The shift data shift_data outputted by the m bit shift register is inputted into D flip-flop D4 to be latched and then outputted into the RAM across the clock domain.

[0041] The frequency of the clock clk_ser is half of the frequency of the serial image data, which is the accompanying clock. The word correction level control signal bitsip_even becomes high only at the rising edge of the two pulses bitsip, and is enabled to be inverted at the rising edge of each pulse bitsip and connected to the EN end of the inverter INV1. The bitsip_even controls the m bit shift register to realize different parallel data combinations in the high level and low level stages, respectively. The parallel data loading enable signal load_parallel is generated by m / 2bit shift register. The data input end D of the m / 2bit shift register is connected to low level 0, the parallel set end s is connected to high level 1, and the parallel set control end l is connected to the control signal bitslip_req. The m / 2bit shift register increases 1 bit of 0 every time it moves;

[0042] When the values in the m / 2 bit shift register are all 0, then the next clock sets them all to 1; when the values in the m / 2 bit shift register are all 0, the parallel data load enable signal load_parallel is set to high, otherwise it is set to low. The bitsip_even connects the enable terminal EN of the D flip-flop D5; the second enable input terminal of the D flip-flop D5 is connected to the low 3 bits of the m / 2 bit shift register, which are the second bit and the zeroth bit after being negated and ANDed with the first bit; the third enable input terminal of the D flip-flop D5 is the negation of the control signal bitslip_req through the inverter INV2. That is, when the input bitsip_even of D5 is high, and the low 3 bits of the m / 2 bit shift register are 010 and bitslip_req is low, bitslip_req outputs a high level pulse; that is, when bitsip_even is high, the m / 2 bit shift register directly skips the state where the low 3 bits are 001. The parallel data load enable signal load_parallel output by the m / 2 bit shift register controls D4, and when load_parallel is high, D4 is enabled to output.

[0043] In this embodiment, the control of the RAM write operation across the clock domain: the write enable is generated by delaying the parallel data load enable signal load_parallel by one clock signal; the write address is incremented by 1 each time load_parallel is high;

[0044] The process of bit correction is as follows:

[0045] I. According to the frequency f of the serial image data serial_data , the reference clock frequency f of the IODELAY reference , and the maximum tap number n of the iodelay tap_max Estimate the maximum tap number n corresponding to the stable region that can be detected data_tap_max ;

[0046]

[0047] II. According to the relative relationship between the frequency f of the serial image data serial_data and the reference clock frequency f of the IODELAY reference , determine the number of transition edges that bit correction can detect:

[0048]

[0049] In the formula, t jitter_left is the left jitter time of the parallel data, t jitter_rightThis represents the right-side jitter time of the parallel data.

[0050] Using the ChipScope function of an online logic analyzer (a function provided by the controller), the delay time t from the start of a change in the tap value of IODELAY (i.e., when IODELAY's ce is at a valid high level) to the start of a change in the received parallel data was tested. iodelay_ce_delay Then, set the delay time from when the iodelay tap value starts changing to when the parallel data stability detection begins, and the detection process duration, to be the same as p pixel clock cycles. The p pixel clock cycles need to meet the following conditions:

[0051]

[0052] In the formula, m is the bit width of the parallel data.

[0053] Using the ChipScope function, the length t of the stable region of serial image data was measured. sdata_wending ,Right now:

[0054]

[0055] 3. After detecting the first transition edge, determine the relative position of the first transition edge:

[0056] a) When the position of the first detected transition edge is less than the maximum number of taps n of IODELAY tap_max half of When IODELAY is delayed, the delay direction is an increase in the number of taps;

[0057] b) When the position of the first detected transition edge is greater than or equal to the maximum number of taps n of IODELAY tap_max half of When IODELAY is delayed, the delay direction is a decrease in the number of taps;

[0058] In this embodiment, the operation of detecting the transition edge position during the bit correction stage can potentially traverse a maximum of 2n taps. tap_max :

[0059] a) If no transition edge is detected, the number of taps traversed reaches 2n. tap_max Then stop the bit correction operation; the maximum number of taps that this training method can detect is n. tap_max Then the final sampling position value loc_eye_mid is

[0060] b) When only one transition edge is detected, and the position of that transition edge has exceeded the maximum number of taps n tap_max Half of n and less than n tap_maxWhen two edges are detected, the final sampling position takes the value of loc_eye_mid which is half of the position of loc_eye_start.

[0061] loc_eye_mid = loc_eye_start / 2;

[0062] c) When two edges are detected, the bit correction operation is stopped, and when the tap number n corresponding to the stable sampling region between the two edges is greater than or equal to n data_tap_check and less than n , the final sampling position takes the value of loc_eye_mid which is half of the position of loc_eye_start. data_tap_max

[0063]

[0064] When two edges are detected, the final sampling position takes the value of loc_eye_mid which is half of the position of loc_eye_start.

[0065] When the tap number n corresponding to the stable sampling region between the two edges is greater than n data_tap_max , the final sampling position takes the value of loc_eye_mid which is half of the position of loc_eye_start.

[0066] n data_tap_check＞ n data_tap_max

[0067] When the tap number n corresponding to the stable sampling region between the two edges is greater than n sdata_wending , the final sampling position takes the value of loc_eye_mid which is half of the position of loc_eye_start.

[0068] In this embodiment, IBUFDS, IODELAY, IDDR, m-bit shift register, D flip-flop, inverter, memory RAM, etc. are virtex 6 devices and their internal resources; the detector uses a customized product of Changguanchen Chip Co., Ltd.​

Claims

1. A low resource footprint, companion clock based training method, characterized in that: The training method is implemented by a low-resource-occupancy training system based on a companion clock, and the specific steps are as follows: Step one, according to the frequency f of serial image data serial_data , reference clock frequency f of IODELAY reference and the maximum tap number n of IODELAY tap_max estimate the maximum tap number n corresponding to the detected stable region data_tap_max ; the frequency of the internal clock clk_ser of FPGA is half of the frequency of serial image data, as the accompanying clock; the specific estimation process is as follows: a) When no jump edge is detected, the number of taps traversed reaches 2n tap_max After stopping the bit correction operation; this training method can detect the maximum number of taps n tap_max The final sampling position value loc_eye_mid is b) when only one edge is detected, and the edge position has exceeded half of the maximum tap number n tap_max , and is less than n tap_max , then the final sample position is set to loc_eye_mid which is half of the edge position loc_eye_start. c) when two jump edges are detected, stop the bit correction operation, and when the tap number n corresponding to the stable sampling region between the two jump edges is greater than or equal to data_tap_check and less than n , then the final sampling position takes the average value of the two jump edge positions data_tap_max . When the tap number corresponding to the stable sampling region between two jump edges is greater than n data_tap_max , the final sampling position is the second jump edge position minus the length t of the stable region of serial image data sdata_wending . Step two, determining the number of possible detected transition edges from the relative relationship of the frequency f of the serial image data and the reference clock frequency f of the IODELAY serial_data reference ​​ Step three, when the first jump edge is detected, the relative position of the first jump edge is determined to determine the delay direction of IODELAY; Step four, in the operation process of detecting the jump edge position in the bit correction stage, the maximum tap number of traversal is 2n tap_max , determine the final sampling position value.

2. The low-resource companion clock-based training method of claim 1, wherein: The maximum tap number n corresponding to the stable region detected in step one data_tap_max The formula is as follows:

3. The low-resource companion clock-based training method of claim 1, wherein: In step two, the number of detected jump edges is determined as follows: In the formula, t jitter_left is the left jitter time of the parallel data, t jitter_right is the right jitter time of the parallel data; The delay time t in which the tap value of the IODELAY starts to change from the IODELAY enable signal ce being active high to the received parallel data starts to change iodelay_ce_delay The delay time in which the tap value of the IODELAY starts to change and the detection process duration are set to be the same p pixel clock periods, and the p pixel clock periods need to satisfy the following conditions: In the formula, m is the bit width of the parallel data. Test the length t of the stable region of the serial image data sdata_wending is expressed by the following equation:

4. The low-resource-compute-companion clock-based training method of claim 1, wherein: In step three, when the first jump edge is detected, the relative position of the first jump edge is determined to determine the delay direction of IODELAY, and the specific process is as follows: a) when the first detected jump along position is less than half of the maximum tap number n of IODELAY, i.e. tap_max then the delay direction of IODELAY is tap number increment;​ b) when the first detected jump edge position is greater than or equal to half of the maximum tap number n of IODELAY tap_max , then the delay direction of IODELAY is tap number decreasing. ​ 5. The low-resource-compute-companion clock-based training method of claim 1, wherein: The training system comprises a differential-to-single-ended converter IBUFDS, an input-output delay converter IODELAY, a double-edge sampler IDDR, an m bit shift register, a RAM, five D flip-flops, an inverter INV1, an inverter INV2 and an m / 2 bit shift register. The differential serial image data data_serailin_p and data_serailin_n output by the detector are converted into single-ended data data_ser by IBUFDS, delayed by IODELAY, and sent to IDDR for double-edge sampling with the same frequency as the FPGA internal clock clk_ser. The two signals after double-edge sampling are signal iddr_q1 and signal iddr_q2. Signal iddr_q1 is sent to the m bit shift register as the rising edge sampling signal data_1 after passing through D flip-flop D1. Iddr_q2 is output as the falling edge sampling signal data_2 after passing through D flip-flop D2 and sent to the m bit shift register. At the same time, the falling edge sampling signal data_2 is sent to the m bit shift register as the falling edge sampling delay signal data_2_q after passing through D flip-flop D3. The shift data shift_data output by the m bit shift register is sent to the RAM through D flip-flop D4 and then output. The rising edge of the two pulses bitsip becomes high only when the word correction level control signal bitsip_even is enabled at the rising edge of each pulse bitsip and connected to the EN end of the inverter INV1. Bitsip_even controls the m bit shift register to realize different parallel data combinations in the high level and low level stages, respectively. The parallel data load enable signal load_parallel is generated through the m / 2 bit shift register. The data input end D of the m / 2 bit shift register is connected to low level 0, the parallel set end s is connected to high level 1, and the parallel set control end l is connected to the control signal bitslip_req. The m / 2 bit shift register increases 1 bit of 0 every time it moves. When the values in the m / 2 bit shift register are all 0, then the next clock is set to all 1; when the values in the m / 2 bit shift register are all 0, the parallel data load enable signal load_parallel is set to high level, otherwise it is set to low level; the first enable input end of the D flip-flop D5 is connected with bitsip_even; the second enable input end of the D flip-flop D5 is connected with the low 3 bits of the m / 2 bit shift register, which are the second bit and the zero bit after being inverted and then ANDed with the first bit; the third enable input end of the D flip-flop D5 is the inverted control signal bitslip_req after passing through the inverter INV2; the three enable input ends are connected to the EN end of D5 after being "line and" operated; The parallel data load enable signal load_parallel output by the m / 2 bit shift register controls the D flip-flop D4, and when load_parallel is high, the D flip-flop D4 is enabled to output.

6. The low-resource companion clock-based training method of claim 1, wherein: The control process of the RAM write operation across the clock domain is that the write enable signal is generated by delaying the parallel data load enable signal load_parallel by one clock signal; the write address is incremented by 1 every time load_parallel is high.

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