Readout circuit for a photoelectric imaging array, readout circuit calibration method and system

Abstract

The application discloses a readout circuit of a photoelectric imaging array, a readout circuit calibration method and system, relates to the technical field of integrated circuits, and solves the problem that random deviation exists in a CDS capacitor and a feedback capacitor in an MDAC of an existing readout circuit, which causes the output voltage of the MDAC to exceed the input voltage range of a backend ADC. The technical scheme is as follows: a saturation detection circuit is added to determine whether the output of the backend ADC is saturated; when the saturation detection circuit detects that the output of the backend ADC is saturated, a DAC input is configured through an SPI CFG, so that the output voltage of the integrator is equal to the reference voltage of a SUBADC, the proportional deviation of the sampling capacitor in the integrator and the feedback capacitor in the MDAC is detected, the reference voltage of the SUBADC is automatically adjusted, and the purpose of ensuring that the entire signal link works normally is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and more particularly, to a readout circuit of a photoelectric imaging array, a readout circuit calibration method and system. BACKGROUND

[0002] Photoelectric imaging array: a photodiode is a PN junction composed of an N-type semiconductor and a P-type semiconductor, which is reversely biased in operation and generates charges under light, and the amount of generated charges is proportional to the intensity of incident light. An array structure composed of multiple photodiodes can be used for imaging. After array exposure, the amount of charges generated on the diodes reflects the information of the image.

[0003] Readout circuit: the signal generated by the photodiode array is converted into a digital signal by the readout circuit for each pixel. The charge information of the diode array is read out row by row, and each column of diodes shares one readout circuit. The charge in the diode is first converted into a voltage by an integrator, and then converted into a digital signal by an ADC (analog-to-digital converter), and the information of the image is reconstructed through digital signal processing.

[0004] PPIPELINE ADC (multi-stage serial working analog-to-digital converter) first stage is a multi-bit MDAC (multiplying digital-to-analog converter) to generate high-bit digital output, and the residual of the MDAC is converted into low-bit output by the ADC in the later stage. After the combination of the high-bit digital signal and the low-bit digital signal, the ADC output is obtained. This structure can realize a high-precision and high-speed analog-to-digital converter.

[0005] In the original readout circuit structure, the SUBADC (sub-analog-to-digital converter) and the CDS capacitor (sampling capacitor) are placed in the integrator channel. Due to the random deviation between the CDS capacitor and the feedback capacitor in the MDAC, the output voltage of the MDAC exceeds the input voltage range of the ADC in the later stage, resulting in an error in the entire ADC conversion result. SUMMARY

[0006] The purpose of the present application is to provide a readout circuit of a photoelectric imaging array, a readout circuit calibration method and system, to detect the proportional deviation between the sampling capacitor in the integrator and the feedback capacitor in the MDAC, automatically adjust the reference voltage of the SUBADC, and ensure the normal operation of the entire signal link.

[0007] The above technical purpose of the present application is achieved by the following technical scheme:

[0008] A readout circuit calibration method for a photoelectric imaging array, comprising the following steps:

[0009] S1. Detecting the state of the backend ADC output value under the current SUBADC reference voltage;

[0010] S2. When the backend ADC output value is an abnormal value, adjusting the SUBADC reference voltage through an internal register to obtain an adjusted backend ADC output value, updating the backend ADC output value with the adjusted backend ADC output value, and performing S1; and when the backend ADC output value is not an abnormal value, outputting a normal backend ADC value.

[0011] Further, the backend ADC output value being an abnormal value includes: when the backend ADC input value is greater than a maximum input threshold of the backend ADC, the backend ADC output value being 1; and when the backend ADC input value is less than a minimum input threshold of the backend ADC, the backend ADC output value being 0.

[0012] Further, the precision of the SUBADC is 5 bits.

[0013] Further, the maximum input threshold of the backend ADC is 2 V.

[0014] Further, the minimum input threshold of the backend ADC is -2 V.

[0015] A readout circuit calibration system of a photoelectric imaging array includes: a detection module configured to detect a state of a backend ADC output value under a current SUBADC reference voltage; and a configuration module configured to, when the backend ADC output value is an abnormal value, adjust the SUBADC reference voltage through an internal register to obtain an adjusted backend ADC output value, update the backend ADC output value with the adjusted backend ADC output value, and perform S2; and when the backend ADC output value is not an abnormal value, output a normal backend ADC value.

[0016] Further, the configuration module includes an internal register and a DAC buffer; an input end of the internal register is connected to an output end of the detection module; an input end of the DAC buffer is connected to an output end of the internal register; and an output end of the DAC buffer is connected to an input end of an integrator through a charge injection capacitor.

[0017] Further, the DAC buffer includes a DAC circuit and a buffer driving circuit connected to an output end of the DAC circuit; the DAC circuit is connected to the internal register; and an output end of the buffer driving circuit is connected to the charge injection capacitor.

[0018] Further, the readout circuit of the photoelectric imaging array includes the readout circuit calibration system of the photoelectric imaging array, and further includes a PIPELINE ADC circuit, wherein an output end of a backend ADC in the PIPELINE ADC circuit is connected with an input end of the detection circuit.

[0019] Further, the backend ADC is a successive approximation ADC.

[0020] Compared with the prior art, the present application has the following beneficial effects:

[0021] The readout circuit calibration method of the photoelectric imaging array detects the proportion deviation of the sampling capacitor in the integrator and the feedback capacitor in the MDAC by detecting the output value of the backend ADC, and automatically adjusts the reference voltage of the SUBADC through the internal register, so as to ensure the normal operation of the entire signal link. BRIEF DESCRIPTION OF DRAWINGS

[0022] The accompanying drawings, which are included to provide a further understanding of the embodiments of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application. In the drawings:

[0023] Figure 1 FIG. 1 is a circuit structure diagram of a PIPELINE ADC (analog-digital converter working in a multi-stage serial structure);

[0024] Figure 2 FIG. 2 is a structural schematic diagram of an existing readout circuit of a photoelectric imaging array;

[0025] Figure 3 FIG. 3 is a transfer curve of the input and output of the MDAC in the existing readout circuit of the photoelectric imaging array, wherein 3(a) represents the MDAC transfer curve when CSp=CSn / Cf=16, 3(b) represents the MDAC transfer curve when the gain between CSp and CSn exceeds 16.25, and 3(c) represents the MDAC transfer curve when the gain between CSp and CSn is lower than 15.75;

[0026] Figure 4 FIG. 4 is a structural schematic diagram of the readout circuit of the photoelectric imaging array in the embodiment;

[0027] Figure 5 FIG. 5 is a structural schematic diagram of the integrator circuit used in the readout circuit of the photoelectric imaging array in the embodiment;

[0028] Figure 6 FIG. 6 is the MDAC transfer curve after calibration of the readout circuit of the photoelectric imaging array in the embodiment. DETAILED DESCRIPTION

[0029] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the embodiments and drawings, and the illustrative embodiments of the present application and their descriptions are only used to explain the present application and do not limit the present application.

[0030] It should be noted that when a component is referred to as being "fixed" or "set" on another component, it can be directly on the other component or indirectly on the other component. When a component is referred to as being "connected" to another component, it can be directly or indirectly connected to the other component.

[0031] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0032] Embodiment: a readout circuit of a photoelectric imaging array, a readout circuit calibration method and system.

[0033] As Figure 1 The PIPELINE ADC (analog-to-digital converter with multiple stages working in series) circuit structure diagram is shown. The first stage is an MDAC (multiply DAC), which includes PART1, PART2 and PART3. PART1 includes the following parts: IP and IN are differential input terminals, SW1 and SW2 are sampling switches, CSp and CSn are sampling capacitors for sampling the differential input signal. SUBADC (sub-analog-to-digital converter) converts the differential input into a digital signal, and the SUBADC is a multi-bit output. PART2 includes the following parts: SWP, SWN and SWD are sampling switches, which are turned off during sampling, and SWD is a switch for outputting the multi-bit digital signal of the SUBADC. PART3 includes the following parts: DACP and DACN are differential DACs (differential digital-to-analog converters), whose input is the output of the SUBADC, Cf is a feedback capacitor, and OP is a residual amplifier. The above three parts of the MDAC realize analog output sampling, use the SUBADC to coarsely quantize, then input and subtract the DAC output to amplify and output the residual error, and output the coarsely quantized result of the SUBADC.

[0034] The backend ADC of the PIPELINE ADC converts the residual of the MDAC to get the digital output of the backend ADC. The total ADC digital output is the combination of the first stage SUBADC output and the backend ADC output.

[0035] As shown in Figure 2 The structure of the readout circuit of the existing photoelectric imaging array is shown. The photodiodes of each column share an integrator channel. In the figure, INT is an integrator that converts the charge of the photodiode into a voltage. The Figure 1 The PART1 of the PIPELINE ADC shown in is placed in the integrator channel, and the PART2 is used as a MUX switch. The MDAC subtracts the analog sampling voltage from the DAC voltage controlled by the SUBADC to obtain a residual voltage. The MDAC also functions as a MUX buffer. The analog sampling of each integrator channel passes through the MDAC to obtain a residual voltage, and then passes through the backend ADC for conversion.

[0036] In the above, the precision of the SUBADC is 5 bits, the sampling capacitances in the integrator are CSp and CSn, the ratio of the feedback capacitance Cf of the MDAC is 16, and the input range of the backend ADC is -2V to 2V. The transfer curve of the input and output of the MDAC is shown in Figure 3 In the above, the precision of the SUBADC is 5 bits, the sampling capacitances in the integrator are CSp and CSn, the ratio of the feedback capacitance Cf of the MDAC is 16, and the input range of the backend ADC is -2V to 2V. The transfer curve of the input and output of the MDAC is shown in

[0037] The embodiment provides a readout circuit calibration method of a photoelectric imaging array, which comprises the following steps:

[0038] S1. State detection is performed on the backend ADC output value under the current SUBADC reference voltage;

[0039] S2. When the backend ADC output value is an abnormal value, the SUBADC reference voltage is adjusted through an internal register to obtain an adjusted backend ADC output value, the backend ADC output value is updated with the adjusted backend ADC output value, and S1 is performed. When the backend ADC output value is a non-abnormal value, a normal backend ADC output value is output. When the backend ADC input value is greater than the maximum input threshold of the backend ADC, the backend ADC output value is 1. When the backend ADC input value is less than the minimum input threshold of the backend ADC, the backend ADC output value is 0. The accuracy of the SUBADC is 5 bits, the maximum input threshold of the backend ADC is 2V, and the minimum input threshold of the backend ADC is -2V, and the backend ADC input range is -2V to 2V.

[0040] The accuracy of the SUBADC is 5 bits, the sampling capacitance in the integrator is CSp and CSn, the ratio of the feedback capacitance Cf of the MDAC is 16, the input range of the backend ADC is -2V to 2V, if the input of the backend ADC exceeds 2V, the output is all 1, if the input of the backend ADC is less than -2V, the output is all 0. If it is detected that the backend ADC output is all 1, it indicates that the ratio of the integrator sampling capacitance and the MDAC feedback capacitance exceeds 16.25, and if it is detected that the backend ADC output is all 0, it indicates that the ratio of the integrator sampling capacitance and the MDAC feedback capacitance exceeds 15.75. If it is detected that the backend ADC output is all 1, the digital input of the DAC is configured to be reduced through the SPICFG (internal register configured through the SPI interface) module, at this time, the reference voltages of the integrator and the SUBADC are reduced, which is equivalent to reducing the analog input corresponding to each code, and the DAC output is reduced through the SPICFG configuration until the output of the backend ADC is in the normal range.

[0041] Similarly, when it is detected that the backend ADC output is all 0, the DAC input is increased through the SPICFG module until the backend ADC output is in the normal range.

[0042] The embodiment also provides a readout circuit calibration system of a photoelectric imaging array, comprising:

[0043] The detection module is used by S1 to perform status detection on the backend ADC output value under the current SUBADC reference voltage;

[0044] The configuration module is used in step S2. When the backend ADC output value is abnormal, the SUBADC reference voltage is adjusted through an internal register to obtain an adjusted backend ADC output value. This adjusted backend ADC output value is then used to update the backend ADC output value, and step S2 is executed. When the backend ADC output value is not abnormal, a normal backend ADC value is output. The configuration module includes an internal register and a DAC buffer. The input of the internal register is connected to the output of the detection module. The input of the DAC buffer is connected to the output of the internal register. The output of the DAC buffer is connected to the input of the integrator via a charge injection capacitor. The DAC buffer includes a DAC circuit and a buffer driver circuit connected to the output of the DAC circuit. The DAC circuit is connected to the internal register, and the output of the buffer driver circuit is connected to the charge injection capacitor.

[0045] This embodiment also provides a readout circuit for an optoelectronic imaging array, including a readout circuit calibration system for the optoelectronic imaging array, and further including a PIPELINE ADC circuit, wherein the output terminal of the backend ADC in the PIPELINE ADC circuit is connected to the input terminal of the detection circuit. The backend ADC is a SAR ADC (Successive Approximation ADC).

[0046] like Figure 4 As shown, in Figure 2 The original readout circuit shown is modified by adding a saturation detection circuit, an SPICFG circuit, a DAC circuit and its buffer driver circuit, which serve as the reference voltage for the SUBADC. The DAC buffer output voltage is adjusted via register configuration, and a charge injection capacitor is added to the integrator input, with the DAC buffer output connected to this capacitor. When the saturation detection circuit detects that the backend ADC output is saturated, the SUBADC reference is adjusted via the SPICFG circuit, and the integrator output voltage changes simultaneously until the MDAC output voltage is within the normal input range of the backend ADC.

[0047] As shown in Figure 5, a capacitor Cd is added to the integrator input. The capacitance value of Cd is adjustable. The integrator capacitor is Cint, and its value is also adjustable. During saturation detection, Cd and Cint are ensured to be equal. The SPICFG circuit writes configuration information to the internal register via the SPI bus to control the digital input of the DAC. The DAC and backend ADC use the same reference voltage VREF. A buffer circuit is added to the DAC output to improve drive capability. The buffer output serves as the reference voltage for the SUBADC, and is also connected to the capacitor Cd at the integrator input. Since Cd and Cint are equal, the integrator output voltage equals the SUBADC reference voltage, corresponding to the maximum value of the integrator output. During saturation detection, the saturation detection circuit, SPICFG, DAC, buffer, integrator, MDAC, and backend ADC form a signal link. The saturation detection circuit is connected to the output of the backend ADC. If the backend ADC input exceeds 2V, all its outputs are 1; if the backend ADC input is less than -2V, all its outputs are 0. If all backend ADC outputs are 1, it indicates the ratio of the integrator sampling capacitor to the MDAC feedback capacitor exceeds 16.25. If all backend ADC outputs are 0, it indicates the ratio exceeds 15.75. If all backend ADC outputs are 1, the digital input to the DAC is reduced via the SPICFG module. This reduces the reference voltages of both the integrator and SUBADC, effectively reducing the analog input for each code. The DAC output is then reduced via SPICFG until the backend ADC output is within the normal range. Similarly, if all backend ADC outputs are 0, the DAC input is increased via SPICFG until the backend ADC output is within the normal range. The adjusted MDAC transfer curve is attached. Figure 6 As shown. The final SPICFG configuration value is used as the DAC input during normal operation.

[0048] like Figure 6 As shown, the calibrated transfer curves are illustrated with two different gain deviation scenarios. Figure 6 As shown in (a), when CSp = CSn / Cf = 16.6, reducing the SUBADC reference voltage to 3.84V does not change the SUBADC accuracy to 5 bits. Each LSB represents a voltage of 0.12V. After multiplying by the gain of 16.6, the MDAC output voltage remains between -1V and 1V, and the backend ADC operates normally. Figure 6(b) As shown, when CSp= CSn / Cf= 15.4, the SUBADC reference voltage is increased to 4.16V, the SUBADC precision is still 5bit, and the voltage represented by each 1LSB is 0.13V. After multiplied by the 15.4 times gain, the MDAC output voltage is still between -1V and 1V, and the backend ADC works normally.

[0049] As can be seen from the above, compared with the prior art, the readout circuit of the photoelectric imaging array, the readout circuit calibration method and the system provided by the embodiment can judge whether the backend ADC output is saturated by adding a saturation detection circuit. When the saturation detection circuit detects that the backend ADC output is saturated, the DAC input is configured through SPICFG, so that the integrator output voltage is equal to the SUBADC reference voltage, the proportional deviation of the sampling capacitor in the integrator and the feedback capacitor in the MDAC is detected, the reference voltage of the SUBADC is automatically adjusted, and the purpose of ensuring that the whole signal link works normally is achieved.

[0050] The specific embodiments are described above to further explain the purposes, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A readout circuit for a photoelectric imaging array, characterized by The pipeline ADC circuit and the readout circuit calibration system are included in the plurality of integrator channels. The pipeline ADC circuit includes a multiplying digital-to-analog converter and a backend ADC; wherein the multiplying digital-to-analog converter includes three parts PART1, PART2 and PART3; PART1 includes a differential input terminal IP, IN, sampling switches SW1, SW2, a sampling capacitor CSp, CSn and a sub-analog-to-digital converter SUBADC; PART2 includes sampling switches SWP, SWN, SWD; PART3 includes a differential digital-to-analog converter DACP, DACN, a feedback capacitor Cf and a residual amplifier OP; wherein the sub-analog-to-digital converter SUBADC converts the differential input of the differential input terminal IP, IN into a digital signal, the sampling switch SWD is a switch for outputting a multi-bit digital signal of the sub-analog-to-digital converter SUBADC, and the output of the sub-analog-to-digital converter SUBADC is used as the input of the differential digital-to-analog converter DACP, DACN; PART1 of the multiplying digital-to-analog converter is placed in the integrator channel, PART2 is used as a MUX switch, the multiplying digital-to-analog converter subtracts a residual voltage from an analog sampling voltage and a DAC voltage controlled by the sub-analog-to-digital converter SUBADC, and the multiplying digital-to-analog converter also serves as a MUX buffer; the analog sampling of each integrator channel passes through the MDAC to obtain the residual voltage, and then passes through the backend ADC to convert, so as to obtain the backend ADC output value; The readout circuit calibration system includes a detection module and a configuration module. The detection module is configured to detect the state of the backend ADC output value under the current SUBADC reference voltage. The configuration module is configured to, when the backend ADC output value is an abnormal value, adjust the SUBADC reference voltage through an internal register to obtain an adjusted backend ADC output value, update the backend ADC output value with the adjusted backend ADC output value, and detect the state of the backend ADC output value under the current SUBADC reference voltage; and when the backend ADC output value is a non-abnormal value, output a normal backend ADC value. The configuration module includes an internal register and a DAC buffer; an input terminal of the internal register is connected with an output terminal of the detection module; an input terminal of the DAC buffer is connected with an output terminal of the internal register; an output terminal of the DAC buffer is connected with an input terminal of the integrator through a charge injection capacitor; the DAC buffer includes a DAC circuit and a buffer driving circuit connected with an output terminal of the DAC circuit; wherein the DAC circuit is connected with the internal register; and an output terminal of the buffer driving circuit is connected with the charge injection capacitor.

2. A readout circuit for a photoelectric imaging array as claimed in claim 1, characterized in that The backend ADC output value is an abnormal value, including: When the backend ADC input value is greater than the backend ADC maximum input threshold value, the backend ADC output value is 1; When the backend ADC input value is less than the backend ADC minimum input threshold value, the backend ADC output value is 0.

3. A readout circuit for a photoelectric imaging array as claimed in claim 2, characterized in that The precision of the SUBADC is 5 bits.

4. A readout circuit for a photoelectric imaging array as claimed in claim 3, characterized in that The backend ADC maximum input threshold value is 2V.

5. A readout circuit for a photoelectric imaging array as claimed in claim 3, characterized in that: The backend ADC minimum input threshold value is -2V.

6. A readout circuit for a photoelectric imaging array as claimed in claim 1, characterized in that The backend ADC is a successive approximation ADC.

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