Plasma chamber targets for reducing defects in workpieces during dielectric sputtering

Abstract

Methods and apparatus are provided for plasma chamber targets for reducing defects in workpieces during dielectric sputtering. For example, the dielectric sputtering deposition target may include a dielectric compound having a predetermined average grain size ranging from about 65 μm to 500 μm, wherein the dielectric compound is at least one of magnesium oxide or aluminum oxide.

Description

Technical Field

[0001]

[0013] Embodiments of the present disclosure generally relate to substrate processing chambers used in semiconductor manufacturing systems. Background Art

[0002] Sputtering (also known as physical vapor deposition (PVD)) is a method of forming features in integrated circuits, typically performed in a processing chamber. Sputtering deposits a layer of material (such as a dielectric material) on a workpiece (such as a substrate / substrate). A source material (such as a target) is bombarded by ions that are strongly accelerated by an electric field. The ion bombardment causes material to be ejected from the target and causes the material to accumulate or deposit on the substrate (such as the workpiece). During deposition, the ejected particles may also be deposited on other surfaces, such as other internal surfaces of the processing chamber or a shield.

[0003] Unwanted coating of the shield may cause defects in the substrate being processed, or cause defects in subsequent processing of the substrate. For example, defects may occur when unwanted deposits form on the shield and charge accumulates on the unwanted deposits causing arcing, or when dielectric material accumulated on the shield flakes off.

[0004]

[0013] The inventors therefore provide embodiments of improved target materials for reducing defects during dielectric sputtering. Summary of the invention

[0005] Methods and apparatus for plasma chamber targets used to reduce defects in a workpiece during dielectric sputtering are provided herein. For example, in some embodiments, an apparatus may include a dielectric sputtering deposition target that may include a dielectric compound having a predefined average grain size ranging from about 65 μm to 500 μm, wherein the dielectric compound is at least one of magnesium oxide or aluminum oxide.

[0006] In at least some embodiments, a processing chamber includes: a chamber body defining an interior space; a substrate support for supporting a substrate within the interior space; and a plurality of targets to be sputtered onto the substrate, the plurality of targets including at least one dielectric target and at least one metal target, wherein the dielectric target includes a dielectric compound having a predetermined average grain size ranging from about 65 μm to 500 μm.

[0007] In at least some embodiments, a method for performing physical vapor deposition in a processing chamber may include the steps of selecting a first target in the processing chamber and depositing a dielectric compound on a workpiece via the first target, wherein the dielectric compound has a predetermined average grain size ranging from about 65 μm to 500 μm; and selecting a second target in the processing chamber and depositing a metal over the dielectric compound on the workpiece via the second target.

[0008] Other and further embodiments of the disclosure are described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The embodiments of the present disclosure have been briefly summarized above and discussed in more detail below, and these embodiments can be understood by referring to the illustrative embodiments of the present disclosure depicted in the accompanying drawings. However, the drawings only show typical embodiments of the present disclosure, and since the present disclosure may admit to other equally effective embodiments, the drawings should not be considered to limit the scope.

[0010] Figure 1 depicts a schematic diagram of a multi-cathode processing chamber according to an exemplary embodiment described herein;

[0011] Figure 2 According to the exemplary embodiments described herein Figure 1 The spatial structure diagram of the middle chamber;

[0012] Figure 3 It is a magnified image of a target with a specific grain size;

[0013] Figure 4 is an enlarged image of a target material having a grain size according to an exemplary embodiment described herein; and

[0014] Figure 5 A flow chart of a method for reducing defects on a workpiece according to exemplary embodiments described herein is depicted.

[0015] For ease of understanding, the same reference numerals are used, where possible, to represent the same elements common to the various figures. For clarity, the figures are not drawn to scale and may be simplified. Elements and features in one embodiment may be advantageously used in other embodiments without repetition. DETAILED DESCRIPTION

[0016] Magnetic random access memory (MRAM) requires a barrier layer to be built as part of the memory device. The barrier layer must have high purity and low defect count to work properly. One of magnesium oxide (MgO) and / or aluminum oxide (Al2O3) is a dielectric material that can be used as a barrier layer. However, using RF power to deposit MgO on the substrate surface inherently leads to poor defect performance.

[0017] Provided herein is an embodiment of a sputtering deposition target material, which includes a dielectric compound having a predetermined average grain size for reducing defects in a workpiece (e.g., a substrate) when manufacturing MRAM. As used herein, the grain size is the average grain size of a compound throughout the target material, wherein the size itself has a wide distribution range. In some embodiments, each grain is within 20% of a predetermined grain size, and in other embodiments, each grain is within 30% of an average grain size (e.g., a predetermined grain size). According to some embodiments, at least 80% of the grains in the target material or at least 90% of the grains in the target material in other embodiments have a grain size within 20% or 30% of the preferred grain size. The preferred grain size ranges from about 20 μm, 40 μm, and 50 μm to 500 μm, even for pure single crystals. In another embodiment, at least 80% of the grains in the target material have a grain size of at least 20 μm.

[0018] During physical vapor deposition of a dielectric film on a substrate (e.g., a substrate) in a processing chamber, dielectric powder may also form on a shield in the processing chamber because the shield is closer to the target than the workpiece. Later, when RF power is applied to the processing chamber, arcing, such as sheath voltage, may occur between the shield and the substrate due to the high concentration of positive ions on the shield. In other words, since the dielectric film is accumulated on the shield and the dielectric film is not conductive, charge accumulates on the shield. The charge on the shield is not easy to dissipate and causes arcing. In addition, after processing multiple subsequent substrates in the processing chamber, more dielectric film may accumulate on the shield, and due to poor adhesion of the film to the shield, the film may flake or peel off and deposit on the substrate. The inventors have found that modifying the target grain size and the configuration of the target and the shield reduces defects in the workpiece by preventing arcing and preventing the dielectric film from peeling off from the shield.

[0019] The inventors have observed that if a target containing a dielectric compound (e.g., MgO, Al2O3) is used in a processing chamber, most of the defects on the workpiece are dielectric particle defects. For example, the inventors observed that when a metal target (e.g., tantalum) was exposed in a processing chamber with a shield, the number of Ta defects was insignificant. However, when a dielectric target was exposed in the chamber, a large number of defects in the form of dielectric particles were found on the workpiece. The origin of these defects was verified experimentally (such as energy dispersive x-ray spectrometry (EDX)), but other methods can also be used. The shield remained unchanged, so it was confirmed that these defects originated from the dielectric target.

[0020] In some embodiments, a multi-cathode PVD chamber (e.g., processing chamber 100) includes a plurality of cathodes 106 having a corresponding plurality of targets (at least one dielectric target 110 and at least one metal target 112), the plurality of cathodes 106 (e.g., 6 cathodes in a 3RF×3DC alternating configuration) attached (e.g., via a top adapter assembly 142) to a chamber body 140 that defines an interior space. Other RF / DC cathode configurations may also be used, such as 1×1, 2×2, 4×4, 5×5, and the like. These numbers represent the ratio of RF-powered cathodes to DC-powered cathodes. In some embodiments, RF and DC cathodes alternate in the top adapter assembly 142. In other embodiments, RF cathodes may be adjacent to other RF cathodes and the same is true for DC cathodes. In other embodiments, the ratio of RF cathodes to DC cathodes may be a non-equal ratio, such as 1×2, 2×1, 1×3, 3×1, 2×3, and the like. When multiple RF cathodes are used, the operating frequencies may be offset to reduce any interference during the deposition process. For example, in an embodiment with three RF cathodes, the first RF cathode may operate at a frequency of 13.56 MHz, the second RF cathode at a frequency of 13.66 MHz (+100 kHz), and the third RF cathode at a frequency of 13.46 MHz (-100 kHz). The offset may be selected based on crosstalk prevention for a given number of cathodes.

[0021] RF cathodes are typically used with dielectric targets 110 for depositing dielectric films on substrates. DC cathodes are typically used with metal targets 112 for pasting after depositing dielectric films on substrates. Pasting reduces the chance of defects and particle formation in the deposited film. Having a processing chamber with RF and DC cathodes allows substrates to be produced faster because pasting and dielectric deposition can be done in one chamber. In addition, having multiple cathodes of the same type allows for higher pasting and deposition rates. Higher deposition rates mean that the substrate spends less time in the chamber to reach a certain film thickness. The reduced time or dwell time in the chamber results in fewer substrate defects.

[0022] In some embodiments, the metal target 112 may be formed of a metal such as, for example, tantalum, aluminum, titanium, molybdenum, tungsten, and / or magnesium. The dielectric target 110 may be formed of a metal oxide such as, for example, titanium oxide, titanium magnesium oxide, and / or tantalum magnesium oxide. However, other metals and / or metal oxides may be used alternatively.

[0023] The dielectric target 110 includes a dielectric compound having a predetermined grain size, and the grains are generally uniform throughout the dielectric target 110, with a small amount of size variation, such as 20-30%. The predetermined grain size varies in different embodiments. In some embodiments, the grain size is selected from a range of about 20 μm to 500 μm. In some embodiments, at least 80% of the grains in the target, or in some embodiments at least 90% of the grains in the target have a grain size equal to a preferred grain size (e.g., 20 μm, 40 μm, 50 μm, and up to about 500 μm or even larger).

[0024] Figure 3 represents an exemplary target material having a grain size of 8 μm. In this case, the substrate contains 218 defects with a particle size greater than 40 nm. However, when the target grain size increases to about 30 μm, as shown in FIG. Figure 4 As shown, the number of particles (defects) is reduced to, for example, 96. In some embodiments, the grain size is increased to about 40 μm, in which case the defects are estimated to be about 50-60 particles in number, a significant reduction from 218 defects. Other embodiments have targets with grain sizes of about 80 μm, 120 μm, 400 μm, 500 μm, or even larger. Although the results for all grain sizes contemplated in this embodiment are not shown, Figure 3 and Figure 4The reduction of particle defects on the substrate is illustrated, for example, by increasing the target grain size of the dielectric target 110. Although some embodiments described herein are directed to the aforementioned grain sizes, other grain sizes of approximately equal to or greater than 20 μm may also be used to reduce the number of defects on the substrate.

[0025] As the grain size increases from 8 μm to at least 20 μm, the number of grain defects decreases significantly because the surface area to volume ratio is significantly reduced at larger grain sizes, while smaller grains have a larger surface area to volume ratio. The increase in grain size reduces the grain boundary area, such as that found in Figure 4 As seen in . Due to the larger grain size, the grain boundary area is smaller, resulting in fewer defects. In other embodiments, the finish of the dielectric target 110 is modified. For example, the target may have a sputtered surface having a surface roughness ranging from a surface roughness of about 6 μm to a polished surface with a mirror finish (almost no surface roughness). The inventors have found that the closer to the mirror finish, the fewer particles are detected on the workpiece. In some embodiments, the dielectric target 110 has a density of at least 99.7% pure single crystal MgO to reduce defects in the workpiece, or in some cases, has a density of at least 99.98% pure single crystal MgO to reduce defects in the workpiece. As used herein, target density refers to the percentage of the target relative to the theoretical pure single crystal density that can be theoretically provided.

[0026] The processing chamber 100 also includes a substrate support 130 to support a substrate 132. The processing chamber 100 includes an opening (not shown) (e.g., a slit valve) through which an end effector (not shown) can extend to place the substrate 132 on lift pins (not shown) for lowering the substrate 132 onto the supporting surface 131 of the substrate support 130. Figure 1 In the illustrated embodiment, the dielectric target 110 and the metal target 112 are disposed substantially parallel to the support surface 131. The substrate support 130 includes a bias source 136 coupled to a bias electrode 138 disposed in the substrate support 130 via a matching network 134. A top adapter assembly 142 is coupled to an upper portion of the chamber body 140 of the processing chamber 100 and is grounded. Each cathode 106 may have a DC power source 108 or an RF power source 102 and an associated magnetron. In the case of an RF power source 102, the RF power source 102 is coupled to the cathode 106 via an RF matching network 104.

[0027] The shield 121 is rotatably coupled to the top adapter assembly 142 and is shared by the cathode 106. In some embodiments, the shield 121 includes a shield body 122 and a shield top 120. In other embodiments, the shield 121 has multiple aspects of the shield body 122 and the shield top 120 integrated into a single (unitary) piece. In other embodiments, the shield 121 can be more than two pieces. Depending on the number of targets that need to be sputtered at the same time, the shield 121 can have one or more holes to expose the corresponding one or more targets. The shield 121 advantageously limits or eliminates cross contamination between multiple targets (including dielectric targets 110 and metal targets 112). The shield 121 is rotatably coupled to the top adapter assembly 142 via a shaft 123. The shaft 123 is attached to the shield 121 via a coupling 119. In addition, because the shield 121 is rotatable, areas of the shield 121 that are normally not subject to sputtering are moved so that these areas can now be sputtered, thereby significantly reducing particle formation and shedding of aggregated deposits. The processing chamber 100 may also include at least one shunt disposed on the top side of the shield 121 to accommodate and shield at least another target of the plurality of targets that are not to be sputtered.

[0028] The actuator 116 is coupled to the shaft 123, opposite the shield 121. The actuator 116 is configured to rotate the shield 121 as indicated by arrow 144, and to move the shield 121 up and down in a vertical direction along a central axis 146 of the processing chamber 100 as indicated by arrow 145. During processing, the shield 121 is raised to an upward position. The raised position of the shield 121 exposes the target material used during processing and also shields the target material not used during processing. The raised position also grounds the shield for RF processing.

[0029] In some embodiments, the processing chamber 100 further includes a processing gas supply 128 to supply processing gas to the interior space 125 of the processing chamber 100. The processing chamber 100 may also include an exhaust pump 124 fluidly coupled to the interior space 125 to exhaust the processing gas from the processing chamber 100. In some embodiments, for example, after the metal target 112 is sputtered, the processing gas supply 128 may supply oxygen to the interior space 125.

[0030] Figure 2 According to the exemplary embodiments described herein Figure 1 A diagram of the spatial structure of the middle processing chamber 100.

[0031] According to some embodiments, the dielectric target 110 and the metal target 112 (along with any other targets) are positioned away from the edge of the shield 121, typically about 0.5 inches to 2.0 inches from the edge of the shield 121. When the targets are positioned at the edge of the shield, the film deposited there tends to be more stressed than other areas, causing particles to break off and deposit on the workpiece. Since the targets are positioned toward the center of the shield 121, the amount of stress on the film is significantly reduced because the concentration of the film in the narrow area is lower, resulting in reduced particle defects and shedding deposited on the workpiece.

[0032] Figure 5 Depicted is a flow chart of a method 500 for depositing a film on a substrate according to exemplary embodiments described herein.

[0033] Method 500 begins at 502 and proceeds to 504. At 504, a first target is selected in processing chamber 100, and a dielectric compound (e.g., MgO, Al2O3) is deposited on a workpiece (e.g., a semiconductor substrate) via the first dielectric target. For example, in at least some embodiments, the dielectric compound can be a single crystal target having a diameter from about two inches to about six inches. The predetermined grain size varies in different embodiments. For example, in some embodiments, the predetermined grain size is selected from a range of about 20 μm to 500 μm. In some embodiments, the predetermined grain size can be about 65 μm to about 500 μm. In some embodiments, at least 80% of the grains in the target, or in some embodiments at least 90% of the grains in the target have a grain size equal to a preferred grain size (e.g., 20 μm, 40 μm, 50 μm, 400 μm, 500 μm, or even larger).

[0034] Next, at 506, a second target is selected in the processing chamber 100, and a second metal is deposited over the dielectric material on the workpiece via the second target. The second target is typically a metal target and the metal may be, for example, tantalum.

[0035] Thereafter, the processing chamber 100 is prepared for the next or subsequent workpiece and the method 500 ends at 508 .

[0036] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof.

Claims

1. A dielectric sputtering deposition target, mainly composed of the following parts: a dielectric compound having a predetermined average grain size ranging from greater than 400 μm and at most 500 μm, wherein the dielectric compound is at least one of magnesium oxide or aluminum oxide, and Wherein at least 90% of the grains in the dielectric compound have a grain size equal to the predetermined average grain size.

2. The dielectric sputtering deposition target of claim 1, wherein the dielectric compound is a single crystal.

3. The dielectric sputtering deposition target of claim 1, wherein the dielectric compound has a density of at least 99.7%.

4. The dielectric sputtering deposition target of any one of claims 1 to 3, wherein the dielectric compound has a density of at least 99.98%.

5. A processing chamber comprising: a chamber body defining an interior space; a substrate support member, the substrate support member being used to support the substrate in the internal space; and a plurality of targets to be sputtered onto the substrate, the plurality of targets comprising at least one dielectric target and at least one metal target, wherein the dielectric target comprises a dielectric compound having a predetermined average grain size ranging from greater than 400 μm and at most 500 μm, Wherein at least 90% of the grains in the dielectric compound have a grain size equal to the predetermined average grain size.

6. The processing chamber of claim 5, wherein the dielectric compound is a single crystal.

7. The processing chamber of claim 5, further comprising: A plurality of cathodes are coupled to the chamber body and correspond to the plurality of targets.

8. The processing chamber of claim 5, further comprising a shield coupled to the chamber body and having at least one hole for exposing at least one of the plurality of targets to be sputtered, wherein the plurality of targets are disposed at least 0.5 inches from an edge of the shield.

9. The processing chamber of claim 8, wherein the shield is rotatably coupled to an upper portion of the chamber body.

10. The processing chamber of claim 8, wherein the shield further comprises: At least one flow diverter is disposed on a top side of the shield to accommodate and shield at least another target of the plurality of targets that is not to be sputtered.

11. The processing chamber of claim 8 or 10, wherein the shield is configured to rotate about a central axis of the processing chamber and to move linearly along the central axis of the processing chamber.

12. A method for performing physical vapor deposition in a processing chamber, the method comprising the steps of: selecting a first target in the processing chamber and sputter-depositing a dielectric compound on a workpiece via the first target, wherein the dielectric compound has a predetermined average grain size ranging from greater than 400 μm and up to 500 μm, wherein at least 90% of the grains in the dielectric compound have a grain size equal to the predetermined average grain size; and A second target is selected in the processing chamber, and a metal is sputter-deposited via the second target onto the dielectric compound on the workpiece.

13. The method of claim 12, wherein the first target is a dielectric target and the second target is a metallic target.

14. The method of claim 12, wherein the metal is tantalum.

15. The method of claim 12, wherein the first target is disposed 0.5 inches to 2.0 inches from an edge of a shield of the processing chamber.

16. The method of any one of claims 12 to 15, wherein the first target has a mirror finish.

Images