Display panel and display device

Abstract

A display panel and a display device. The display panel includes: a pixel unit (101) including a pixel circuit (10) and a light-emitting element (20), the pixel circuit (10) including a first transistor (T2), the pixel unit (101) including a first pixel unit (101a) and a second pixel unit (101b) that are in the same row and adjacent columns; a first gate line (GT1) connected to a gate (T20) of the first transistor (T2) of the first pixel unit (101a); a second gate line (GT2) connected to a gate (T20) of the first transistor (T2) of the second pixel unit (101b); a first gate signal line (SL1) extending along a first direction (X), connected to the first pixel unit (101a), and configured to provide a first scan signal to the first pixel unit (101a); a second gate signal line (SL2) extending along the first direction (X), connected to the second pixel unit (101b), and configured to provide a second scan signal to the second pixel unit (101b); a first connection line (CL1) extending along a second direction (Y), the first gate line (GT1) being connected to the first gate signal line (SL1) through the first connection line (CL1); and a second connection line (CL2) extending along the second direction (Y), the second gate line (GT2) being connected to the second gate signal line (SL2) through the second connection line (CL2).

Description

[0001] Cross-reference to related applications

[0002] For all purposes, this patent application claims the priority of PCT Patent Application No. PCT / CN2020 / 140199 filed on December 28, 2020, and the content disclosed in the above PCT patent application is hereby incorporated by reference in its entirety as part of the embodiments of this disclosure. Technical field

[0003] At least one embodiment of the present disclosure relates to a display panel and a display device. Background art

[0004] With the continuous development of display technology, Active-Matrix Organic Light-Emitting Diode (AMOLED) display technology has been increasingly applied to display devices such as mobile phones, tablet computers, digital cameras, etc. due to its advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, high response speed, etc. Summary of the invention

[0005] At least one embodiment of the present disclosure relates to a display panel and a display device.

[0006] At least one embodiment of the present disclosure provides a display panel, including: a pixel unit, including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel circuit including a first transistor, the pixel unit including a first pixel unit and a second pixel unit located in the same row and adjacent columns; a first gate line connected to the gate of the first transistor of the first pixel unit; a second gate line connected to the gate of the first transistor of the second pixel unit; a first gate signal line extending in a first direction, connected to the first pixel unit, and configured to provide a first scan signal to the first pixel unit; a second gate signal line extending in the first direction, connected to the second pixel unit, and configured to provide a second scan signal to the second pixel unit; a first connection line extending in a second direction, the first gate line being connected to the first gate signal line through the first connection line; and a second connection line extending in the second direction, the second gate line being connected to the second gate signal line through the second connection line, the second direction intersecting the first direction.

[0007] For example, in some embodiments of the present disclosure, the first gate signal line and the second gate signal line are insulated from each other.

[0008] For example, in some embodiments of the present disclosure, the first gate line and the second gate line are separated from each other and arranged along the first direction.

[0009] For example, in some embodiments of the present disclosure, the second gate signal line is closer to the first gate line than the first gate signal line.

[0010] For example, in some embodiments of the present disclosure, the orthographic projections of the first gate signal line and the second gate signal line on the substrate do not overlap with the orthographic projection of the channel region of the first transistor on the substrate.

[0011] For example, in some embodiments of the present disclosure, the first gate line, the first connection line, and the first gate signal line are located in three different layers, and the second gate line, the second connection line, and the second gate signal line are located in three different layers.

[0012] For example, in some embodiments of the present disclosure, the first gate line and the second gate line are located in the same layer, the first connection line and the second connection line are located in the same layer, and the first gate signal line and the second gate signal line are located in the same layer.

[0013] For example, in some embodiments of the present disclosure, the first gate line and the second gate line are located in the first conductive pattern layer; the first gate signal line and the second gate signal line are located in the second conductive pattern layer; the first connection line and the second connection line are located in the third conductive pattern layer; the first conductive pattern layer is closer to the substrate than the second conductive pattern layer, and the second conductive pattern layer is closer to the substrate than the third conductive pattern layer.

[0014] For example, in some embodiments of the present disclosure, the display panel further includes a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer. The first conductive pattern layer is located on the first gate insulating layer, the second gate insulating layer is provided between the first conductive pattern layer and the second conductive pattern layer, the interlayer insulating layer is located on the second conductive pattern layer, and the third conductive pattern layer is located on the interlayer insulating layer; one end of the first connection line is connected to the first gate line through a first via hole penetrating through the second gate insulating layer and the interlayer insulating layer, and the other end of the first connection line is connected to the first gate signal line through a second via hole penetrating through the interlayer insulating layer; one end of the second connection line is connected to the second gate line through a third via hole penetrating through the second gate insulating layer and the interlayer insulating layer, and the other end of the second connection line is connected to the second gate signal line through a fourth via hole penetrating through the interlayer insulating layer.

[0015] For example, in some embodiments of the present disclosure, the pixel circuit further includes a driving transistor and a second transistor; the gate of the second transistor of the first pixel unit is connected to the first gate line, the gate of the second transistor of the second pixel unit is connected to the second gate line, the first pole of the second transistor is connected to the second pole of the driving transistor, and the second pole of the second transistor is connected to the gate of the driving transistor.

[0016] For example, in some embodiments of the present disclosure, the display panel further includes a first power supply terminal and a data line. Among them, the first power supply terminal is configured to provide a first voltage signal to the pixel circuit, and the data line is configured to provide a data signal to the pixel circuit; the pixel circuit further includes a storage capacitor; the first pole of the first transistor is connected to the data line, and the first pole of the driving transistor is connected to the second pole of the first transistor; the first pole of the storage capacitor is connected to the gate of the driving transistor, and the second pole of the storage capacitor is connected to the first power supply terminal.

[0017] For example, in some embodiments of the present disclosure, the positive projection of the first gate signal line and the second gate signal line on the substrate does not overlap with the positive projection of the channel region of the second transistor on the substrate.

[0018] For example, in some embodiments of the present disclosure, the display panel further includes an initialization signal line, and the initialization signal line is configured to provide an initialization signal to the pixel circuit. The pixel circuit further includes a first reset transistor; the first pole of the first reset transistor is connected to the initialization signal line, and the second pole of the first reset transistor is connected to the gate of the driving transistor.

[0019] For example, in some embodiments of the present disclosure, the first gate signal line and the second gate signal line are located between the second transistor and the first reset transistor.

[0020] For example, in some embodiments of the present disclosure, the pixel unit further includes a third pixel unit in the same column as the first pixel unit. The data line includes a first data line, a second data line, and a third data line. The first data line is connected to the first pixel unit, the second data line is connected to the second pixel unit, and the third data line is connected to the third pixel unit.

[0021] For example, in some embodiments of the present disclosure, the pixel unit further includes a fourth pixel unit in the same column as the second pixel unit. The data line includes a fourth data line, and the fourth data line is connected to the fourth pixel unit.

[0022] For example, in some embodiments of the present disclosure, the display panel further includes a connection element. The light-emitting element is connected to the pixel circuit through the connection element. The connection element includes a shielding portion that extends along the second direction. The data line and the shielding portion are located on the same layer. The data line includes two adjacent data lines, and the shielding portion is located between the two adjacent data lines. The orthographic projection of the first connection line on the substrate does not overlap with the orthographic projection of the shielding portion on the substrate.

[0023] For example, in some embodiments of the present disclosure, the pixel circuit includes a driving transistor and a second transistor. A first pole of the second transistor is connected to a second pole of the driving transistor, and a second pole of the second transistor is connected to a gate of the driving transistor. The display panel further includes a third connection line. The gate of the driving transistor is connected to the second pole of the second transistor through the third connection line. The area of the orthographic projection of the shielding portion on the substrate is larger than the area of the orthographic projection of the third connection line on the substrate.

[0024] For example, in some embodiments of the present disclosure, the orthographic projection of the gate of the driving transistor on the substrate partially overlaps with the orthographic projection of the shielding portion on the substrate, and the overlapping area between the shielding portion and the gate of the driving transistor is smaller than the area of the gate of the driving transistor.

[0025] For example, in some embodiments of the present disclosure, the dimension of the gate of the driving transistor in the first direction is larger than the dimension of the shielding portion in the first direction; the dimension of the shielding portion in the second direction is larger than the dimension of the gate of the driving transistor in the second direction.

[0026] For example, in some embodiments of the present disclosure, the orthographic projection of the shielding portion on the substrate overlaps with the orthographic projection of the first gate line or the second gate line on the substrate.

[0027] At least one embodiment of the present disclosure further provides a display device, including any of the above display panels. Description of the Drawings

[0028] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0029] Figure 1 It is a schematic diagram of a 7T1C pixel circuit;

[0030] Figure 2 It is Figure 1The working timing diagram of the pixel circuit shown;

[0031] Figure 3 The pixel circuit diagram of a repeating unit of a display panel provided by an embodiment of the present disclosure;

[0032] Figure 4 The plan view of the semiconductor pattern in a display panel provided by an embodiment of the present disclosure;

[0033] Figure 5 The plan view of the first conductive pattern layer in a display panel provided by an embodiment of the present disclosure;

[0034] Figure 6 The plan view of the second conductive pattern layer in a display panel provided by an embodiment of the present disclosure;

[0035] Figure 7 The plan view of the third conductive pattern layer in a display panel provided by an embodiment of the present disclosure;

[0036] Figure 8 The plan view of the fourth conductive pattern layer in a display panel provided by an embodiment of the present disclosure;

[0037] Figure 9 The plan view of the structure of the repeating unit after forming the fourth conductive pattern layer in a display panel provided by an embodiment of the present disclosure;

[0038] Figure 10 The plan view of the structure of the pixel unit after forming the fourth conductive pattern layer in a display panel provided by an embodiment of the present disclosure;

[0039] Figure 11 is Figure 10 The cross-sectional view along line AB;

[0040] Figure 12 The plan view of the structure of the pixel unit after forming the light-emitting element in a display panel provided by an embodiment of the present disclosure; and

[0041] Figure 13 is Figure 12 The cross-sectional view along line CD. Detailed implementation manners

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0043] Unless otherwise defined, the technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "comprising" or "including" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. The terms "connected" or "coupled" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0044] The dual-gate and dual-data line (Dual gate&Dual source) technical solution can solve the problem of insufficient compensation time in high-frequency displays. However, this solution has problems such as pixel layout space limitations and parasitic capacitance between signal lines in high-resolution display device applications.

[0045] Currently, there is a large demand for high-frame-rate AMOLED display panels in the market. For example, the dual-data (Dual Data) solution can achieve a 120Hz drive while ensuring the display effect.

[0046] Figure 1 It is a schematic diagram of a 7T1C pixel circuit. Figure 2 For Figure 1 The timing diagram of the pixel circuit shown. Figure 1 The pixel circuit shown may be a pixel circuit of a common low-temperature poly-silicon (LTPS) AMOLED in the related art.

[0047] Figure 1 It shows the pixel circuit of a pixel unit of the display panel, as Figure 1As shown, the pixel unit 101 includes a pixel circuit 10 and a light-emitting element 20. The pixel circuit 10 includes six switching transistors (T2-T7), a driving transistor T1, and a storage capacitor Cst. The six switching transistors are respectively a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, and a second reset transistor T7. The light-emitting element 20 includes a first electrode 201, a second electrode 202, and a light-emitting functional layer located between the first electrode 201 and the second electrode 202. For example, the first electrode 201 is an anode and the second electrode 202 is a cathode. Generally, the threshold compensation transistor T3 and the first reset transistor T6 adopt the form of double-gate thin film transistors (Thin Film Transistor, TFT) to reduce leakage.

[0048] As Figure 1 shown, the display panel includes gate lines GT, data lines DT, a first power supply terminal VDD, a second power supply terminal VSS, a light-emitting control signal line EML, an initialization signal line INT, a reset control signal line RT, etc. For example, the reset control signal line RT includes a first reset control signal line RT1 and a second reset control signal line RT2. The first power supply terminal VDD is configured to provide a constant first voltage signal ELVDD to the pixel unit 101, the second power supply terminal VSS is configured to provide a constant second voltage signal ELVSS to the pixel unit 101, and the first voltage signal ELVDD is greater than the second voltage signal ELVSS. The gate line GT is configured to provide a scan signal SCAN to the pixel unit 101, the data line DT is configured to provide a data signal DATA (data voltage VDATA) to the pixel unit 101, the light-emitting control signal line EML is configured to provide a light-emitting control signal EM to the pixel unit 101, the first reset control signal line RT1 is configured to provide a reset control signal RESET to the pixel unit 101, the second reset control signal line RT2 is configured to provide a scan signal SCAN to the pixel unit 101, and the initialization signal line INT is configured to provide an initialization signal Vinit to the pixel unit 101. For example, the initialization signal Vinit is a constant voltage signal, and its magnitude can be, for example, between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto. For example, the initialization signal Vinit can be greater than or equal to the second voltage signal ELVSS. For example, the initialization signal line INT includes a first initialization signal line INT1 and a second initialization signal line INT2. For example, the first initialization signal line INT1 is configured to provide an initialization signal Vinit1 to the pixel unit 101, and the second initialization signal line INT1 is configured to provide an initialization signal Vinit2 to the pixel unit 101. For example, in some embodiments, the first initialization signal Vinit1 and the second initialization signal Vinit2 are equal and are both Vinit.

[0049] As Figure 1 shown, the driving transistor T1 is electrically connected to the light-emitting element 20, and outputs a driving current to drive the light-emitting element 20 to emit light under the control of signals such as a scan signal SCAN, a data signal DATA, a first voltage signal ELVDD, and a second voltage signal ELVSS.

[0050] For example, the light-emitting element 20 is an organic light-emitting diode (OLED), and the light-emitting element 20 emits red light, green light, blue light, or white light, etc. under the drive of its corresponding pixel circuit 10. For example, one pixel includes a plurality of pixel units. One pixel may include a plurality of pixel units that emit different colors of light. For example, one pixel includes a pixel unit that emits red light, a pixel unit that emits green light, and a pixel unit that emits blue light, but is not limited thereto. The number of pixel units included in one pixel and the light-emitting situation of each pixel unit can be determined according to needs.

[0051] For example, as Figure 1 shown, the gate T20 of the data writing transistor T2 is connected to the gate line GT, the first pole T21 of the data writing transistor T2 is connected to the data line DT, and the second pole T22 of the data writing transistor T2 is connected to the first pole T11 of the driving transistor T1.

[0052] For example, as Figure 1 shown, the pixel circuit 10 further includes a threshold compensation transistor T3. The gate T30 of the threshold compensation transistor T3 is connected to the gate line GT, the first pole T31 of the threshold compensation transistor T3 is connected to the second pole T12 of the driving transistor T1, and the second pole T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.

[0053] For example, as Figure 1 shown, the display panel further includes a light emission control signal line EML. The pixel circuit 10 further includes a first light emission control transistor T4 and a second light emission control transistor T5. The gate T40 of the first light emission control transistor T4 is connected to the light emission control signal line EML, the first pole T41 of the first light emission control transistor T4 is connected to the first power supply terminal VDD, and the second pole T42 of the first light emission control transistor T4 is connected to the first pole T11 of the driving transistor T1; the gate T50 of the second light emission control transistor T5 is connected to the light emission control signal line EML, the first pole T51 of the second light emission control transistor T5 is connected to the second pole T12 of the driving transistor T1, and the second pole T52 of the second light emission control transistor T5 is connected to the first pole 201 of the light-emitting element 20.

[0054] As Figure 1As shown, the first reset transistor T6 is connected to the gate T10 of the driving transistor T1 and is configured to reset the gate T10 of the driving transistor T1. The second reset transistor T7 is connected to the first pole 201 of the light-emitting element 20 and is configured to reset the first pole 201 of the light-emitting element 20. The first initialization signal line INT1 is connected to the gate of the driving transistor T1 through the first reset transistor T6. The second initialization signal line INT2 is connected to the first pole 201 of the light-emitting element 20 through the second reset transistor T7. For example, the first initialization signal line INT1 and the second initialization signal line INT2 are connected to be input with the same initialization signal, but not limited thereto. In some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 may also be insulated from each other and are configured to be input with signals respectively.

[0055] For example, as Figure 1 shown, the first pole T61 of the first reset transistor T6 is connected to the first initialization signal line INT1, the second pole T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1, the first pole T71 of the second reset transistor T7 is connected to the second initialization signal line INT2, and the second pole T72 of the second reset transistor T7 is connected to the first pole 201 of the light-emitting element 20. For example, as Figure 1 shown, the gate T60 of the first reset transistor T6 is connected to the first reset control signal line RT1, and the gate T70 of the second reset transistor T7 is connected to the second reset control signal line RT2.

[0056] As Figure 1 shown, the first power supply terminal VDD is configured to supply a first voltage signal ELVDD to the pixel circuit 10. The pixel circuit further includes a storage capacitor Cst. The first pole Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1, and the second pole Cb of the storage capacitor Cst is connected to the first power supply terminal VDD.

[0057] For example, as Figure 1 shown, the display panel further includes a second power supply terminal VSS, and the second power supply terminal VSS is connected to the second pole 202 of the light-emitting element 20.

[0058] As Figure 2 shown, in a frame display period, the driving method of the pixel unit includes a first reset stage t1, data writing and threshold compensation, a second reset stage t2, and a light-emitting stage t3. When the reset control signal RESET is at a low level, the gate of the driving transistor T1 is reset. When the scan signal SCAN is at a low level, the first pole 201 (for example, the anode) of the light-emitting element 20 is reset. For example, as Figure 1As shown, when the scan signal SCAN is at a low level, the data voltage VDATA is written, and at the same time, the threshold voltage Vth of the driving transistor T1 is obtained, and the data voltage VDADA containing the data information on the data line is stored in the capacitor Cst; when the light emission control signal EML is at a low level, the light emitting element 20 emits light, and the voltage of the first node N1 (gate pole point) is maintained (the light emission stability of the light emitting element 20) by the storage capacitor Cst. During the driving process of the pixel circuit 10, in the light emission stage, the storage capacitor is used to hold the voltage signal so that the potential of its signal holding end is kept constant, and a voltage difference is formed between the gate and the source of the driving transistor, thereby controlling the driving transistor to form a driving current, and then driving the light emitting element 20 to emit light.

[0059] As Figure 2 shown, in the reset stage t1, the light emission control signal EM is set to the off voltage, the reset control signal RESET is set to the on voltage, and the scan signal SCAN is set to the off voltage.

[0060] As Figure 2 shown, in the data writing and threshold compensation stage and the second reset stage t2, the light emission control signal EM is set to the off voltage, the reset control signal RESET is set to the off voltage, and the scan signal SCAN is set to the on voltage.

[0061] As Figure 2 shown, in the light emission stage t3, the light emission control signal EM is set to the on voltage, the reset control signal RESET is set to the off voltage, and the scan signal SCAN is set to the off voltage.

[0062] As Figure 2 shown, both the first voltage signal ELVDD and the second voltage signal ELVSS are constant voltage signals. For example, the initialization signal Vinit is between the first voltage signal ELVDD and the second voltage signal ELVSS.

[0063] For example, in the embodiments of the present disclosure, the on voltage refers to the voltage that can turn on the first and second poles of the corresponding transistor, and the off voltage refers to the voltage that can turn off the first and second poles of the corresponding transistor. When the transistor is a P-type transistor, the on voltage is a low voltage (for example, 0V), and the off voltage is a high voltage (for example, 5V); when the transistor is an N-type transistor, the on voltage is a high voltage (for example, 5V), and the off voltage is a low voltage (for example, 0V). Figure 2 The driving waveforms shown are all described by taking the P-type transistor as an example. For example, the on voltage is a low voltage (for example, 0V), and the off voltage is a high voltage (for example, 5V), but it is not limited thereto.

[0064] Please refer to Figure 1 and Figure 2, in the first reset stage t1, the emission control signal EM is at the off voltage, the reset control signal RESET is at the on voltage, and the scan signal SCAN is at the off voltage. At this time, the first reset transistor T6 is in the conducting state, while the second reset transistor T7, the data writing transistor T2, the threshold compensation transistor T3, the first emission control transistor T4, and the second emission control transistor T5 are in the off state. The first reset transistor T6 transmits the first initialization signal (initialization voltage Vinit) Vinit1 to the gate of the driving transistor T1 and is stored by the storage capacitor Cst, resets the driving transistor T1, and erases the data stored during the previous (previous frame) emission.

[0065] In the data writing, threshold compensation, and second reset stage t2, the emission control signal EM is at the off voltage, the reset control signal RESET is at the off voltage, and the scan signal SCAN is at the on voltage. At this time, the data writing transistor T2 and the threshold compensation transistor T3 are in the conducting state, and the second reset transistor T7 is in the conducting state. The second reset transistor T7 transmits the second initialization signal (initialization voltage Vinit) Vinit2 to the first electrode 201 of the light-emitting element 20 to reset the light-emitting element 20. The first emission control transistor T4, the second emission control transistor T5, and the first reset transistor T6 are in the off state. At this time, the data writing transistor T2 transmits the data voltage VDATA to the first pole of the driving transistor T1, that is, the data writing transistor T2 receives the scan signal SCAN and the data voltage VDATA and writes the data voltage VDATA to the first pole of the driving transistor T1 according to the scan signal SCAN. The threshold compensation transistor T3 conducts to connect the driving transistor T1 into a diode structure, whereby the gate of the driving transistor T1 can be charged. After the charging is completed, the gate voltage of the driving transistor T1 is VDATA + Vth, where VDATA is the data voltage and Vth is the threshold voltage of the driving transistor T1, that is, the threshold compensation transistor T3 receives the scan signal SCAN and compensates the threshold voltage of the gate voltage of the driving transistor T1 according to the scan signal SCAN. In this stage, the voltage difference across the storage capacitor Cst is ELVDD - VDATA - Vth.

[0066] During the light-emitting stage t3, the light-emitting control signal EM is at an on voltage, the reset control signal RESET is at an off voltage, and the scan signal SCAN is at an off voltage. The first light-emitting control transistor T4 and the second light-emitting control transistor T5 are in an on state, while the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6, and the second reset transistor T7 are in an off state. The first voltage signal ELVDD is transmitted through the first light-emitting control transistor T4 to the first pole of the driving transistor T1, and the gate voltage of the driving transistor T1 is maintained at VDATA + Vth. The light-emitting current I flows through the first light-emitting control transistor T4, the driving transistor T1, and the second light-emitting control transistor T5 into the light-emitting element 20, and the light-emitting element 20 emits light. That is, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 receive the light-emitting control signal EM and control the light-emitting element 20 to emit light according to the light-emitting control signal EM. The light-emitting current I satisfies the following saturation current formula:

[0067] K(Vgs - Vth) 2 = K(VDATA + Vth - ELVDD - Vth) 2 = K(VDATA - ELVDD) 2

[0068] Wherein, μ n is the channel mobility of the driving transistor, Cox is the channel capacitance per unit area of the driving transistor T1, W and L are the channel width and channel length of the driving transistor T1 respectively, and Vgs is the voltage difference between the gate and the source of the driving transistor T1 (i.e., the first pole of the driving transistor T1 in this embodiment).

[0069] It can be seen from the above formula that the current flowing through the light-emitting element 20 is independent of the threshold voltage of the driving transistor T1. Therefore, this pixel circuit compensates very well for the threshold voltage of the driving transistor T1.

[0070] For example, the proportion of the duration of the light-emitting stage t3 in a frame display period can be adjusted. In this way, the light-emitting brightness can be controlled by adjusting the proportion of the duration of the light-emitting stage t3 in a frame display period. For example, the proportion of the duration of the light-emitting stage t3 in a frame display period is adjusted by controlling the scan driving circuit in the display panel or an additionally provided driving circuit.

[0071] For example, the embodiments of the present disclosure are not limited to Figure 1 the specific pixel circuit shown, and other pixel circuits that can achieve compensation for the driving transistor can be adopted. Based on the description and teaching of the present disclosure for this implementation manner, other setting manners that can be easily thought of by those of ordinary skill in the art without creative efforts all fall within the protection scope of the present disclosure.

[0072] Figure 3 A pixel circuit diagram of a repeating unit of a display panel provided by an embodiment of the present disclosure. As Figure 3 shown, the display panel includes a first pixel unit 101a, a second pixel unit 101b, a third pixel unit 101c, and a fourth pixel unit 101d, and the first pixel unit 101a, the second pixel unit 101b, the third pixel unit 101c, and the fourth pixel unit 101d form a repeating unit RP. Multiple repeating units RP can form an array. The repeating unit RP is the smallest repeating unit of the display array.

[0073] For example, the display panel adopts a dual-gate and dual-data line driving method, which can realize independent control of the first pixel unit 101a, the second pixel unit 101b, the third pixel unit 101c, and the fourth pixel unit 101d respectively. During the driving process of the display panel, the first pixel unit 101a, the second pixel unit 101b, the third pixel unit 101c, and the fourth pixel unit 101d are lit in sequence respectively. Because of the dual-gate and dual-data line control, the gate line of the first pixel unit 101a can be continuously turned on until the data signal writing of the fourth pixel unit 101d is completed. The same applies to other pixel units, so that each pixel unit can have sufficient compensation time.

[0074] As Figure 3 shown, the first pixel unit 101a and the second pixel unit 101b are located in the same row and adjacent columns, and the third pixel unit 101c and the fourth pixel unit 101d are located in the same row and adjacent columns. The first pixel unit 101a and the third pixel unit 101c are located in the same column and adjacent rows, and the second pixel unit 101b and the fourth pixel unit 101d are located in the same column and adjacent rows.

[0075] Figure 3 The first data line DT1, the second data line DT2, the third data line DT3, and the fourth data line DT4 are shown. Referring to Figure 3 , the first data line DT1 is connected to the first pixel unit 101a, the second data line DT2 is connected to the second pixel unit 101b, the third data line DT3 is connected to the third pixel unit 101c, and the fourth data line DT4 is connected to the fourth pixel unit 101d.

[0076] In Figure 3 , in the same pixel unit, the first reset transistor T6 and the second reset transistor T7 are connected to the same reset control signal line RT to be input with the same reset control signal at the same time, but the embodiments of the present disclosure are not limited thereto.

[0077] In other embodiments, in the same pixel unit, the first reset transistor T6 and the second reset transistor T7 can also be respectively connected to the first reset control signal line and the second reset control signal line, and the first reset control signal line and the second reset control signal line are insulated from each other to be respectively input with signals. In this case, the first reset transistor T6 and the second reset transistor T7 are input with signals at different times. As described above, the first reset transistor T6 is input with the reset control signal RESET in the first reset stage t1, and the second reset transistor T7 is input with the scan signal SCAN in the data writing, threshold compensation, and second reset stage t2. For example, the gate line GT of this stage is connected to the reset control signal line of the next stage. For example, the gate line GT and the second reset control signal line RT2 can be electrically connected to input the same signal at the same time.

[0078] The following will describe Figures 4 to 11 the display panel provided by the embodiments of the present disclosure. Figure 4 is a plan view of a semiconductor pattern in a display panel provided by an embodiment of the present disclosure. Figure 5 is a plan view of a first conductive pattern layer in a display panel provided by an embodiment of the present disclosure. Figure 6 is a plan view of a second conductive pattern layer in a display panel provided by an embodiment of the present disclosure. Figure 7 is a plan view of a third conductive pattern layer in a display panel provided by an embodiment of the present disclosure. Figure 8 is a plan view of a fourth conductive pattern layer in a display panel provided by an embodiment of the present disclosure. Figure 9 is a plan view of the structure of a repeating unit after forming the fourth conductive pattern layer in a display panel provided by an embodiment of the present disclosure. Figure 10 is a plan view of the structure of a pixel unit after forming the fourth conductive pattern layer in a display panel provided by an embodiment of the present disclosure. Figure 11 is Figure 10 a cross-sectional view along line AB. Figure 12 is a plan view of the structure of a pixel unit after forming a light-emitting element in a display panel provided by an embodiment of the present disclosure. Figure 13 is Figure 12 a cross-sectional view along line CD in

[0079] Figures 4 to 10 shows a first direction X and a second direction Y, and the second direction Y intersects with the first direction X. For example, in the embodiments of the present disclosure, the first direction X is perpendicular to the second direction Y is taken as an example. For example, the first direction X is the row direction of the pixel unit, and the second direction Y is the column direction of the pixel unit. Both the first direction X and the second direction Y are directions parallel to the substrate BS. Figure 11 and Figure 13The third direction Z is shown, and the third direction Z is perpendicular to the substrate BS. The third direction Z is perpendicular to the first direction X and perpendicular to the second direction Y.

[0080] In the embodiments of the present disclosure, for clarity of illustration, in the plan view, the insulating layer is shown in the form of vias, the insulating layer itself is made transparent, and the first conductive pattern layer, the second conductive pattern layer, the third conductive pattern layer, and the fourth conductive pattern layer are made semi-transparent.

[0081] Figure 4 The semiconductor pattern SCP is shown, Figure 5 The first conductive pattern layer LY1 is shown. For example, a first gate insulating layer (first gate insulating layer GI1, refer to Figure 11 ) is provided between the first conductive pattern layer LY1 and the semiconductor pattern SCP. For example, the semiconductor pattern SCP and subsequent various components are formed on the substrate. As Figure 5 shown, the first conductive pattern layer LY1 includes a first reset control signal line RT1, a first gate line GT1, a second gate line GT2, a first pole Ca of the storage capacitor Cst (gate T10 of the driving transistor T1), a light emission control signal line EML, and a second reset control signal line RT2.

[0082] Using the first conductive pattern layer LY1 as a mask, the semiconductor pattern SCP is doped so that the region of the semiconductor pattern SCP covered by the first conductive pattern layer LY1 retains semiconductor characteristics, forming an active layer ACT (see Figure 10 ), and the region of the semiconductor pattern SCP not covered by the first conductive pattern layer LY1 is made conductive, forming the source and drain of the thin film transistor. As shown in 10, the active layer ACT formed after the semiconductor pattern SCP is partially made conductive is shown.

[0083] For example, during the fabrication of a display panel, a self-alignment process is adopted. Using the first conductive pattern layer LY1 as a mask, the semiconductor pattern layer SCP is subjected to a conductorization process. For example, the semiconductor pattern layer SCP is heavily doped using an ion implantation process, so that the portions of the semiconductor pattern layer SCP not covered by the first conductive pattern layer LY1 are conductorized, forming the source region (first pole T11) and drain region (second pole T12) of the driving transistor T1, the source region (first pole T21) and drain region (second pole T22) of the data writing transistor T2, the source region (first pole T31) and drain region (second pole T32) of the threshold compensation transistor T3, the source region (first pole T41) and drain region (second pole T42) of the first light-emitting control transistor T4, the source region (first pole T51) and drain region (second pole T52) of the second light-emitting control transistor T5, the source region (first pole T61) and drain region (second pole T62) of the first reset transistor T6, and the source region (first pole T71) and drain region (second pole T72) of the second reset transistor T7. The portions of the semiconductor pattern layer SCP covered by the first conductive pattern layer L1 retain semiconductor characteristics, forming the channel regions of the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light-emitting control transistor T4, the second light-emitting control transistor T5, the first reset transistor T6, and the second reset transistor T7. The channel regions of the respective transistors constitute the active layer ACT (refer to Figure 10 ).

[0084] For example, referring to Figure 1 , Figure 4 , Figure 9 and Figure 10 , the second pole T72 of the second reset transistor T7 and the second pole T52 of the second light-emitting control transistor T5 are integrally formed; the first pole T51 of the second light-emitting control transistor T5, the second pole T12 of the driving transistor T1, and the first pole T31 of the threshold compensation transistor T3 are integrally formed; the first pole T11 of the driving transistor T1, the second pole T22 of the data writing transistor T2, and the second pole T42 of the first light-emitting control transistor T4 are integrally formed; the second pole T32 of the threshold compensation transistor T3 and the second pole T62 of the first reset transistor T6 are integrally formed.

[0085] For example, the channel region (active layer) of the transistor adopted in the embodiments of the present disclosure can be single-crystalline silicon, polycrystalline silicon (such as low-temperature polycrystalline silicon), or metal oxide semiconductor materials (such as IGZO, AZO, etc.). In one embodiment, the transistors are all P-type low-temperature polycrystalline silicon (LTPS) thin-film transistors. In another embodiment, the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are metal oxide semiconductor thin-film transistors, that is, the channel material of the transistor is a metal oxide semiconductor material (such as IGZO, AZO, etc.). The metal oxide semiconductor thin-film transistor has a low leakage current, which can help reduce the gate leakage current of the driving transistor T1. For example, in this case, the LTPO (Low Temperature Polycrystalline Oxide) process can be used to fabricate the display panel. The LTPO process combines the advantages of low-temperature polycrystalline silicon (LTPS) and oxide. That is, two TFT devices, low-temperature polycrystalline silicon (LTPS) and oxide, are integrated in the same pixel unit.

[0086] For example, the transistors adopted in the embodiments of the present disclosure can include various structures, such as top-gate type, bottom-gate type, or double-gate structure. In some embodiments, the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are double-gate thin-film transistors, which can help reduce the gate leakage current of the driving transistor T1.

[0087] For example, as Figure 5 , Figure 9 and Figure 10 shown, a part of the light-emitting control signal line EML serves as the gate T40 of the first light-emitting control transistor T4, a part of the light-emitting control signal line EML serves as the gate T50 of the second light-emitting control transistor T5, the gate T60 of the first reset transistor T6 is a part of the first reset control signal line RT1, the gate T70 of the second reset transistor T7 is a part of the second reset control signal line RT2, the gate T20 of the data writing transistor T2 is a part of the gate line GT, and the gate T30 of the threshold compensation transistor T3 is a part of the gate line GT. The gate line GT is the first gate line GT1 or the second gate line GT2.

[0088] As Figure 5 shown, the first reset control signal line RT1, the first gate line GT1, the second gate line GT2, the light-emitting control signal line EML, and the second reset control signal line RT2 all extend along the first direction X.

[0089] As Figure 8 , Figure 9 and Figure 10As shown, the data line DT extends along the second direction Y, and the first data line DT1, the third data line DT3, the fourth data line DT4, and the second data line DT2 are arranged along the first direction X.

[0090] Figure 6 The second conductive pattern layer LY2 is shown. For example, a second gate insulating layer (second gate insulating layer GI2, refer to Figure 11 ) is provided between the second conductive pattern layer LY2 and the first conductive pattern layer LY1. The second conductive pattern layer LY2 includes a stopper BK, a first initialization signal line INT1, a second initialization signal line INT2, a second pole Cb of the storage capacitor Cst, a first gate signal line SL1, and a second gate signal line SL2. For example, the first gate signal line SL1 extends along the first direction X, and the second gate signal line SL2 extends along the first direction X. For example, referring to Figure 6 , the first initialization signal line INT1 extends along the first direction X, and the second initialization signal line INT2 extends along the first direction X. The first initialization signal line INT1, the first gate signal line SL1, the second gate signal line SL2, and the second initialization signal line INT2 are arranged along the second direction Y. As Figure 6 shown, the first gate signal line SL1 and the second gate signal line SL2 are located between the first initialization signal line INT1 and the second pole Cb of the storage capacitor Cst. As Figure 6 shown, the first initialization signal line INT1 and the second initialization signal line INT2 are located on both sides of the second pole Cb of the storage capacitor Cst, the first initialization signal line INT1 and the second initialization signal line INT2 are located on both sides of the stopper BK, and the first gate signal line SL1, the second gate signal line SL2, the second pole Cb of the storage capacitor Cst, and the stopper BK are provided between the first initialization signal line INT1 and the second initialization signal line INT2. As Figure 6 shown, the first initialization signal line INT1, the first gate signal line SL1, the second gate signal line SL2, the stopper BK, the second pole Cb of the storage capacitor Cst, and the second initialization signal line INT2 are arranged in sequence along the second direction Y.

[0091] As Figure 7 shown, the third conductive pattern layer LY3 includes a power supply connection line VDD0, a first connection electrode CEa, a second connection electrode CEb, a third connection electrode CEc, a fourth connection electrode CEd, a fifth connection electrode CEe, a first connection line CL1, and a second connection line CL2. An interlayer insulating layer (interlayer insulating layer ILD, refer to Figure 11 ) is provided between the third conductive pattern layer LY3 and the second conductive pattern layer LY2.

[0092] Referring to Figures 5 to 7 , Figure 9 and Figure 10, the power supply connection line VDD0 is electrically connected to the first pole T41 of the first light-emitting control transistor T4 through the via hole H2. The power supply connection line VDD0 is electrically connected to the second pole Cb of the storage capacitor Cst through the via holes H3 and H30. The power supply connection line VDD0 is electrically connected to the conductive block BK through the via hole H0. One end of the first connection electrode CEa is electrically connected to the first initialization signal line INT1 through the via hole H12, and the other end of the first connection electrode CEa is connected to the first pole T61 of the first reset transistor T6 through the via hole H11, so that the first pole T61 of the first reset transistor T6 is electrically connected to the first initialization signal line INT1. One end of the second connection electrode CEb is electrically connected to the second pole T62 of the first reset transistor T6 through the via hole H22, and the other end of the second connection electrode CEb is electrically connected to the gate T10 of the driving transistor T1 (i.e., the first pole Ca of the storage capacitor Cst) through the via hole H21, so that the second pole T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1 (i.e., the first pole Ca of the storage capacitor Cst). One end of the third connection electrode CEc is electrically connected to the second initialization signal line INT2 through the via hole H32, and the other end of the third connection electrode CEc is connected to the first pole T71 of the second reset transistor T7 through the via hole H31, so that the first pole T71 of the second reset transistor T7 is electrically connected to the second initialization signal line INT2. The fourth connection electrode CEd is electrically connected to the second pole T52 of the second light-emitting control transistor T5 through the via hole H40. The fourth connection electrode CEd can be used to connect to the sixth connection electrode CEf formed subsequently, and then be electrically connected to the first electrode 201 of the light-emitting element 20 (refer to Figure 9 ). The fifth connection electrode CEe is electrically connected to the first pole T21 of the data writing transistor T2 through the via hole H5. The fifth connection electrode CEe is used to connect to the data line.

[0093] Figure 8 shows the fourth conductive pattern layer LY4. The fourth conductive pattern layer LY4 includes a data line DT, a sixth connection electrode CEf, and a first power supply line VDD1. A passivation layer (passivation layer PVX, refer to Figure 11 ) and a first planarization layer (first planarization layer PLN1, refer to Figure 11)。The first power supply line VDD1 is connected to the power supply connection line VDD0 through a via hole H6 that penetrates the passivation layer and the first planarization layer. The sixth connection electrode CEf is connected to the fourth connection electrode CEd through a via hole H7 that penetrates the passivation layer and the first planarization layer. The data line DT is connected to the fifth connection electrode CEe through a via hole H8, and is further electrically connected to the first pole T21 of the data writing transistor T2. For example, the sixth connection electrode CEf (connection electrode CEf) and the fourth connection electrode CEd (connection electrode CEd) constitute a connection element CE0. For example, the light emitting element 20 is connected to the pixel circuit 10 through the connection element CE0. For example, the pixel circuit 10 is connected to the fourth connection electrode CEd (connection electrode CEd), the fourth connection electrode CEd (connection electrode CEd) is connected to the sixth connection electrode CEf (connection electrode CEf), and the sixth connection electrode CEf (connection electrode CEf) is connected to the light emitting element 20.

[0094] Figure 8 The first data line DT1, the second data line DT2, the third data line DT3, and the fourth data line DT4 are shown. Figure 8 The positions of the first pixel unit 101a, the second pixel unit 101b, the third pixel unit 101c, and the fourth pixel unit 101d are also shown. As Figure 8 shown, the first data line DT1 is connected to the fifth connection electrode CEe at the corresponding position through a via hole H81, the second data line DT2 is connected to the fifth connection electrode CEe at the corresponding position through a via hole H82, the third data line DT3 is connected to the fifth connection electrode CEe at the corresponding position through a via hole H83, and the fourth data line DT4 is connected to the fifth connection electrode CEe at the corresponding position through a via hole H84.

[0095] As Figure 9 shown, in order to avoid damaging the channel when forming the via hole and affecting the performance of the data writing transistor T2, the positive projections of the first gate signal line SL1 and the second gate signal line SL2 on the substrate do not overlap with the positive projection of the channel region T23 of the data writing transistor T2 on the substrate.

[0096] As Figure 9 shown, in order to avoid damaging the channel when forming the via hole and affecting the performance of the threshold compensation transistor T3, the positive projections of the first gate signal line SL1 and the second gate signal line SL2 on the substrate do not overlap with the positive projection of the channel region T33 of the threshold compensation transistor on the substrate.

[0097] As Figure 8 and Figure 9 shown, the data line DT extends along the second direction Y, and the first data line DT1, the third data line DT3, the fourth data line DT4, and the second data line DT2 are arranged along the first direction X.

[0098] For example, the first power supply line VDD1 is configured to supply a first voltage signal ELVDD to the pixel circuit 10. The first power supply line VDD1 is connected to the stopper BK to supply a constant voltage to the stopper BK. The first power supply line VDD1 is connected to the first power supply terminal VDD, and the second pole Cb of the storage capacitor Cst is connected to the first power supply line VDD1. For example, the second pole Cb of the storage capacitor Cst is connected to the first power supply terminal VDD through the power supply connection line VDD0 and the first power supply line VDD1. Figure 9 A plan view showing the structure after forming the fourth conductive pattern layer LY4 is shown.

[0099] For example, the first pole T41 of the first light-emitting control transistor T4 is connected to the first power supply terminal VDD through the power supply connection line VDD0 and the first power supply line VDD1 (refer to Figure 9 and Figure 10 ).

[0100] As Figure 10 shown, the threshold compensation transistor T3 is a double-gate transistor. The threshold compensation transistor T3 includes a first channel T331 and a second channel T332, and the first channel T331 and the second channel T332 are connected by a first conductive connection portion CP1. As Figure 10 shown, the first reset transistor T6 is a double-gate transistor. The first reset transistor T6 includes a first channel T631 and a second channel T632, and the first channel T631 and the second channel T632 are connected by a second conductive connection portion CP2.

[0101] As Figure 10 shown, the stopper BK is configured to block the first conductive connection portion CP1 between the two channels of the threshold compensation transistor T3. The stopper BK and the first conductive connection portion CP1 form a capacitor (stabilizing capacitor) to prevent the threshold compensation transistor T3 from generating leakage current and affecting the display effect. As Figure 9 shown, in the plan view, the stopper BK and the first conductive connection portion CP1 partially overlap.

[0102] As Figure 10 shown, in the plan view, the first initialization signal line INT1 and the second conductive connection portion CP2 partially overlap, and a capacitor (stabilizing capacitor) is formed between the first initialization signal line INT1 and the second conductive connection portion CP2 to prevent the first reset transistor T6 from generating leakage current and affecting the display effect.

[0103] Refer to Figure 3 and Figure 9 , the first gate line GT1 is connected to the gate of the data writing transistor T2 of the first pixel unit 101a; the second gate line GT2 is connected to the gate of the data writing transistor T2 of the second pixel unit 101b.

[0104] Reference Figure 6 and Figure 9 As shown in FIGS. and, a first gate signal line SL1 extends along a first direction X, is connected to a first pixel unit 101a, and is configured to provide a first scan signal to the first pixel unit 101a; a second gate signal line SL2 extends along the first direction X, is connected to a second pixel unit 101b, and is configured to provide a second scan signal to the second pixel unit 101b.

[0105] Reference Figure 7 and Figure 9 As shown in FIGS. and, a first connection line CL1 extends along a second direction Y, and a first gate line GT1 is connected to the first gate signal line SL1 through the first connection line CL1; a second connection line CL2 extends along the second direction Y, and a second gate line GT2 is connected to the second gate signal line SL2 through the second connection line CL2.

[0106] The display panel provided by an embodiment of the present disclosure can implement a Dual gate & Dual source technical solution at high resolution. The display panel provided by an embodiment of the present disclosure realizes the horizontal routing of Dual gate signals through a second conductive pattern layer, and the connection lines in the third conductive pattern layer are respectively connected to the gate lines in the first conductive pattern layer and the gate signal lines in the second conductive pattern layer through vias. The pixel layout structure is compact, which is beneficial to realizing high PPI. For example, in some embodiments, the Dual source & Dual gate technical solution is applied at a high resolution of 413 PPI.

[0107] For example, as Figure 6 and Figure 9 shown, the first gate signal line SL1 and the second gate signal line SL2 are insulated from each other to respectively input scan signals to two adjacent columns of pixel units in the same row of pixel units. For example, the first gate signal line SL1 is used to input a scan signal to odd-column pixel units, and the second gate signal line SL2 is used to input a scan signal to even-column pixel units.

[0108] For example, as Figure 5 and Figure 9 shown, the first gate line GT1 and the second gate line GT2 are separated from each other and are arranged along the first direction X. For example, in the same row of pixel units, a second gate line GT2 is provided between two adjacent first gate lines GT1, and a first gate line GT1 is provided between two adjacent second gate lines GT2. For example, as Figure 5 and Figure 9 shown, the first gate line GT1 extends along the first direction X, and the second gate line GT2 extends along the first direction X. In the embodiments of the present disclosure, a component extending along a certain direction means the overall extension trend of the component, and not necessarily that each part of the component extends along the extension direction.

[0109] For example, as Figure 7 and Figure 9 shown, the second gate signal line SL2 is closer to the first gate line GT1 than the first gate signal line SL1, and the length of the first connection line CL1 along the second direction Y is greater than the length of the second connection line CL2 along the second direction Y.

[0110] For example, referring to Figure 5 , Figure 6 , Figure 7 and Figure 9 , the first gate line GT1, the first connection line CL1, and the first gate signal line SL1 are located in three different layers, and the second gate line GT2, the second connection line CL2, and the second gate signal line SL2 are located in three different layers.

[0111] For example, referring to Figure 5 , Figure 6 , Figure 7 and Figure 9 , the first gate line GT1 and the second gate line GT2 are located in the same layer, the first connection line CL1 and the second connection line CL2 are located in the same layer, and the first gate signal line SL1 and the second gate signal line SL2 are located in the same layer.

[0112] For example, referring to Figure 5 , Figure 6 , Figure 7 , Figure 9 , Figure 11 and Figure 13 , the first gate line GT1 and the second gate line GT2 are located in the first conductive pattern layer LY1; the first gate signal line SL1 and the second gate signal line SL2 are located in the second conductive pattern layer LY2; the first connection line CL1 and the second connection line CL2 are located in the third conductive pattern layer LY3; the first conductive pattern layer LY1 is closer to the substrate BS than the second conductive pattern layer LY2, and the second conductive pattern layer LY2 is closer to the substrate BS than the third conductive pattern layer LY3.

[0113] For example, referring to Figure 11 and Figure 13 , the display panel further includes a first gate insulating layer GI1, a second gate insulating layer GI2, and an interlayer insulating layer ILD; the first conductive pattern layer LY1 is located on the first gate insulating layer GI1, a second gate insulating layer GI2 is provided between the first conductive pattern layer LY1 and the second conductive pattern layer LY2, the interlayer insulating layer ILD is located on the second conductive pattern layer LY2, and the third conductive pattern layer LY3 is located on the interlayer insulating layer ILD.

[0114] For example, referring to Figure 7 and Figure 9, one end of the first connection line CL1 is connected to the first gate line GT1 through a first via hole V1 that penetrates the second gate insulating layer GI2 and the interlayer insulating layer ILD, and the other end of the first connection line CL1 is connected to the first gate signal line SL1 through a second via hole V2 that penetrates the interlayer insulating layer ILD; one end of the second connection line CL2 is connected to the second gate line GT2 through a third via hole V3 that penetrates the second gate insulating layer GI2 and the interlayer insulating layer ILD, and the other end of the second connection line CL2 is connected to the second gate signal line SL2 through a fourth via hole V4 that penetrates the interlayer insulating layer ILD.

[0115] For example, as Figure 9 shown, the gate of the threshold compensation transistor T3 of the first pixel unit 101a is connected to the first gate line GT1, the gate of the threshold compensation transistor T3 of the second pixel unit 101b is connected to the second gate line GT2, the first pole of the threshold compensation transistor T3 is connected to the second pole of the driving transistor T1, and the second pole of the threshold compensation transistor T3 is connected to the gate of the driving transistor T1.

[0116] For example, as Figure 9 shown, the first gate signal line SL1 and the second gate signal line SL2 are located between the threshold compensation transistor T3 and the first reset transistor T6, so that the positions of the first gate signal line SL1 and the second gate signal line SL2 in the second direction are defined.

[0117] As Figure 8 shown, the length of the sixth connection electrode CEf in the second direction Y is larger than the length of a normal connection electrode. As Figure 8 shown, the length of the sixth connection electrode CEf in the second direction Y is greater than the length of the sixth connection electrode CEf in the first direction X. For example, the length of the sixth connection electrode CEf in the second direction Y is greater than 2 - 5 times the maximum length of the sixth connection electrode CEf in the first direction X. In some embodiments, the length of the sixth connection electrode CEf in the second direction Y is greater than 3 times, 4 times or 5 times the maximum length of the sixth connection electrode CEf in the first direction X. Figure 8 The sixth connection electrode CEf shown can be referred to as a shielding portion CEs. The shielding portion CEs and the fourth connection electrode CEd (connection electrode CEd) form a connection element CE0.

[0118] Referring to Figure 7 , Figure 9 and Figure 10 , one end of the second connection electrode CEb is electrically connected to the gate T10 of the driving transistor T1 (i.e., the first pole Ca of the storage capacitor Cst) through a via hole H21, the other end of the second connection electrode CEb is electrically connected to the second pole T62 of the first reset transistor T6 through a via hole H22, and the second connection electrode CEb can also be referred to as a third connection line CL3. As Figure 11As shown, the gate T10 of the driving transistor T1 is connected to the second pole T32 of the threshold compensation transistor T3 through the third connection line CL3.

[0119] Reference Figure 8 , Figure 9 and Figure 10 , the shielding part CEs extends along the second direction Y. For example, the light-emitting element 20 is connected to the pixel circuit 10 through the connection element CE0 (including the fourth connection electrode CEd and the shielding part CEs).

[0120] Reference Figure 8 and Figure 9 , the data line DT and the shielding part CEs are on the same layer, and both the data line DT and the shielding part CEs are located in the fourth conductive pattern layer LY4. The data line DT includes two adjacent data lines DT, the shielding part CEs is located between the two adjacent data lines DT, and the orthographic projection of the shielding part CEs on the substrate BS at least partially overlaps with the orthographic projection of the third connection line CL3 on the substrate BS. Reference Figure 8 and Figure 9 , the data line DT includes the first data line DT1 and the third data line DT3, the first data line DT1 and the third data line DT3 are adjacent, and in the first direction X, the shielding part CEs is located between the first data line DT1 and the third data line DT3. In the embodiments of the present disclosure, that component A and component B are adjacent means that there is no component A and no component B between component A and component B. The shielding part CEs extends along the second direction and is interspersed between two adjacent data lines DT. At positions where the adjacent data lines are relatively close, the shielding effect is more obvious.

[0121] For example, in some embodiments, the orthographic projection of the third connection line CL3 on the substrate BS completely falls within the orthographic projection of the shielding part CEs on the substrate BS.

[0122] For example, in some embodiments, reference Figure 8 and Figure 9 , the orthographic projection of the first connection line CL1 on the substrate BS does not overlap with the orthographic projection of the shielding part CEs on the substrate BS. Reference Figure 8 and Figure 9 , the orthographic projection of the second connection line CL2 on the substrate BS does not overlap with the orthographic projection of the shielding part CEs on the substrate BS.

[0123] As Figure 10 shown, the display panel includes a first conductive structure CDT1, and the first conductive structure CDT1 is connected to the gate T10 of the driving transistor T1.

[0124] For example, the material of the first conductive structure CDT1 is the same as that of the first conductive connection part CP1. For example, the first conductive structure CDT1 and the first conductive connection part CP1 can be fabricated from the same film layer through the same process.

[0125] For example, the material of the first conductive structure CDT1 includes a conductive material obtained by doping a semiconductor material. For example, the material of the first conductive structure CDT1 includes a conductive material obtained by doping polysilicon, but is not limited thereto.

[0126] For example, as Figure 10 shown, the first conductive structure CDT1 is multiplexed as the second pole T62 of the first reset transistor T6. In the embodiments of the present disclosure, the first conductive structure CDT1 is taken as an example of the second pole T62 of the first reset transistor T6 for illustration.

[0127] For example, as Figure 10 shown, the first conductive structure CDT1, the third connection line CL3, and the gate T10 of the driving transistor T1 constitute the gate signal part PT1 of the driving transistor T1.

[0128] For example, as Figure 10 shown, the positive projection of the shielding part CEs on the substrate base BS and the positive projection of the gate signal part PT1 on the substrate base BS overlap at least partially, so that the shielding part CEs shields the parasitic capacitance between the gate signal part PT1 and the data line, reducing the longitudinal crosstalk problem.

[0129] In the embodiments of the present disclosure, the positive projection of the shielding part CEs on the substrate base BS and the positive projection of the third connection line CL3 on the substrate base BS overlap at least partially, so that the shielding part CEs shields the parasitic capacitance between the gate signal part PT1 (gate pole) and the data line, reducing the longitudinal crosstalk problem.

[0130] For example, in a 120Hz driving scheme using a time-division writing method, that is, the data signal is first stored in the storage capacitor, and then the scanning signal is turned on and written into the pixel unit. The interference between data signals will affect the accurate writing of the data signal and the display effect. In the embodiments of the present disclosure, the shielding part CEs is located between two adjacent data lines DT, and the positive projection of the third connection line CL3 on the substrate base BS and the positive projection of the shielding part CEs on the substrate base BS overlap at least partially, which can well reduce the coupling effect and improve this problem.

[0131] For example, as Figure 9 and Figure 10As shown, in order to minimize longitudinal crosstalk, the orthographic projection of the shielding portion CEs on the substrate BS is larger than the orthographic projection of the third connection line CL3 on the substrate BS. For example, the area of the orthographic projection of the shielding portion CEs on the substrate BS is larger than the area of the orthographic projection of the third connection line CL3 on the substrate BS. For example, the orthographic projection of the shielding portion CEs on the substrate BS covers the orthographic projection of the third connection line CL3 on the substrate BS. For example, in the plan view, the shielding portion CEs covers the third connection line CL3. For example, as Figure 9 and Figure 10 shown, the main surface of the substrate BS is the surface for fabricating each component, and each component is disposed on the main surface of the substrate BS.

[0132] For example, in order to significantly reduce longitudinal crosstalk, the orthographic projection of the gate T10 of the driving transistor T1 on the substrate BS partially overlaps with the orthographic projection of the shielding portion CEs on the substrate BS, and the area of the overlapping portion between the shielding portion CEs and the gate T10 of the driving transistor T1 is smaller than the area of the gate T10 of the driving transistor T1.

[0133] For example, as Figure 9 and Figure 10 shown, in order to improve the display quality, the dimension of the gate T10 of the driving transistor T1 in the first direction X is larger than the dimension of the shielding portion CEs in the first direction X; the dimension of the shielding portion CEs in the second direction Y is larger than the dimension of the gate of the driving transistor T1 in the second direction Y.

[0134] For example, as Figure 9 and Figure 10 shown, the gate T10 of the driving transistor T1 extends beyond the shielding portion CEs from both sides in the first direction X.

[0135] For example, as Figure 9 and Figure 10 shown, the orthographic projection of the shielding portion CEs on the substrate BS overlaps with the orthographic projection of the gate line GT on the substrate BS. The gate line GT may include a first gate line GT1 or a second gate line GT2.

[0136] For example, as Figure 9 shown, the orthographic projection of the first gate line GT1 or the second gate line GT2 on the substrate BS partially overlaps with the orthographic projection of the shielding portion CEs on the substrate BS.

[0137] For example, the pixel unit includes two adjacent pixel units located in the same column, and two adjacent data lines DT are respectively connected to the two pixel units. Figure 9 Shows the positions of the first pixel unit 101a, the second pixel unit 101b, the third pixel unit 101c, and the fourth pixel unit 101d.

[0138] For example, as Figure 9 and Figure 10 shown, the second pole T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1 through a third connection line CL3. As described above, the second pole T62 of the first reset transistor T6 is integrally formed with the second pole T32 of the threshold compensation transistor T3. Thus, the second pole T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.

[0139] For example, as Figure 9 and Figure 10 shown, the positive projection of the shielding portion CEs on the substrate substrate BS overlaps at least partially with the positive projection of the second pole T62 of the first reset transistor T6 on the substrate substrate BS. Similarly, since the second pole T62 of the first reset transistor T6 is integrally formed with the second pole T32 of the threshold compensation transistor T3, the positive projection of the shielding portion CEs on the substrate substrate BS overlaps at least partially with the positive projection of the second pole T32 of the threshold compensation transistor T3 on the substrate substrate BS.

[0140] For example, as Figure 9 and Figure 10 shown, the positive projection of the shielding portion CEs on the substrate substrate BS does not overlap with the positive projection of the second gate signal line SL2 on the substrate substrate BS. Thus, the upper end position of the shielding portion CEs in the second direction Y is defined.

[0141] For example, referring to Figure 9 and Figure 10 , the first initialization signal line INT1 and the second initialization signal line INT2 are respectively disposed on opposite sides of the gate T10 of the driving transistor T1, and the positive projection of the shielding portion CEs on the substrate substrate BS overlaps partially with the positive projection of the second initialization signal line INT2 on the substrate substrate BS.

[0142] Further for example, the positive projection of the second initialization signal line INT2 on the substrate substrate BS overlaps partially with the positive projection of the second conductive connection portion CP2 of the pixel unit in the next row on the substrate substrate BS. Thus, a capacitor is formed between the second initialization signal line INT2 and the shielding portion CEs. This capacitor serves as a stabilizing capacitor and functions to reduce the leakage current of the first reset transistor T6.

[0143] For example, referring to Figure 9 , the first reset control signal line RT1 and the second reset control signal line RT2 are respectively disposed on opposite sides of the gate T10 of the driving transistor T1. Referring to Figure 9, the orthographic projection of the second reset control signal line RT2 on the substrate substrate BS and the orthographic projection of the shielding portion CEs on the substrate substrate BS do not overlap. Thus, the lower end position of the shielding portion CEs in the second direction Y is defined.

[0144] For example, referring to Figure 9 and Figure 10 , the orthographic projection of the first reset control signal line RT1 on the substrate substrate BS and the orthographic projection of the shielding portion CEs on the substrate substrate BS do not overlap.

[0145] For example, referring to Figure 9 and Figure 10 , the first reset control signal line extends along the first direction X, and the second reset control signal line extends along the first direction X.

[0146] In Figure 9 , each sixth connection electrode CEf is connected to a light-emitting element, that is, each sixth connection electrode CEf corresponds to a pixel unit 101. Or, in Figure 9 , each shielding portion CEs is connected to a light-emitting element, that is, each shielding portion CEs corresponds to a pixel unit 101.

[0147] For example, referring to Figure 9 , the orthographic projections of the first gate T601 and the second gate T602 of the first reset transistor T6 on the substrate substrate BS overlap with the orthographic projections of the first channel T631 and the second channel T632 of the first reset transistor T6 on the substrate substrate BS, respectively. For example, referring to Figure 9 , the orthographic projections of the first gate T301 and the second gate T302 of the threshold compensation transistor T3 on the substrate substrate BS overlap with the orthographic projections of the first channel T331 and the second channel T332 of the threshold compensation transistor T3 on the substrate substrate BS, respectively.

[0148] For example, as Figure 9 shows, the first power supply line VDD1 is connected to the second pole Cb of the storage capacitor Cst through the power supply connection line VDD0.

[0149] In the conventional technology, the threshold compensation transistor T3 is a double-gate transistor. The intermediate node (the first conductive connection portion CP1) of the threshold compensation transistor T3 is disturbed by the jump of the scan signal. The voltage increases instantaneously when the scan signal is turned off, and the leakage to the gate of the driving transistor T1 becomes more serious, which will cause the Flicker problem.

[0150] For example, referring to Figure 9, in order to reduce the leakage current of the threshold compensation transistor T3, the positive projection of the stopper BK on the substrate BS overlaps at least partially with the positive projection of the first conductive connection portion CP1 on the substrate BS. A stable capacitance is formed between the stopper BK and the first conductive connection portion CP1. Increasing the parasitic capacitance between the intermediate node of the threshold compensation transistor T3 and the first voltage signal ELVDD can reduce the disturbance amount and improve the leakage current problem.

[0151] A pixel circuit is formed on the substrate, forming Figure 9 or Figure 10 the display panel shown, in Figure 9 or Figure 10 Based on the display panel shown, a light-emitting element is further formed to obtain a display panel that can perform display. Thus, the pixel circuit is closer to the substrate than the light-emitting element. As Figure 13 shown, the pixel circuit 10 is closer to the substrate BS than the light-emitting element 20.

[0152] Figure 12 The first pole 201 of the light-emitting element 20 is shown. Figure 13 This is a cross-sectional view of a display panel provided by an embodiment of the present disclosure. Figure 12 The film layer above the first pole 201 of the light-emitting element is omitted in Figure 12 . The layers above the first pole 201 of the light-emitting element 20 can be referred to the cross-sectional view. Of course, the setting position and shape of the first pole 201 of the light-emitting element are not limited to

[0153] shown, and those skilled in the art can adjust the setting position and shape of the first pole 201 of the light-emitting element according to needs.

[0153] Refer to Figure 12 and Figure 13 , the buffer layer BL is located on the substrate BS, the isolation layer BR is located on the buffer layer BL, the channel region, source and drain of the transistor are located on the isolation layer BR, a first gate insulating layer GI1 is formed on the channel region, source and drain of the transistor, a first conductive pattern layer LY1 is located on the first gate insulating layer GI1, a second gate insulating layer GI2 is located on the first conductive pattern layer LY1, a second conductive pattern layer LY2 is located on the second gate insulating layer GI2, an interlayer insulating layer ILD is located on the second conductive pattern layer LY2, a third conductive pattern layer LY3 is located on the interlayer insulating layer ILD, a passivation layer PVX is located on the first conductive pattern layer LY, a first planarization layer PLN1 is located on the passivation layer PVX, and a fourth conductive pattern layer LY4 is located on the first planarization layer PLN1.

[0154] Refer to Figure 13, the second planarization layer PLN2 is located on the fourth conductive pattern layer LY4, the first electrode 201 of the light-emitting element 20 is located on the second planarization layer PLN2, the pixel definition layer PDL and the spacer PS are located on the second planarization layer PLN2, the pixel definition layer PDL has an opening OPN, and the opening OPN is configured to define the light-emitting area (light-emitting region, effective light-emitting area) of the pixel unit. The spacer PS is configured to support the fine metal mask when forming the light-emitting functional layer 203.

[0155] For example, as Figure 12 and Figure 13 shown, the opening OPN is the light-emitting region of the pixel unit. The light-emitting functional layer 203 is located above the first electrode 201 of the light-emitting element 20, the second electrode 202 of the light-emitting element 20 is located on the light-emitting functional layer 203, and a packaging layer CPS is provided on the light element 20. The packaging layer CPS includes a first packaging layer CPS1, a second packaging layer CPS2, and a third packaging layer CPS3. For example, the first packaging layer CPS1 and the third packaging layer CPS3 are inorganic material layers, and the second packaging layer CPS2 is an organic material layer. For example, the first electrode 201 is the anode of the light-emitting element 20, and the second electrode 202 is the cathode of the light-emitting element 20, but it is not limited thereto.

[0156] As Figure 12 and Figure 13 shown, the first electrode 201 of the light-emitting element 20 is connected to the shielding portion CEs (the sixth connection electrode CEf) through a via hole H9 penetrating the second planarization layer PLN2.

[0157] For example, the light-emitting element 20 includes an organic light-emitting diode. The light-emitting functional layer 203 is located between the second electrode 202 and the first electrode 201. The second electrode 202 is located on the side of the first electrode 201 away from the substrate BS, and the light-emitting functional layer 203 includes at least a light-emitting layer, and may also include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

[0158] As shown in Figure 6 and Figure 13 shown, the second electrode Cb of the storage capacitor has an opening OPN1, and the setting of the opening OPN1 facilitates the connection of the second connection electrode CEb to the gate T10 of the driving transistor T1.

[0159] For example, the transistors in the pixel circuit of the embodiment of the present disclosure are all thin film transistors. For example, the first conductive pattern layer LY1, the second conductive pattern layer LY2, the third conductive pattern layer LY3, and the fourth conductive pattern layer LY4 are all made of metal materials. For example, the first conductive pattern layer LY1 and the second conductive pattern layer LY2 are formed of metal materials such as nickel and aluminum, but not limited thereto. For example, the third conductive pattern layer LY3 and the fourth conductive pattern layer LY4 are formed of materials such as titanium and aluminum, but not limited thereto. For example, the third conductive pattern layer LY3 and the fourth conductive pattern layer LY4 are respectively structures formed of three sublayers of Ti / AL / Ti, but not limited thereto. For example, the substrate substrate can be a glass substrate or a polyimide substrate, but not limited thereto, and can be selected as needed. For example, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the passivation layer PVX, the first planarization layer PLN1, the second planarization layer PLN2, the pixel definition layer PDL, and the spacer PS are all made of insulating materials. The materials of the first pole 201 and the second pole 202 of the light-emitting element can be selected as needed. In some embodiments, the first electrode 201 may be made of at least one of a transparent conductive metal oxide and silver, but is not limited thereto. For example, the transparent conductive metal oxide includes indium tin oxide (ITO), but is not limited thereto. For example, the first electrode 201 may be made of a structure in which three sub-layers of ITO-Ag-ITO are stacked. In some embodiments, the second electrode 202 may be a metal with a low work function, and may be made of at least one of magnesium and silver, but is not limited thereto.

[0160] In the display panel provided by the embodiment of the present disclosure, the shielding portion CEs shown in FIG. 16 may not be provided. Instead, a connecting electrode with a shorter length in the second direction may be used. That is, the sixth connecting electrode CEf / shielding portion CEs may be of other sizes and shapes.

[0161] In the embodiment of the present disclosure, the data writing transistor T2 may be referred to as a first transistor, and the threshold compensation transistor T3 may be referred to as a second transistor.

[0162] For example, when the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are metal oxide semiconductor thin film transistors (using the LTPO process), at least one of the first gate signal line SL1 and the second gate signal line SL2 can output the turn-on signal of the N-type transistor; the film layer selected for the first gate line GT1 and the second gate line GT2 is not limited to the first conductive pattern layer LY1, and the film layer selected for the first gate signal line SL1 and the second gate signal line SL2 is not limited to the second conductive pattern layer LY2, and can also be other metal film layers, such as the metal film layer above the second conductive pattern layer LY2, such as the third conductive pattern layer LY3, which can also serve as the gate of the oxide TFT, etc.; oxide semiconductors can also be used as connecting lines, or transfer structures, etc. through a conductorization process.

[0163] At least one embodiment of the present disclosure further provides a display device, including any one of the above display panels. For example, the display device includes an OLED or a product with high frame rate driving including an OLED. For example, the display device includes any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, etc., containing the above display panel.

[0164] The above takes the pixel circuit of 7T1C as an example for illustration, and the embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin film transistors and the number of capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display panel may also be a structure including other numbers of transistors, such as 7T2C structure, 6T1C structure, 6T2C structure or 9T2C structure, and the embodiments of the present disclosure do not limit this.

[0165] In the embodiments of the present disclosure, elements located in the same layer can be formed by the same film layer through the same patterning process. For example, elements located in the same layer can be located on the surface of the same element far from the substrate.

[0166] It should be noted that, for clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of the layer or region is enlarged. It can be understood that when an element such as a layer, a film, a region or a substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under another element, or there can be intermediate elements.

[0167] In the embodiments of the present disclosure, patterning or patterning process may only include photolithography process, or include photolithography process and etching steps, or may include other processes for forming a predetermined pattern, such as printing, inkjet, etc. The photolithography process refers to a process including film formation, exposure, development, etc., and uses photoresist, mask, exposure machine, etc. to form a pattern. The corresponding patterning process can be selected according to the structure formed in the embodiments of the present disclosure.

[0168] Without conflict, the features in the same embodiment and different embodiments of the present disclosure can be combined with each other.

[0169] As described above, only the specific implementation manners of the present disclosure are provided, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claimed rights.

Claims

1. A display panel, comprising: Pixel units, including pixel circuits and light-emitting elements, the pixel circuits being configured to drive the light-emitting elements, the pixel circuits including a first transistor, and the pixel units including a first pixel unit and a second pixel unit that are in the same row and in adjacent columns; A first gate line connected to the gate of the first transistor of the first pixel unit; A second gate line connected to the gate of the first transistor of the second pixel unit; A first gate signal line extending in a first direction, connected to the first pixel unit, and configured to provide a first scan signal to the first pixel unit; A second gate signal line extending in the first direction, connected to the second pixel unit, and configured to provide a second scan signal to the second pixel unit; A first connection line extending in a second direction, the first gate line being connected to the first gate signal line through the first connection line; And A second connection line extending in the second direction, the second gate line being connected to the second gate signal line through the second connection line, the second direction intersecting the first direction, The second gate signal line is closer to the first gate line than the first gate signal line, The length of the first connection line in the second direction is greater than the length of the second connection line in the second direction, The first gate line, the first connection line, and the first gate signal line are in three different layers, and the second gate line, the second connection line, and the second gate signal line are in three different layers.

2. The display panel according to claim 1, wherein The first gate signal line and the second gate signal line are insulated from each other.

3. The display panel according to claim 1, wherein, The first gate line and the second gate line are separated from each other and arranged in the first direction.

4. The display panel according to claim 1, wherein, The first gate signal line, the second gate signal line, and the first gate line are spaced apart from each other in the second direction and arranged in sequence.

5. The display panel according to claim 1, wherein, The orthographic projections of the first gate signal line and the second gate signal line on the substrate do not overlap with the orthographic projection of the channel region of the first transistor on the substrate.

6. The display panel according to any one of claims 1-5, wherein, The first gate signal line, the second gate signal line, and the second gate line are spaced apart from each other in the second direction and arranged in sequence.

7. The display panel according to any one of claims 1-5, wherein, The first gate line and the second gate line are in the same layer, the first connection line and the second connection line are in the same layer, and the first gate signal line and the second gate signal line are in the same layer.

8. The display panel according to any one of claims 1-5, wherein The first gate line and the second gate line are in a first conductive pattern layer; The first gate signal line and the second gate signal line are in a second conductive pattern layer; The first connection line and the second connection line are in a third conductive pattern layer; The first conductive pattern layer is closer to the substrate than the second conductive pattern layer, and the second conductive pattern layer is closer to the substrate than the third conductive pattern layer.

9. The display panel according to claim 8, further comprising a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer, The first conductive pattern layer is located on the first gate insulating layer. A second gate insulating layer is provided between the first conductive pattern layer and the second conductive pattern layer. The interlayer insulating layer is located on the second conductive pattern layer, and the third conductive pattern layer is located on the interlayer insulating layer. One end of the first connection line is connected to the first gate line through a first via hole penetrating the second gate insulating layer and the interlayer insulating layer, and the other end of the first connection line is connected to the first gate signal line through a second via hole penetrating the interlayer insulating layer. One end of the second connection line is connected to the second gate line through a third via hole penetrating the second gate insulating layer and the interlayer insulating layer, and the other end of the second connection line is connected to the second gate signal line through a fourth via hole penetrating the interlayer insulating layer.

10. The display panel according to claim 9, wherein, The pixel circuit further includes a driving transistor and a second transistor. The gate of the second transistor of the first pixel unit is connected to the first gate line, and the gate of the second transistor of the second pixel unit is connected to the second gate line. The first pole of the second transistor is connected to the second pole of the driving transistor, and the second pole of the second transistor is connected to the gate of the driving transistor.

11. The display panel according to claim 10 further includes a first power terminal and a data line, wherein, The first power supply terminal is configured to provide a first voltage signal to the pixel circuit, and the data line is configured to provide a data signal to the pixel circuit. The pixel circuit further includes a storage capacitor. The first pole of the first transistor is connected to the data line, and the first pole of the driving transistor is connected to the second pole of the first transistor. The first pole of the storage capacitor is connected to the gate of the driving transistor, and the second pole of the storage capacitor is connected to the first power supply terminal.

12. The display panel according to claim 10, wherein, The positive projection of the first gate signal line and the second gate signal line on the substrate does not overlap with the positive projection of the channel region of the second transistor on the substrate.

13. The display panel according to any one of claims 10-12 further includes an initialization signal line, wherein, The initialization signal line is configured to provide an initialization signal to the pixel circuit. The pixel circuit further includes a first reset transistor. The first pole of the first reset transistor is connected to the initialization signal line, and the second pole of the first reset transistor is connected to the gate of the driving transistor.

14. The display panel according to claim 13, wherein, The first gate signal line and the second gate signal line are located between the second transistor and the first reset transistor.

15. The display panel according to claim 11, wherein, The pixel unit further includes a third pixel unit in the same column as the first pixel unit. The data line includes a first data line, a second data line, and a third data line. The first data line is connected to the first pixel unit, the second data line is connected to the second pixel unit, and the third data line is connected to the third pixel unit.

16. The display panel according to claim 11, wherein, The pixel unit further includes a fourth pixel unit in the same column as the second pixel unit. The data line includes a fourth data line, and the fourth data line is connected to the fourth pixel unit.

17. The display panel according to any one of claims 1-5 further includes a connecting element, wherein, The light-emitting element is connected to the pixel circuit through the connection element. The connection element includes a shielding portion that extends along the second direction. The display panel further includes data lines configured to provide data signals to the pixel circuits. A first pole of the first transistor is connected to the data lines. The data lines and the shielding portion are located in the same layer. The data lines include two adjacent data lines. The shielding portion is located between the two adjacent data lines. A positive projection of the first connection line on the substrate does not overlap with a positive projection of the shielding portion on the substrate.

18. The display panel according to claim 17, wherein, The pixel circuit includes a driving transistor and a second transistor. A first pole of the second transistor is connected to a second pole of the driving transistor. A second pole of the second transistor is connected to a gate of the driving transistor. The display panel further includes a third connection line. The gate of the driving transistor is connected to the second pole of the second transistor through the third connection line. An area of a positive projection of the shielding portion on the substrate is greater than an area of a positive projection of the third connection line on the substrate.

19. The display panel according to claim 18, wherein, A positive projection of the gate of the driving transistor on the substrate partially overlaps with a positive projection of the shielding portion on the substrate. An area of an overlapping portion between the shielding portion and the gate of the driving transistor is smaller than an area of the gate of the driving transistor.

20. The display panel according to claim 18, wherein, A dimension of the gate of the driving transistor in the first direction is greater than a dimension of the shielding portion in the first direction. A dimension of the shielding portion in the second direction is greater than a dimension of the gate of the driving transistor in the second direction.

21. The display panel according to claim 17, wherein, A positive projection of the shielding portion on the substrate overlaps with a positive projection of the first gate line or the second gate line on the substrate.

22. A display device, comprising the display panel according to any one of claims 1-21.

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