Surrounding gate transistor and manufacturing method thereof, electronic device

Abstract

The embodiment of the application discloses a surrounding gate transistor and a manufacturing method thereof and an electronic device, which comprises a channel, a source, a gate and a drain arranged on a substrate, the gate is arranged around the channel, one end of the channel is connected with the source, and the other end of the channel is connected with the drain; a modulation electrode is arranged between the drain and the gate, the modulation electrode comprises a modulation electrode dielectric layer arranged around the channel and a modulation electrode metal layer arranged around the modulation electrode dielectric layer, wherein the modulation electrode metal layer is separated from the drain and the gate. Thus, the surrounding gate transistor adopts a GAA surrounding gate design, the gate control capability is stronger, the modulation electrode is arranged between the gate and the drain, coupling charges are generated on the modulation electrode, the energy band structure between the gate and the drain is modulated, the barrier width of carrier tunneling is increased, the tunneling probability of the carrier is reduced, and the leakage current of the surrounding gate transistor in the off state is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a gate-all-around transistor, its fabrication method, and an electronic device. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are the most important devices in integrated circuits such as microprocessors and memory, dominating the application and development of integrated circuits. Among them, planar MOSFET devices can continuously shrink in size proportionally along Moore's Law, thereby continuously improving the integration and performance of circuits while reducing manufacturing costs.

[0003] Currently, as the size of planar MOSFET devices moves from the micrometer level to the deep submicrometer level and even the nanometer level, non-ideal effects such as the short-channel effect are becoming increasingly apparent, resulting in increasingly large leakage currents in the off-state of planar MOSFET devices. This leakage current makes the static power consumption of integrated circuits unacceptable and also affects the operating performance of integrated circuits.

[0004] Among them, FinFET and Nanowire (NW) transistors have better suppression of off-state leakage current, which can significantly improve circuit control and reduce leakage current. However, it is difficult to make the size of FinFET devices smaller than 3nm.

[0005] For gate-all-around transistors (GALLs) at nodes of 3nm and below, due to the small channel size, severe gate-induced drain leakage (GIDL) occurs when the GALL is off. The tunneling current of the GALL increases the leakage current of the GALL, thereby affecting the power consumption and performance of the circuit and severely restricting the development of integrated circuits. Summary of the Invention

[0006] This application provides a gate-all-around transistor and its fabrication method, as well as an electronic device, which reduces the leakage current of small-sized gate-all-around transistors in the off-state, thus reducing the impact on device performance.

[0007] To achieve the above objectives, this application adopts the following technical solution:

[0008] A first aspect of this application provides a gate-all-around transistor (GAT), comprising: a channel, a source, a gate, and a drain disposed on a substrate, the gate surrounding the channel, one end of the channel being connected to the source and the other end being connected to the drain; and a modulation electrode disposed between the drain and the gate, the modulation electrode comprising: a modulation electrode dielectric layer disposed around the channel, and a modulation electrode metal layer disposed around the modulation electrode dielectric layer, wherein the modulation electrode metal layer is separated from the drain and the gate. Thus, the GAT employs a gate-all-around design, resulting in stronger gate control capability. By disposing a modulation electrode between the gate and the drain, coupling charges are generated on the modulation electrode due to the electric field coupling between the modulation electrode and the drain, modulating the band structure between the gate and the drain. This makes the band bending between the drain and the gate smoother, increasing the barrier width for carrier tunneling and reducing the tunneling probability of carriers. This suppresses the gate-drain leakage effect when the GAT is off, reducing leakage current when the GAT is off.

[0009] In one optional implementation, the distance between the modulation electrode metal layer and the drain is smaller than the distance between the modulation electrode metal layer and the gate. Consequently, as the distance between the modulation electrode and the drain decreases, the capacitance between them increases, resulting in more coupling charge generated at the edge of the modulation electrode. This coupling charge on the modulation electrode has a stronger bandgap modulation capability between the gate and the drain, making the bandgap between the drain and the gate smoother. This increases the barrier width for carrier tunneling, further reducing the tunneling probability of carriers, thereby suppressing the gate-to-drain leakage effect when the gate-around transistor is off, and reducing leakage current when the gate-around transistor is off.

[0010] In one alternative implementation, the dielectric constant of the modulation electrode dielectric layer is greater than that of SiO2. Therefore, the modulation electrode dielectric layer can be made of a high-dielectric-constant gate dielectric material, which reduces the thickness of the modulation electrode dielectric layer, facilitating the miniaturization of the gate-around transistor and improving the modulation sensitivity of the modulation electrode.

[0011] In one optional implementation, the metal-semiconductor work function difference between the modulation electrode metal layer and the channel semiconductor material is (-1, 1) e·V. When the metal-semiconductor work function difference between the modulation electrode metal layer and the channel semiconductor material is small, the tunneling probability in the off-state of the gate-all-around transistor can be reduced, the gate-induced drain leakage effect in the off-state of the gate-all-around transistor can be suppressed, and the leakage current in the off-state of the gate-all-around transistor can be reduced.

[0012] In one alternative implementation, the modulation electrode dielectric layer covers the channel between the gate and the drain. This allows the gate-all-around transistor to provide optimal channel control.

[0013] A second aspect of this application provides a method for fabricating a gate-all-around transistor, comprising: forming a modulation electrode dielectric layer around a channel between the drain and the gate of the gate-all-around transistor, wherein the modulation electrode dielectric layer and the gate are disposed around the channel, one end of the channel is connected to the source of the gate-all-around transistor, and the other end is connected to the drain; forming a modulation electrode metal layer around the modulation electrode dielectric layer, wherein the modulation electrode metal layer is disposed around the modulation electrode dielectric layer, and the modulation electrode metal layer is separated from the drain and the gate.

[0014] In one alternative implementation, a modulation electrode dielectric layer is formed around the channel between the drain and gate of the gate transistor. This includes forming the modulation electrode dielectric layer around the channel between the drain and gate of the gate transistor using an atomic layer deposition process. The modulation electrode dielectric material is selected from HfO2 or Al2O3. This reduces the complexity of the manufacturing process.

[0015] In one alternative implementation, a modulation electrode dielectric layer is formed around the channel between the drain and gate of the gate transistor, comprising: forming the modulation electrode dielectric layer around the channel between the drain and gate of the gate transistor using a plasma-enhanced chemical vapor deposition process, wherein the modulation electrode dielectric material is SiO2. This reduces the complexity of the manufacturing process.

[0016] In one optional implementation, a modulation electrode metal layer is formed around the modulation electrode dielectric layer, comprising: forming the modulation electrode metal layer around the modulation electrode dielectric layer using a chemical vapor deposition process, wherein the modulation electrode metal layer is made of Al or Ni. This reduces the complexity of the manufacturing process.

[0017] In one optional implementation, a modulation electrode metal layer is formed around the modulation electrode dielectric layer, comprising: forming the modulation electrode metal layer around the modulation electrode dielectric layer using a plasma-enhanced chemical vapor deposition process, wherein the modulation electrode metal layer is made of polycrystalline silicon. This reduces the complexity of the manufacturing process.

[0018] In one alternative implementation, the distance between the modulation electrode metal layer and the drain is less than the distance between the modulation electrode metal layer and the gate.

[0019] In one alternative implementation, the dielectric constant of the modulation electrode dielectric layer is greater than the dielectric constant of SiO2.

[0020] In one alternative implementation, the metal-semiconductor work function difference between the modulation electrode metal layer and the semiconductor material of the channel is (-1,1)e·V.

[0021] In one alternative implementation, the modulation electrode dielectric layer covers the channel between the gate and the drain.

[0022] A third aspect of this application provides an electronic device including a substrate and a gate-all-around transistor as described above, the gate-all-around transistor being disposed on the surface of the substrate. Thus, by employing the aforementioned gate-all-around transistor, the electronic device reduces leakage current when the gate-all-around transistor is off, thereby improving device performance. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a gate-around transistor.

[0024] Figure 2 for Figure 1 Simulation diagram of tunneling probability distribution of a gate-all-around transistor in the off-state;

[0025] Figure 3 for Figure 1 Simulation diagram of the energy band structure curve of a gate-all-around transistor in the off-state;

[0026] Figure 4 This is a schematic diagram of a gate-all-around transistor provided in an embodiment of this application;

[0027] Figure 5 for Figure 4 Simulation diagram of tunneling probability distribution of a gate-around transistor in the off-state;

[0028] Figure 6 for Figure 4 Simulation diagram of the energy band structure curve of a gate-all-around transistor in the off-state;

[0029] Figure 7 A flowchart illustrating a method for fabricating a gate-all-around transistor, as provided in an embodiment of this application;

[0030] Figure 8A , Figure 8B , Figure 8C , Figure 8D To execute Figure 7 A schematic diagram of the product structure obtained from each step;

[0031] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0033] In the following description, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0034] Furthermore, in this application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0035] The following explains the terminology that may appear in the embodiments of this application.

[0036] Definitions:

[0037] Short-channel effects: These are some effects that occur in transistors when the conductive channel length of a MOSFET is reduced to the order of tens of nanometers or even a few nanometers. These effects mainly include a decrease in threshold voltage as the channel length decreases, a decrease in the drain-induced barrier, carrier surface scattering, velocity saturation, ionization, and hot electron effects.

[0038] Energy bands: In the formation of molecules, atomic orbitals constitute molecular orbitals with discrete energy levels. Crystals are formed by the orderly stacking of a large number of atoms. The number of molecular orbitals formed by atomic orbitals is so large that the energy levels of the formed molecular orbitals can be considered quasi-continuous, thus forming energy bands.

[0039] Gate-induced drain leakage tunneling current: when the gate-drain voltage V at the gate-drain overlap region... DG When the current is large, band-to-band tunneling (BTBT) occurs between the valence and conduction bands in silicon near the overlap region interface, forming a current known as gate-to-drain leakage tunneling current. As device dimensions decrease, the gate-to-drain leakage tunneling current increases dramatically.

[0040] Metal-semiconductor work function difference: When metal and semiconductor are in contact (MS contact), the potentials on both sides are different. The work function is the difference between E0 (electron energy) and Ef (Fermi level energy), which is the energy required for an electron to escape from the medium. From semiconductor to metal, electrons need to overcome a potential barrier; conversely, from metal to semiconductor, electrons are blocked by a potential barrier. When a forward bias is applied, the potential barrier on the semiconductor side decreases; conversely, when a reverse bias is applied, the potential barrier on the semiconductor side increases. This gives the metal-semiconductor contact a rectifying effect.

[0041] For P-type semiconductors, the work function of the metal is greater than that of the semiconductor; for N-type semiconductors, the work function of the metal is less than that of the semiconductor. Let the work function of the metal be W. m =E0-(E f The work function of a semiconductor is Ws = E0 - (Em) f The work function difference between metals and semiconductors is: W s -W m .

[0042] Equivalent oxide layer thickness: The thickness of the pure SiO2 gate dielectric when the high dielectric constant gate dielectric and the pure SiO2 gate dielectric achieve the same gate capacitance.

[0043] Figure 1 This is a schematic diagram of a gate-all-around transistor. Figure 1 As shown, the gate-all-around transistor includes one or more channels 100, a source 101, a gate 102, and a drain 103.

[0044] In this configuration, the source 101, gate 102, and drain 103 are sequentially disposed on the upper surface of the substrate along a first direction. The gate 102 is disposed around the channel 100, and one end of the channel 100 is connected to the source 101, while the other end is connected to the drain 103.

[0045] The embodiments of this application do not limit the structure of the channel 100. In one implementation of this application, the channel 100 may be designed as a nanowire, and in another implementation of this application, the channel 100 may be designed as a nanosheet. These are all within the protection scope of this application.

[0046] It should be noted that the first direction can be any direction parallel to the upper surface of the substrate. The gate 102 can be a gate all around (GAA) design, where the gate 102 completely surrounds a section of the channel 100. This gate all around transistor employs a gate all around design, resulting in stronger gate control capabilities.

[0047] like Figure 1 As shown, the source 101, gate 102, and drain 103 each include: a first surface and a second surface opposite to each other, and a side surface connecting the first surface and the second surface. The first surface of the source 101 is opposite to the second surface of the gate 102, and the first surface of the gate 102 is opposite to the second surface of the drain 103. A channel 100 passes through the first surface and the second surface of the gate 102 and is connected to the first surface of the source 101 and the second surface of the drain 103, respectively.

[0048] It should be noted that the first surface of Source 101 is Figure 1 The right side of the source electrode 101, the second surface of the gate electrode 102 is Figure 1 The left side of the gate 102, the first surface of the gate 102 is Figure 1 The right side of the gate 102, the second drain 103 is Figure 1 The left side of the middle drain electrode 103.

[0049] This application embodiment does not limit the specific structure of the source 101, gate 102, and drain 103. The source 101 includes a source region 1011 and a source metal 1012 disposed in the source region 1011, wherein the source metal 1012 is in direct contact with the upper surface of the source region 1011. The drain 103 includes a drain region 1031 and a drain metal 1032 disposed in the drain region 1031, wherein the drain metal 1032 is in direct contact with the upper surface of the drain region 1031. The gate 102 includes a gate dielectric layer 1021 and a gate metal 1022. A gate metal 1022 is disposed on each side of the gate dielectric layer 1021. The side of the gate dielectric layer 1021 includes: Figure 1 The upper surface, lower surface, front surface and rear surface of the middle gate dielectric layer 1021.

[0050] Figure 2 for Figure 1 Simulation diagram of the tunneling probability distribution of the gate-around transistor in the off-state. Among them, Figure 2 Point A in the diagram represents the connection point between gate 102 and drain 103, where, as shown... Figure 2 As shown, the tunneling probability at the edge of gate 102 is 6.69 × 10⁻⁶. 23 cm -3 〃s -1 The carriers at the edge of the gate 102 have a high probability of tunneling, which causes the gate-to-drain transistor to produce a gate-to-drain leakage effect when it is off. The gate-to-drain leakage tunneling current increases the leakage current of the gate-to-drain transistor, thereby affecting the power consumption and performance of the circuit and severely restricting the development of integrated circuits.

[0051] Figure 3 for Figure 1 Simulated band structure curves of a gate-all-around transistor in the off-state. The horizontal axis represents distance in μm, and the vertical axis represents energy in e·V. Where E... F For the Fermi level line, E C The curve shows the conduction band energy as a function of distance in the off-state, E. V This is a curve showing how valence band energy changes with distance. Figure 3 L1 in the figure represents the Fermi level line E. F The distance between the intersection of the conduction band and the price band, that is... Figure 2The width of the tunneling barrier at the gate edge in region A. For example... Figure 3 As shown, the large band bending amplitude between the drain 103 and the gate 102 and the small tunneling barrier width L1 cause the following... Figure 2 The increased probability of carrier tunneling at the gate edge affects the power consumption and performance of the circuit, severely restricting the development of integrated circuits.

[0052] To reduce leakage current in the off-state of a gate-all-around (GAW) transistor, one could modify the impurity distribution in the channel to create a lower doping concentration gradient in the PN junction between the drain and the channel, or employ a PN junctionless GAW structure to increase the tunneling barrier width and suppress gate-to-drain leakage current. However, given the extremely small size of GAW devices, achieving a low doping concentration gradient in the PN junction between the drain and the channel through annealing is extremely difficult in terms of fabrication. Furthermore, a low doping concentration gradient in the channel leads to an increase in the channel's equivalent series resistance, degrading device performance. On the other hand, a PN junctionless GAW transistor exhibits a drain-induced barrier reduction effect, resulting in a larger off-state leakage current and impacting device performance.

[0053] Therefore, embodiments of this application provide a gate-all-around transistor, such as Figure 4 As shown, the gate-all-around transistor includes: a channel 100, a source 101, a gate 102, and a drain 103 as described above, and a modulation electrode 104. The modulation electrode 104 is located between the drain region 1031 and the gate dielectric layer 1021, and is disposed around the channel 100 between the drain region 1031 and the gate dielectric layer 1021.

[0054] It should be noted that when there are multiple channels 100, the modulation electrode 104 can be arranged to surround the entire channel 100, or it can surround each channel 100 independently. These are all within the protection scope of this application.

[0055] The modulation electrode 104 includes a modulation electrode dielectric layer 1041 and a modulation electrode metal layer 1042. The modulation electrode dielectric layer 1041 is disposed around the channel 100 between the drain region 1031 and the gate dielectric layer 1021, and completely covers a section of the channel 100 between the drain region 1031 and the gate dielectric layer 1021.

[0056] In one implementation of this application, the modulation electrode dielectric layer 1041 can completely enclose the channel 100, thereby improving the modulation capability of the modulation electrode 104 for the channel region.

[0057] The modulation electrode metal layer 1042 is disposed, for example, around the modulation electrode dielectric layer 1041, and the modulation electrode metal layer 1042 is separated from the gate 102 and the drain 103.

[0058] like Figure 4 As shown, the modulation electrode dielectric layer 1041 includes: a first surface and a second surface opposite to each other, and a side surface connecting the first surface and the second surface, wherein the first surface of the modulation electrode 104 is opposite to the second surface of the drain region 1031, the second surface of the modulation electrode 104 is opposite to the first surface of the gate dielectric layer 1021, and each side surface of the modulation electrode dielectric layer 1041 is provided with a modulation electrode metal layer 1042.

[0059] This application does not limit the material of the channel 100. The material of the channel 100 region is a semiconductor material doped with impurities. The semiconductor material can be silicon (Si), silicon germanium (SiGe), or other semiconductor materials, and the doping type can be N-type doping or P-type doping.

[0060] N-type doping refers to the addition of a small amount of phosphorus (or antimony) impurities to a semiconductor. Because the semiconductor atoms (such as silicon atoms) are replaced by impurity atoms, four of the five outer electrons of the phosphorus atom form covalent bonds with the surrounding semiconductor atoms. The extra electron is almost unbound and easily becomes a free electron. Thus, an N-type semiconductor becomes a semiconductor with a high electron concentration, and its conductivity is mainly due to the free electrons. Compared to the intrinsic region, N-type doped semiconductors have an excess of free electrons.

[0061] P-type doping refers to the addition of a small amount of boron (or indium) impurity to a semiconductor. When the impurity atom replaces a semiconductor atom (such as silicon), the three outer electrons of the boron atom form covalent bonds with the surrounding semiconductor atoms, creating a "hole." This hole can attract bound electrons to "fill" it, making the boron atom a negatively charged ion. Thus, this type of semiconductor, containing a high concentration of holes ("equivalent" to positive charge), becomes a conductive material. Compared to the intrinsic region, P-type doped semiconductors have an excess of holes.

[0062] The voltage at gate 102 can be expressed as V. G The voltage at the drain 103 can be expressed as V. D The voltage at the source 101 can be expressed as Vs, and the driving voltage of the gate-all-around transistor can be expressed as VDD.

[0063] In the on-state, both VG and VD are positive voltages. For example, V G =V D =V DD >0, V S =0.

[0064] When in the off state, the voltage V at the drain of 103 is D The voltage V at gate 102 is greater than 0. G=0. For example, V D =1V.

[0065] Figure 5 for Figure 4 Simulation diagram of the tunneling probability distribution of the gate-around transistor in the off-state. Among them, Figure 5 Point B in the diagram represents the connection point between the gate 102 and the modulation electrode 104, where the tunneling probability at the gate edge is 5.911 × 10⁻⁶. 17 cm -3 〃s -1 less than Figure 3 The probability of tunneling through the gate edge.

[0066] Figure 6 for Figure 4 Simulation diagram of the energy band structure curve of a gate-all-around transistor in the off-state. Among them, Figure 6 The horizontal axis represents distance in μm, and the vertical axis represents energy in e·V. F for Figure 4 The Fermi level line of the gate-around transistor in the off-state, Ec is Figure 4 The curve showing the conduction band energy of a gate-around transistor in the off-state as a function of distance. Ev is... Figure 4 The curve showing the change of valence band energy with distance in the off-state of a gate-around transistor.

[0067] Figure 6 L2 in the figure represents the Fermi level line E. F The distance between the intersection points of the conduction band and the price band, i.e. Figure 5 The width of the tunneling barrier at the gate edge in region B. Figure 3 compared to, Figure 6 The band bending in the middle is more gradual, making Figure 6 The tunneling barrier width L2 of the gate-all-around transistor is greater than Figure 3 The tunneling barrier width L1 of the gate transistor reduces the probability of carrier tunneling at the gate edge in the off state.

[0068] Therefore, the gate-all-around transistor provided in this application increases the tunneling barrier width of the charge carriers by providing a modulation electrode 104 between the gate 102 and the drain 103, thereby reducing the tunneling probability of the charge carriers and suppressing the gate-drain leakage effect when the gate-all-around transistor is off, thus reducing the leakage current when the gate-all-around transistor is off.

[0069] Furthermore, compared to changing the impurity distribution in the channel or using a PN junction-free gate-around transistor structure to reduce the tunneling barrier width, the modulation electrode 104 does not increase the channel equivalent series resistance nor cause additional drain-induced barrier reduction effect.

[0070] It should be noted that the source region 1011, drain region 1031, gate dielectric layer 1021, and modulation electrode dielectric layer 1041 can be cylindrical with a rectangular cross-section, cylindrical with a circular cross-section, or cylindrical with other cross-section shapes, such as cylindrical with a quadrilateral cross-section, cylindrical with a triangular cross-section, cylindrical with an elliptical cross-section, etc. This application does not limit the specific shape of the source region 1011, drain region 1031, gate dielectric layer 1021, and modulation electrode dielectric layer 1041, and these are all within the protection scope of this application.

[0071] This application does not limit the specific material of the modulation electrode 104. However, the material of the modulation electrode metal layer 1042 should satisfy the following: the metal-semiconductor work function difference Φ between the modulation electrode metal layer 1042 and the semiconductor material constituting the channel 100. fps The preset threshold is, for example, (-1,1)e〃V.

[0072] Among them, tunneling current I off The metal-semiconductor work function difference Φ between the modulation electrode metal layer 1042 and the channel semiconductor material varies. fps The increase first decreases and then increases (in an exponential manner).

[0073] This is because when a metal and a semiconductor come into contact, the Fermi levels on both sides become equal due to the uniformity of the electronic systems. In the case of an n-type semiconductor, W... m >W s For example, in this case: because W m >Ws, therefore (E f )m<(E f Electrons readily flow from the semiconductor to the metal, causing the semiconductor surface to become positively charged and the metal surface to become negatively charged. A potential difference V is generated upon contact. d =V m -V s =(W s -W m ) / q.

[0074] When the metal-semiconductor work function difference Φ between the modulation electrode metal layer 1042 and the channel semiconductor material fps When the value is negative (e.g., -1e·V), the modulation electrode 104 will generate an electric field perpendicular to the channel and downward. Due to the edge effect between the gate 102 and the modulation electrode 104, the peak electric field at the edge of the gate 102 is increased, thereby aggravating the gate-induced drain leakage effect and increasing the tunneling current.

[0075] When the metal-semiconductor work function difference Φ between the modulation electrode metal layer 1042 and the channel semiconductor material is... fpsWhen the voltage is positive (e.g., +1 eV), band tunneling at the edge of gate 102 essentially disappears, but band tunneling occurs at the edge of modulation electrode 104, resulting in an increase in tunneling current. This is because a strong repulsive electric field is generated at the edge of modulation electrode 104, forming a heavily P-type doped region on the channel surface. This heavily P-type doped region forms a reverse-biased PN junction with the heavily N-type doped drain region 1031. Under the influence of the reverse-biased electric field of drain 103 and modulation electrode 104, band tunneling occurs, leading to an increase in tunneling current.

[0076] When the metal-semiconductor work function difference Φ between the modulation electrode metal layer 1042 and the channel semiconductor material fps When I is 0, the tunneling current I off Minimum, therefore, the modulation electrode metal layer can be made with the same Φ as the channel semiconductor material. fps Similar materials. For example, the semiconductor material constituting the channel 100 may be silicon, and the material of the modulation electrode metal layer 1042 may be a metal, such as aluminum (Al), nickel (Ni), or polycrystalline silicon, all of which fall within the scope of protection of this application.

[0077] This application does not limit the specific material of the modulation electrode dielectric layer. For example, the modulation electrode dielectric layer can be made of a material with a relatively high permittivity. The relative permittivity of the modulation electrode dielectric layer is, for example, greater than a preset value, which is, for example, the relative permittivity of a pure SiO2 gate dielectric layer.

[0078] The relationship between the relative permittivity ε of the modulation electrode dielectric layer 1041 and the equivalent oxide layer thickness Eox of the modulation electrode dielectric layer 1041 satisfies the following equation:

[0079]

[0080] Where t is the physical thickness of the modulation electrode dielectric layer 1041, and ε SiO2 It is the relative permittivity of the pure SiO2 gate dielectric layer. It should be noted that the equivalent oxide layer thickness Eox of the modulation electrode dielectric layer 1041 refers to the thickness of the pure SiO2 gate dielectric when the modulation electrode dielectric layer 1041 and the pure SiO2 gate dielectric achieve the same gate capacitance.

[0081] According to equation (1), when the equivalent oxide layer thickness Eox of the modulation electrode dielectric layer 1041 is constant, the larger the relative permittivity ε of the modulation electrode dielectric layer 1041 is, the larger the physical thickness of the modulation electrode dielectric layer 1041 is.

[0082] Therefore, when the relative permittivity of the modulation electrode dielectric layer 1041 is greater than that of the pure SiO2 gate dielectric layer, the physical thickness of the modulation electrode dielectric layer 1041 is greater than that of the equivalent oxide layer thickness of the modulation electrode dielectric layer 1041, thereby increasing the physical thickness of the modulation electrode dielectric layer 1041 and improving its insulation performance.

[0083] For example, the material of the modulation electrode dielectric layer 1041 can be a material with a relatively high permittivity, such as hafnium dioxide (HfO2) or aluminum oxide (Al2O3).

[0084] If the equivalent oxide layer thickness of the modulation electrode dielectric layer 1041 using the aforementioned material with a relatively high permittivity is, for example, 1 nm, then the thickness of the modulation electrode dielectric layer 1041 is greater than 1 nm.

[0085] Therefore, the modulation electrode dielectric layer 1041 adopts a high dielectric constant gate dielectric material. Compared with SiO2, the physical thickness of the modulation electrode dielectric layer 1041 can be increased, the insulation performance of the modulation electrode dielectric layer 1041 can be improved, and the leakage current of the gate transistor in the off state can be reduced.

[0086] The specific material of the gate 102 is not limited in the embodiments of this application. In one implementation of this application, the gate dielectric layer 1021 can be made of the same material as the modulation electrode dielectric layer 1041, and the gate metal layer 1022 can be made of the same material as the modulation electrode metal layer 1042.

[0087] In another implementation of this application, the material of the gate 102 may be different from that of the modulation electrode 104. The metal layer of the gate 102 may be aluminum (Al), tungsten (W), nickel (Ni), or a metal compound, such as titanium aluminum nitride (TiAlN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium nitride (TiN), or polycrystalline silicon.

[0088] The specific location of the modulation electrode 104 is not limited in the embodiments of this application. In one implementation of this application, the modulation electrode 104 is located at the midpoint between the drain 103 and the gate 102.

[0089] In another implementation of this application, the distance between the modulation electrode metal layer 1042 and the drain 103 is smaller than the distance between the modulation electrode metal layer 1042 and the gate 102.

[0090] Among them, the tunneling current I around the gate transistor off It decreases as the distance between the modulation electrode 104 and the drain electrode 103 decreases.

[0091] This is because as the distance between the modulation electrode 104 and the drain 103 decreases, the capacitance increases, resulting in more coupling charge generated at the edge of the modulation electrode 104. This enhances the modulation of the band structure between the gate and drain, causing the capacitance to decrease exponentially as the distance between the modulation electrode 104 and the drain 103 decreases. Furthermore, the gate-to-drain leakage current caused by the "band-to-band tunneling" effect at the gate edge is the primary source of the tunneling current surrounding the gate transistor. Therefore, the tunneling current I... off The distance L between the modulation electrode 104 and the drain electrode 103 varies. cb It decreases as it decreases.

[0092] Therefore, by placing the modulation electrode close to the drain, the tunneling probability of carriers can be reduced in the off state, and the barrier width of carrier tunneling can be increased, thereby suppressing the gate-to-drain leakage effect of the gate-around transistor in the off state and reducing the leakage current of the gate-around transistor in the off state.

[0093] This application also provides a method for fabricating a gate-all-around transistor. For example... Figure 7 As shown, the method includes the following steps:

[0094] S101, such as Figure 8A As shown, a modulation electrode dielectric layer 1041 is formed around the channel 100 between the drain 103 and the gate 102 of the gate transistor.

[0095] The modulation electrode dielectric layer 1041 is disposed around the channel 100 between the drain region 1031 and the gate dielectric layer 1021, and completely covers a section of the channel 100 between the drain region 1031 and the gate dielectric layer 1021.

[0096] In one implementation of this application, the modulation electrode dielectric layer 1041 covers the entire channel 100 between the drain 103 and the gate 102, thereby improving the modulation capability of the modulation electrode 104 for the channel region.

[0097] The gate-all-around transistor includes a source region 1011, a gate dielectric layer 1021, and a drain region 1031 arranged sequentially. The gate dielectric layer 1021 is disposed around the channel 100, with one end connected to the source region 1011 and the other end connected to the drain region 1031.

[0098] The source region 1011, the gate dielectric layer 1021, and the drain region 1031 each include: a first surface and a second surface opposite to each other, and a side surface connecting the first surface and the second surface. Specifically, the first surface of the source region 1011 is opposite to the second surface of the gate dielectric layer 1021, and the first surface of the gate dielectric layer 1021 is opposite to the second surface of the drain region 1031.

[0099] The aforementioned gate-all-around transistor further includes a source 101, a drain 103, and a gate 102. The source 101 is located in the source region 1011 and is in direct contact with the first side of the source region 1011. The drain 103 is located in the drain region 1031 and is in direct contact with the first side of the drain region 1031. The first side of the source region 1011 and the first side of the drain region 1031 are, for example, located on the same plane. A gate metal 1022 is provided on each side of the gate dielectric layer 1021.

[0100] When forming the modulation electrode dielectric layer 1041, different methods can be selected to form the modulation electrode dielectric layer 1041 depending on the material of the modulation electrode dielectric layer 1041, such as atomic layer deposition, plasma-enhanced chemical vapor deposition, etc. The material of the modulation electrode dielectric layer 1041 can be a dielectric material, such as silicon dioxide (SiO2), hafnium dioxide (HfO2), aluminum oxide (Al2O3), etc.

[0101] In one implementation of this application, the material of the modulation electrode dielectric layer 1041 is hafnium dioxide (HfO2), aluminum oxide (Al2O3), etc., which can be formed by atomic layer deposition process.

[0102] In another implementation of this application, the material of the modulation electrode dielectric layer 1041 is silicon dioxide (SiO2), which can be formed by plasma-enhanced chemical vapor deposition.

[0103] Assuming that the material constituting the modulation electrode dielectric layer 1041 is silicon dioxide (SiO2), the wafer can be placed in a high-temperature oxygen atmosphere, which enables the silicon dioxide (SiO2) to grow at a certain rate, generating a silicon dioxide (SiO2) layer of a certain thickness as the modulation electrode dielectric layer 1041. The specific thickness of the generated silicon dioxide (SiO2) layer can be determined according to the needs of the actual application.

[0104] The modulation electrode dielectric layer 1041 can completely cover the surface area of ​​the channel 100, thereby enabling the fabricated gate-all-around transistor to provide optimal channel control capabilities.

[0105] S102, such as Figure 8B , Figure 8C , Figure 8D As shown, a modulation electrode metal layer 1042 is formed around the modulation electrode dielectric layer 1041.

[0106] The modulation electrode metal layer 1042 is disposed, for example, around the modulation electrode dielectric layer 1041, and the modulation electrode metal layer 1042 is separated from the gate 102 and the drain 103.

[0107] This application embodiment does not limit the width and position of the modulation electrode metal layer 1042. The width of the modulation electrode metal layer 1042 may be less than or equal to the width of the modulation electrode dielectric layer 1041.

[0108] For example, in one implementation of this application, such as Figure 8B As shown, the modulation electrode dielectric layer 1041 only covers part of the channel 100 between the drain 103 and the gate 102, and the width of the modulation electrode metal layer 1042 is equal to the width of the modulation electrode dielectric layer 1041.

[0109] In another implementation of this application, such as Figure 8C As shown, the modulation electrode dielectric layer 1041 only covers a portion of the channel 100 between the drain 103 and the gate 102, the width of the modulation electrode metal layer 1042 is smaller than the width of the modulation electrode dielectric layer 1041, and the modulation electrode metal layer 1042 is located, for example, in the middle of the drain 103 and the gate 102.

[0110] In another implementation of this application, such as Figure 8D As shown, the modulation electrode dielectric layer 1041 only covers a portion of the channel 100 between the drain 103 and the gate 102. The width of the modulation electrode metal layer 1042 is smaller than the width of the modulation electrode dielectric layer 1041, and the distance between the modulation electrode metal layer 1042 and the drain 103 is smaller than the distance between the modulation electrode metal layer 1042 and the gate 102. Therefore, by placing the modulation electrode close to the drain, the tunneling probability of carriers can be reduced in the off-state, increasing the barrier width for carrier tunneling. This suppresses the gate-to-drain leakage effect of the gate-all-around transistor in the off-state and reduces the leakage current of the gate-all-around transistor in the off-state.

[0111] After the modulation electrode dielectric layer 1041 is formed, a modulation electrode metal layer 1042 can be formed on the outside of the modulation electrode dielectric layer 1041 by processes such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, and thermal evaporation. The modulation electrode metal layer 1042 can be made of metal, such as aluminum (Al) or nickel (Ni), or it can be polycrystalline silicon.

[0112] When forming the modulation electrode metal layer 1042, different methods can be selected to form the modulation electrode dielectric layer 1041 depending on the material of the modulation electrode metal layer 1042. For example, in one implementation of this application, the material of the modulation electrode metal layer 1042 is aluminum (Al) or nickel (Ni), etc., and it can be formed by thermal evaporation or chemical vapor deposition processes.

[0113] In another implementation of this application, the material of the modulation electrode metal layer 1042 is polycrystalline silicon, which can be formed by plasma-enhanced chemical vapor deposition.

[0114] In this configuration, the modulation electrode metal layer 1042 is separately disposed from the gate 102 and the drain 103, with a gap between the modulation electrode metal layer 1042 and the drain 103 and the gate 102, so that the drain metal 1032 and the modulation electrode metal layer 1042 form a capacitor. In the off state, the drain voltage V D >0, gate voltage V G =0. At this time, due to the electric field coupling between the modulation electrode 104 and the drain 103, a coupling charge will be generated on the modulation electrode 104, which modulates the band structure of the channel 100 between the source region 1011 and the gate dielectric layer 1021 in the off state, increases the tunneling barrier width of the carrier tunneling, reduces the tunneling probability of the carrier, thereby suppressing the gate-induced drain leakage effect when the gate-around transistor is off, and reducing the leakage current when the gate-around transistor is off.

[0115] This gate-all-around transistor can be used in integrated circuits such as microprocessors and memories in electronic devices such as mobile phones and computers. Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 9 As shown, the electronic device may also include, for example, a substrate 200, on which the gate-all-around transistor can be fabricated. The substrate 200 not only plays an electrical role in the fabrication of the gate-all-around transistor, but also provides mechanical support.

[0116] It should be noted that the material constituting the substrate 200 can be a semiconductor material without any impurities, such as silicon (Si), silicon dioxide (SiO2), or other semiconductor materials, or it can be a semiconductor material doped with impurities, which can be n-type impurities or p-type impurities. Therefore, the substrate can include n-type substrates, p-type substrates, and undoped substrates.

[0117] Therefore, by employing the aforementioned gate-around transistor, the leakage current of the gate-around transistor in the off state is reduced, thereby improving the device performance.

[0118] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A gate-all-around transistor, characterized in that, include: A channel, a source, a gate, and a drain are disposed on a substrate, the gate being disposed around the channel, and one end of the channel being connected to the source and the other end being connected to the drain; A modulation electrode is disposed between the drain and the gate and surrounding the channel. The modulation electrode includes a modulation electrode dielectric layer surrounding the channel and a modulation electrode metal layer surrounding the modulation electrode dielectric layer, wherein the modulation electrode metal layer is separated from the drain and the gate. The difference in metal-semiconductor work function between the modulation electrode metal layer and the semiconductor material of the channel is (-1, 1) e•V.

2. The gate-all-around transistor according to claim 1, characterized in that, The distance between the modulation electrode metal layer and the drain is less than the distance between the modulation electrode metal layer and the gate.

3. The gate-all-around transistor according to claim 1 or 2, characterized in that, The dielectric constant of the modulation electrode dielectric layer is greater than that of SiO2.

4. The gate-all-around transistor according to claim 1 or 2, characterized in that, The modulation electrode dielectric layer covers the channel between the gate and the drain.

5. The gate-all-around transistor according to claim 1 or 2, characterized in that, The channel is a nanowire channel or a nanosheet channel.

6. A method for fabricating a gate-all-around transistor, characterized in that, include: A modulation electrode dielectric layer is formed around a channel between the drain and gate of a gate transistor, wherein the modulation electrode dielectric layer and the gate are disposed around the channel, and one end of the channel is connected to the source of the gate transistor and the other end is connected to the drain. A modulation electrode metal layer is formed around the modulation electrode dielectric layer, wherein the modulation electrode metal layer is disposed around the modulation electrode dielectric layer and is separated from the drain and the gate. The difference in metal-semiconductor work function between the modulation electrode metal layer and the semiconductor material of the channel is (-1, 1) e•V.

7. The manufacturing method according to claim 6, characterized in that, The method of forming a modulation electrode dielectric layer around the channel between the drain and gate of the gate transistor includes: The modulation electrode dielectric layer is formed around the channel between the drain and gate of the gate transistor using an atomic layer deposition process; wherein the material of the modulation electrode dielectric layer is selected as HfO2 or Al2O3.

8. The manufacturing method according to claim 6, characterized in that, The method of forming a modulation electrode dielectric layer around the channel between the drain and gate of the gate transistor includes: The modulation electrode dielectric layer is formed around the channel between the drain and gate of the gate transistor using a plasma-enhanced chemical vapor deposition process; wherein the material of the modulation electrode dielectric layer is SiO2.

9. The manufacturing method according to any one of claims 6-8, characterized in that, The process of forming a modulation electrode metal layer around the modulation electrode dielectric layer includes: The modulation electrode metal layer is formed around the modulation electrode dielectric layer using thermal evaporation or chemical vapor deposition processes; wherein the material of the modulation electrode metal layer is Al or Ni.

10. The manufacturing method according to any one of claims 6-8, characterized in that, The distance between the modulation electrode metal layer and the drain is less than the distance between the modulation electrode metal layer and the gate.

11. The manufacturing method according to any one of claims 6-8, characterized in that, The dielectric constant of the modulation electrode dielectric layer is greater than that of SiO2.

12. The manufacturing method according to any one of claims 6-8, characterized in that, The modulation electrode dielectric layer covers the channel between the gate and the drain.

13. The manufacturing method according to any one of claims 6-8, characterized in that, The channel is a nanowire channel or a nanosheet channel.

14. An electronic device, characterized in that, It includes a substrate and a gate-all-around transistor as claimed in any one of claims 1-5, the gate-all-around transistor being disposed on the surface of the substrate.

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