Charge pump circuit and nonvolatile memory

Abstract

The charge pump circuit and the nonvolatile memory, wherein the charge pump circuit comprises: a charge pump unit adapted to generate an output voltage signal based on a voltage of a power supply terminal, wherein the output voltage signal comprises a direct current voltage signal and a ripple voltage signal; a comparison unit adapted to generate a first comparison signal based on a comparison result of a voltage value of the direct current voltage signal in the output voltage signal and a preset first threshold voltage; a boost control unit adapted to generate a first clock control signal based on a voltage value of the ripple voltage signal in the output voltage signal and a preset clock signal; and a signal feedback unit adapted to generate a second clock control signal based on the first comparison signal and the first clock control signal, and output the second clock control signal to the charge pump unit to control a boost state of the charge pump unit. The peak current output by the power supply terminal can be reduced by using the charge pump circuit.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of integrated circuits, and in particular to a charge pump circuit and a non-volatile memory. BACKGROUND

[0002] An embedded flash memory generally consists of a high-voltage generation circuit, a control logic circuit and a flash cell. The high-voltage generation circuit raises the output voltage to the high voltage required for erasing, writing and reading the flash cell through a charge pump circuit. In practical applications, a flash cell may require multiple different high-voltage ranges, so multiple charge pump circuits are usually used to generate high voltages in different voltage ranges.

[0003] When the charge pump is started, continuous output charge is required to raise the output voltage to the required high-voltage range without interruption. In this process, a large current is continuously provided by the power supply terminal, and the power supply terminal voltage is generally provided by a low dropout regulator (LDR), which puts high demands on the load capacity and instantaneous response capability of the LDR.

[0004] However, in some products, such as an embedded SIM (eSIM) card, a large peak current is output by the power supply terminal to raise the output voltage of the charge pump circuit to the target voltage, and the LDR is limited by the application scenario and cannot provide sufficient load capacity. SUMMARY

[0005] Therefore, embodiments of the present application provide a charge pump circuit and a non-volatile memory that can reduce the peak current output by the power supply terminal.

[0006] First, embodiments of the present application provide a charge pump circuit, comprising: a charge pump unit, a comparison unit, a boost control unit and a signal feedback unit, wherein:

[0007] The charge pump unit is coupled to the power supply terminal and is adapted to generate an output voltage signal based on the voltage of the power supply terminal until the voltage value of the output voltage signal reaches a target voltage, wherein the output voltage signal includes a direct current voltage signal and a ripple voltage signal;

[0008] The comparison unit is coupled to the charge pump unit and the signal feedback unit and is adapted to generate a first comparison signal based on the comparison result of the voltage value of the direct current voltage signal in the output voltage signal of the charge pump unit and a preset first threshold voltage, and output the first comparison signal to the signal feedback unit;

[0009] The boost control unit is coupled with the charge pump unit and the signal feedback unit, and is adapted to generate a first clock control signal based on a voltage value of a ripple voltage signal in the voltage signal output by the charge pump unit and a preset clock signal, and output the first clock control signal to the signal feedback unit;

[0010] The signal feedback unit is coupled with the comparison unit, the boost control unit and the charge pump unit, and is adapted to generate a second clock control signal based on the first comparison signal and the first clock control signal, and output the second clock control signal to the charge pump unit to control a boost state of the charge pump unit.

[0011] Correspondingly, the embodiment of the present application further provides a nonvolatile memory, comprising: a control logic unit, a high-voltage generating circuit and a memory array, wherein:

[0012] The control logic unit is adapted to control an enabling state and a discharging process of the high-voltage generating circuit;

[0013] The high-voltage generating circuit is coupled with the control logic unit and the memory array respectively, and is adapted to provide a voltage for erasing, reading or / and writing the memory array based on the control of the control logic unit, which comprises the charge pump circuit mentioned above;

[0014] The memory array comprises a plurality of flash memory units, and is adapted to store information.

[0015] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0016] The charge pump circuit in the embodiment of the present application comprises a charge pump unit, a comparison unit, a voltage boost control unit and a signal feedback unit. The charge pump unit is coupled with the power supply end, so that the output voltage signal can be generated based on the voltage of the power supply end until the voltage value of the output voltage signal reaches the target voltage. The output voltage signal comprises a direct current voltage signal and a ripple voltage signal. The comparison unit is coupled with the charge pump unit and the signal feedback unit. The comparison unit can generate the first comparison signal based on the comparison result of the voltage value of the direct current voltage signal in the output voltage signal and the preset first threshold voltage, and output the first comparison signal to the signal feedback unit. The voltage boost control unit is coupled with the charge pump unit and the signal feedback unit. The voltage boost control unit can generate the first clock control signal based on the voltage value of the ripple voltage signal in the output voltage signal of the charge pump unit and the preset clock signal, and output the first clock control signal to the signal feedback unit. The signal feedback unit can generate the second clock control signal based on the first comparison signal and the first clock control signal. The second clock control signal can control the voltage boost state of the charge pump unit. By adjusting the clock frequency of the second clock control signal, the voltage boost speed of the output voltage of the charge pump unit can be slowed down, so that the peak current output by the power supply end can be reduced.

[0017] Further, the charge pump circuit further comprises a voltage division unit. Since the voltage division unit is coupled between the charge pump unit and the first comparison unit, the voltage output by the charge pump unit can be avoided from being directly input to the first comparison unit, so that the first comparison unit can be implemented by using low-voltage devices. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 A structure schematic diagram of a charge pump circuit is shown.

[0019] Figure 2 A structure schematic diagram of a charge pump circuit is shown. Figure 1 A waveform diagram of the corresponding monitoring points of the charge pump circuit in the output voltage boost process is shown.

[0020] Figure 3 A waveform diagram of the peak current output by the power supply end is shown. Figure 2 A waveform diagram of the peak current output by the power supply end is shown.

[0021] Figure 4 A structure schematic diagram of a charge pump circuit in the embodiment of the present application is shown.

[0022] Figure 5 A structure schematic diagram of a charge pump circuit in the embodiment of the present application is shown.

[0023] Figure 6 The diagram shows the waveforms of corresponding monitoring points of a charge pump circuit during the output voltage rise process in an embodiment of the present invention.

[0024] Figure 7 A comparison diagram of the peak current variation waveform at the power supply terminal in the embodiment of the present invention and in the prior art is shown.

[0025] Figure 8 The diagram shows a comparison of the peak current variation waveforms at the power supply terminal under different discharge current conditions in embodiments of the present invention.

[0026] Figure 9 A schematic diagram of a non-volatile memory according to an embodiment of the present invention is shown. Detailed Implementation

[0027] As described in the background section, in specific application scenarios, a large peak current needs to be output from the power supply to raise the output voltage to the target voltage. However, LDRs are limited by the application scenarios and cannot provide sufficient load capacity.

[0028] The following detailed explanation, with specific examples and accompanying diagrams, addresses the issue of excessive peak current at the power supply terminal during the output voltage rise process of existing charge pump circuits.

[0029] Reference Figure 1 The diagram shows a charge pump circuit 10 powered by a power supply terminal VDD. The charge pump circuit 10 includes a charge pump 11, a voltage divider resistor module 12, a comparator 13, and a NOR gate 14, wherein:

[0030] The input terminal of the charge pump 11 is coupled to the power supply terminal VDD, and its output terminal is coupled to the first terminal of the voltage divider resistor module 12. The second terminal of the voltage divider resistor module 12 is coupled to the non-inverting input terminal of the comparator 13. The inverting input terminal of the comparator 13 is adapted to input a preset threshold voltage VREF, and its output terminal is coupled to the first input terminal of the NOR gate 14. The second input terminal of the NOR gate 14 is adapted to input a preset clock signal CLK, and its output terminal is coupled to the charge pump 11. The preset clock signal CLK can control the rise rate of the output voltage of the charge pump 11, thereby affecting the peak current output by the power supply terminal.

[0031] When the charge pump circuit 10 is started, the charge pump 11 can obtain the output voltage V based on the voltage at the power supply terminal VDD. pump The output voltage V pump The voltage divider module 12 outputs a divided voltage V. pump _DIV, since the charge pump 11 is in a charging state, its output voltage Vpump The voltage V output by the voltage divider resistor module 12 is always less than the target voltage. pump If _DIV is always less than the preset threshold voltage VREF, the level of the comparison signal STOP_CLK output by the comparator 13 is low level 0, then the feedback signal Pump_CLK output by the NOR gate NOR14 is opposite to the state of the preset clock signal CLK.

[0032] Since the feedback signal Pump_CLK follows the preset clock signal CLK, and the preset clock signal CLK can control the rise rate of the output voltage of the charge pump 11, the output voltage V of the charge pump 11... pump It can rise continuously following the feedback signal Pump_CLK until the output voltage V of the charge pump 11 is reached. pump It equals the target voltage.

[0033] However, at the output voltage V of charge pump 11 pump As the feedback signal Pump_CLK continues to rise, a large peak current will be generated at the power supply terminal VDD.

[0034] Combination Figure 1 and refer to Figure 2 shown Figure 1 The waveforms of the charge pump circuit at corresponding monitoring points during the output voltage rise process are shown in the figure below. Figure 2 As shown, at time t1, the charge pump circuit 10 starts up, and the charge pump 11 is charged by the power supply terminal VDD. The output voltage of the charge pump 11 is V pump The voltage V of the charge pump 11 continues to increase, and at time t2, the output voltage V... pump The target voltage has been reached.

[0035] At the output voltage V pump During the voltage increase process, due to the voltage V obtained through the voltage divider resistor module 12 pump Since _DIV is always less than the preset threshold voltage VREF, the level of the comparison signal STOP_CLK output by the comparator 13 is always low (0) during the time period from t1 to t2.

[0036] Continue to refer to Figure 2 During the period from t1 to t2, the feedback signal Pump_CLK is in a flipping state, and the power supply VDD continuously supplies current to the charge pump 11, thereby generating a large peak current. Since the generated peak current is in the direction from the negative to the positive terminal inside the power supply terminal, the monitored current value is negative, as shown in the waveform of current i in the dashed box in Figure 2. The current value i is less than 0mA and the current waveform is relatively dense.

[0037] However, when the output voltage V of the charge pump 11 pump When the target voltage is reached, the charge pump 11 may experience leakage, or its internal impedance may consume part of the voltage value, thereby causing the voltage of the comparison signal STOP_CLK output by the comparator 13 to fluctuate.

[0038] Reference Figure 3 shown Figure 2 The waveform diagram of the peak current change at the power supply terminal is shown in the figure. Figure 3 It can be seen that during the period when the output voltage of charge pump 11 increases, the peak current 31 output by power supply terminal VDD per microsecond can reach up to 2.2mA, which is much greater than the load capacity and instantaneous response capability of LDR; when the output voltage of charge pump reaches the target voltage, the peak current output by power supply terminal VDD per microsecond stabilizes at 0.3mA.

[0039] Research and experiments have shown that when a charge pump receives the feedback signal Pump_CLK, it outputs charge to the output terminal, simultaneously generating a ripple voltage. The higher the toggling frequency of the feedback signal Pump_CLK, the greater the ripple current at the output terminal. During this process, a large peak current is generated at the power supply terminal VDD. Based on this characteristic, by monitoring the ripple voltage at the output terminal and controlling the toggling frequency of the feedback signal Pump_CLK during the charge pump voltage rise process when the ripple voltage exceeds a certain threshold, the voltage rise rate of the charge pump unit's output voltage can be slowed down, thereby reducing the peak current output at the power supply terminal.

[0040] Specifically, to solve the above problems, the charge pump circuit of this embodiment of the invention is adopted. Based on the comparison result between the voltage value of the DC voltage signal in the generated voltage signal and the preset first threshold voltage, a first comparison signal is generated. Based on the voltage value of the ripple voltage signal in the generated voltage signal and the preset clock signal, a first clock control signal is generated. Based on the first comparison signal and the first clock control signal, a second clock control signal is generated. The second clock control signal can control the boost state of the charge pump unit, thereby reducing the peak current output from the power supply terminal.

[0041] To enable those skilled in the art to better understand, implement and realize the embodiments of the present invention, the following detailed description is provided with reference to the accompanying drawings and specific embodiments.

[0042] Reference Figure 4 The diagram shown is a structural schematic of a charge pump circuit in an embodiment of the present invention. In this embodiment, the charge pump circuit 40 is powered by the power supply terminal VDD. The charge pump circuit 40 may include a charge pump unit 41, a comparator unit 42, a boost control unit 43, and a signal feedback unit 44, wherein:

[0043] The charge pump unit 41 is coupled to the power supply terminal VDD and is adapted to generate an output voltage signal V based on the voltage of the power supply terminal VDD. pump Until the output voltage signal V pump The voltage value reaches the target voltage, wherein the output voltage signal V pump Includes DC voltage signal and ripple voltage signal;

[0044] The comparison unit 42 is coupled to the charge pump unit 41 and the signal feedback unit 44, and is adapted to be based on the output voltage signal V of the charge pump unit 41. pump The comparison result between the voltage value of the DC voltage signal and the preset first threshold voltage VREF generates a first comparison signal STOP_CLK, and outputs the first comparison signal STOP_CLK to the signal feedback unit 44.

[0045] The boost control unit 43 is coupled to the charge pump unit 41 and the signal feedback unit 44, and is adapted to output a voltage signal V from the charge pump unit 41. pump The voltage value of the ripple voltage signal and the preset clock signal CLK are used to generate a first clock control signal CLK_RAMP, and the first clock control signal CLK_RAMP is output to the signal feedback unit 44.

[0046] The signal feedback unit 44 is coupled to the comparison unit 42, the boost control unit 43 and the charge pump unit 41, and is adapted to generate a second clock control signal PUMP_CLK based on the first comparison signal STOP_CLK and the first clock control signal CLK_RAMP, and output the second clock control signal PUMP_CLK to the charge pump unit 41 to control the boost state of the charge pump unit 41.

[0047] The following combination Figure 4 The working principle of the above charge pump circuit is explained in detail:

[0048] In a specific implementation, due to the output voltage signal V generated by the charge pump unit 41 pump The voltage value in the signal is much greater than the maximum voltage that the comparator unit 42 can withstand. Directly coupling the output terminal of the charge pump unit 41 to the comparator unit 42 would burn out the comparator unit 42. Therefore, a voltage divider unit 45 can be coupled between the charge pump unit 41 and the comparator unit 42. The voltage divider unit 45 is adapted to divide the DC voltage signal in the output voltage signal of the charge pump unit 41, and outputs the divided voltage signal V through the voltage divider terminal of the voltage divider unit 45. pump _DIV to the comparison unit 42.

[0049] The charge pump circuit 40 works as follows: when the charge pump circuit 40 is started, the charge pump circuit 40 is powered by the power supply terminal VDD, and since the input terminal of the charge pump unit 41 is coupled to the power supply terminal VDD, an output voltage signal V pump is generated based on the voltage of the power supply terminal VDD, until the voltage of the output voltage signal V pump reaches a target voltage, wherein the output voltage signal V pump may include a direct current voltage signal and a ripple voltage signal.

[0050] In one aspect, the voltage value of the direct current voltage signal in the output voltage signal V pump is divided by the voltage dividing unit 45, and the obtained divided voltage signal V pump _DIV is output to the comparison unit 42, and the comparison unit 42 generates a first comparison signal STOP_CLK based on the comparison result of the voltage value in the divided voltage signal V pump _DIV and a preset first threshold voltage VREF, and outputs the first comparison signal STOP_CLK to the signal feedback unit 44.

[0051] On the other hand, the voltage value of the ripple voltage signal in the output voltage signal V pump generated by the charge pump unit 41 is based on the preset clock signal CLK, and the boost control unit 43 generates a first clock control signal CLK_RAMP, and outputs the first clock control signal CLK_RAMP to the signal feedback unit 44.

[0052] The signal feedback unit 44 can generate a second clock control signal PUMP_CLK based on the first comparison signal STOP_CLK and the first clock control signal CLK_RAMP, and output the second clock control signal PUMP_CLK to the charge pump unit 41 to control the boost state of the charge pump unit 41, until the voltage value of the output voltage signal V pump output by the charge pump unit 41 reaches the target voltage.

[0053] By using the above charge pump circuit 40, the boost speed of the output voltage of the charge pump unit 41 can be slowed down by adjusting the flip frequency of the second clock control signal PUMP_CLK, so that the peak current output by the power supply terminal can be reduced.

[0054] In order for those skilled in the art to better understand and implement the embodiments of the present application, the following will exemplarily illustrate the implementation manner of each specific module in combination with a specific application circuit.

[0055] Reference is made to Figure 5The schematic diagram shown in this embodiment of the invention illustrates a specific structure of a charge pump circuit. The charge pump circuit 50 is powered by the power supply terminal VDD, and the charge pump circuit 50 is connected to... Figure 4 The charge pump circuit 40 shown has a similar structure and may include: a charge pump unit 51, a voltage divider unit 52, a comparator unit 53, a boost control unit 54, and a signal feedback unit 55.

[0056] In a specific implementation, the charge pump unit 51 can generate an output voltage signal V based on the power supply terminal VDD voltage. pump The output voltage signal V pump This includes DC voltage signals and ripple voltage signals.

[0057] As a specific example, the charge pump unit 51 can be a capacitor charge pump, which can use a capacitor to store electrical energy.

[0058] In a specific implementation, the voltage divider unit 52 can process the output voltage signal V generated by the charge pump unit 51. pump The voltage of the DC voltage signal is divided to obtain the divided voltage signal V. pump _DIV, and output to the comparison unit 53 through the voltage divider terminal.

[0059] As a specific example, the voltage divider unit 52 may include a first resistor R1 and a second resistor R2, wherein the first resistor R1 and the second resistor R2 are coupled between the output terminal of the charge pump unit 51 and ground, and the voltage divider signal V pump The voltage value of _DIV is equal to the output voltage signal V. pump The voltage value is multiplied by R2 / (R1+R2).

[0060] By coupling a voltage divider unit 52 between the charge pump circuit 51 and the comparator unit 53, the voltage output by the charge pump circuit 51 can be divided, thus enabling the comparator unit 53 to be a low-voltage device.

[0061] It should be noted that, depending on the application scenario, a first resistor R1 and a second resistor R2 with different ratios can be selected.

[0062] In a specific implementation, the comparison unit 53 can adjust the voltage based on the voltage divider signal V. pump The comparison result between the voltage value of _DIV and the preset first threshold voltage VREF generates a first comparison signal STOP_CLK, which is then output to the signal feedback unit 55.

[0063] As a specific example, the comparison unit 53 can be a comparator, a positive input end of which is coupled with a voltage dividing end of the voltage dividing unit 52, and adapted to input the voltage dividing voltage signal V pump _DIV, and a negative input end of which is adapted to input the first threshold voltage VREF.

[0064] In a specific implementation, the boost control unit 54 can include a coupling module 541, a discharging module 542, a first comparison module 543, and a signal latching module 544, wherein:

[0065] The coupling module 541 is adapted to couple a ripple voltage signal in the voltage signal generated by the charge pump unit 51 to an input end of the first comparison module 543, and generate a trigger voltage signal Vtrig;

[0066] The discharging module 542 is coupled between the coupling module 541 and the ground, and is adapted to discharge when a voltage value of the trigger voltage signal Vtrig is greater than a second threshold voltage preset by the first comparison module 543;

[0067] The first comparison module 543 is adapted to generate a second comparison signal STOP_b based on a comparison result of the voltage value of the trigger voltage signal Vtrig and the second threshold voltage preset by the first comparison module;

[0068] The signal latching module 544 is adapted to output the first clock control signal CLK_RAMP according to the second comparison signal STOP_b input by an enable end EN and the preset clock signal CLK input by an input end IN.

[0069] As a specific example, the coupling module 541 can include a coupling capacitor C_couple, a first end of the coupling capacitor C_couple being coupled with an output end of the charge pump unit 51.

[0070] The discharging module 542 can include a current mirror, a first end of the current mirror being coupled with a second end of the coupling module 541, and a second end of the current mirror being coupled with the ground.

[0071] The first comparison module 543 can include an inverter P1, an input end of the inverter P1 being coupled with the second end of the coupling module 541, and an output end of the inverter P1 being coupled with the signal latching module 544.

[0072] The signal latching module 544 can include a latch, an enable end EN of the latch being coupled with the output end of the inverter P1, an input end IN of the latch being adapted to input the preset clock signal CLK, and an output end OUT of the latch being coupled with the signal feedback unit 55.

[0073] In a specific implementation, the second clock control signal outputted by the signal feedback unit 55 is obtained by NOR operation of the first clock control signal CLK_RAMP and the first comparison signal STOP_CLK.

[0074] As a specific example, the signal feedback unit 55 can include a NOR gate, a first end of the NOR gate is coupled to the output end of the comparison unit 53, and a second end of the NOR gate is coupled to the output end OUT of the latch 544.

[0075] In a specific implementation, when the charge pump circuit 50 is started, the charge pump unit 51 is charged by the power supply end VDD, and the charge pump unit 51 can generate an output voltage signal V pump based on the voltage of the power supply end VDD. pump The output voltage signal V pump includes a direct current voltage signal and a ripple voltage signal.

[0076] In one aspect, the output voltage signal V pump includes a direct current voltage signal and a ripple voltage signal. pump The direct current voltage signal is divided by the first resistor R1 and the second resistor R2, and a divided voltage signal V pump _DIV is outputted to the non-inverting input end of the comparator. The comparator can generate the first comparison signal STOP_CLK according to the comparison result of the voltage value of the divided voltage signal V pump _DIV and the preset first threshold voltage VREF. When the voltage value of the divided voltage signal V pump _DIV is greater than the preset first threshold voltage VREF, the level of the first comparison signal STOP_CLK is high level 1, indicating that the voltage value of the voltage signal V pump outputted by the charge pump unit 51 reaches the target voltage. When the voltage value of the divided voltage signal V pump _DIV is less than the preset first threshold voltage VREF, the level of the first comparison signal STOP_CLK is low level 0, indicating that the voltage value of the voltage signal V pump outputted by the charge pump unit 51 does not reach the target voltage, and the voltage outputted by the charge pump unit 51 needs to continue to rise.

[0077] In another aspect, in order to slow down the flip frequency of the second clock signal PUMP_CLK in the process of rising the voltage outputted by the charge pump unit 51, the voltage signal V pumpThe ripple voltage signal in the output voltage signal VDD is coupled to the input end of the inverter P1, and generates a trigger voltage signal Vtrig. According to the voltage value of the trigger voltage signal Vtrig and the threshold voltage of the inverter P1, the flip frequency of the second clock signal PUMP CLK can be controlled, the voltage boost speed of the output voltage signal of the charge pump unit 51 is slowed down, and thus the peak current output by the power supply end VDD can be reduced.

[0078] Scenario one: the voltage value of the trigger voltage signal Vtrig is greater than the threshold voltage of the inverter P1.

[0079] When the voltage value of the trigger voltage signal Vtrig is greater than the threshold voltage of the inverter P1, it means that the voltage value of the ripple voltage signal in the output voltage signal VDD is too large, and accordingly, the flip frequency of the second clock signal PUMP CLK is too fast. At this time, the level of the second comparison signal STOP_b generated is low level 0. Since the second comparison signal STOP_b is output to the enable end EN of the latch, the enable end EN of the latch is low level 0, and the current state of the output end OUT of the latch is saved. At this time, the first clock control signal CLK_RAMP output by the output end OUT is high level 1. pump

[0080] When the voltage value of the output voltage signal VDD generated by the charge pump unit 51 is less than the target voltage, the level of the second comparison signal STOP_b output by the comparator is always low level 0. Since the first clock control signal CLK_RAMP is high level 1, the second clock control signal PUMP CLK generated by the NOR gate is low level 0, that is, the second clock control signal PUMP CLK does not flip, and the current output by the power supply end VDD is 0 mA. pump

[0081] When the voltage value of the trigger voltage signal Vtrig is greater than the threshold voltage of the inverter P1, the voltage value of the trigger voltage signal Vtrig can be discharged by the current mirror, so that the voltage value of the trigger voltage signal Vtrig gradually decreases. During the process of decreasing the voltage value of the trigger voltage signal Vtrig, since the voltage value of the trigger voltage signal Vtrig is still greater than the threshold voltage of the inverter P1, the level of the second comparison signal STOP_b is still low level 0, so that the second clock control signal PUMP CLK is low level 0, and the current output by the power supply end VDD is still 0 mA.

[0082] Scenario two: the voltage value of the trigger voltage signal Vtrig is less than the threshold voltage of the inverter P1.

[0083] ​​When the voltage value of the trigger voltage signal Vtrig is less than the threshold voltage of the inverter P1, it indicates that the flip-flop frequency of the second clock signal PUMP CLK does not exceed the preset frequency, and the level of the second comparison signal STOP_b generated is 1 (high level). Since the output end of the inverter P1 is coupled with the enable end EN of the phase-locked loop, the level of the enable end EN is high level 1, the latch is turned on, and the first clock control signal CLK_RAMP output from the output end OUT follows the preset clock signal CLK to flip.

[0084] When the voltage value of the output voltage signal V pump generated by the charge pump unit 51 is less than the target voltage, the level of the second comparison signal STOP_b output by the comparator is always low level 0, and the second clock control signal PUMP_CLK generated by the NOR gate from the first clock control signal CLK_RAMP and the first comparison signal STOP_b follows the first clock control signal CLK_RAMP to flip, and their states are opposite.

[0085] Specifically, when the first clock control signal CLK_RAMP is high level, the second clock control signal PUMP_CLK generated by the NOR gate is low level; when the first clock control signal CLK_RAMP is low level, the second clock control signal PUMP_CLK generated by the NOR gate is high level.

[0086] When the voltage value of the output voltage signal V pump of the charge pump 51 reaches the target voltage, the voltage value of the voltage division voltage signal V pump _DIV output by the voltage division unit 52 is the same as the preset first threshold voltage VREF, the level of the first comparison signal STOP_CLK output by the comparator is high level 1, and the second clock control signal PUMP_CLK output by the NOR gate from the first comparison signal STOP_CLK and the first clock control signal CLK_RAMP is always low level 0, regardless of the level of the first clock control signal CLK_RAMP output from the output end OUT of the latch, the second clock control signal PUMP_CLK no longer flips, and the power supply end VDD stops supplying power to the charge pump unit 51, and the output current i is 0 mA.

[0087] The level changes of each signal during the output voltage lifting process of the charge pump unit are described in detail below with reference to the accompanying drawings.

[0088] In combination with Figure 5 , reference is made to Figure 6The waveform diagram of the corresponding monitoring point of the charge pump circuit in the embodiment of the present invention shown is as follows: during the output voltage rise process, the charge pump circuit is a type of circuit. Figure 6 As shown, at time t1, the charge pump circuit 50 starts, and the charge pump unit 51 is charged by the voltage source terminal VDD. The output voltage signal V generated by the charge pump unit 51 is... pump The voltage value increases slowly. During this slow increase, the comparator generates a first comparison signal STOP_CLK. Figure 6 The voltage level (not shown in the image) is always low (0); at time t3, the output voltage signal V... pump When the voltage value reaches the target voltage, the level of the first comparison signal STOP_CLK generated by the comparator is high (1). Figure 6 (not shown in the image), and Figure 2 The V shown pump Compared to the waveform of the previous circuit, the voltage rise of the charge pump circuit in this embodiment of the invention is more gradual.

[0089] The output voltage signal V of the charge pump unit 51 pump During the slow increase of the voltage value, the output voltage signal V pump The ripple voltage signal is coupled to the input of the inverter P1 via the coupling capacitor C_couple, generating a trigger voltage signal Vtrig. During the initial charging period, because the voltage value of the trigger voltage signal Vtrig is greater than the threshold voltage of the inverter P1, the level of the second comparison signal STOP_b output by the inverter P1 is low (0). Figure 6 As shown, during the time period from t1 to t2, the level of the second comparison signal STOP_b is low (0).

[0090] Since the output of the inverter P1 is coupled to the enable terminal EN of the phase-locked loop (PLL), the latch stores the current state of its output terminal OUT. At this time, the level of the first clock control signal CLK_PUMP is high (1). Because the first clock control signal CLK_PUMP is high (1), the NOR gate outputs a second clock control signal PUMP_CLK based on the first comparison signal STOP_CLK and the first clock control signal CLK_PUMP, which is low (0). The second clock control signal PUMP_CLK does not toggle. At this time, the current output from the power supply terminal VDD is 0mA. Figure 6 As shown in the dashed box, the current i is 0 mA during the time period from t1 to t2.

[0091] Since the current mirror is coupled between the coupling capacitor C_couple and the ground, the voltage value of the trigger voltage signal Vtrig can be discharged by the current mirror, so that the voltage value of the trigger voltage signal Vtrig decreases, and during the voltage value decreasing, the voltage value of the trigger signal Vtrig is still greater than the threshold voltage of the inverter P1, and the level of the second clock control signal PUMP_CLK is still low level 0, that is, the second clock control signal PUMP_CLK does not flip, at this time, the current output by the power supply end VDD is still 0 mA.

[0092] When the voltage value of the trigger voltage signal Vtrig decreases to be lower than the threshold voltage of the inverter P1, the level of the second comparison signal STOP_b output by the inverter P1 is high level 1, the level of the phase-locked loop enable end EN is high level 1, the latch is turned on, the first clock control signal CLK_RAMP output by the output end OUT of the latch follows the preset clock signal CLK to flip, and the second clock control signal PUMP_CLK output by the NOR gate according to the second comparison signal STOP_b and the first clock control signal CLK_RAMP follows the first clock control signal CLK_RAMP to flip, and the signal states of the two signals are opposite.

[0093] When the charge pump unit 51 receives the second clock control signal PUMP_CLK with the level of high level 1, on the one hand, the power supply end VDD can output current, since the direction of the current inside the power supply end VDD is from the negative electrode to the positive electrode, as shown by the dashed box in Figure 6 , the waveform of the obtained current i is below the vertical axis, that is, the current i is negative; on the other hand, the charge pump unit 51 can output a ripple voltage signal, when the voltage value of the ripple voltage signal generated by the coupling capacitor is greater than the threshold of the inverter P1, the level of the second clock control signal PUMP_CLK becomes low level 0, and the current output by the power supply end VDD is 0 mA, until the voltage value of the ripple voltage signal is less than the threshold of the inverter P1, and the current output by the power supply end VDD is not 0 mA.

[0094] Therefore, as shown in Figure 6As shown in the waveform diagram, during the period from t2 to t3, the second clock control signal PUMP_CLK is intermittently flipped, that is, when the voltage value of the trigger voltage signal Vtrig is greater than the threshold voltage of the inverter P1, the second clock control signal PUMP_CLK is at low level 0, and the current i output by the power supply end is 0 mA; when the voltage value of the trigger voltage signal Vtrig is less than the threshold voltage of the inverter P1, the second clock control signal PUMP_CLK is flipped following the first clock control signal CLK_RAMP, at this time, the current i output by the power supply end is not 0 mA, therefore, during the process of increasing the voltage value of the voltage signal V pump output by the charge pump unit 51, the current value of the current i appears a phenomenon of 0 mA for a period of time, so as to reduce the peak current output by the power supply end.

[0095] It should be noted that, during the process of slowly increasing the voltage value of the voltage signal V pump output by the charge pump unit 51, since the frequency of the second clock control signal PUMP_CLK is consistent, as shown by the current i in Figure 6 , the current i generated by the charge pump unit 51 at the power supply end VDD is the same.

[0096] Since the charge pump circuit 50 of the embodiment of the present application adopts the boost control unit 54, the flip frequency of the second clock control signal PUMP_CLK can be controlled by the boost control unit 54, so that the second clock control signal PUMP_CLK can be indirectly flipped during the process of increasing the voltage output by the charge pump unit 51, and when the level of the second clock control signal PUMP_CLK is at low level 0, the current output by the power supply end VDD is 0, so as to reduce the current density and further reduce the peak current output by the power supply end VDD.

[0097] As can be known from the waveform diagrams of the currents i in Figure 2 and Figure 6 , the current density in Figure 6 is less than the current density in Figure 2 , therefore, the charge pump circuit in the embodiment of the present application can reduce the peak current output by the power supply end.

[0098] In combination with Figure 3 , and with reference to the comparison diagram of the peak current variation waveform of the power supply end in the prior art and the embodiment of the present application shown in Figure 7 , wherein the horizontal axis represents time t, the unit is μs (microsecond), and the vertical axis represents the peak current i, the unit is mA.

[0099] As can be known from the waveform diagrams of the currents i in Figure 7It can be seen that during the period when the output voltage of the charge pump circuit rises, the peak current 71 output per microsecond at the power supply terminal using the charge pump circuit in this embodiment of the invention is approximately 1.3mA, which is much smaller than the maximum value of the peak current 31 output per microsecond at the power supply terminal in the prior art, which is 2.2mA. Therefore, the peak current output at the power supply terminal can be reduced by using the charge pump circuit in this embodiment of the invention. Moreover, when the output voltage of the charge pump circuit reaches the target voltage, the peak current 31 and the peak current 71 are the same, that is, the current power consumption of the charge pump circuit in this embodiment of the invention is the same as that of the existing charge pump circuit.

[0100] In practice, the discharge current value of the current mirror can be adjusted according to actual needs to control the rate of decrease of the trigger voltage signal, thereby reducing the flip frequency of the second clock control signal, slowing down the rise speed of the output voltage of the charge pump unit, and further reducing the peak current value output by the power supply.

[0101] In this embodiment of the invention, the current mirror has multiple current mirror branches with different current values. Each current mirror branch has a switch to control its opening and closing. According to actual needs, different current mirror branches can be selected by controlling the switch, so different discharge current values ​​can be achieved. Therefore, different peak currents are output at the power supply terminal VDD.

[0102] Specifically, refer to Figure 8 The diagram shown is a comparison of the peak current variation waveforms at the power supply terminal under different discharge current conditions in the embodiments of the present invention. The horizontal axis represents time t, in μs (microseconds), and the vertical axis represents the peak current i, in mA.

[0103] Depend on Figure 8 It can be seen that the peak current 81 output per microsecond at the power supply terminal under the first discharge current value is much smaller than the peak current 82 output per microsecond at the power supply terminal under the second discharge current value, and the peak current 81 output per microsecond at the power supply terminal under the first discharge current value is less than 1mA. Among them, the first discharge current value is greater than the second discharge current value.

[0104] Therefore, by reducing the discharge current value of the current mirror, the peak current output from the power supply can be reduced during the period when the output voltage of the charge pump circuit rises.

[0105] It should be noted that, due to the reduction in the discharge current value, the rise rate of the output voltage of the charge pump unit is slowed down. Therefore, the voltage output by the charge pump circuit at the second discharge current value can reach the target voltage more quickly.

[0106] This invention also provides a non-volatile memory 90, which will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0107] ReferenceFigure 9 The non-volatile memory 90 shown can include a control logic unit 91, a high-voltage generating circuit 92 and a storage array 93, wherein:

[0108] The control logic unit 91 is adapted to control the enable state and discharge process of the high-voltage generating circuit 92.

[0109] The high-voltage generating circuit 92 is coupled with the control logic unit 91 and the storage array 93 respectively, and is adapted to provide the voltage for erasing, reading or / and writing of the storage array 93 based on the control of the control logic unit 91, wherein the high-voltage generating circuit 92 can include a charge pump circuit 921, which can be the charge pump circuit as described in any of the foregoing embodiments, and the working principle and structure thereof are referred to the foregoing description, which will not be repeated here.

[0110] The storage array 93 includes a plurality of flash memory units, and is adapted to store information.

[0111] In a specific implementation, when the voltage output by the charge pump circuit 921 reaches the voltage for erasing, reading or / and writing of the storage array 93, the enable state and discharge process of the high-voltage generating circuit 92 can be controlled by the control logic unit 91, and the high-voltage generating circuit 92 selects different charge pump circuits according to the enable state to discharge the storage array 93 coupled therewith, and provides the voltage for erasing, reading or / and writing of each flash memory unit of the storage array 93, so as to realize the erasing, reading or / and writing operation of the information stored in the flash memory unit, wherein the discharge process can include discharge sequence, discharge time, etc.

[0112] Although the embodiments of the present application are disclosed as above, the present application is not limited to this. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A charge pump circuit, characterized by, include: The unit comprises a charge pump, a comparator, a boost control unit, and a signal feedback unit, wherein: The charge pump unit is coupled to a power supply terminal and is adapted to generate an output voltage signal based on the voltage of the power supply terminal until the voltage value of the output voltage signal reaches a target voltage. The output voltage signal includes a DC voltage signal and a ripple voltage signal. The comparison unit is coupled to the charge pump unit and the signal feedback unit, and is adapted to generate a first comparison signal based on the comparison result of the voltage value of the DC voltage signal in the output voltage signal of the charge pump unit and a preset first threshold voltage, and output the first comparison signal to the signal feedback unit. The boost control unit is coupled to the charge pump unit and the signal feedback unit, and is adapted to generate a first clock control signal based on the voltage value of the ripple voltage signal in the output voltage signal of the charge pump unit and a preset clock signal, and output the first clock control signal to the signal feedback unit. The signal feedback unit is coupled to the comparison unit, the boost control unit and the charge pump unit, and is adapted to generate a second clock control signal based on the first comparison signal and the first clock control signal, and output the second clock control signal to the charge pump unit to control the boost state of the charge pump unit.

2. The charge pump circuit of claim 1, wherein, The boost control unit includes: a coupling module, a discharge module, a first comparison module, and a signal latch module, wherein: The coupling module is adapted to couple the ripple voltage signal in the voltage signal generated by the charge pump unit to the input terminal of the first comparison module, and generate a trigger voltage signal. The discharge module is coupled between the coupling module and ground, and is adapted to discharge when the voltage value of the trigger voltage signal is greater than the second threshold voltage preset by the first comparison module; The first comparison module is adapted to generate a second comparison signal based on the comparison result between the voltage value of the trigger voltage signal and a second threshold voltage preset by the first comparison module; The signal latching module is adapted to output the first clock control signal based on the second comparison signal input at the enable terminal and the preset clock signal input at the input terminal.

3. The charge pump circuit of claim 2, wherein, The coupling module includes a coupling capacitor, the first end of which is coupled to the output terminal of the charge pump circuit.

4. The charge pump circuit of claim 2, wherein, The first comparison module includes an inverter, the input of which is coupled to the second end of the coupling module, and its output is coupled to the signal latching module.

5. The charge pump circuit of claim 2, wherein, The discharge module includes a current mirror, the first end of which is coupled to the second end of the coupling module, and the second end is coupled to ground.

6. The charge pump circuit of claim 2, wherein, The signal latch module includes: a latch, whose enable terminal is coupled to the output terminal of the first comparison module; its input terminal is adapted to input the preset clock signal; and its output terminal is coupled to the signal feedback unit.

7. The charge pump circuit according to claim 1, characterized in that, The second clock control signal is obtained by performing a OR NOT operation between the first clock control signal and the first comparison signal.

8. The charge pump circuit according to claim 7, characterized in that, The signal feedback unit includes a NOR gate.

9. The charge pump circuit according to any one of claims 1 to 8, characterized in that, Also includes: A voltage divider unit, coupled between the charge pump unit and the comparator unit, is adapted to divide the DC voltage signal in the output voltage signal of the charge pump unit and output the divided voltage through the voltage divider terminal of the voltage divider unit.

10. A non-volatile memory, characterized in that, include: The control logic unit, high-voltage generation circuit, and memory array include: The control logic unit is adapted to control the enable state and discharge process of the high voltage generation circuit. The high-voltage generation circuit is coupled to the control logic unit and the memory array respectively, and is adapted to provide the erase, read and / or write voltage to the memory array based on the control of the control logic unit, and includes the charge pump circuit according to any one of claims 1 to 9; A storage array, comprising multiple flash memory cells, is suitable for storing information.

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