Secure self-clearing memory partition

Abstract

This application is directed to secure self-cleaning memory partitions. Systems, techniques, and devices are described herein in which data stored in a portion of a secure partition of memory can be removed from the secure partition. In some examples, a portion of a secure partition can be allocated as self-cleaning memory such that data stored therein can be selectively removed in response to a logical address associated with the data being overwritten. In some cases, the data can be removed by programming the memory cells associated with the data to a particular voltage distribution. In some cases, the secure partition can include separate portions having different sets of operating parameters for access operations.

Description

[0001] Cross-referencing

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 240,940, filed April 26, 2021, entitled "Secure Self-Purging Memory Partitions," which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to secure self-cleaning memory partitions. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any one of those two possible states. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically updated by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even in the absence of an external power supply. Summary of the Invention

[0006] A method is described. The method may include: configuring a first set of operating parameters for access operations on a first portion of a secure partition of a memory device, the secure partition being configured to store data for an authentication system; configuring a second set of operating parameters for access operations on a second portion of the secure partition, the second set of operating parameters being different from the first set of operating parameters used for the first portion of the secure partition; writing data to the second portion of the secure partition using the second set of operating parameters; and overwriting the data stored in the second portion of the secure partition, at least in part, based on the data written using the second set of operating parameters.

[0007] A device is described. The device may include a memory device having a secure partition configured to store information for an authentication system, wherein the secure partition includes: a first portion configured to store a first set of operating parameters for access operations; and a second portion configured to store a second set of operating parameters for access operations. The device may also include a controller associated with the memory device, wherein the controller is configured to cause the device to: write data to the second portion of the secure partition of the memory device using the second set of operating parameters; and overwrite the data stored in the second portion of the secure partition of the memory device, at least in part, based on the data written using the second set of operating parameters.

[0008] A non-transitory computer-readable medium storing code is described. The code may include instructions executable by a processor to: configure a first set of operating parameters for access operations on a first portion of a secure partition of a memory device, the secure partition being configured to store data for an authentication system; configure a second set of operating parameters for access operations on a second portion of the secure partition, the second set of operating parameters being different from the first set of operating parameters for the first portion of the secure partition; write data to the second portion of the secure partition using the second set of operating parameters; and overwrite the data stored in the second portion of the secure partition, at least in part, based on the data written using the second set of operating parameters. Attached Figure Description

[0009] Figure 1 This document describes examples of systems that support secure self-cleaning memory partitions, based on the examples disclosed herein.

[0010] Figure 2 This document describes examples of memory devices that support secure self-cleaning memory partitions, based on the examples disclosed herein.

[0011] Figure 3 ,4A Figures 4B and 4C show the instance distribution graphs of the examples that support secure self-clearing memory partitions according to the examples disclosed herein.

[0012] Figure 5 A block diagram of a memory system supporting secure self-cleaning memory partitions, based on the examples disclosed herein, is shown.

[0013] Figure 6 The flowchart illustrates one or more methods supporting secure self-cleaning memory partitions, based on examples disclosed herein. Detailed Implementation

[0014] A memory system may include one or more portions configured to securely store data (e.g., more securely than other portions of the memory system configured to store data). For example, a memory system may include a replay-protected memory block (RPMB) configured to securely store data. Data written to and read from the RPMB may be authenticated (using HMAC signatures and a secret shared key) to prevent tampering. Some systems may store encryption keys for secure communication or other purposes within the RPMB block. In some instances, when those keys or other secure data stored within the RPMB are no longer valid, they may need to be physically erased, for example, to prevent the information from being used to attack a secure system. In other instances, encryption keys or secure data may be stored in another portion of the memory device that does not have specific security features (e.g., in normal logic cells).

[0015] Many security applications require the removal of encryption keys from physical memory after key use (e.g., RPMB). For block memory devices, logical addresses are often used to identify memory portions and their contents. In such systems, encryption keys can be associated with logical addresses that store the keys in a physical location within memory. To remove an encryption key, the logical address associated with the key can be overwritten. However, in some instances, overwriting the logical address can cause it to become associated with a different physical location in memory, without removing data from the initial physical location. Therefore, in these systems, the original encryption key cannot be removed from the initial physical memory until a physical removal (e.g., a wipe operation) is performed. Performing a wipe operation on a memory system can be inefficient, time-consuming, and increases wear and tear on memory cells, making it difficult to perform wipe operations frequently, even if possible, and thus increasing the exposure of deleted secure content.

[0016] Systems, apparatuses, and techniques for use with memory, wherein keys and other data can be selectively or automatically removed from their location in physical memory after use. Systems, apparatuses, and techniques described herein include data stored in a portion of physical memory that can be removed from a secure partition of the memory (e.g., from an RPMB). In some instances, a portion of the secure partition of the memory may be allocated as a self-clearing memory, such that data stored therein can be selectively removed in response to the logical address associated with said data being overwritten. In some cases, data can be removed by programming some or all of the memory cells associated with the data to the same voltage distribution. In some cases, the secure partition may contain separate sections having different sets of operating parameters for access operations. In some cases, the secure partition may be an instance of an RPMB.

[0017] First, as referenced Figure 1 and 2 Features of this disclosure are described in the context of the systems and apparatus described herein. Further details are provided in reference to [reference needed]. Figures 3 to 4C The features of this disclosure are described in the context of the distribution curves described herein. Further details are provided by reference to, for example... Figures 5 to 6 The device diagrams and flowcharts describing the secure self-cleaning memory partition are used to illustrate and refer to these and other features of this disclosure.

[0018] Figure 1 This document describes an example of a system 100 that supports secure self-cleaning memory partitions, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0020] System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or any other computing device containing memory and processing means.

[0021] System 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a control component configured to cause the host system 105 to perform various operations according to the examples disclosed herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed via the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although in Figure 1 The image shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0022] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0023] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0024] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute these commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 can convert responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may serve as a cache memory for the memory system controller 115. For example, data may be stored in local memory 120 when read from or written to memory device 130, and said data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0028] although Figure 1 The example of memory system 110 described herein includes memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135 that can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, as Figure 1 As described, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as single-level cells (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0033] In some cases, plane 165 may refer to a group of blocks 170 (e.g., blocks 170-a, 170-b, 170-c, and 170-d), and in some cases, concurrent operations may occur within different planes 165. For example, concurrent operations can be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175, which have the same page address within their respective planes 165 (e.g., regarding command decoding, page address decoding circuitry, and other circuitry shared across planes 165).

[0034] In some cases, block 170 may contain memory cells organized in rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells cannot be rewritten with new data until they have been erased. Therefore, for example, in some cases, the used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0036] In some cases, to update some data within block 170 while retaining other data within block 170, memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise represent data held in the old block 170 as invalid or obsolete, and may update the logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 instead of the old invalid block 170. In some cases, for example due to latency or wear considerations, this copying and remapping may be performed instead of erasing and rewriting the entire old block 170. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or plane 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0037] In some cases, the memory system controller 115 or the local controller 135 may perform operations for the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, clearing, garbage collection, scrubbing, block scanning, health monitoring, or others, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data in order to erase and reuse block 170, an algorithm called "garbage collection" may be invoked to allow block 170 to be erased and freed up as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting block 170 containing both valid and invalid data, selecting pages 175 in the block containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, allowing more blocks 170 to be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0038] System 100 may contain any number of non-transitory computer-readable media that support secure self-cleaning memory partitions. For example, host system 105, memory system controller 115, or memory device 130 may contain or otherwise access one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions described herein that pertain to host system 105, memory system controller 115, or memory device 130. For example, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), such instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0039] In some instances, it may be necessary to erase data stored in a secure partition of the memory system (e.g., removing data from the RPMB). To access the data, the logical block address currently associated with the physical location can be used. To erase the original data, a demapping command can be transmitted from the host system 105 to the memory system to indicate that the data stored at the associated logical block address is invalid. This can signal that new data may be stored there, but it does not cause the original data to be erased from the original physical location; it may involve whether some type of data, such as sensitive personal information or security data (e.g., encryption keys), is used. To erase the original data from the original physical location, one of the operations described above can be performed on the secure partition of the memory (e.g., garbage collection, scrubbing). This can be inefficient and time-consuming. It may also increase wear and tear on the memory cells.

[0040] In some cases, a limited number of logical addresses can be allocated to a security partition (e.g., an RPMB) to store security information in a way that is erasable under certain conditions. Writing to these logical block addresses causes the data associated with the write command to be stored in the private section. Reading from these logical addresses causes data to be retrieved from the private section. In some cases, data can be removed from the private section using commands.

[0041] Figure 2 This describes an example of a memory device 200 that supports a secure self-cleaning memory partition, based on the examples disclosed herein. The memory device 200 may be an example of memory device 130. The memory device 200 may include a memory controller 202 capable of operating on one or more memory cells 205 of the memory device 200. The memory controller 202 may be a reference... Figure 1 An example of the local controller 135 is discussed.

[0042] Memory cell 205 may be, for example, flash or other types of NAND memory cells. Each memory cell 205 may include a transistor having a charge trapping structure (e.g., a floating gate, a replacement gate, or a dielectric material) for storing the amount of charge representing a logic value. For example, Figure 2 The enlarged view illustrates a NAND memory cell 205, which includes a transistor 210 (e.g., a metal-oxide-semiconductor (MOS) transistor) for storing logic values. The transistor 210 may have a control gate 215 and may also include a charge trapping structure 220 (e.g., a floating gate or a replacement gate). The charge trapping structure 220 may be sandwiched between two portions of a dielectric material 225. The transistor 210 may include a first node 230 (e.g., a source or drain) and a second node 235 (e.g., a drain or source).

[0043] A logic value can be stored in a transistor 210 by placing (e.g., writing, storing) a certain number of electrons (e.g., a certain amount of charge) on a charge trapping structure 220. The amount of charge to be stored on the charge trapping structure 220 may depend on the logic value to be stored. The charge stored on the charge trapping structure 220 may affect the threshold voltage of the transistor 210, and thus affect the amount of current that can flow through the transistor 210 after it is activated (e.g., after a voltage is applied to the control gate 215).

[0044] Data can be stored in the form of the threshold voltage of transistor 210 (i.e., the voltage at which transistor 210 is turned on). Therefore, SLC memory cell 205 can be written to by applying one of two voltages (e.g., a voltage above or below the threshold) to memory cell 205 to store or not store charge on charge trap structure 220, and thus causing memory cell 205 to store one of two possible logic values.

[0045] Storing charge on charge trapping structure 220 can be referred to as programming memory cell 205 and can occur as part of a programming operation. A programmed memory cell can be considered as storing logic 0 in some cases. Removing charge from charge trapping structure 220 can be referred to as erasing memory cell 205 and can occur as part of an erasure operation. An erased memory cell can be considered as storing logic 1 in some cases. The logic value stored in transistor 210 can be sensed (e.g., as part of a read operation) by applying a voltage to control gate 215 (e.g., via word line 260 to control node 240) to activate transistor 210 and measuring (e.g., detecting, sensing) the amount of current flowing through first node 230 or second node 235 (e.g., via digital line 265). For example, the sensing component can determine whether SLC memory cell 205 stores logic 0 or logic 1 in binary form (e.g., based on the presence or absence of current through memory cell 205 in response to a read voltage applied to control gate 215, or based on whether the current is above or below a threshold current).

[0046] Memory device 200 may include memory array 204, which includes a plurality of memory cells (e.g., memory cell 205). Memory array 204 may include one or more partitions. For example, the memory array may include a first partition 270 and a second partition 275. A limited number of logical addresses may be associated with the first partition 270, such that the logical addresses can use the first partition 270 to read and write data. Writing to these logical addresses causes the data associated with the write command to be physically stored in the first partition 270. Reading from a logical address causes data to be retrieved from the first partition 270. In some cases, data may be automatically removed from the first partition 270 after it has been read. In some cases, data may be automatically removed in response to a logical address being overwritten (i.e., the logical address becomes associated with a different physical location in the first partition).

[0047] The first partition 270 may be a secure partition 270 configured to store data for an authenticated system, and the second partition 275 may be an insecure partition 275. In some instances, the first partition 270 may be an instance of an RPMB. Partitions may be separate entities or portions of the same memory. Each partition may contain memory cells (e.g., memory cells 205) in one or more areas (e.g., one or more blocks 170, pages 175, or other areas of memory cells of memory device 200), each configured to store data. In some cases, a partition (e.g., a secure or enhanced partition 270) may be configured to store data more securely and reliably than one or more insecure partitions (e.g., insecure partition 275) at memory device 200. For example, block 170 associated with secure partition 270 may contain SLC, which may be generally more reliable than other types of memory cells.

[0048] In some cases, secure partition 270 (e.g., RPMB) or one or more of its portions (e.g., first portion 280 or second portion 285) may perform authentication before storing or accessing information. For example, a memory system may use one or more keys (e.g., RPMB authentication keys) to access data stored at secure partition 270. In some cases, secure partition 270 or one or more of its portions may not be accessible using standard command protocols, but rather using a unique command protocol (e.g., the RPMB protocol) that enhances the security of secure partition 270 or one or more of its portions. Secure partition 270 or one or more of its portions may provide authenticated and replay-protected access to sensitive information stored thereon. In some instances, protocols associated with secure partition 270 or one or more of its portions (e.g., keys used to write to and read from the secure partition) may mitigate the risk associated with replay attacks compared to standard memory (e.g., insecure partition 275).

[0049] In some cases, secure partition 270 or one or more portions thereof may be configured to store data such as encryption keys. For example, secure partition 270 or one or more portions thereof may store encryption keys associated with other data stored in memory system 110 or used by host system 105 for other purposes (e.g., secure communication with other systems). For example, blocks of secure partition 270 (e.g., RPMBs) may store encryption keys used to encrypt and decrypt data stored on another block of memory device 200. In some cases, encryption keys may be derived from hardware-unique keys (e.g., associated with memory system 110). Additionally, data may be associated with applications that use encrypted data; users of these applications may have user credentials, and encryption keys may be associated with those user credentials.

[0050] Security partition 270 may comprise one or more portions, each configurable with a different set of operating parameters. For example, security partition 270 may comprise a first portion 280 having a first set of operating parameters for access operations and a second portion 285 having a second set of operating parameters for access operations different from the first set. The first portion 280 may be an instance of a portion that stores and accesses information using the RPMB protocol. The second portion 285 may store security information using a different protocol in a manner that allows some of the information to be erased. The set of operating parameters may be contained in fine-tuning parameters stored for each portion. In some cases, security partition 270 or a portion thereof (e.g., the first portion 280 or the second portion 285) may be an instance or an RPMB or may comprise one or more RPMBs.

[0051] In some cases, secure partition 270 or one or more of its portions may use symmetric key authentication, where the host and device use the same authentication key (e.g., a shared secret key). In some cases, secure partition 270 or one or more of its portions may use a counter (e.g., an RPMB counter) as part of the authentication. The counter may be associated with the secure partition and configured to reduce the likelihood of a successful replay attack on data stored in the secure partition. In some cases, the counter may be incremented after each write message to secure partition 270 or one or more of its portions, and the new value of the counter may be included in the calculation of the next authentication code to be used.

[0052] In some cases, data stored in at least one of the portions (e.g., partial security partitions) 270 may be removed from security partition 270. This may be particularly useful for certain types of data, such as sensitive data (e.g., personal information) or security data (e.g., encryption keys). In some cases, data removal may be triggered by overwriting the logical block address associated with the physical location where the data is stored. To perform the overwrite, a write command may be transmitted from host system 105 to the associated logical block address (e.g., via memory system controller 115) to write new data thereto. This may trigger the removal of the original data from the original physical location in security partition 270 in the manner discussed herein. This may also cause the logical block address to become associated with a different physical location in security partition 270 and where new data may be physically stored.

[0053] Figure 3 This document illustrates an example of a distribution graph 300 supporting a secure self-cleaning memory partition, based on the examples disclosed herein. Distribution graph 300 illustrates an example distribution of an SLC as disclosed herein. In some cases, based on the examples herein, distribution graph 300 may be associated with a first portion of the memory (e.g., a first portion 280 of secure partition 270).

[0054] To reflect the stored data bits, the state of a memory cell (e.g., charge) can be programmed to a corresponding voltage level. For example, to program a memory cell in a first portion of the memory to a logic 1 or 0 state, a charge pulse can be applied to the memory cell during a write operation, causing its threshold to shift from a first write voltage 307 (also known as the erase level) to a second write voltage 312 (also known as the programmable level).

[0055] Ideally, the threshold voltage of a memory cell would correspond to the write voltage. However, due to variations during programming and other disturbances after writing, the threshold voltage of cells programmed to the same state can span a voltage window distribution across those states. This results in a threshold voltage distribution of memory cells spanning a voltage range for each state. For example, for a first portion of the memory, a cell storing logic 1 could have a threshold voltage anywhere in the L0 voltage distribution 305, and a cell storing logic 0 could have a threshold voltage anywhere in the L1 voltage distribution 310. L0 and L1 can be referred to as the states of the cell.

[0056] During a read operation of a memory cell, the charge of the memory cell can be compared with a read reference voltage. For example, to determine the logic value stored by one or more memory cells in a portion of the memory, the memory device can apply a read reference voltage 315 to one or more memory cells to read the data page stored by said one or more memory cells. For memory cells with a threshold voltage higher than the reference voltage (e.g., to the right of read reference voltage 315), current can flow from the memory cell after read reference voltage 315 is applied to the memory cell, representing the logic value '0'. In contrast, for memory cells with a charge lower than the reference voltage (e.g., to the left of read reference voltage 315), current may not flow from the memory cell after read reference voltage 315 is applied to the memory cell, representing the logic value '1'. To ensure correct reading of memory cells, read reference voltage 315 can be between L0 distribution 305 and L1 distribution 310, such as... Figure 3 As shown in the diagram. In some cases, the system may have a read window budget equal to the voltage difference between L0 distribution 305 and L1 distribution 310.

[0057] The first write voltage 307 associated with the L0 state, the second write voltage 312 associated with the L1 state, the read reference voltage 315, or any combination thereof may be a first set of operating parameters for access operations of the first portion of the memory and may be stored as fine-tuning parameters.

[0058] Figures 4A-4CExamples of distribution graphs 400 (400-a, 400-b, 400-c) supporting secure self-erasing memory partitions according to the examples disclosed herein are illustrated. Distribution graph 400 illustrates the distribution of an instance of SLC as described herein. In some cases, according to the examples herein, distribution graph 400 may be associated with a second portion of the memory (e.g., the second portion 285 of secure partition 270). The second portion of the memory (e.g., the second portion 285 of secure partition 270) may differ from the first portion of the memory (e.g., the first portion 280 of secure partition 270). Different operating parameters for the second portion 285 of secure partition 270 may enable the erasure of data stored in the second portion 285 using a first set of conditions, while data stored in the first portion 280 of secure partition 270 may not be erasable below the first set of conditions.

[0059] Similar to distribution curve 300, Figure 4A The distribution curve 400-a may also include an L0 voltage distribution 405 based on a first write voltage 407 and an L1 voltage distribution 410 based on a second write voltage 412. However, relative to the distribution curve 300, the second write voltage 412 associated with the L1 state may be shifted to a higher voltage level, thereby causing the L1 voltage distribution 410 to also be higher. That is, the second write voltage 412 used to write the L1 logic state of a memory cell associated with a second portion of the memory may be different from (e.g., greater than) the second write voltage 312 used to write the L1 logic state of a memory cell associated with a first portion of the memory. To achieve a higher second write voltage 412, more and / or stronger charge pulses may be applied during the write operation.

[0060] Due to the larger second write voltage 412, the voltage distribution level of the memory cell used to store the L1 logic state associated with the second portion of the memory can be different from (e.g., higher than) the voltage distribution level of the memory cell used to store the L1 logic state associated with the first portion of the memory. The higher L1 voltage distribution 410 can result in a larger read window budget for the second portion 285 of the memory. Therefore, the read reference voltage 415 for the second portion of the memory can be shifted to a higher voltage level relative to the read reference voltage 315 of the first portion of the memory to allow for greater variation in the L0 voltage distribution. Thus, during a read operation of a memory cell associated with the second portion of the memory, the charge of the memory cell can be compared to a read reference voltage (e.g., read reference voltage 415) that is different from (e.g., higher than) the read reference voltage (e.g., read reference voltage 315) used to compare the charge of the memory cell associated with the first portion of the memory.

[0061] The first write voltage 407 (which may be equal to the first write voltage 307 in some cases), the second write voltage 412, the read reference voltage 415, or any combination thereof may be part of a set of second operating parameters for access operations of the second portion 285 of the memory and may be stored as fine-tuning parameters.

[0062] After data has been stored in one or more cells of the second part of the memory (e.g., the second part 285 of security partition 270), it may be necessary to remove the data from the cells. For example, it may be necessary to remove the authorization key from the second part 285 of security partition 270 after the key has been used. As discussed above, one way to remove data is by performing a wipe or other similar operation that removes the charge from the memory cell, thereby moving the L1 cell to the L0 distribution state. However, this has significant drawbacks because erasure can be performed at the block granular level, which can be inefficient or time-consuming. This may also increase wear on the affected memory cells.

[0063] In some cases, alternative methods of removing data from memory cells can be used. Removing data from memory can broadly mean changing the state of the corresponding memory cell to a point where it is impossible to determine what data was previously stored there. Erasing the memory cell is one way to do this. Alternatively, removing data from memory can be achieved by stabilizing the cell in the same state, making it extremely unlikely that the previous data was known. For example, it may be possible to remove data by stabilizing the cell in the L1 state. To do this, a charge can be added to a cell in the L0 state to move the L0 cell to the L1 state. Because the cell can subsequently be in the L1 state, any data previously stored in the cell may be unknown. This effectively removes the data from the cell. Figure 4B The example distribution curve 400-b illustrates the second part 285 of the safety partition 270 after the cell has been moved to the L1 voltage distribution 410'. Due to the programming changes in moving the L0 cell, the L1 voltage distribution 410' can cover a larger voltage range compared to the L1 voltage distribution 410 before the cell was moved to the L1 state.

[0064] In some cases, this alternative method of removing data can be performed selectively or automatically. For example, this method of removing data from the physical location of the second part 285 of security partition 270 can be triggered by overwriting the logical block address associated with said physical location. In another instance, it can be triggered by reading the logical block address associated with said physical location.

[0065] After data has been removed from a memory cell (e.g., the memory cell has been moved to L1 state), it may be necessary to reprogram (e.g., rewrite or overwrite) the cell with new data. This can be done by moving some cells from L1 voltage distribution 410' to L0 voltage distribution 405' for cells corresponding to logic 1 using a first write voltage 407. In some cases, the first write voltage 407 of the second portion of the memory may be the same as the first write voltage 307 of the first portion of the memory. Because cells corresponding to logic 0 may already be in L1 distribution 410', those cells do not need to be reprogrammed. Figure 4C The diagram 400-c illustrates the instance distribution curves of the second portion of the memory after the cells have been reprogrammed with new data. Due to the programming changes when some cells in the L1 state are moved to the L0 state, the L0 voltage distribution 405' can cover a larger voltage range than the L0 voltage distribution 405 before the cells were moved to the L1 state—large enough to potentially exceed the read reference voltage 315 of the first portion of the memory. However, because the read reference voltage 415 may be at a higher voltage than the read reference voltage 315, the L0 cells in the second portion of the memory can still be read using the read reference voltage 415. Using different operating parameters (e.g., a higher write voltage for the L1 state and the higher read reference voltage state), the cells in the second portion 285 of the secure partition can be erasable and reprogrammable, whereas if the operating parameters used for the first portion 280 were used, the data might be non-erasable or possibly non-reprogrammable.

[0066] Figure 5 A block diagram 500 illustrates a memory system 520 supporting a secure self-cleaning memory partition according to an example disclosed herein. The memory system 520 may be as described in the reference... Figure 1 Examples of aspects of the memory system described in sections 4. Memory system 520 or its various components may be examples of means for performing the various aspects of secure self-cleaning memory partitioning as described herein. For example, memory system 520 may include partition configuration component 525, memory writer 530, memory reader 535, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0067] Partition configuration component 525 may be configured or otherwise support means for configuring a first set of operating parameters for access operations on a first portion of a secure partition of a memory device, the secure partition being configured to store data for an authentication system. Partition configuration component 525 may be configured or otherwise support means for configuring a second set of operating parameters for access operations on a second portion of the secure partition, the second set of operating parameters being different from the first set of operating parameters for the first portion of the secure partition. Memory writer 530 may be configured or otherwise support means for writing data to a second portion of the secure partition using the second set of operating parameters. Memory writer 530 may be configured or otherwise support means for overwriting data stored in the second portion of the secure partition, at least in part, based on writing data using the second set of operating parameters.

[0068] In some instances, to support overwriting data, the memory writer 530 may be configured or otherwise supported to support components for writing second data to a second portion of the security partition such that each memory cell storing the data is stabilized at the same voltage distribution.

[0069] In some instances, the memory writer 530 may be configured or otherwise supported as a means for writing third data to a second portion of a secure partition at the location where the data is stored, at least in part based on overwrite data.

[0070] In some instances, the memory writer 530 may be configured or otherwise support means for writing second data to a first portion of a secure partition, wherein a first logic state is written to the first portion using a first write voltage.

[0071] In some instances, to support writing data to the second portion, the memory writer 530 may be configured or otherwise supported to support means for writing the first logical state to the second portion using a second write voltage different from the first write voltage. In some instances, to support writing second data to the first portion of the secure partition, the memory writer 530 may be configured or otherwise supported to support means for writing the second logical state to the first portion using a third write voltage. In some instances, to support writing data to the second portion, the memory writer 530 may be configured or otherwise supported to support means for writing the second logical state to the second portion using a third write voltage.

[0072] In some instances, the first voltage distribution of the memory cells storing the first logical state in the first part of the security partition may differ from the second voltage distribution of the memory cells storing the first logical state in the second part of the security partition. In some instances, the third voltage distribution of the memory cells storing the second logical state in the first part of the security partition may be the same as that of the memory cells storing the second logical state in the second part of the security partition.

[0073] In some instances, the memory reader 535 may be configured or otherwise supported to compare a first charge of a first memory cell in the first portion with a first read reference voltage for a first read operation as a first portion. In some instances, the memory reader 535 may be configured or otherwise supported to compare a second charge of a second memory cell in the second portion with a second read reference voltage different from the first read reference voltage for a second read operation as a second portion.

[0074] In some instances, a security partition may contain replay protected memory blocks.

[0075] In some instances, the first operating parameters of the first set of operating parameters for the first portion of the security partition may include a first read reference voltage. In some instances, the second operating parameters of the second set of operating parameters for the second portion of the security partition may include a second read reference voltage greater than the first read reference voltage.

[0076] In some instances, the first operating parameters of the first set of operating parameters for the first portion of the security partition may include a first write voltage for writing the first logical state to the memory cell. In some instances, the second operating parameters of the second set of operating parameters for the second portion of the security partition may include a second write voltage, different from the first write voltage, for writing the first logical state to the memory cell.

[0077] In some instances, a secure partition may contain replay-protected memory blocks. In some instances, a counter may be associated with the secure partition and configured to reduce the likelihood of a successful replay attack on data stored in the secure partition.

[0078] Figure 6 A flowchart illustrating a method 600 for supporting a secure self-cleaning memory partition, based on examples disclosed herein, is shown. The operation of method 600 can be implemented by a memory system or its components as described herein. For example, the operation of method 600 can be implemented by, as referenced... Figures 1 to 5The described memory system performs the function. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory system may use dedicated hardware to perform aspects of the described function.

[0079] At 605, the method may include configuring a first set of operating parameters for access operations on a first portion of a secure partition of a memory device, the secure partition being configured to store data for an authentication system. The operation of 605 can be performed according to examples disclosed herein. In some instances, aspects of the operation of 605 may be as described in references... Figure 5 The described partition configuration component 525 is executed.

[0080] In 610, the method may include configuring a second set of operation parameters for access operations for a second portion of the security partition, the second set of operation parameters being different from the first set of operation parameters for the first portion of the security partition. The operations of 610 can be performed according to the examples disclosed herein. In some instances, aspects of the operations of 610 may be as described in the references... Figure 5 The described partition configuration component 525 is executed.

[0081] In 615, the method may include writing data to a second portion of the secure partition using a second set of operation parameters. The operation of 615 can be performed according to examples disclosed herein. In some instances, aspects of the operation of 615 may be as described in the references... Figure 5 The memory writer 530 described is executed.

[0082] In 620, the method may include overwriting data stored in a second portion of the secure partition, at least in part, based on writing data using a second set of operation parameters. The operation of 620 can be performed according to examples disclosed herein. In some instances, aspects of the operation of 620 may be as described in the references... Figure 5 The memory writer 530 described is executed.

[0083] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: configuring a first set of operating parameters for access operations on a first portion of a secure partition of a memory device, the secure partition being configured to store data for an authentication system; configuring a second set of operating parameters for access operations on a second portion of the secure partition, the second set of operating parameters being different from the first set of operating parameters for the first portion of the secure partition; writing data to the second portion of the secure partition using the second set of operating parameters; and overwriting data stored in the second portion of the secure partition, at least in part, based on the data written using the second set of operating parameters.

[0084] In some instances of the method 600 and apparatus described herein, the overwrite data may include operations, features, circuitry, logic, components, or instructions for writing second data to a second portion of a secure partition such that each memory cell storing the data is stabilized at the same voltage distribution.

[0085] Some instances of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for writing third data to a second part of a secure partition at a location where the data is stored, based at least in part on overwriting the data.

[0086] Some examples of the method 600 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for writing second data to a first portion of a secure partition, wherein a first logic state may be written to the first portion using a first write voltage.

[0087] In some instances of the method 600 and device described herein, writing data to a second part may include operations, features, circuitry, logic, components, or instructions for writing a first logic state to the second part using a second write voltage different from the first write voltage.

[0088] In some instances of the method 600 and apparatus described herein, the first voltage distribution of the memory cells storing the first logical state in the first part of the security partition may differ from the second voltage distribution of the memory cells storing the first logical state in the second part of the security partition.

[0089] In some instances of the method 600 and device described herein, writing second data to a first portion of a secure partition may include operations, features, circuitry, logic, components, or instructions for writing a second logic state to the first portion using a third write voltage, and wherein writing data to a second portion includes writing the second logic state to the second portion using the third write voltage.

[0090] In some instances of the method 600 and device described herein, the third voltage distribution of the memory cell storing the second logic state in the first part of the security partition may be the same as that of the memory cell storing the second logic state in the second part of the security partition.

[0091] Some examples of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: a portion of a first read operation, as a first part, comparing a first charge of a first memory cell in the first part with a first read reference voltage; and a portion of a second read operation, as a second part, comparing a second charge of a second memory cell in the second part with a second read reference voltage different from the first read reference voltage.

[0092] In some instances of the method 600 and device described herein, the security partition includes replay of protected memory blocks.

[0093] In some instances of the method 600 and apparatus described herein, the method, apparatus, and non-transitory computer-readable medium may include further operations, features, circuitry, logic, components, or instructions for: wherein a second set of second operating parameters of a second portion of a security partition includes a second read reference voltage that may be greater than a first read reference voltage.

[0094] In some instances of the method 600 and apparatus described herein, the method, apparatus, and non-transitory computer-readable medium may include further operations, features, circuitry, logic, components, or instructions for: wherein a second set of second operating parameters of a second portion of a security partition includes a second write voltage for writing a first logic state to a memory cell and may be different from the first write voltage.

[0095] In some instances of the method 600 and device described herein, a counter may be associated with a secure partition and may be configured to reduce the likelihood of a successful replay attack on data stored in the secure partition.

[0096] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0097] A device is described. The device may include a memory device with a secure partition configured to store information for an authentication system. The secure partition may include a first portion configured to store a first set of operating parameters for access operations and a second portion configured to store a second set of operating parameters for access operations. The device may also include a controller associated with the memory device. The controller may be configured to cause the device to write data to the second portion of the secure partition of the memory device using the second set of operating parameters, and to overwrite data stored in the second portion of the secure partition of the memory device at least in part based on the data written using the second set of operating parameters.

[0098] In some cases, the controller may be further configured such that the device writes second data to a second portion of the secure partition of the memory device, thereby stabilizing each memory cell storing the data with the same voltage distribution.

[0099] In some cases, the controller may be further configured such that the device writes third data to a second part of the secure partition at the location where the data is stored, at least in part, based on overwriting the data.

[0100] In some cases, the controller may be further configured such that the device writes second data to a first portion of the secure partition, wherein, in order to write the second data to the first portion of the secure partition, the controller may be further configured such that the device uses a first write voltage to write a first logic state to the first portion, and wherein, in order to write data to a second portion of the secure partition, the controller may be further configured such that the device uses a second write voltage different from the first write voltage to write the first logic state to the second portion.

[0101] In some cases, the controller may be further configured such that the device: a portion of a first read operation, as a first part, compares a first charge of a first memory cell in the first part with a first read reference voltage; and a portion of a second read operation, as a second part, compares a second charge of a second memory cell in the second part with a second read reference voltage different from the first read reference voltage.

[0102] In some instances of the device, the first operating parameters of the first operating parameter set of the first part of the security partition include a first read reference voltage, and the second operating parameters of the second operating parameter set of the second part of the security partition include a second read reference voltage greater than the first read reference voltage.

[0103] In some instances of the device, the first operating parameters of the first operating parameter set of the first portion of the security partition include a first write voltage for writing a first logical state to a memory cell, and the second operating parameters of the second operating parameter set of the second portion of the security partition include a second write voltage for writing the first logical state to a memory cell, which is different from the first write voltage.

[0104] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof, can be used to represent data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a bus of signals, which may have various bit widths.

[0105] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0106] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If a component, such as a controller, couples other components together, then the component initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0107] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. If a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0108] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0109] Additionally, the terms "directly in response to" or "directly responding to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly responding to" such other condition or action.

[0110] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0111] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0112] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concept of the described instances.

[0113] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0114] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations.

[0115] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0116] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list followed by phrases such as "at least one of" or "one or more of"), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0117] Computer-readable media includes both non-transitory computer storage media and communication media that include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable ROM (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically. Combinations of these are also included within the scope of computer-readable media.

[0118] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: A first set of operating parameters for access operations is configured for a first portion of a secure partition of a memory device, the secure partition being configured to store data for an authentication system; Configure a second set of operation parameters for access operations for the second part of the security partition, the second set of operation parameters being different from the first set of operation parameters for the first part of the security partition; The data is written to the second part of the secure partition using the second set of operation parameters; as well as The data stored in the second part of the secure partition is overwritten at least in part based on writing the data using the second set of operating parameters.

2. The method of claim 1, wherein overwriting the data further comprises: The second data is written to the second portion of the secure partition such that each memory cell storing the data is stabilized at the same voltage distribution.

3. The method according to claim 1, further comprising: The third data is written to the second part of the secure partition at the location where the data is stored, at least in part based on overwriting the data.

4. The method of claim 1, further comprising: The second data is written to the first portion of the secure partition, wherein a first logic state is written to the first portion using a first write voltage, and Writing the data to the second part includes: The first logic state is written to the second part using a second write voltage different from the first write voltage.

5. The method of claim 4, wherein the first voltage distribution of the memory cell storing the first logical state in the first part of the security partition is different from the second voltage distribution of the memory cell storing the first logical state in the second part of the security partition.

6. The method of claim 4, wherein writing the second data to the first portion of the secure partition comprises: The second logic state is written to the first part using a third write voltage; and Writing the data to the second part includes: The second logic state is written to the second part using the third write voltage.

7. The method of claim 6, wherein the third voltage distribution of the memory cell storing the second logic state in the first part of the security partition is the same as that of the memory cell storing the second logic state in the second part of the security partition.

8. The method of claim 1, further comprising: As part of the first read operation of the first part, the first charge of the first memory cell in the first part is compared with the first read reference voltage; as well as As part of the second read operation of the second part, the second charge of the second memory cell in the second part is compared with a second read reference voltage that is different from the first read reference voltage.

9. The method of claim 1, wherein the security partition includes replaying the protected memory block.

10. The method of claim 1, wherein the first operating parameter of the first operating parameter set of the first portion of the security partition includes a first read reference voltage; and The second operating parameter of the second operating parameter set of the second part of the security partition includes a second read reference voltage that is greater than the first read reference voltage.

11. The method of claim 1, wherein the first operating parameter of the first operating parameter set of the first portion of the security partition includes a first write voltage for writing a first logic state to a memory cell; and The second operating parameters of the second operating parameter set of the second part of the security partition include a second write voltage, which is different from the first write voltage, for writing the first logical state to the memory cell.

12. The method of claim 1, wherein the counter is associated with the secure partition and configured to reduce the likelihood of a successful replay attack on the data stored in the secure partition.

13. An apparatus comprising: A memory device having a secure partition configured to store information for an authentication system, wherein the secure partition includes: The first part, configured to store a first set of operational parameters for access operations; and The second part is configured to store a second set of operational parameters for access operations; and The device further includes: a controller associated with the memory device, wherein the controller is configured to cause the device to: The data is written to the second portion of the secure partition of the memory device using the second set of operating parameters; and The data stored in the second portion of the secure partition of the memory device is overwritten, at least in part, based on writing the data using the second set of operating parameters.

14. The device of claim 13, wherein the controller is further configured such that the device: The second data is written to the second portion of the secure partition of the memory device such that each memory cell storing the data is stabilized at the same voltage distribution.

15. The device of claim 13, wherein the controller is further configured such that the device: The third data is written to the second part of the secure partition at the location where the data is stored, at least in part based on overwriting the data.

16. The device of claim 13, wherein the controller is further configured such that the device: The second data is written to the first portion of the secure partition, wherein, in order to write the second data to the first portion of the secure partition, the controller is further configured such that the device uses a first write voltage to write a first logic state to the first portion, and In order to write the data to the second part of the secure partition, the controller is further configured such that the device uses a second write voltage different from the first write voltage to write the first logic state to the second part.

17. The device of claim 13, wherein the controller is further configured such that the device: As part of the first read operation of the first part, the first charge of the first memory cell in the first part is compared with a first read reference voltage; and As part of the second read operation of the second part, the second charge of the second memory cell in the second part is compared with a second read reference voltage that is different from the first read reference voltage.

18. The device according to claim 13, wherein: The first operating parameter set of the first portion of the security partition includes a first read reference voltage; and The second operating parameter of the second operating parameter set of the second part of the security partition includes a second read reference voltage that is greater than the first read reference voltage.

19. The device according to claim 13, wherein: The first operating parameter set of the first portion of the security partition includes a first write voltage for writing a first logical state to a memory cell; and The second operating parameter set of the second part of the security partition includes a second write voltage, which is different from the first write voltage, for writing the first logic state to the memory cell.

20. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to: A first set of operating parameters for access operations is configured for a first portion of a secure partition of a memory device, the secure partition being configured to store data for an authentication system; Configure a second set of operation parameters for access operations for the second part of the security partition, the second set of operation parameters being different from the first set of operation parameters for the first part of the security partition; The data is written to the second part of the secure partition using the second set of operation parameters; as well as The data stored in the second part of the secure partition is overwritten at least in part based on writing the data using the second set of operating parameters.

21. The non-transitory computer-readable medium of claim 20, wherein the instructions are further executable by the processor to: The second data is written to the second portion of the secure partition of the memory device such that each memory cell storing the data is stabilized at the same voltage distribution.

22. The non-transitory computer-readable medium of claim 20, wherein the instructions are further executable by the processor to: The third data is written to the second part of the secure partition at the location where the data is stored, at least in part based on overwriting the data.

23. The non-transitory computer-readable medium of claim 20, wherein the instructions are further executable by the processor to: The second data is written to the first portion of the secure partition, wherein, in order to write the second data to the first portion of the secure partition, the instruction can further be executed by the processor to write a first logical state to the first portion using a first write voltage, and In order to write the data to the second part of the secure partition, the instruction can be further executed by the processor to write the first logical state to the second part using a second write voltage different from the first write voltage.

24. The non-transitory computer-readable medium of claim 23, wherein a first voltage distribution of the memory cell storing the first logical state in the first portion of the secure partition is different from a second voltage distribution of the memory cell storing the first logical state in the second portion of the secure partition.

25. The non-transitory computer-readable medium of claim 20, wherein the instructions are further executable by the processor to: As part of the first read operation of the first part, the first charge of the first memory cell in the first part is compared with a first read reference voltage; and As part of the second read operation of the second part, the second charge of the second memory cell in the second part is compared with a second read reference voltage that is different from the first read reference voltage.

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