Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application discloses a semiconductor device manufacturing method and a semiconductor device. The manufacturing method comprises the following steps: arranging a plurality of gate structures on a substrate; arranging a first dielectric layer on the substrate between two adjacent gate structures; arranging a protective layer on the upper surface of each gate structure, wherein the protective layer completely covers the upper surface of the gate structure and does not extend above the first dielectric layer; arranging a second dielectric layer on the first dielectric layer and the protective layer; performing an etching process in the first dielectric layer and the second dielectric layer between two adjacent gate structures to form a cavity with a first predetermined depth; and correspondingly arranging a contact component in the cavity. The application also relates to a semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0002] Existing methods for fabricating contact conductors 115 in semiconductor devices (such as...) Figures la-le As shown and Figures 2a-2b As shown), Figure la As shown, a semiconductor device 100 is provided, comprising: a substrate 101, a plurality of alternative gate structures 102 disposed on the substrate 101, an active structure 103, and an isolation region 104 (e.g., STI shallow trench isolation region 104) disposed in the substrate 101. The active structure 103 includes a source and a drain (not shown). A stop layer (contact etch stop layer 106, CESL) and a first dielectric layer 107 are sequentially disposed on the alternative gate structures 102, the active structure 103, and the substrate surface. Of course, sidewall spacers 105 are disposed on both sides of the alternative gate structure 102 between the alternative gate structure 102 and the contact etch stop layer 106. Specifically, the prior art fabrication method includes: a first step (e.g. Figure lb (As shown), the alternative gate structure 102 is exposed by grinding the contact etch stop layer 106 and the first dielectric layer 107, and the upper surfaces of the alternative gate structure 102, the contact etch stop layer 106, and the first dielectric layer 107 are kept at the same height. Then, a capping layer 109 is formed on the semiconductor device 100 with the upper surfaces at the same height; the second step (as shown) Figure lc As shown), a second dielectric layer 111 is disposed on the cover layer 109; the third step (as shown) Figure Id As shown), a photolithographic layer with a preset pattern (not shown) is deposited above the second dielectric layer 111, and etched according to the patterned photolithographic layer on the second dielectric layer 111, the capping layer 109, and / or the first dielectric layer 107, and / or the etch stop layer 106 to form a cavity 114. There are three possibilities for the partial area at the bottom of the cavity 114 to abut against the active structure: the first is that the partial area abuts against the gate structure; the second is that the partial area abuts against the gate structure; and the third is that the partial area abuts against the substrate. The reason it is a partial area is that a cavity 114 with a contact conductor 115 may partially abut against the gate structure and partially abut against the substrate. It is particularly important to note that the cavity 114 needs to be etched through the capping layer 109; the fourth step (as shown in the figure)... Figure le As shown), a contact conductor 115 is deposited and formed in the cavity 114. The contact conductor 115 includes: a spacer layer 117 abutting the surface of the cavity 114 and a contact 118 abutting the surface of the spacer layer 117. Figure le(Used in bold black).

[0003] In the existing fabrication method described above, the formation of the cavity 114 generally requires etching through the dielectric layer and the capping layer 109. Since the capping layer 109 is made of a different material than the first dielectric layer 107 and the second dielectric layer 111, under the same etching conditions (such as...), Figure le When etching the capping layer 109, the etching rates of the first dielectric layer 107 and the second dielectric layer 111 are different. This results in faster etching of the first dielectric layer 107 and the second dielectric layer 111, while the etching rate of the capping layer 109 is slower. This easily leads to a lack of consistent smoothness between the dielectric layer and the capping layer 109 in the cavity 114. Often, the capping layer 109 forms a protrusion that extends beyond the inner wall of the cavity 114 (see attached diagram). Figure le As shown, the inner wall of cavity 114 has a cover layer 109 extending out, which reduces the opening of cavity 114. This reduction in the opening of cavity 114 leads to two problems: first, when depositing the spacer layer 117 of the contact conductor 115, the bottom surface of the protruding portion of the cover layer 109 may lack the spacer layer 117, causing problems such as element diffusion and poor surface adhesion between the contact 118 and the cover layer 109 / first dielectric layer 107; second, the protrusion reduces the filling opening of the contact conductor 115, affecting its filling and covering ability and causing the problem of voids 119 after filling.

[0004] Alternatively, under the same etching conditions and ensuring that the inner wall surface of cavity 114 is smooth, i.e., when there are no protrusions extending from the inner wall surface of cavity 114 (such as...). Figures 2a-2b As shown, this can lead to difficulty in controlling the etching endpoint, resulting in over-etching of the active structure 103 and the shallow trench isolation region 104, thereby damaging the performance of the semiconductor device 100. Figure 2b As shown, a contact conductor 115 is provided in the cavity 114. Due to excessive etching of the active structure 103, problems such as the absence of the active structure 103 and the excessively close distance between the substrate and the contact conductor 115 result in poor isolation.

[0005] Therefore, a method is needed to solve the above problems. Summary of the Invention

[0006] The main objective of this application is to propose a method for fabricating a semiconductor device and a semiconductor device in order to optimize the structure of the semiconductor device so that, under the same etching conditions, the active structure and isolation region are not over-etched, and the inner wall surface of the cavity is smooth (i.e., the inner wall surface of the cavity has no protrusions).

[0007] To achieve the above objectives, this application proposes a method for fabricating a semiconductor device, the method comprising:

[0008] Multiple gate structures are disposed on a substrate;

[0009] a first dielectric layer is disposed on the substrate between two adjacent gate structures;

[0010] a protection layer is disposed on the upper surface of each gate structure, wherein the protection layer just completely covers the upper surface of each gate structure and does not extend above the first dielectric layer;

[0011] a second dielectric layer is disposed on the first dielectric layer and the protection layer;

[0012] an etching process is performed in the first dielectric layer and the second dielectric layer between two adjacent gate structures to form a cavity with a first predetermined depth;

[0013] a contact member is correspondingly disposed in the cavity.

[0014] In the embodiment, since the protection layer is disposed on the gate structure and there is no protection layer on the first dielectric layer, the first dielectric layer, the second dielectric layer and the protection layer do not have different etching rates. Therefore, under the same etching conditions, it is possible to control not to etch the active structure and the isolation region excessively and to make the inner sidewall surface of the cavity smooth (i.e., the inner sidewall surface of the cavity has no protrusions).

[0015] In an embodiment, the protection layer disposed on the upper surface of each gate structure comprises:

[0016] the first dielectric layer is extended by a first predetermined height based on self-aligned growth of the first dielectric layer, so that the extended two adjacent first dielectric layers and the gate structure between the two adjacent first dielectric layers form a first groove;

[0017] the first groove is filled to form the protection layer on the upper surface of the gate structure.

[0018] In the embodiment, the self-aligned growth / extension based on the first dielectric layer means that only other materials are formed above the first dielectric layer without reacting with the gate structure, and the first groove is formed by self-aligned growth, which can effectively avoid the size deviation problem caused by the mask method, so that only the protection layer is disposed on the gate structure, and under the same etching conditions, it is possible to control not to etch the active structure and the isolation region excessively and to make the inner sidewall surface of the cavity smooth (i.e., the inner sidewall surface of the cavity has no protrusions).

[0019] In an embodiment, the filling of the first groove to form the protection layer on the upper surface of the gate structure comprises:

[0020] the first groove is filled to form a cover layer on the upper surface of the entire device in which the first groove is formed.

[0021] planarizing the cap layer to expose the first dielectric layer and remaining cap layer forms the protective layer on the upper surface of the gate structure.

[0022] In one embodiment, the extending the first dielectric layer to a first predetermined height by self-aligned growth based on the first dielectric layer comprises:

[0023] performing a first treatment on the first dielectric layer to form a second recess of a second predetermined depth between two adjacent gate structures and the first dielectric layer therebetween;

[0024] filling the second recess to form a seed layer over the first dielectric layer after the first treatment, an upper surface of the seed layer is at the same level as an upper surface of the gate structure;

[0025] performing a second treatment on the seed layer by self-aligned growth to convert the seed layer into a preset layer, an upper surface of the preset layer is higher than the upper surface of the gate structure by the first predetermined height.

[0026] In this embodiment, the process of depositing the seed layer over the first dielectric layer is relatively easy, and the formed continuous seed layer material has a good removal selectivity ratio with the gate structure, i.e., the seed layer over the surface of the gate structure is easy to remove. In addition, the growth of the preset layer does not cause performance impact on the replacement gate structure, such as removing the material of the gate structure or forming a material film on the surface of the gate structure, and the formed preset layer material is a low-K material to reduce the RC delay between devices.

[0027] In one embodiment, the filling the second recess to form a seed layer over the first dielectric layer after the first treatment comprises:

[0028] filling the second recess to deposit a continuous seed layer precursor on the upper surface of the entire device with the second recess formed thereon;

[0029] planarizing the seed layer precursor to expose the gate structure and remaining seed layer precursor forms the seed layer in the second recess.

[0030] In one embodiment, the performing a first treatment on the first dielectric layer to form a second recess of a second predetermined depth comprises:

[0031] partially etching back a top portion of the first dielectric layer to form a second recess of a second predetermined depth.

[0032] In one embodiment, the performing a second treatment on the seed layer to convert the seed layer into a preset layer comprises:

[0033] The seed layer is processed by a thermal oxidation process to expand the volume of the seed layer to form the preset layer.

[0034] In an embodiment, the seed layer material is elemental silicon or silicide material.

[0035] In this embodiment, the silicide material is used because the seed layer is oxidized by the thermal oxidation process to expand the volume to form the preset layer.

[0036] In an embodiment, the thickness of the seed layer is

[0037] In this embodiment, the thickness of the seed layer is set to Because if the seed layer is too thick, too much silicon material cannot be converted into silicon oxide, resulting in silicon dielectric between adjacent gate structures, which is easy to cause the constant of the interlayer dielectric to be too high.

[0038] The application also provides a semiconductor device made by the manufacturing method described above. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiment or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to the structures shown in these drawings without creative labor.

[0040] Figures la-le A schematic diagram of a manufacturing method of a prior art semiconductor device is shown;

[0041] Figures 2a-2b A schematic diagram of a manufacturing method of a prior art semiconductor device is shown;

[0042] Figures 3a-3i A schematic diagram of a manufacturing method of a semiconductor device of the present application is shown.

[0043] Explanation of reference signs:

[0044] Reference Name Reference Name 100 Semiconductor device 101 Substrate 102 Replacement gate structure 103 Active structure 104 Isolation region 105 Sidewall spacer 106 Contact etch stop layer 107 First dielectric layer 108 First recess 109 Cap layer 110 Protection layer 111 Second dielectric layer 112 Second recess 113 Seed layer 114 Cavity 115 Contact member 116 Seed layer precursor 117 Spacer layer 118 Contact member 119 Pore H1 First predetermined height H2 Second predetermined depth

[0045] The purpose of the present application, functional characteristics and advantages will be further described with reference to the drawings. DETAILED DESCRIPTION

[0046] With reference to the drawings and the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0047] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly.

[0048] In addition, if the embodiments of the present application involve descriptions such as “first”, “second”, etc., the descriptions of “first”, “second”, etc. are only for description purposes, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by “first”, “second” can explicitly or implicitly include at least one of the features. In addition, the technical solutions of the various embodiments can be combined with each other, but it must be based on the fact that a person of ordinary skill in the art can realize it, and when the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist, and is also not within the scope of protection claimed by the present application.

[0049] Figures 3a-3i A schematic diagram of a method for manufacturing a semiconductor device 100 of the present application is shown;

[0050] Referring to Figure la It is shown that a semiconductor device 100 is provided, which includes a substrate 101, a plurality of replacement gate structures 102 disposed on the substrate 101, an active structure 103 including a source and a drain (not shown), and an isolation region 104 (for example, an STI shallow trench isolation region 104) disposed in the substrate 101, and a stop layer (a contact etch stop layer 106, CESL) and a first dielectric layer 107 disposed in sequence on the replacement gate structure 102, the active structure 103, and the substrate surface. Of course, a sidewall spacer 105 is disposed on both sides of the replacement gate structure 102 between the replacement gate structure 102 and the contact etch stop layer 106.

[0051] Referring to Figures 3a-3f It is shown that the method for manufacturing a semiconductor device 100 of the present application includes the following steps:

[0052] As Figures 3a-3dAs shown in 1a, a protective layer 110 is provided on the upper surface of each gate structure 102, wherein the protective layer 110 completely covers the upper surface of each gate structure 102 and does not extend above the first dielectric layer; a second dielectric layer 111 is provided on the first dielectric layer 107 and the protective layer 110; an etching process is performed between the first dielectric layer 107 and the second dielectric layer 111 between two adjacent gate structures 102 to form a cavity 114 of a first predetermined depth; a contact conductor 115 is correspondingly provided in the cavity 114.

[0053] In this embodiment, the gate structure can be an alternative gate structure 102, i.e., a metal gate that replaces the polysilicon gate. The semiconductor device may include sidewall spacers 105 forming the gate structure and a contact etch stop layer 106 abutting the sidewall spacers 105. The protective layer may also cover the sidewall spacers 105 and the contact etch stop layer 106. Since the protective layer 110 is only provided on the alternative gate structure 102, and there is no protective layer 110 on the first dielectric layer 107, there is no difference in the etching rates of the first dielectric layer 107, the second dielectric layer 111, and the protective layer 110. Therefore, under the same etching conditions, it is possible to control the active structure and isolation region from being over-etched, and to make the inner sidewall surface of the cavity 114 smooth (i.e., the inner sidewall surface of the cavity 114 has no protrusions).

[0054] In one embodiment, such as Figure 3e As shown, the first dielectric layer 107 is extended to a first predetermined height H1 by self-aligned growth based on the first dielectric layer 107, so that two adjacent extended first dielectric layers 107 and the alternative gate structure 102 between the two adjacent first dielectric layers 107 form a first groove 108; the first groove 108 is filled to form a protective layer 110 on the upper surface of the alternative gate structure 102. It should be noted that, in this document, self-aligned growth / extension means forming other materials only above the first dielectric layer 107 without reacting with the alternative gate structure 102. Forming the first groove 108 by self-aligned growth can effectively avoid the dimensional offset problem caused by using a mask method. Since the protective layer 110 is only provided on the replacement gate structure 102, the first dielectric layer 107, the second dielectric layer 111 and the protective layer 110 do not have different etching rates. This allows the active structure and isolation region to be controlled from being over-etched under the same etching conditions, while also making the inner wall surface of the cavity 114 smooth (i.e., the inner wall surface of the cavity 114 has no protrusions).

[0055] In one embodiment, such as Figure 3f As shown, the first groove 108 is filled to deposit a capping layer 109 on the entire upper surface of the device in which the first groove 108 is formed; as Figure 3aAs shown, the capping layer 109 is planarized to expose the first dielectric layer 107, and the remaining capping layer 109 forms a protective layer 110 on the upper surface of the alternative gate structure 102.

[0056] like Figure 3g As shown, extending the first dielectric layer 107 to a first predetermined height through self-aligned growth includes: partially etching back the first dielectric layer 107 to form a second groove 112 of a second predetermined depth H2; specifically, as... Figure 3h As shown, the second groove 112 is filled to deposit a continuous seed layer precursor 116 on the entire upper surface of the device in which the second groove 112 is formed; as Figure 3i As shown, the seed layer 113 precursor is planarized to expose the alternative gate structure 102, and the remaining seed layer 113 precursor forms the seed layer 113 in the second groove 112. The upper surface of the seed layer 113 is at the same level as the upper surface of the alternative gate structure 102. The seed layer 113 is subjected to a thermal oxidation process by self-aligned growth to cause the seed layer 113 to expand in volume and form a preset layer, wherein the upper surface of the preset layer is higher than the upper surface of the alternative gate structure 102 by a first predetermined height H1.

[0057] In this embodiment, the process of depositing the seed layer 113 above the first dielectric layer 107 is relatively easy. The resulting continuous seed layer material has a good removal selectivity with the gate structure, meaning that the seed layer 113 above the gate structure surface is easily removed. Furthermore, the growth of the preset layer does not affect the performance of the replacement gate structure; for example, it does not remove the gate structure material or form a material film on the gate structure surface. The resulting preset layer material is a low-k material to reduce RC delay between devices.

[0058] Additionally, it should be noted that the seed layer material in this paper is elemental silicon or a silicide material. The seed layer material 113 can be selected from at least one of any silicon-containing materials (e.g., amorphous silicon, SiCN, SiN, SiOCN, etc.), and is transformed into a predetermined layer through at least one of oxidation processes, epitaxy, doping, etc. Preferably, the seed layer material is elemental silicon, so that a silicon oxide material consistent with the dielectric layer can be formed through oxidation, and the K value of the silicon oxide material is more difficult to meet the requirements of semiconductor devices. Further, the seed layer material 113 is transformed into a predetermined layer by thermal oxidation (temperature not higher than 400°C), causing the seed layer 113 to oxidize and expand in volume. In one embodiment, the seed layer 113 is amorphous silicon, and the specific process of transforming the seed layer 113 into the predetermined layer of silicon oxide through thermal oxidation is as follows:

[0059] 1) An amorphous silicon seed layer 113 is deposited above the first dielectric layer 107 by electron beam evaporation;

[0060] 2) Convert the amorphous silicon seed layer 113 into a nanoporous silicon seed layer 113 by hydrogenation-assisted plasma;

[0061] 3) Convert the nanoporous silicon seed layer 113 into a preset layer of silicon oxide by a thermal oxidation process. For example, the seed layer of amorphous silicon material A-Si is converted into a preset layer of silicon oxide after being treated by the thermal oxidation process. At this time, the preset layer of silicon oxide has a larger volume than the seed layer 113 of amorphous silicon material A-Si, so that the first dielectric layer 107 provided with the preset layer is higher than the replacement gate structure 102, so as to form a first recess 108 between the two adjacent first dielectric layers 107.

[0062] Furthermore, by converting the seed layer into a nanoporous seed layer, the reaction area of the seed layer is expanded, so as to improve the oxidation conversion rate of the seed layer and avoid the problem that part of the material in the bottom of the seed layer cannot be converted.

[0063] The thickness of the seed layer 113 is set to be less than 100 nm. If the seed layer 113 is too thick, too much silicon material cannot be converted into silicon oxide, so that there is silicon dielectric between adjacent gate structures, which is easy to cause the dielectric constant between layers to be too high. The device temperature in the thermal oxidation process is not higher than 400°C, so as to reduce the influence of temperature on the gate structure as much as possible.

[0064] The inner side wall surface of the cavity 114 obtained by the manufacturing method of the present application is smooth (i.e., the inner side wall surface of the cavity 114 does not extend out of the protective layer 110), that is, the spacer layer 117 provided on the inner side wall surface of the cavity 114 does not lack. However, referring to Figure le It is shown that in the prior art, the inner side wall surface of the cavity 114 extends out of the covering layer 109, so that the corner formed by the extended covering layer 109 and the inner side wall surface of the cavity 114 will have a missing spacer layer 117.

[0065] The above description is only an optional embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structural transformation made by using the content of the present application specification and drawings, or direct / indirect application in other related technical fields is included in the patent protection scope of the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The manufacturing method comprises: providing a plurality of gate structures, active structures and isolation regions on a substrate; providing a first dielectric layer on the substrate between two adjacent gate structures; providing a protection layer on the top surface of each gate structure, wherein the protection layer completely covers the top surface of the gate structure and does not extend above the first dielectric layer; providing a second dielectric layer on the first dielectric layer and the protection layer; performing an etching process on the first dielectric layer and the second dielectric layer between two adjacent gate structures under the same etching condition to form a plurality of cavities with a first predetermined depth; correspondingly providing a contact member in each cavity; the step of providing a protection layer on the top surface of each gate structure comprises: extending the first dielectric layer by a first predetermined height based on self-aligned growth of the first dielectric layer, so that the extended first dielectric layer and the gate structure between the two adjacent first dielectric layers form a first recess; filling the first recess to form the protection layer on the top surface of the gate structure; the step of extending the first dielectric layer by a first predetermined height based on self-aligned growth of the first dielectric layer comprises: performing a first treatment on the first dielectric layer to form a second recess with a second predetermined depth between two adjacent gate structures and the first dielectric layer between the two adjacent gate structures; filling the second recess to form a seed layer above the first dielectric layer after the first treatment, wherein the top surface of the seed layer is at the same level as the top surface of the gate structure; performing a second treatment on the seed layer by self-aligned growth to convert the seed layer into a preset layer, wherein the top surface of the preset layer is higher than the top surface of the gate structure by the first predetermined height; the step of performing a second treatment on the seed layer to convert the seed layer into a preset layer comprises: performing a thermal oxidation process on the seed layer to make the seed layer expand in volume to form the preset layer; the material of the seed layer is elemental silicon or silicide material.

2. The method of claim 1, wherein the step of filling the first recess to form the protection layer on the top surface of the gate structure comprises: filling the first recess to deposit a cover layer on the top surface of the entire device in which the first recess is formed; planarizing the cover layer to expose the first dielectric layer and the remaining cover layer forms the protection layer on the top surface of the gate structure.

3. The method of claim 1, wherein the step of filling the second recess to form a seed layer above the first dielectric layer after the first treatment comprises: filling the second recess to deposit a continuous seed layer precursor on the top surface of the entire device in which the second recess is formed; planarizing the seed layer precursor to expose the gate structure and the remaining seed layer precursor forms the seed layer in the second recess.

4. The method of claim 1, wherein the step of performing a first treatment on the first dielectric layer to form a second recess with a second predetermined depth comprises: partially etching the top of the first dielectric layer to form a second recess with a second predetermined depth.

5. The production method according to any one of claims 1 to 4, wherein the thickness of the seed layer is 40-80 Å.

6. A semiconductor device, characterized by, made by the manufacturing method of any one of claims 1-5.

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