Semiconductor device fabrication methods and semiconductor devices

Abstract

This application discloses a method for fabricating a semiconductor device and a semiconductor device. The method includes: providing a substrate, on which an active structure and a gate structure are disposed, the gate structure including a sacrificial gate structure for removal and a reserved gate structure remaining after removal; removing the sacrificial gate structure at a predetermined region to form a corresponding gate opening; after forming the gate opening, depositing a barrier layer and / or an interlayer dielectric layer abutting the sidewalls of the reserved gate structure above the substrate and within the gate opening; and forming a gate spacer in the gate opening where the barrier layer and / or the interlayer dielectric layer are formed.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a method for manufacturing a semiconductor device and a semiconductor device. Background Technology

[0002] With the development of integrated circuits (ICs), the geometric dimensions (i.e., critical dimensions, the smallest size achievable using semiconductor processes) are gradually shrinking while the functional density (i.e., the number of interconnect devices per unit chip area) is gradually increasing. In current semiconductor manufacturing processes, multiple gate structures spaced apart and arranged in a linear pattern are first formed on a substrate. Then, a barrier layer and a first dielectric layer abutting the sidewalls of the gate structure are deposited on the substrate. Next, a portion of the gate is removed within a predetermined region of a gate structure to form a gate opening. Finally, a dielectric material (i.e., an interlayer dielectric layer) is filled into the gate opening to form a gate spacer, achieving electrical isolation of the gate structure in the semiconductor device. Figures 1(a)-(h) show schematic diagrams of the prior art process for forming gate spacers.

[0003] Referring to Figure 1(a), a substrate 101 is provided, and a plurality of gate structures may be disposed at intervals on the substrate 101. Each gate structure includes a gate 104 and a sidewall 105, wherein a mask layer 103 may be disposed above the gate 104. Of course, an active structure (e.g., fin structure 116) may be formed on the substrate 101 before forming the gate structure, and then the gate structure may be formed on the substrate 101 and the fin structure 116. The same gate structure includes two parts: one part is used for the gate structure to be removed, which is the sacrificial gate structure, and the other part is the gate structure remaining after removal, which is the reserved gate structure.

[0004] Referring to Figure 1(b), a barrier layer 110 is deposited on the substrate 101 and on both sides of the adjacent two gate structures. After the barrier layer 110 is formed, a first dielectric layer 112 is filled between the adjacent two gate structures. Then, the layer is planarized to remove the mask layer 103 and expose the gate structure.

[0005] Referring to Figure 1(c), an etch stop layer 115 is deposited over the gate structure, the barrier layer 110, and the first dielectric layer 112.

[0006] Referring to Figures 1(d)-(e), a photolithography layer 106 is deposited above the etch stop layer 115, and a first opening 107 corresponding to the predetermined removal region is formed in the photolithography layer 106. The fin structure 116 is perpendicular to the gate structure. Assuming the direction in which the fin structure 116 extends in the horizontal plane is the X-axis, and the direction in which the gate structure extends in the horizontal plane is the Y-axis, the predetermined region for removing the sacrificial gate structure in the same X-axis direction can be for only one gate structure or can span multiple adjacent gate structures simultaneously. Figure 1(f) shows an example of two adjacent sacrificial gate structures in the same X-axis direction.

[0007] Referring to FIG1(f), a portion of the gate in the sacrificial gate structure (the pure black portion indicated by the dashed circle in FIG1(f) shows a small amount of gate 104 residue) and a portion of the etch stop layer 115 are removed according to the first opening 107 to form a gate opening 114, which serves as a filling area for the subsequent setting of the gate spacer 102.

[0008] Referring to Figure 1(g), a second dielectric layer 113 is filled in the gate opening 114 and the second dielectric layer 113 covers the etch stop layer 115.

[0009] Referring to Figure 1(h), after filling the second dielectric layer 113, the semiconductor device is planarized to expose the first dielectric layer 112. After the semiconductor device is planarized, the second dielectric layer 113 remaining in the gate opening 114 serves as the gate spacer 102. Note that the first dielectric layer 112 and the second dielectric layer 113 can be the same or different dielectric materials.

[0010] In the prior art, based on the first dielectric layer 112, the sacrificial gate structure is first removed to form a gate opening 114, and then the gate opening 114 is filled to form a gate spacer 102. At this time, the depth-to-width ratio of the gate opening 114 is too high. Therefore, during the process of removing the gate 104 of the gate structure, some gate is easily left in the corner of the gate opening 114, which leads to problems such as difficulty in filling the gate spacer or poor quality.

[0011] Therefore, a method is needed to solve the above problems. Summary of the Invention

[0012] The main objective of this application is to propose a method for fabricating a semiconductor device that aims to reduce residual gate material in the corners of the gate opening and reduce the fabrication difficulty of the gate spacer during the removal of the sacrificial gate structure, thereby improving the quality of the semiconductor device.

[0013] To achieve the above objectives, this application proposes a method for fabricating a semiconductor device, the method comprising:

[0014] A substrate is provided, on which an active structure and a gate structure are disposed, the gate structure including a sacrificial gate structure for removal and a reserved gate structure remaining after removal;

[0015] At a predetermined region, the sacrificial gate structure is removed to form a corresponding gate opening;

[0016] After forming the gate opening, a barrier layer and / or an interlayer dielectric layer abutting the sidewalls of the reserved gate structure are deposited over the substrate and within the gate opening; and

[0017] A gate spacer is formed in the gate opening where the barrier layer and / or the interlayer dielectric layer are formed.

[0018] In this application, since the barrier layer and / or the interlayer dielectric layer and the gate spacer are formed simultaneously, the residual gate material in the corner of the gate opening is reduced and the fabrication difficulty of the gate spacer is reduced, making the process steps for forming the gate spacer simpler, saving process costs, and improving the quality of semiconductor devices.

[0019] In one embodiment, removing the sacrificial gate structure at a predetermined region to form a corresponding gate opening includes:

[0020] A photolithographic layer is deposited over the gate structure and the substrate;

[0021] A first opening for the sacrificial gate structure corresponding to the removal of the predetermined region is formed in the photolithographic layer, and

[0022] The sacrificial gate structure at the predetermined region is removed along the first opening to form the corresponding gate opening.

[0023] In one embodiment, removing the sacrificial gate structure at the predetermined region along the first opening to form the corresponding gate opening includes:

[0024] After forming the first opening of a predetermined depth on the photolithography layer, the photolithography layer is etched along the first opening to form a second opening that exposes the sacrificial gate structure.

[0025] A dielectric film is deposited on the inner wall and bottom of the second opening, as well as over the remaining photolithographic layer; and

[0026] The remaining sacrificial gate structure is removed along the second opening where the dielectric film is deposited to form the corresponding gate opening.

[0027] In one embodiment, removing the remaining sacrificial gate structure along the second opening where the dielectric film is deposited includes:

[0028] Using a first etching selectivity ratio, a portion of the photolithographic layer abutting the sidewall of the sacrificial gate structure and / or a portion of the sidewall of the sacrificial gate structure is removed along the sidewall of the second opening where the dielectric film is deposited; and

[0029] The remaining sacrificial gate structure is removed along the second opening where the dielectric film is deposited using a second etch selectivity ratio, wherein the first etch selectivity ratio is less than the second etch selectivity ratio.

[0030] In one embodiment, forming a gate spacer in the gate opening where the barrier layer and the interlayer dielectric layer are formed includes:

[0031] Remove all photolithographic layers from the substrate and the reserved gate structure;

[0032] The barrier layer is deposited above the substrate, at the bottom of the gate opening, inside the gate opening, and above the reserved gate structure; and

[0033] An interlayer dielectric layer is filled within the gate opening where the barrier layer is deposited, and the interlayer dielectric layer also covers the barrier layer above the substrate and the reserved gate structure;

[0034] The entire semiconductor device on which the interlayer dielectric layer is deposited is etched and / or planarized to expose the reserved gate structure and to form gate spacers with the remaining barrier layer and interlayer dielectric layer in the gate opening.

[0035] In one embodiment, when multiple gate structures spaced apart from each other are disposed above the substrate, the same gate structure includes the sacrificial gate structure and the reserved gate structure remaining after removal; the predetermined region corresponds to one or more of the sacrificial gate structures and / or abuts the sidewall of the sacrificial gate structure and its extended gate spacing space.

[0036] In one embodiment, taking the direction in which the active structure extends in the horizontal plane as the X-axis and the direction in which the gate structure extends in the horizontal plane as the Y-axis, the predetermined region should satisfy the following formula:

[0037]

[0038] And / or,

[0039]

[0040] Wherein, W: the width of the predetermined region in the X-axis direction; L i : The width of a gate structure in the X-axis direction; S i: The width of the space between the sides of a gate structure and the wall of the gate structure in the X-axis direction; n: The number of sacrificial gate structures corresponding to the predetermined region, n≥1; i=1.

[0041] In one embodiment, each gate structure includes a gate and sidewalls abutting both sides of the gate, and a mask layer is disposed above the gate.

[0042] This application also provides a semiconductor device, which is formed using the fabrication method described above.

[0043] This application also provides a semiconductor device, the semiconductor device comprising:

[0044] Substrate;

[0045] An active structure disposed above the substrate and a plurality of gate structures spaced apart from each other, the gate structures including electrically isolated gate openings; and

[0046] A barrier layer and / or an interlayer dielectric layer that continuously fills the gap between the gate opening and the gate structure extending along the gate opening, and covers the substrate and the active structure above and abuts the sidewall of the gate structure. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0048] Figures 1(a)-(h) show schematic diagrams of the prior art process for forming gate spacers;

[0049] Figure 2 A schematic diagram of a prior art semiconductor device having a gate opening formed thereon is shown;

[0050] Figures 3(a)-(k) show schematic flowcharts of forming a gate spacer according to an embodiment of this application.

[0051] Figure 4 A schematic diagram of removing a sacrificial gate structure that spans multiple gate structures on the same substrate is shown.

[0052] Explanation of icon numbers:

[0053] label name label name 100 semiconductor devices 101 substrate 102 Gate spacer 104 gate 102a Sacrificial gate structure 102b Reserved gate structure 103 mask layer 106 Photolithography layer 105 side walls 106b intermediate photolithography layer 106a upper photolithography layer 107 First opening 106c Lower photolithography layer 109 dielectric membrane 108 Second opening 110 Barrier layer 111 Interlayer dielectric layer 113 Second dielectric layer 112 First dielectric layer 115 Etching stop layer 114 Gate opening 116 Fin structure

[0054] The functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0055] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0056] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0057] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0058] The formation process of the gate spacer in a conventional FinFET device is as follows, refer to... Figure 2 As shown,

[0059] S1. A fin structure 116 and a spaced-apart linear gate structure 104 are formed above a substrate;

[0060] S2. Fill the gaps between the gate structures with various capping layers, such as etch stop layer (CESL) and interlayer dielectric layer (ILD). Figure 2 (Not shown);

[0061] S3. Based on this, a gate opening 114 is formed by removing a portion of the gate structure in the predetermined region;

[0062] S4. Fill the gate opening with material to form a gate spacer, thereby achieving electrical isolation in the semiconductor device. Figure 2 (Not shown).

[0063] As device feature sizes shrink, the aforementioned conventional processes face increasing challenges, including the following issues. First, during the formation of the gate aperture using photolithography, the photolithographic aperture designed with optical proximity correction must precisely correspond to the predetermined area to avoid erroneous damage to structures in non-predetermined areas. Damage to the etch stop layer (CESL) or the interlayer dielectric layer (ILD) resulting in a reduction in their height will subsequently affect the gate height.

[0064] Second, the sidewalls of the gate opening formed by photolithography are usually sloping, and due to the high aspect ratio of the gate opening, a small amount of gate material is easily left in the gate opening during the removal of the gate structure in the predetermined area. Furthermore, due to the high aspect ratio of the gate opening, filling voids are easily created during the filling process to form the gate spacer.

[0065] Third, the existing process requires at least two filling processes, including filling various capping layers in step S2 and filling materials to form gate spacers in step S4. Therefore, the existing process is relatively complicated.

[0066] Finally, during the process of forming multiple gate openings in two or more adjacent gate structures along the same direction perpendicular to the extension direction of the gate structure, it is unavoidable that the top of a portion of the first dielectric layer 112 between two adjacent gate structures is incorrectly removed, resulting in a reduction in the height of the first dielectric layer 112 (see Figure 1(f)). Subsequently, during the chemical mechanical polishing (CMP) process, in order to ensure a uniform height across the entire surface of the semiconductor device, it is necessary to remove a portion of the top of the gate structure. However, this results in a reduction in the overall height of the semiconductor device, significantly decreasing its quality (see Figures 1(g) and 1(h)).

[0067] This application proposes technical solutions to address these problems in the prior art. Figures 3(a)-(j) show schematic flowcharts of forming a gate spacer according to an embodiment of this application.

[0068] Referring to Figure 1(a), a substrate 101 is provided, and a plurality of gate structures are disposed at intervals on the substrate 101. Each gate structure includes a gate 104 and a sidewall 105. In one embodiment, a mask layer 103 may be provided above the gate 104, and the mask layer 103 may be divided into a first mask layer and a second mask layer. Of course, in another embodiment, a fin structure 116 may be formed above the substrate 101 before forming the gate structure, and then the gate structure may be formed above the substrate 101 and the fin structure 116. The same gate structure includes two parts: one part is for the gate structure to be removed, namely the sacrificial gate structure 102a, and the other part is the gate structure remaining after removal, namely the reserved gate structure 102b.

[0069] Figure 3(a1) is a cross-sectional view formed by cutting along XX according to Figure 3(b1), and Figure 3(a2) is a cross-sectional view formed by cutting along YY according to Figure 3(b1).

[0070] Referring to FIG3(a1), a photolithography layer 106 is deposited over the entire semiconductor device shown in FIG1(a) so that the photolithography layer 106 covers the substrate 101, the fin structure 116 and the gate structure, wherein the photolithography layer 106 includes a lower photolithography layer 106c, a middle photolithography layer 106b and an upper photolithography layer 106a deposited sequentially.

[0071] Referring to Figures 3(b1)-(b2), the dashed lines in Figure 3(b1) represent a predetermined region for removing the sacrificial gate structure 102a, which indicates the area along which the sacrificial gate structure 102a will be subsequently removed. Within the same gate structure, the gate structure enclosed by the dashed lines is the sacrificial gate structure 102a, and the gate structure outside the dashed lines is the reserved gate structure 102b. Figure 3(b2) is a cross-sectional view formed by cutting along the YY direction according to Figure 3(b1).

[0072] Referring to FIG3(c), a first opening 107 for subsequent removal of the sacrificial gate structure 102a in the upper photolithography layer 106a is formed. The predetermined region may include, in addition to the sacrificial gate structure, an extended spacing space abutting the sidewall of the sacrificial gate structure. The size of the first opening 107 in the upper photolithography layer 106a corresponds to the size of the predetermined region after optical proximity correction (OPC).

[0073] In this embodiment, the fin structure 116 and the gate structure are perpendicular to each other. If we take the direction in which the fin structure 116 extends on the horizontal plane as the X-axis and the direction in which the gate structure extends on the horizontal plane as the Y-axis, and assume that the width of a certain gate structure on the X-axis is L... i And the distance between two adjacent gate structures is S iThe width of the sidewall along the X-axis is h. When the first opening 107 corresponds to one or more sacrificial gate structures 102a, the width W of the corresponding predetermined region along the X-axis satisfies...

[0074]

[0075] And / or,

[0076]

[0077] Where i equals 1, and n represents the number of sacrificial gate structures 102a corresponding to the first opening 107, n is greater than or equal to 1. For example, in Figure 3(c), the width W of the predetermined region along the X-axis is greater than or equal to the width L of the gate structure A and less than or equal to the distance L+2S between the two gate structures (B, C) adjacent to the gate structure A.

[0078] Similarly, in the prior art, referring to Figure 1(e), if each gate structure is the same and the spacing between two adjacent gate structures is also the same, then when the first opening 107 corresponds to one or more sacrificial gate structures, the width W of the corresponding predetermined region in the X-axis direction should be n*L+(n-1)*S-2h.

[0079] As can be seen from the above comparison, the upper limit of the size of the predetermined region that can be achieved by this application [n*L+(n+1)*S] is significantly larger than the corresponding size [n*L+(n-1)*S-2h] in the prior art. That is, the opening size formed in its process is large, which greatly reduces the difficulty of the photolithography process.

[0080] Furthermore, the first opening 107 in this application requires a larger dimensional adjustment space corresponding to the sacrificial gate structure 102a, with lower precision requirements, making the operation simpler compared to existing technologies. This is because, in this application, based on ensuring no loss of adjacent gate structures, the predetermined region of the sacrificial gate structure can be removed extending to the spacing space on both sides of the sacrificial gate structure. The width W of this predetermined region can be adjusted within a fluctuation range of 2S (i.e., the difference between the upper and lower limits of the width W, relative to equally spaced gate structures), resulting in a larger process space for the corresponding first opening 107. However, in existing technologies, the adjustable fluctuation range of the width W of the predetermined region is negligible.

[0081] Referring to Figure 3(d), the middle photolithography layer 106b is etched along the first opening 107 to expose the lower photolithography layer 106c.

[0082] Referring to Figure 3(e), the lower photolithography layer 106c is etched along the first opening 107 to form a second opening 108 that exposes the sacrificial gate structure 102a, and all other upper photolithography layers 106a are removed. The width M2 of the second opening 108 on the X-axis is less than or equal to n*L+(n+1)*S.

[0083] Understandably, a first opening 107 is formed on the upper photolithography layer 106a using a photomask, and this first opening 107 is sequentially transferred to the middle photolithography layer 106b and the lower photolithography layer 106c to expose the sacrificial gate structure 102a.

[0084] Referring to Figure 3(f), the mask layer 103 and part of the sacrificial gate structure 102a on the sacrificial gate structure 102a are removed along the second opening 108, while all the middle photolithography layer 106b and part of the lower photolithography layer 106c are removed.

[0085] Referring to Figure 3(g), a dielectric film 109 is deposited on the inner wall and bottom of the second opening 108 and above the lower photolithography layer 106c. The dielectric film can be deposited using atomic layer deposition. It should be noted that this step is not essential; its advantage lies in protecting the adjacent reserved gate structure and preventing damage during the removal of the sacrificial gate structure.

[0086] Referring to FIG3(h), the remaining sacrificial gate structure 102a is removed along the second opening 108 where the dielectric film 109 is deposited to form a gate opening 114. During the formation of the gate opening 114, as the etching proceeds deeper toward the substrate 101, the remaining dielectric film 109 and part of the lower photolithography layer 106c are removed.

[0087] In the process of removing the sacrificial gate structure described above, the etching process of this application is less difficult and largely avoids the problem of residual sacrificial gate structure, and will not damage the structure of non-determined areas. Because in this application, the sidewalls of the sacrificial gate structure abut against a removable photolithography layer, the composition of the object in its environment is relatively simple, consisting only of the gate structure material. The etching process only needs to consider removing the gate structure as quickly as possible. Conversely, in the prior art, as shown in Figure 1(f), the sidewalls of the sacrificial gate structure abut against the barrier layer 110. During removal, the object involves various different material structures, including the first dielectric layer 112, the barrier layer 110, the gate 104, and the sidewall 105. It is necessary to avoid removing materials in non-determined areas as much as possible, and to strictly weigh and select appropriate etching process conditions, which may result in incomplete removal of the sacrificial gate. Furthermore, the upper limit of the size of the predetermined area achievable in this application is significantly larger than the corresponding size in the prior art, further solving the problem of residue in the gate opening.

[0088] Furthermore, it should be understood that the gate opening 114 formed in this application can be for a single gate structure, or it can simultaneously span multiple gate structures along the X-axis direction (see reference). Figure 4 ). Figure 4 A first opening 107 is shown for subsequent removal of the sacrificial gate structure 102a spanning multiple gate structures. The present application's solution is more effective for gate openings 114 spanning multiple gate structures. This is because the photolithography and etching processes of the present application are less complex during the removal of multiple sacrificial gate structures 102a, and there is no issue of needing to remove the top portion of the reserved gate structure. In one embodiment, the removal of the sacrificial gate structure can be achieved through cyclic etching. First, a first etching selectivity (etching gas such as CF4 / O2 can be considered) is used to remove a portion of the dielectric film, a portion of the lower photolithography layer 106c, and a portion of the sacrificial gate structure 102a along the sidewall of the second opening 108 where the dielectric film 109 is deposited. Then, a second etching selectivity (etching gas such as HBr / O2 can be considered) is used to remove the remaining sacrificial gate structure 102a along the second opening 108 where the dielectric film 109 is deposited, wherein the first etching selectivity is less than the second etching selectivity. That is, a low etch selectivity ratio is first used to remove the material around the sacrificial gate structure and the sidewalls in order to expand the plasma filling space during the second etch; then, a high etch selectivity ratio is used to completely and quickly remove the sacrificial gate structure to avoid residual problems.

[0089] Referring to Figure 3(i), all lower photolithography layers 106c on the entire semiconductor device are removed. After removing all lower photolithography layers 106c, a barrier layer 110 is deposited on the entire semiconductor device to cover the top of the substrate 101, the bottom and sidewalls of the gate opening 114, the sidewalls of the reserved gate structure 102b, and the top of the reserved gate structure 102b.

[0090] Referring to Figure 3(j), an interlayer medium material is deposited over all the barrier layers 110 to form an interlayer medium layer 111.

[0091] Referring to FIG3(k), the barrier layer 110 and the interlayer dielectric layer 111 are etched and / or planarized to expose the reserved gate structure 102b and the barrier layer material and interlayer dielectric layer material filling the region of the original sacrificial gate structure 102a in the gate opening 114 to form a gate spacer 102, wherein the gate spacer 102 serves to achieve electrical isolation of the gate structure by removing a portion of the gate structure in a predetermined region of the gate structure and replacing it with insulating material.

[0092] During the filling process, the gate spacer formed in this application has a more complete filling effect and better quality. This is because the gate spacer in this application is formed simultaneously with the interlayer dielectric layer, resulting in a more abundant filling environment; while in the prior art, the gate opening is narrower, which easily leads to the problem of filling voids.

[0093] Moreover, in this application, since the interlayer dielectric layer 111 and the gate spacer 102 are formed simultaneously, the process steps for forming the gate spacer 102 are simpler and save process costs. In the prior art, two steps are required: 1) the interlayer dielectric layer 111 needs to be formed first and CMP needs to be performed, and then 2) after the gate opening 114 is formed, the dielectric material is filled again and CMP is performed to form the gate spacer 102.

[0094] Specifically, the process of forming the gate spacer 102 in this application is as follows: after forming the gate opening, the materials of the barrier layer 110 and the interlayer dielectric layer 111 are sequentially covered on the semiconductor device, and then planarized to expose the gate structure. This simultaneously forms the barrier layer 110 and the interlayer dielectric layer 111 required for the device, as well as the material filling the gate opening, serving as the gate spacer 102. See Table 1 below:

[0095] Table 1

[0096]

[0097] Referring to Table 1 above, it is clear that the prior art requires 7 steps to form the gate spacer 102, while the present application only requires 5 steps to form the gate spacer 102.

[0098] Finally, this application is not limited to the FinFET devices listed in the embodiments, but can also be applied to two-dimensional semiconductor devices (e.g., element doping above a substrate by ion implantation to form an active structure).

[0099] The above description is merely an optional embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the content of the specification and drawings of this application under the concept of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The manufacturing method includes: A substrate is provided on which a plurality of active structures spaced apart from each other and a plurality of gate structures spaced apart from each other in the extension direction of the active structures are disposed, wherein the extension direction of the active structures is perpendicular to the extension direction of the gate structures, and the gate structures include a sacrificial gate structure for removal and a reserved gate structure remaining after removal. At a predetermined region, the sacrificial gate structure is removed to form a corresponding gate opening, including: A photolithography layer is deposited over the plurality of gate structures and the substrate to cover the substrate, the active structure and the gate structure, the photolithography layer fills the space between the plurality of gate structures and abuts the sidewalls of the plurality of gate structures, a first opening is formed in the photolithography layer for removing the sacrificial gate structure corresponding to the predetermined region, and the sacrificial gate structure and a portion of the photolithography layer at the predetermined region are removed along the first opening to form the corresponding gate opening; After forming the gate opening, a barrier layer and / or an interlayer dielectric layer abutting the sidewalls of the reserved gate structure are deposited over the substrate and within the gate opening; and A gate spacer is formed in the gate opening where the barrier layer and / or the interlayer dielectric layer are formed; The predetermined region corresponds to one or more of the sacrificial gate structures and the sidewalls abutting the sacrificial gate structures and the gate spacing space extending therefrom.

2. The manufacturing method as described in claim 1, characterized in that, The step of removing the sacrificial gate structure at the predetermined region along the first opening to form the corresponding gate opening includes: After forming the first opening of a predetermined depth on the photolithography layer, the photolithography layer is etched along the first opening to form a second opening that exposes the sacrificial gate structure. A dielectric film is deposited on the inner wall and bottom of the second opening, as well as over the remaining photolithographic layer; and The remaining sacrificial gate structure is removed along the second opening where the dielectric film is deposited to form the corresponding gate opening.

3. The manufacturing method as described in claim 2, characterized in that, The removal of the remaining sacrificial gate structure along the second opening where the dielectric film is deposited includes: Using a first etching selectivity ratio, a portion of the photolithographic layer abutting the sidewall of the sacrificial gate structure and / or a portion of the sidewall of the sacrificial gate structure is removed along the sidewall of the second opening where the dielectric film is deposited; and The remaining sacrificial gate structure is removed along the second opening where the dielectric film is deposited using a second etch selectivity ratio, wherein the first etch selectivity ratio is less than the second etch selectivity ratio.

4. The manufacturing method according to any one of claims 1-3, characterized in that, The method of forming a gate spacer in the gate opening where the barrier layer and the interlayer dielectric layer are formed includes: Remove all photolithographic layers from the substrate and the reserved gate structure; The barrier layer is deposited above the substrate, at the bottom of the gate opening, inside the gate opening, and above the reserved gate structure; and An interlayer dielectric layer is filled within the gate opening where the barrier layer is deposited, and the interlayer dielectric layer also covers the barrier layer above the substrate and the reserved gate structure; The entire semiconductor device on which the interlayer dielectric layer is deposited is etched and / or planarized to expose the reserved gate structure and to form gate spacers with the remaining barrier layer and interlayer dielectric layer in the gate opening.

5. The manufacturing method as described in claim 1, characterized in that, Taking the direction in which the active structure extends in the horizontal plane as the X-axis and the direction in which the gate structure extends in the horizontal plane as the Y-axis, the predetermined region should satisfy the following formula. And / or, Wherein, W: the width of the predetermined region in the X-axis direction; L i : The width of a gate structure in the X-axis direction; S i : The width of the space between the sides of a gate structure and the wall of the gate structure in the X-axis direction; n: The number of sacrificial gate structures corresponding to the predetermined region, n≥1; i=1.

6. The manufacturing method as described in claim 1, characterized in that, Each gate structure includes a gate and sidewalls abutting both sides of the gate, and a mask layer is disposed above the gate.

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