Elastic heat dissipation cover plate for chip packaging, packaging structure and packaging method

Abstract

The application discloses a flexible heat dissipation cover plate for chip packaging, a packaging structure and a packaging method, the heat dissipation cover plate comprises a top cover plate and side cover plates extending outward along the edges of the top cover plate, the top cover plate is used for being placed on the chip, and the side cover plates are at least partially flexible, and the flexible part can at least enable the side cover plates to perform expansion and contraction movements in a direction perpendicular to the top cover plate. The application solves the problem that, in the packaging process of large-size products, the different thermal expansion coefficients of the substrate, the heat dissipation cover plate and the chip cause stress, and the heat dissipation cover plate and the substrate and the chip are delaminated, the side cover plate part of the heat dissipation cover plate is arranged as a flexible part, the risk that the heat dissipation cover plate and the substrate and the chip are delaminated due to deformation caused by stress release in a high-temperature environment is reduced, and the heat dissipation performance of the packaging structure of the large-size product is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, and in particular to an elastic heat dissipation cover plate for chip packaging, a packaging structure and a packaging method. BACKGROUND

[0002] FCBGA (Flip Chip Ball Grid Array) is a kind of semiconductor packaging, which has a chip arranged on one side of a substrate and a ball grid array arranged on the other side of the substrate, and the ball grid array can mount the FCBGA on a printed circuit board. The heat generated during the operation of the chip needs to be dissipated to a fluid medium such as air to ensure the normal operation of the FCBGA.

[0003] The commonly used packaging structure at present includes a fixed heat dissipation cover plate arranged above the substrate, which is usually connected to the back of the chip through a TIM (Thermal Interface Material) heat dissipation adhesive to dissipate the heat generated during the operation of the chip to the outside air. However, with the increase of the size of the FCBGA packaging product, the size of the heat dissipation cover plate matched therewith increases, and due to the difference in the thermal expansion coefficient between the heat dissipation cover plate and the substrate, with the increase of the size, the warpage of the product increases, the stress between the heat dissipation cover plate and the substrate increases, and there is a risk of delamination of the heat dissipation cover plate and the substrate and the chip, which leads to the reduction of the heat dissipation performance of the chip packaging structure. SUMMARY

[0004] The present application aims to provide an elastic heat dissipation cover plate for chip packaging, a packaging structure and a packaging method.

[0005] To achieve one of the above-mentioned purposes, an embodiment of the present application provides an elastic heat dissipation cover plate for chip packaging, which comprises a top cover plate and a side cover plate extending outward along the edge of the top cover plate, and the top cover plate is arranged on the chip, wherein,

[0006] At least a part of the side cover plate is an elastic member, and the elastic member can at least allow the side cover plate to perform a stretching and contracting movement in a direction perpendicular to the top cover plate.

[0007] As a further improvement of the embodiment of the present application, the elastic member is arranged obliquely or perpendicularly to the top cover plate.

[0008] As a further improvement of the embodiment of the present application, the elastic member is of a folded structure.

[0009] As a further improvement of the embodiment of the present application, the elastic member is surrounded by a flexible filling adhesive.

[0010] As a further improvement of the embodiment of the present application, the top cover plate partial area is a grid structure.

[0011] As a further improvement of the embodiment of the present application, the grid structure comprises a horizontal baffle layer and a plurality of grid pieces vertically arranged on the upper and lower surfaces of the baffle layer, both ends of the grid pieces do not exceed the top cover plate area, the baffle layer and the grid pieces divide the top cover plate partial area into a plurality of grid slots, the grid slots are filled with heat-conducting metal materials, and the heat-conducting metal materials cover the grid pieces.

[0012] As a further improvement of the embodiment of the present application, the area of the top cover plate area with the grid structure is the same as the area of the chip.

[0013] As a further improvement of the embodiment of the present application, the heat dissipation cover plate further comprises a support part, which is arranged at the end of the side cover plate away from the top cover plate.

[0014] The present application provides a packaging structure, which comprises a chip carrier, a chip, and the elastic heat dissipation cover plate for chip packaging in any one of the above embodiments,

[0015] The chip is flip-chip bonded above the chip carrier, the heat dissipation cover plate is arranged on the chip carrier, and a cavity is formed between the heat dissipation cover plate and the chip carrier, and the chip is arranged in the cavity.

[0016] The top cover plate is arranged on the upper surface of the chip, and the side cover plate connects the top cover plate and the chip carrier.

[0017] As a further improvement of the embodiment of the present application, the grid structure is arranged directly above the chip.

[0018] As a further improvement of the embodiment of the present application, a metal layer is further arranged between the top cover plate and the chip.

[0019] As a further improvement of the embodiment of the present application, the chip carrier is a substrate, and the chip is welded to the substrate by metal solder balls and is electrically connected to the substrate.

[0020] As a further improvement of the embodiment of the present application, the chip carrier is a redistribution layer, which comprises a plurality of dielectric layers and a metal layer arranged in the dielectric layers, the upper surface of the dielectric layer is formed with a photoetching pattern opening, the photoetching pattern opening extends to the metal layer and exposes the surface of the metal layer, a metal electrode is arranged at the photoetching pattern opening, and the chip is welded to the metal electrode by metal columns / metal bumps and is electrically connected to the redistribution layer.

[0021] As a further improvement of the embodiment of the present application, the medium layer is a resin material with photoetching features, and the metal layer is a single-layer or multi-layer metal structure.

[0022] The present application also provides a packaging method, which comprises the steps of:

[0023] providing a chip carrier;

[0024] providing a chip, and setting the functional surface of the chip on the chip carrier in a flip-chip manner and electrically connecting the chip with the chip carrier;

[0025] providing a heat dissipation cover plate, and placing the heat dissipation cover plate on the chip carrier to form a cavity between the chip carrier and the heat dissipation cover plate, wherein the chip is arranged in the cavity, and the heat dissipation cover plate is the elastic heat dissipation cover plate for chip packaging as described in any one of the above embodiments, and the top cover plate is placed on the upper surface of the chip, and the side cover plate connects the top cover plate with the chip carrier.

[0026] As a further improvement of the embodiment of the present application, before the step of providing a heat dissipation cover plate, the method further comprises the steps of:

[0027] forming a metal layer on the upper surface of the chip.

[0028] As a further improvement of the embodiment of the present application, the steps of providing a chip carrier and providing a chip, and setting the functional surface of the chip on the chip carrier in a flip-chip manner and electrically connecting the chip with the chip carrier specifically comprise the steps of:

[0029] providing a substrate;

[0030] electrically connecting the chip with the substrate by welding the functional surface of the chip to the electrical pads of the substrate through metal solder balls.

[0031] As a further improvement of the embodiment of the present application, the steps of providing a chip carrier and providing a chip, and setting the functional surface of the chip on the chip carrier in a flip-chip manner and electrically connecting the chip with the chip carrier specifically comprise the steps of:

[0032] providing a re-distribution layer, which comprises a plurality of medium layers and metal layers arranged in the medium layers;

[0033] forming photoetching pattern openings on the upper surfaces of the medium layers, extending the photoetching pattern openings to the metal layers and exposing the surfaces of the metal layers, and arranging metal electrodes at the photoetching pattern openings;

[0034] electrically connecting the chip with the substrate by welding the functional surface of the chip to the metal electrodes arranged on the upper surfaces of the re-distribution layer through metal columns or metal bumps.

[0035] As a further improvement of the embodiment of the present application, the medium layer is a resin material with photoetching features, and the metal layer is a single-layer or multi-layer metal structure.

[0036] The present application has the advantages of solving the problem of delamination of the heat dissipation cover plate from the substrate and the chip due to stress caused by different thermal expansion coefficients of the substrate, the heat dissipation cover plate and the chip during packaging of large-size products, reducing the risk of delamination of the heat dissipation cover plate from the substrate and the chip due to deformation caused by stress release in a high-temperature environment by setting the side cover plate part of the heat dissipation cover plate as an elastic member, and improving the heat dissipation performance of the packaging structure of large-size products. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 The figure is a schematic diagram of the elastic heat dissipation cover plate structure for chip packaging in an embodiment of the present application.

[0038] Figure 2 The figure is a schematic diagram of the packaging structure in Example 1 of the present application.

[0039] Figure 3 The figure is a schematic diagram of the packaging structure in Example 2 of the present application.

[0040] Figure 4 The figure is a schematic diagram of the packaging method flow in an embodiment of the present application.

[0041] Figures 5(a)-(d) are schematic diagrams of the manufacturing process steps of the packaging structure in Example 1 of the present application.

[0042] Figures 6(a)-(f) are schematic diagrams of the manufacturing process steps of the packaging structure in Example 2 of the present application. DETAILED DESCRIPTION

[0043] To make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described clearly and completely below in combination with the specific embodiments of the present application and corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0044] The embodiments of the present application will be described in detail below, and examples of the embodiments are shown in the drawings, in which the same or similar reference signs represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0045] For ease of explanation, this document uses terms indicating relative spatial position, such as "above," "below," "behind," and "front," to describe the relationship of one unit or feature shown in the accompanying drawings relative to another unit or feature. Terms indicating relative spatial position can include different orientations of the device during use or operation besides those shown in the figures. For example, if the device in the figures is flipped, a unit described as being "below" or "above" other units or features will be located "below" or "above" other units or features. Therefore, the exemplary term "below" can encompass both "below" and "above" spatial orientations.

[0046] like Figure 1 As shown, this embodiment provides a flexible heat dissipation cover 1 for chip packaging, including a top cover 11 and a side cover 12.

[0047] Preferably, the top cover plate 11 and the side cover plate 12 are made of aluminum silicon carbide composite material with low density, high thermal conductivity and low coefficient of expansion. Of course, in some other embodiments, the top cover plate 11 and the side cover plate 12 can also be made of other high thermal conductivity materials, such as aluminum, copper and other metal materials, or diamond, graphene and other high thermal conductivity carbon materials.

[0048] The top cover plate 11 is used to place on the chip, receive the heat generated during the chip's operation, and dissipate the heat into the surrounding air medium.

[0049] The side cover plate 12 extends outward along the edge of the top cover plate 11. Furthermore, at least a portion of the side cover plate 12 is an elastic element 121, which allows the side cover plate 12 to extend and retract in a direction perpendicular to the top cover plate 11. The elastic element 121 is made of the same material as the side cover plate 12 and also has thermal conductivity.

[0050] Specifically, the elastic element 121 is inclined to the top cover plate 11, allowing the side cover plate 12 to extend and retract in a direction perpendicular to the top cover plate 11, or in a direction parallel to the top cover plate 11. In a specific embodiment of the present invention, the angle between the elastic element 121 and the top cover plate 11 is obtuse, making the overall chip packaging structure more stable when the heat sink cover plate 1 is installed in the chip packaging structure.

[0051] Of course, the angle between the whole elastic member 121 and the top cover plate 11 is not limited to an obtuse angle, in other embodiments of the present application, the angle between the whole elastic member 121 and the top cover plate 11 can also be a right angle, so as to achieve the purpose of enabling the side cover plate 12 to perform the expansion and contraction movement in the direction perpendicular to the top cover plate 11, or the angle between the whole elastic member 121 and the top cover plate 11 can also be an acute angle, so as to enable the side cover plate 12 to perform the expansion and contraction movement in the direction perpendicular to the top cover plate 11 and in the direction parallel to the top cover plate 11.

[0052] More specifically, the whole area of the side cover plate 12 is the elastic member 121, which further increases the elasticity of the whole heat dissipation cover plate 1.

[0053] The elastic member 121 is specifically of a folded structure, including an upper folded surface 1211 and a lower folded surface 1212, when the elastic member 121 performs the expansion and contraction movement in the direction perpendicular to the top cover plate 11, or in the direction parallel to the top cover plate 11, or in both directions, the upper folded surface 1211 and the lower folded surface 1212 are in the same plane when the elastic member 121 is in a completely stretched state. The length of the elastic member 121 can be specifically designed according to the actual situation of its application to different chip packaging structures.

[0054] In other embodiments of the present application, the elastic member 121 can also be designed as a wave-shaped structure, or other elastic and stretchable structures that can be made based on the material of the elastic member 121.

[0055] Further, the elastic member 121 is surrounded by a flexible filling glue 122, which is preferably a low-modulus filling glue. The low-modulus filling glue has the characteristics of high sealing property and high elongation, can buffer the stress suffered by the elastic member 121 due to the warping of the chip packaging structure, and can make the side cover plate 12 more stable, and the whole heat dissipation cover plate 1 structure more stable. In other embodiments of the present application, the flexible filling glue 122 can also be selected from other organic silicone glue substances with high elongation.

[0056] Further, part of the top cover plate 11 is of a grid structure, including a baffle layer 111 arranged horizontally and a plurality of grid pieces 112 arranged vertically on the upper surface and the lower surface of the baffle layer 111. In the specific embodiment of the present application, the grid pieces 112 arranged on the upper surface of the baffle layer 111 are arranged in one-to-one correspondence with the grid pieces 112 arranged on the lower surface of the baffle layer 111, and the baffle layer 111 and the grid pieces 112 are made of the same material as the top cover plate 11 and are integrally formed.

[0057] In other embodiments of the present application, the grid pieces 112 arranged on the upper surface of the baffle layer 111 and the grid pieces 112 arranged on the lower surface of the baffle layer 111 can also be staggered, which is not limited in the present application.

[0058] Specifically, the grid pieces at both ends do not exceed the area of the top cover plate, that is, in the vertical direction, the bottom end of the grid piece 112 arranged on the lower surface of the baffle layer 111 is higher than the lower surface of the top cover plate 11, preventing the grid piece 112 from protruding from the lower surface of the top cover plate 11 and causing the risk of the chip being crushed when the heat dissipation cover plate 1 is packaged above the chip. The baffle layer 111 and the grid piece 112 divide the partial area of the top cover plate 11 into a plurality of grid slots 113, and the grid slots 113 are filled with a heat-conducting metal material 114. Specifically, the heat-conducting metal material 114 covers all the grid pieces 112. The upper surface of the heat-conducting metal material 114 filled on the upper surface of the baffle layer 111 does not exceed the upper surface of the top cover plate 11, and the lower surface of the heat-conducting metal material 114 filled on the lower surface of the baffle layer 111 does not exceed the lower surface of the top cover plate 11.

[0059] In the specific embodiments of the present application, the heat-conducting metal material 114 is a high-heat-conducting metal material, which can be specifically metal indium, or metal silver, or an indium-silver alloy material. In some other embodiments of the present application, the heat-conducting metal material 114 can also be other metal materials or metal alloys with high heat conduction and low melting point.

[0060] It should be noted that too many grid slots 113 will result in too small grid slot 113 areas, and the corners of the grid slot 113 areas will not be filled with the heat-conducting metal material 114, which will cause the problem that the heat-conducting metal material 114 cannot completely fill the grid slot 113. Too few grid slots 113 will not be able to fix the heat-conducting metal material 114, and similarly, too short grid pieces 112 will also not be able to fix the heat-conducting metal material 114. In different embodiments of the present application, the specific number of grid slots 113 and the specific length of grid pieces 112 in the grid structure can be set according to the specific characteristics of the actual manufacturing materials of the top cover plate 11 and the heat-conducting metal material 114.

[0061] More specifically, the area of the top cover plate 11 with the grid structure can be designed according to the size of the chip in different packaging structures. In the specific embodiments of the present application, the area of the top cover plate 11 with the grid structure is the same as the area of the chip to which it is applied. The lower surface of the heat-conducting metal material 114 corresponds to the upper surface of the chip. The heat dissipation cover plate 1 is placed above the chip to complete the packaging, so as to ensure that the upper surface of the chip is in complete contact with the heat-conducting metal material 114.

[0062] In this embodiment, a portion of the top cover plate 11 is configured as a grid structure, which is fully filled with thermally conductive metal material 114. It can be encapsulated with the chip surface using a volatile solvent later. In the actual packaging structure, a metal layer also needs to be formed on the upper surface of the chip. The thermally conductive metal material 114 is welded to the metal layer using a volatile solvent, and the thermally conductive metal material 114 is in complete contact with the surface of the metal layer. This replaces the structure in the prior art where the heat dissipation cover plate 1 and the chip are encapsulated with thermal adhesive, thereby improving the heat dissipation of the chip package.

[0063] Furthermore, the heat dissipation cover 1 also includes a support portion 13, which is disposed at the end of the side cover 12 away from the top cover 11, further increasing the stability of the heat dissipation cover 1 in the packaging structure. Specifically, the support portion 13 is a cuboid structure with its plane parallel to the top cover 11. In other embodiments of the present invention, the support portion 13 may also be a prism structure, a semi-circular structure, or other patterned structure capable of supporting the heat dissipation cover 1 and fixing it to the chip packaging structure.

[0064] Preferably, the material used to make the support part 13 is also an aluminum silicon carbide composite material with low density, high thermal conductivity and low coefficient of expansion. Of course, in some other embodiments, the material used to make the support part 13 can also be other high thermal conductivity materials, such as aluminum, copper and other metal materials, or diamond, graphene and other high thermal conductivity carbon materials.

[0065] This invention provides a packaging structure including a chip carrier, a chip, and a flexible heat dissipation cover plate for chip packaging as described in any of the above embodiments. The chip is flip-chip bonded to the top of the chip carrier, and the heat dissipation cover plate is disposed on the chip carrier, forming a cavity between the cover plate and the chip carrier. The chip is disposed within the cavity. A top cover plate is disposed on the upper surface of the chip, and a side cover plate connects the top cover plate and the chip carrier. The flexible heat dissipation cover plate proposed in this invention can be applied to various chip packaging structures. The following provides two specific embodiments to illustrate the chip packaging structure with a flexible heat dissipation cover plate in some embodiments of this invention.

[0066] Example 1

[0067] like Figure 2 As shown, this is a packaging structure provided in Embodiment 1 of the present invention, including a chip carrier 2, a chip 3, and an elastic heat dissipation cover 1 for chip packaging as described in any of the above embodiments.

[0068] Specifically, the chip carrier 2 is a substrate 21, which has an upper surface and a lower surface opposite to the upper surface. Multiple electrical pads are provided on the upper surface of the substrate 21.

[0069] The chip 3 is flip-chip soldered on the upper surface of the substrate 21 and electrically connected with the substrate 21. Specifically, the chip 3 has a functional surface and a non-functional surface opposite to the functional surface. The functional surface of the chip 3 faces the substrate 21 and is electrically connected with the electric pads on the upper surface of the substrate 21 through metal solder balls. The bottom filling glue 4 is filled around the soldering area of the chip 3 and the substrate 21, i.e. around the metal solder balls, to prevent the soldering area from being broken due to thermal stress or mechanical impact and to enhance the bonding force between the chip 3 and the substrate 21.

[0070] The heat dissipation cover plate 1 is arranged on the substrate 21 and forms a cavity with the substrate 21. The chip 3 is arranged in the cavity. Specifically, the top cover plate 11 is arranged on the upper surface of the chip 3. The side cover plate 12 connects the top cover plate 11 and the substrate 21.

[0071] In the embodiment, the area of the top cover plate 11 with the grid structure is the same as the area of the chip 3. The grid structure is arranged directly above the chip 3.

[0072] Specifically, the grid structure is filled with the heat-conductive metal material 114. The heat-conductive metal material 114 covers all the grid pieces 112. The lower surface of the heat-conductive metal material 114 filled on the lower surface of the baffle layer 111 does not exceed the lower surface of the top cover plate 11. The heat-conductive metal material 114 is in full contact with the upper surface of the chip 3, thereby improving the heat dissipation efficiency.

[0073] Further, a metal layer 5 is arranged between the top cover plate 11 and the chip 3. The upper surface of the metal layer 5 is in full contact with the lower surface of the heat-conductive metal material 114 filled on the lower surface of the baffle layer 111. The metal layer 5 replaces the heat dissipation glue arranged between the heat dissipation cover plate 1 and the chip in the prior art, thereby improving the heat dissipation of the chip package.

[0074] The metal layer 5 can be made of one of titanium-nickel-gold, titanium-nickel-silver, aluminum-titanium-nickel-alumel and aluminum-titanium-tungsten-gold. The metal layer 5 is formed on the upper surface of the chip 3. The heat generated by the chip 3 during operation can be quickly transferred to the heat dissipation cover plate 1 through the metal layer 5 and then transferred to the surrounding air medium through the heat dissipation cover plate 1, thereby forming a chip package structure with high heat dissipation performance.

[0075] In the embodiment, the entire area of the side cover plate 12 is the elastic member 121, which is a folding structure as described above and will not be described herein again. The flexible filling glue 122 is wrapped around the elastic member 121. The flexible filling glue 122 is a low-modulus filling glue, which can buffer the stress of the elastic member 121 caused by the warping of the chip 3, the substrate 21 and the heat dissipation cover plate 1 in the package structure and make the side cover plate 12 more stable.

[0076] Furthermore, the heat dissipation cover 1 also includes a support portion 13, which is disposed at the end of the side cover 12 away from the top cover 11. The heat dissipation cover 1 is disposed above the substrate 21 through the support portion 13 to form a cavity with the substrate 21.

[0077] Specifically, the support portion 13 is fixedly disposed on the upper surface of the substrate 21 by an adhesive layer 6. The main components of the adhesive layer 6 are silicone resin and fillers (silicon dioxide / silver / aluminum, etc.), which increases the bonding force between the heat dissipation cover 1 and the substrate 21. Of course, in other embodiments of the present invention, the adhesive layer 6 can also be made of other high-temperature resistant silicone materials, as long as it can fix the heat dissipation cover 1 to the substrate 21.

[0078] Of course, in a specific embodiment of the present invention, at least one electronic component 7 is also welded on the upper surface of the substrate 21, and a welding ball 8 is formed on the lower surface of the substrate 21. The welding ball 8 can form an electrical connection between the chip 3, the substrate 21 and the external circuit board.

[0079] Furthermore, in this embodiment, the chip carrier 2 can also be a redistribution layer. The specific structure of the redistribution layer will not be described in detail here. Similarly, the chip 3 is flip-chip soldered onto the redistribution layer. The heat sink 1 is bonded and fixed above the redistribution layer by the support part 13, forming a cavity between the support part 13 and the redistribution layer. The chip 3 is disposed in the cavity.

[0080] Example 2

[0081] like Figure 3 As shown, this is a packaging structure provided in Embodiment 2 of the present invention. The chip carrier 2 is specifically a redistribution layer 22, which consists of several dielectric layers 221 and a metal layer 222 disposed therein.

[0082] Specifically, a photolithographic pattern opening 2211 is formed on the upper surface of the redistribution layer 22, i.e., the upper surface of the dielectric layer 221. The photolithographic pattern opening 2211 extends to the upper surface of the metal layer 222 and exposes the upper surface of the metal layer 222. A metal electrode 223 is disposed at the photolithographic pattern opening 2211. The specific shape of the photolithographic pattern opening 2211 is not limited in this invention.

[0083] The dielectric layer 221 is a resin material with photolithographic features, such as polyimide (PI), benzocyclobutene (BCB), etc. The metal layer 222 and the metal electrode 223 can be a single-layer metal structure or a multi-layer metal structure. The specific materials can be copper, nickel, or titanium / copper, titanium-tungsten / nickel, etc.

[0084] Of course, in some other embodiments of the present application, the redistribution layer 22 can be a high-density redistribution layer formed by stacking a plurality of dielectric layers 221 and metal layers 222, and the number of layers and the specific wiring manner of the high-density redistribution layer can be designed according to actual chip packaging requirements.

[0085] The chip 3 is flip-chip soldered on the redistribution layer 22 and electrically connected to the redistribution layer 22. Specifically, the chip 3 has a functional surface and a non-functional surface opposite to the functional surface, the functional surface of the chip 3 faces the redistribution layer 22, and a metal column / metal bump 9 is arranged on the functional surface of the chip 3, and the metal column / metal bump 9 is soldered on the metal electrode 223 through solder 10. Here, the metal column / metal bump 9 is made of conductive metal materials such as copper and nickel, and the solder 10 is pure tin or tin-based solder alloy.

[0086] Further, the packaging structure in the embodiment further includes a plastic encapsulation layer 33 filled in the connection between the chip 3 and the redistribution layer 22, and the top of the plastic encapsulation layer 33 is not higher than the upper surface of the chip 3 in the height direction of the chip 3. Here, the material of the plastic encapsulation layer 33 is preferably epoxy resin plastic encapsulation material.

[0087] Further, a plurality of another photoetching pattern openings 2212 are formed on the lower surface of the dielectric layer 221, the another photoetching pattern openings 2212 extend to the lower surface of the metal layer 222 in the dielectric layer 221 and expose the lower surface of the metal layer 222, and a metal electrode 224 for soldering with external circuits is arranged at the another photoetching pattern openings 2212. Similarly, the specific shape and size of the another photoetching pattern openings 2212 are not limited in the present application.

[0088] Different from the structure in Embodiment 1, the packaging structure in the embodiment further includes an external substrate 42, and the redistribution layer 22 is electrically connected to the external substrate 42 by forming a solder ball at the metal electrode 224 for soldering with external circuits, and a solder ball 8 is further formed on the lower surface of the external substrate 42, and the chip 3, the redistribution layer 22, the external substrate 42 and the external circuit board are electrically connected through the solder ball 8.

[0089] Further, in some other embodiments of the present application, the plastic encapsulation layer 33 can also extend to the upper surface of the external substrate 42 to cover the redistribution layer 22 and enhance the bonding force between the redistribution layer 22 and the external substrate 42.

[0090] The heat dissipation cover plate 1 is arranged on the external substrate 42 to form a cavity between the heat dissipation cover plate 1 and the external substrate 42, and the redistribution layer 22 and the chip 3 are arranged in the cavity. Specifically, a metal layer 5 is further arranged on the upper surface of the chip 3, the top cover plate 11 is arranged on the upper surface of the metal layer 5, and the side cover plate 12 connects the top cover plate 11 and the external substrate 42.

[0091] The heat dissipation cover plate 1 encapsulated on the chip 3 in this embodiment has the same specific structure as the heat dissipation cover plate 1 in Embodiment 1, and will not be described again here. Similarly, the support part 13 of the heat dissipation cover plate 1 in this embodiment is fixedly arranged on the upper surface of the external substrate 42 through the adhesive layer 6.

[0092] As shown in FIG. 1, a packaging method provided by this embodiment includes the following steps: Figure 4

[0093] S1: providing a chip carrier 2.

[0094] S2: providing a chip 3, flip-chip arranging the functional surface of the chip 3 on the chip carrier 2 and electrically connecting the chip carrier 2.

[0095] Figures 5(a) to 5(d) The process step diagram for manufacturing the structure in Embodiment 1. In Embodiment 1, the chip carrier 2 is specifically a substrate 21, and the upper surface of the substrate 21 is provided with a plurality of electrical pads. The functional surface of the chip 3 is welded to the upper surface of the substrate 21 through metal solder balls by using a flip-chip ball bonding process, is electrically connected to the substrate 21, and is filled with a bottom filling adhesive 4 at the welding position, as shown in FIG. 5(a).

[0096] Before step S2, at least one electronic component 7 is also attached to the upper surface of the substrate 21. Of course, the electronic component 7 can also be attached after the step of welding the chip 3.

[0097] S3: providing a heat dissipation cover plate 1, placing the heat dissipation cover plate 1 on the chip carrier 2 to form a cavity between the heat dissipation cover plate 1 and the chip carrier 2, and arranging the chip 3 in the cavity. The heat dissipation cover plate 1 is any one of the elastic heat dissipation cover plates for the chip packaging structure in the above embodiments. The top cover plate 11 is placed on the upper surface of the chip 3, and the side cover plate 12 connects the top cover plate 11 and the chip carrier 2.

[0098] Corresponding to the structure in Embodiment 1, before step S3, a metal layer 5 is also formed on the upper surface of the chip 3, and an adhesive layer 6 is coated on the upper surface of the substrate 2 in the area to be in contact with the heat dissipation cover plate 1, as shown in FIG. 5(b). The heat dissipation cover plate 1 is placed on the substrate 21, as shown in FIG. 5(c). Specifically, the support part 13 of the heat dissipation cover plate is fixed above the substrate 21 through the adhesive layer 6, and the top cover plate 11 is placed on the upper surface of the metal layer 5.

[0099] Specifically, before encapsulating the heat dissipation cover plate 1, a process of spraying a layer of flux on the upper surface of the metal layer 5 is also included, which is used to fixedly weld the top cover plate 11 and the metal layer 5 together. Here, the flux is a volatile solvent, which will volatilize in the subsequent high-temperature furnace reflow soldering process of the encapsulation structure.

[0100] ​More specifically, the top cover plate 11 area part filled with the heat conductive metal material 114 is placed directly above the metal layer 5, after the subsequent reflow process, the flux sprayed on the upper surface of the metal layer 5 volatilizes, the heat conductive metal material 114 is eutectically welded with the metal layer 5, the heat generated by the chip 3 can be quickly transferred to the heat dissipation cover plate 1 through the metal layer 5, and then to the surrounding air medium for heat dissipation.

[0101] Of course, after step S3, there are also process steps such as curing, reflow soldering, etc., and the solder balls 8 are welded on the lower surface of the substrate 21, as shown in FIG. 5(d), so that the chip 3 and the substrate 21 are electrically connected to the external circuit board.

[0102] Further, in the structure manufacturing method of the embodiment, the chip carrier 2 can also be provided as a redistribution layer, and the specific structure of the redistribution layer is not described here. Similarly, the chip 3 is flip-chip soldered on the redistribution layer, and the heat dissipation cover plate 1 is fixedly arranged above the redistribution layer by the support part 13 and is bonded to the redistribution layer, forming a cavity between the redistribution layer and the heat dissipation cover plate 1, and the chip 3 is arranged in the cavity.

[0103] Figures 6(a) to 6(f) The process step diagram for manufacturing the packaging structure in Embodiment 2 of the application is different from the packaging structure manufacturing steps in Embodiment 1, and steps S1 and S2 are as follows:

[0104] A redistribution layer 22 is provided, and the redistribution layer 22 includes a plurality of layers of dielectric layers 221 and metal layers 222 arranged in the dielectric layers 221.

[0105] Specifically, as shown in FIG. 6(a), a photoetching pattern opening 2211 is formed on the upper surface of the dielectric layer 221, the photoetching pattern opening 2211 extends to the upper surface of the metal layer 222 and exposes the upper surface of the metal layer 222, and a metal electrode 223 is formed at the photoetching pattern opening 2211.

[0106] The dielectric layer 221 is a resin material with photoetching characteristics, such as polyimide (PI), benzocyclobutene (BCB), etc., and the metal layer 222 and the metal electrode 223 can be a single-layer metal structure or a multi-layer metal structure, and the specific material can be copper, nickel, or titanium / copper, titanium tungsten / nickel, etc.

[0107] Of course, in some other embodiments of the application, the redistribution layer 22 can be a high-density redistribution layer formed by a plurality of layers of dielectric layers 221 and metal layers 222 spaced and stacked, and the number of layers and the specific wiring mode of the high-density redistribution layer can be designed according to the actual chip packaging requirements.

[0108] Another photoetching pattern opening 2212 is formed on the lower surface of the dielectric layer 221, which extends to the lower surface of the metal layer 222 and exposes the lower surface of the metal layer 222. A metal electrode 224 for soldering with external circuits is formed on the photoetching pattern opening 2212. The detailed manufacturing method of the rewiring layer 22 is a prior art and will not be described herein.

[0109] The functional surface of the chip 3 is soldered to the metal electrode 223 through the metal pillar / metal bump 9 and the solder 10. Here, the metal pillar / metal bump 9 is made of conductive metal materials such as copper and nickel, and the solder 10 is made of pure tin or tin-based solder alloy, as shown in Fig. 6(b).

[0110] The plastic encapsulation layer 33 is filled between the rewiring layer 22 and the chip 3, and the top end of the plastic encapsulation layer 33 is not higher than the upper surface of the chip 3. An external substrate 42 is provided, and the rewiring layer 22 is soldered to the upper surface of the external substrate 42 through soldering balls on the metal electrode 224 on the lower surface of the rewiring layer 22 for soldering with external circuits, so that the rewiring layer 22 is electrically connected to the external substrate 42, as shown in Fig. 6(c). Of course, in other embodiments of the present application, the rewiring layer 22 can be soldered to the external substrate 42 first, and then the plastic encapsulation layer 33 is filled between the chip 3 and the rewiring layer 22. The plastic encapsulation layer 33 can also extend to the upper surface of the external substrate 42.

[0111] Similarly, a metal layer 5 is formed on the upper surface of the chip 3, and an adhesive layer 6 is coated on the upper surface of the external substrate 42 to be in contact with the contact surface area of the heat dissipation cover plate 1, as shown in Fig. 6(d). Before the heat dissipation cover plate 1 is encapsulated, a process of spraying a layer of flux on the upper surface of the metal layer 5 is also included, which is used to fixedly solder the top cover plate 11 to the metal layer 5. Here, the flux is a volatile solvent, which will volatilize in the subsequent high-temperature furnace reflow soldering process of the encapsulation structure.

[0112] The heat dissipation cover plate 1 is placed above the rewiring layer 22, as shown in Fig. 6(e). The support part 13 of the heat dissipation cover plate is fixed above the external substrate 42 through the adhesive layer 6, and the top cover plate 11 is placed on the upper surface of the metal layer 5. Similarly, the area part of the top cover plate 11 filled with the thermally conductive metal material 114 is placed directly above the metal layer 5. After the subsequent reflow process, the flux sprayed on the upper surface of the metal layer 5 volatilizes, the thermally conductive metal material 114 is eutectically soldered to the metal layer 5, and the heat generated by the chip 3 can be quickly transferred to the heat dissipation cover plate 1 through the metal layer 5, and then to the surrounding air medium for heat dissipation.

[0113] Similarly, after step S3, a process step of solidification, reflow soldering, etc. is also included, and soldering balls 8 are soldered on the lower surface of the external substrate 42, as shown in Fig. 6(f), so that the chip 3, the rewiring layer 22 and the external substrate 42 are electrically connected to the external circuits.

[0114] In summary, the application solves the problem of delamination of the heat dissipation cover plate from the substrate and the chip due to stress caused by different thermal expansion coefficients of the substrate, the heat dissipation cover plate and the chip during the packaging process of large-size products. The side cover plate part of the heat dissipation cover plate is set as an elastic member to reduce the risk of delamination of the heat dissipation cover plate from the substrate and the chip due to deformation caused by stress release in a high-temperature environment. In addition, the back of the chip is plated with a metal layer, and the part of the heat dissipation cover plate in contact with the chip is designed as a grid structure, and the grid structure is filled with high-thermal-conductivity metal material, so that the metal layer is in full contact with the high-thermal-conductivity metal material, and the heat generated by the chip can be quickly transferred to the surrounding air medium, replacing the structure in the prior art in which the heat dissipation cover plate and the chip are packaged by heat dissipation glue, to form a large-size high-heat-dissipation chip packaging structure.

[0115] It should be understood that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be appropriately combined to form other embodiments that those skilled in the art can understand.

[0116] The above series of detailed descriptions are only specific descriptions of the feasible embodiments of the present application, and are not intended to limit the protection scope of the present application. Any equivalent embodiments or changes made without departing from the spirit of the present application should be included in the protection scope of the present application.

Claims

1. A resilient heat dissipation cover for chip packaging, the heat dissipation cover comprising a top cover and side cover extending outwardly along the edge of the top cover, the top cover being used to place on the chip, characterized in that: At least a portion of the side cover plate is an elastic element, which allows the side cover plate to extend and retract in a direction perpendicular to the top cover plate. A portion of the top cover plate has a grid structure, which includes a horizontally arranged baffle layer and multiple grid pieces vertically arranged on the upper and lower surfaces of the baffle layer. The two ends of the grid pieces do not extend beyond the top cover plate area. The baffle layer and the grid pieces divide the portion of the top cover plate into multiple grid grooves. The grid grooves are filled with a thermally conductive metal material, which covers the grid pieces.

2. The elastic heat dissipation cover plate for chip packaging according to claim 1, wherein, The elastic element is inclined or perpendicular to the top cover plate.

3. The elastic heat dissipation cover plate for chip packaging according to claim 2, wherein, The elastic element has a folding structure.

4. The elastic heat dissipation cover plate for chip packaging according to claim 3, characterized in that, The elastic element is surrounded by a flexible filler adhesive.

5. The elastic heat dissipation cover plate for chip packaging according to claim 1, wherein, The area of ​​the top cover plate with the grid structure is the same as the area of ​​the chip.

6. The elastic heat dissipation cover plate for chip packaging according to claim 1, wherein, The heat dissipation cover also includes a support portion, which is disposed at the end of the side cover away from the top cover.

7. A packaging structure, characterized in that, The packaging structure includes a chip carrier, a chip, and a flexible heat dissipation cover for chip packaging as described in any one of claims 1-6. The chip is flip-chip bonded to the top of the chip carrier, the heat sink is disposed on the chip carrier, forming a cavity between the chip and the chip carrier, and the chip is disposed in the cavity; The top cover is disposed on the upper surface of the chip, and the side cover connects the top cover and the chip carrier.

8. The packaging structure according to claim 7, characterized in that, The grille structure is positioned directly above the chip.

9. The packaging structure according to claim 8, characterized in that, A metal layer is also provided between the top cover plate and the chip.

10. The packaging structure according to claim 9, characterized in that, The chip carrier is a substrate, and the chip is soldered to the substrate by metal solder balls and electrically connected to the substrate.

11. The packaging structure according to claim 9, characterized in that, The chip carrier is a redistribution layer, which includes several dielectric layers and a metal layer disposed within the dielectric layers. A photolithographic pattern opening is formed on the upper surface of the dielectric layer. The photolithographic pattern opening extends to the metal layer and exposes the surface of the metal layer. A metal electrode is disposed at the photolithographic pattern opening. The chip is soldered to the metal electrode through metal pillars / metal bumps and is electrically connected to the redistribution layer.

12. The packaging structure according to claim 11, characterized in that, The dielectric layer is a resin material with photolithographic features, and the metal layer is a single-layer or multi-layer metal structure.

13. A packaging method, characterized in that, The encapsulation method includes the following steps: Provide a chip carrier; A chip is provided, wherein the functional surface of the chip is flip-chip disposed on the chip carrier and electrically connected to the chip carrier; A heat dissipation cover is provided, which is placed on the chip carrier to form a cavity between the heat dissipation cover and the chip carrier. The chip is disposed in the cavity. The heat dissipation cover is an elastic heat dissipation cover for chip packaging as described in any one of claims 1-8. A top cover is placed on the upper surface of the chip, and a side cover connects the top cover and the chip carrier. A portion of the top cover plate has a grid structure, which includes a horizontally arranged baffle layer and multiple grid pieces vertically arranged on the upper and lower surfaces of the baffle layer. The two ends of the grid pieces do not extend beyond the top cover plate area. The baffle layer and the grid pieces divide the portion of the top cover plate into multiple grid grooves. The grid grooves are filled with a thermally conductive metal material, which covers the grid pieces.

14. The packaging method according to claim 13, characterized in that, Prior to providing a heat dissipation cover, the following are also included: A metal layer is formed on the upper surface of the chip.

15. The packaging method according to claim 14, characterized in that, The provision of a chip carrier; the provision of a chip, wherein the functional surface of the chip is flip-chip disposed on the chip carrier and electrically connected to the chip carrier, specifically includes the following steps: Provide a substrate; The functional surfaces of the chip are soldered onto the substrate using metal solder balls, and are electrically connected to the substrate.

16. The packaging method according to claim 14, characterized in that, The provision of a chip carrier; the provision of a chip, wherein the functional surface of the chip is flip-chip disposed on the chip carrier and electrically connected to the chip carrier, specifically includes the following steps: A rewiring layer is provided, comprising a plurality of dielectric layers and a metal layer disposed within the dielectric layers; A photolithographic pattern opening is formed on the upper surface of the dielectric layer, the photolithographic pattern opening is extended to the metal layer and the surface of the metal layer is exposed, and a metal electrode is disposed at the photolithographic pattern opening; The functional surfaces of the chip are soldered to metal electrodes disposed on the upper surface of the redistribution layer using metal pillars / metal bumps.

17. The packaging method according to claim 16, characterized in that, The dielectric layer is a resin material with photolithographic features, and the metal layer is a single-layer or multi-layer metal structure.

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