Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same, wherein the structure includes: a plurality of second metal layers located on a substrate, the second metal layers are located on the first metal layer or the first metal layer is located on the second metal layers, the plurality of second metal layers are parallel to a second direction, and each of the second metal layers is electrically connected to a plurality of the first electrodes; a plurality of third metal layers located on the substrate, the third metal layers are located on the first metal layer or the first metal layer is located on the third metal layers, the plurality of third metal layers are parallel to the second direction, and each of the third metal layers is electrically connected to a plurality of the second electrodes. That is, the electrode ends of each metal layer do not need to be connected through a thicker electrode plate, the electrode end area of each metal layer can be reduced, so that the number of electrode plates can be increased, and further the density of the MOM capacitor can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] In semiconductor integrated circuits, integrated capacitors made on the same chip as transistor circuits are widely used. There are two main forms of metal-insulator-metal (MIM) capacitors and metal-oxide-metal (MOM) capacitors. Among them, MIM capacitors use upper and lower metal layers as capacitor plates. The production of MIM capacitors generally requires additional photolithography layers. At the same time, the breakdown voltage of the capacitor dielectric layer and the capacitance size are irreconcilable contradictions, and flat capacitors generally require a large area, which is not conducive to the integration of devices. MOM capacitors use a method combining finger structures and stacking to make capacitors with larger capacity on a relatively small area. In addition, when making MOM capacitors, no additional photoresist layer and mask are required, so the manufacturing process is simpler and the cost is lower than that of MIM capacitors. However, due to the limitation of the distance between metal wires, the lateral MOM capacitors in the prior art cannot be made larger and have poor stability.

[0003] With the development of device miniaturization, how to increase the density of MOM capacitors becomes one of the problems to be solved urgently by those skilled in the art. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0005] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a first metal layer located on the substrate, the first metal layer including a plurality of first electrodes and a plurality of second electrodes, the plurality of first electrodes and the plurality of second electrodes are parallel to a first direction and arranged along a second direction, each of the second electrodes is located between two adjacent first electrodes, and the first direction is perpendicular to the second direction; a plurality of second metal layers located on the substrate, the second metal layer is located on the first metal layer or the first metal layer is located on the second metal layer, the plurality of second metal layers are parallel to the second direction, and each of the second metal layers is electrically connected to the plurality of first electrodes respectively; a plurality of third metal layers located on the substrate, the third metal layer is located on the first metal layer or the first metal layer is located on the third metal layer, the plurality of third metal layers are parallel to the second direction, and each of the third metal layers is electrically connected to the plurality of second electrodes respectively.

[0006] Optionally, the second metal layer and the third metal layer are located in the same layer.

[0007] Optionally, the second metal layer and the third metal layer are located above or below the first metal layer.

[0008] Optionally, the second metal layer and the third metal layer are located on different layers.

[0009] Optionally, the second metal layer is higher than the first metal layer, and the third metal layer is lower than the first metal layer; or the second metal layer is lower than the first metal layer, and the third metal layer is higher than the first metal layer.

[0010] Optionally, the first metal layer includes a first region and a second region, the first region and the second region are arranged along a first direction, and the first region and the second region are respectively located at opposite ends of the first metal layer.

[0011] Optionally, each second metal layer is respectively electrically connected to a plurality of the first electrodes in the first region; each third metal layer is respectively electrically connected to a plurality of the second electrodes in the second region.

[0012] Optionally, the number of the second metal layers connected to the first electrodes is 2 or 3; the number of the third metal layers connected to the second electrodes is 2 or 3.

[0013] Optionally, it further includes: a fourth metal layer located on the substrate, the fourth metal layer includes a plurality of third electrodes and a plurality of fourth electrodes, the plurality of third electrodes and the plurality of fourth electrodes are parallel to a second direction and arranged along the first direction, and each of the fourth electrodes is located between two adjacent third electrodes; a plurality of fifth metal layers located on the substrate, the fifth metal layer is located above the fourth metal layer or the fourth metal layer is located above the fifth metal layer, the plurality of fifth metal layers are parallel to the first direction, and each of the fifth metal layers is respectively electrically connected to a plurality of the third electrodes; a plurality of sixth metal layers located on the substrate, the sixth metal layer is located above the fourth metal layer or the fourth metal layer is located above the sixth metal layer, the plurality of sixth metal layers are parallel to the first direction, and each sixth metal layer is respectively electrically connected to a plurality of the fourth electrodes.

[0014] Optionally, the fifth metal layer and the sixth metal layer are located on the same layer.

[0015] Optionally, the fifth metal layer and the sixth metal layer are located above or below the fourth metal layer.

[0016] Optionally, the fifth metal layer and the sixth metal layer are located on different layers.

[0017] Optionally, the fifth metal layer is higher than the fourth metal layer, and the sixth metal layer is lower than the fourth metal layer; or the fifth metal layer is lower than the fourth metal layer, and the sixth metal layer is higher than the fourth metal layer.

[0018] Optionally, the fourth metal layer includes a third region and a fourth region. The third region and the fourth region are arranged along a second direction, and the third region and the fourth region are respectively located at opposite ends of the fourth metal layer.

[0019] Optionally, each fifth metal layer is electrically connected to multiple third electrodes in the third region; each sixth metal layer is electrically connected to multiple fourth electrodes in the fourth region.

[0020] Optionally, the distance between the second metal layer and the fourth metal layer in a direction parallel to the substrate surface ranges from 10 nanometers to 80 nanometers; the distance between the third metal layer and the fourth metal layer in a direction parallel to the substrate surface ranges from 10 nanometers to 80 nanometers; the distance between the fifth metal layer and the first metal layer in a direction parallel to the substrate surface ranges from 10 nanometers to 80 nanometers; the distance between the sixth metal layer and the first metal layer in a direction parallel to the substrate surface ranges from 10 nanometers to 80 nanometers.

[0021] Optionally, any one of the fourth metal layer, the fifth metal layer, and the sixth metal layer can be located in the same layer as one or more of the first metal layer, the second metal layer, and the third metal layer.

[0022] Optionally, the number of fifth metal layers electrically connected to the third electrodes is 2 or 3; the number of sixth metal layers electrically connected to the fourth electrodes is 2 or 3.

[0023] Correspondingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate; forming a first metal layer on the substrate, the first metal layer including a plurality of first electrodes and a plurality of second electrodes, the plurality of first electrodes and the plurality of second electrodes being parallel to a first direction and arranged along a second direction, each of the second electrodes being located between two adjacent first electrodes, the first direction being perpendicular to the second direction; before forming the first metal layer, forming a plurality of second metal layers on the substrate and forming a plurality of first conductive plugs on the second metal layers, a plurality of the first electrodes being located on the first conductive plugs, or after forming the first metal layer, forming a plurality of first conductive plugs on the plurality of first electrodes and forming a plurality of second metal layers, the plurality of second metal layers also being located on the first conductive plugs, the plurality of second metal layers being parallel to the second direction; before forming the first metal layer, forming a plurality of third metal layers on the substrate and forming a plurality of second conductive plugs on the third metal layers, a plurality of the second electrodes being located on the second conductive plugs, or after forming the first metal layer, forming a plurality of second conductive plugs on the plurality of second electrodes and forming a plurality of third metal layers, the plurality of third metal layers also being located on the second conductive plugs, the plurality of third metal layers being parallel to the second direction.

[0024] Optionally, it further includes: forming a fourth metal layer on the substrate, the fourth metal layer including a plurality of third electrodes and a plurality of fourth electrodes, the plurality of third electrodes and the plurality of fourth electrodes being parallel to the second direction and arranged along the first direction, each of the fourth electrodes being located between two adjacent third electrodes; before forming the fourth metal layer, forming a plurality of fifth metal layers on the substrate and forming a plurality of third conductive plugs on the fifth metal layers, a plurality of the third electrodes being located on the third conductive plugs, or after forming the fourth metal layer, forming a plurality of third conductive plugs on the plurality of third electrodes and forming a plurality of fifth metal layers, the plurality of fifth metal layers also being located on the third conductive plugs, the plurality of fifth metal layers being parallel to the first direction; before forming the fourth metal layer, forming a plurality of sixth metal layers on the substrate and forming a plurality of fourth conductive plugs on the sixth metal layers, a plurality of the fourth electrodes being located on the fourth conductive plugs, or after forming the fourth metal layer, forming a plurality of fourth conductive plugs on the plurality of fourth electrodes and forming a plurality of sixth metal layers, the plurality of sixth metal layers also being located on the fourth conductive plugs, the plurality of sixth metal layers being parallel to the first direction.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0026] In the semiconductor structure provided by the technical solution of the present invention, a plurality of second metal layers are located on the substrate. The second metal layer is located on the first metal layer or the first metal layer is located on the second metal layer. The plurality of second metal layers are parallel to the second direction, and each of the second metal layers is electrically connected to a plurality of the first electrodes respectively; a plurality of third metal layers are located on the substrate. The third metal layer is located on the first metal layer or the first metal layer is located on the third metal layer. The plurality of third metal layers are parallel to the second direction, and each of the third metal layers is electrically connected to a plurality of the second electrodes respectively. That is, the electrode ends of each metal layer do not need to be connected through a thick electrode plate, which can reduce the area of the electrode ends of each metal layer, thereby increasing the number of electrode plates, and further improving the density of the MOM capacitor.

[0027] Further, it further includes: a fourth metal layer located on the substrate, a plurality of fifth metal layers located on the substrate, and a plurality of sixth metal layers located on the substrate. That is, the fourth metal layer, the fifth metal layer, and the sixth metal layer form another group of capacitors provided by the technical solution of the present invention. The electrodes of the two groups of capacitors provided by the technical solution of the present invention are vertically distributed with respect to each other.

[0028] In the method for forming the semiconductor structure provided by the technical solution of the present invention, before forming the first metal layer, a plurality of second metal layers are formed on the substrate, and a plurality of first conductive plugs are formed on the second metal layer. A plurality of the first electrodes are located on the first conductive plugs, or after forming the first metal layer, a plurality of first conductive plugs are formed on a plurality of the first electrodes, and a plurality of second metal layers are formed. The second metal layer is also located on the first conductive plug. The plurality of second metal layers are parallel to the second direction; before forming the first metal layer, a plurality of third metal layers are formed on the substrate, and a plurality of second conductive plugs are formed on the third metal layer. A plurality of the second electrodes are located on the second conductive plugs, or after forming the first metal layer, a plurality of second conductive plugs are formed on a plurality of the second electrodes, and a plurality of third metal layers are formed. The third metal layer is also located on the second conductive plug. The plurality of third metal layers are parallel to the second direction. That is, the electrode ends of each metal layer do not need to be connected through a thick electrode plate, which can reduce the area of the electrode ends of each metal layer, thereby increasing the number of electrode plates, and further improving the density of the MOM capacitor.

[0029] Further, a fourth metal layer, a fifth metal layer, and a sixth metal layer are also formed. That is, the fourth metal layer, the fifth metal layer, and the sixth metal layer form another group of capacitors provided by the technical solution of the present invention. The electrodes of the two groups of capacitors provided by the technical solution of the present invention are vertically distributed with respect to each other. Description of the Drawings

[0030] Figure 1 is a top - view structural schematic diagram of a semiconductor structure;

[0031] Figures 2 to 6 is a structural schematic diagram corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the present invention;

[0032] Figures 7 to 9 is a structural schematic diagram corresponding to each step in the method for forming a semiconductor structure according to another embodiment of the present invention. Detailed implementation manners

[0033] As described in the background art, the performance of semiconductor devices formed in the prior art needs to be improved. Now, an analysis will be made in combination with the structure of a semiconductor.

[0034] Figures 1 to 2 is a top - view structural schematic diagram of a semiconductor structure.

[0035] Please refer to Figure 1 , the semiconductor structure includes a plurality of stacked metal layers, and the metal layers include a first metal layer and a second metal layer arranged in parallel with each other, where:

[0036] The first metal layer includes a first electrode 10 and a second electrode 11 in a finger - like structure. The first electrode 10 includes a plurality of first finger - like plates 101 distributed in parallel along a first direction X. One end of the first finger - like plates 101 is connected together through a first electrode terminal 102. The second electrode 11 includes a plurality of second finger - like plates 111 distributed in parallel along the first direction X. One end of the second finger - like plates 111 is connected together through a second electrode terminal 112, and the first electrode 10 and the second electrode 11 are arranged in a relatively staggered manner;

[0037] The second metal layer includes a third electrode 20 and a fourth electrode 21 in a finger - like structure. The third electrode 20 includes a plurality of third finger - like plates 201 distributed in parallel along a second direction Y. One end of the third finger - like plates 201 is connected together through a third electrode terminal 202. The fourth electrode 21 includes a plurality of fourth finger - like plates 211 parallel to the second direction Y. One end of the fourth finger - like plates 211 is connected together through a fourth electrode terminal 212. The second direction Y is perpendicular to the first direction X, and the third electrode 21 and the fourth electrode 22 are arranged in a relatively staggered manner;

[0038] The first electrodes 10 between adjacent first metal layers are connected through a plurality of first conductive plugs 12 located at the first electrode terminal 102, and the second electrodes 11 are connected through a plurality of second conductive plugs 13 located at the second electrode terminal 112;

[0039] The third electrode 20 between adjacent second metal layers is connected by a plurality of third conductive plugs 22 located at the third electrode end 202, and the fourth electrode 21 is connected by a plurality of fourth conductive plugs 23 located at the fourth electrode end 212.

[0040] In the above method, the first electrode 10 and the second electrode 11 form a first group of MOM capacitors, and the third electrode 20 and the fourth electrode 21 form a second group of MOM capacitors. The first electrode end 102, the second electrode end 112, the third electrode end 202, and the fourth electrode end 212 are distributed in a flat plate shape, and their areas are relatively large. In addition, a certain distance is required between the first electrode and the second electrode, and a certain distance is required between the third electrode and the fourth electrode to avoid short circuits. For example, the first finger-shaped electrode plate 101 and the second finger-shaped electrode plate 111 are staggered with a certain distance in the Y direction; in the X direction, a certain distance also needs to be maintained between the first electrode end 102 and the second finger-shaped electrode plate 111, resulting in a small density of MOM devices.

[0041] To solve the above problems, the present invention provides a method for forming a semiconductor structure, including a plurality of second metal layers located on a substrate, the second metal layer is located on the first metal layer or the first metal layer is located on the second metal layer, the plurality of second metal layers are parallel to the second direction, and each second metal layer is electrically connected to a plurality of the first electrodes respectively; a plurality of third metal layers located on the substrate, the third metal layer is located on the first metal layer or the first metal layer is located on the third metal layer, the plurality of third metal layers are parallel to the second direction, and each third metal layer is electrically connected to a plurality of the second electrodes respectively. That is, the electrode ends of each metal layer do not need to be connected by thick electrode plates, which can reduce the area of the electrode ends of each metal layer, thereby increasing the number of electrode plates and further improving the density of MOM capacitors.

[0042] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0043] Figures 2 to 6 It is a schematic structural diagram corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0044] Please refer to Figure 2 , provide a substrate 100.

[0045] In this embodiment, the substrate 100 includes a base, a device layer (not shown in the figure) located on the base, and a first dielectric layer (not shown in the figure) located on the surfaces of the base and the device layer. The device layer includes an isolation structure (not shown in the figure) and a device structure (not shown in the figure) located within the isolation structure. The device structure includes transistors, diodes, triodes, capacitors, inductors, or conductive structures, etc.

[0046] Please refer to Figure 3 , Figure 3 is a top view of the substrate 100 with the substrate 100 omitted. A first metal layer 102 is formed on the substrate 100. The first metal layer 102 includes a plurality of first electrodes 102a and a plurality of second electrodes 102b. The plurality of first electrodes 102a and the plurality of second electrodes 102b are parallel to the first direction X and arranged along the second direction Y. Each of the second electrodes 102b is located between two adjacent first electrodes 102a. The first direction X is perpendicular to the second direction Y.

[0047] In this embodiment, specifically, the first metal layer 102 is formed within the first dielectric layer. The first metal layer 102 is electrically connected to the device structure.

[0048] The method for forming the first metal layer 102 includes: forming a first trench (not shown in the figure) within the first dielectric layer, forming a first metal material layer (not shown in the figure) on the first trench and the surface of the first dielectric layer, and planarizing the first metal material layer until the surface of the first dielectric layer is exposed to form the first metal layer 102.

[0049] Before forming the first metal layer 102, a plurality of second metal layers are formed on the substrate 100, and a plurality of first conductive plugs are formed on the second metal layers. A plurality of the first electrodes 102a are located on the first conductive plugs, or after forming the first metal layer 102, a plurality of first conductive plugs are formed on the plurality of first electrodes 102a, and a plurality of second metal layers are formed. The second metal layers are also located on the first conductive plugs. The plurality of second metal layers are parallel to the second direction Y; before forming the first metal layer 102, a plurality of third metal layers are formed on the substrate 100, and a plurality of second conductive plugs are formed on the third metal layers. A plurality of the second electrodes 102b are located on the second conductive plugs, or after forming the first metal layer 102, a plurality of second conductive plugs are formed on the plurality of second electrodes 102b, and a plurality of third metal layers are formed. The third metal layers are also located on the second conductive plugs. The plurality of third metal layers are parallel to the second direction Y. In this embodiment, for the method of forming the second metal layer and the third metal layer, please refer to Figures 4 to 6 .

[0050] Please refer to FIGS. 4 to Figure 6 , Figure 4 is a top view, Figure 5 and Figure 4 is a schematic cross-sectional structure view along the Y1Y2 direction in Figure 6 and Figure 4 is a schematic cross-sectional structure view along the Y3Y4 direction in . After forming the first metal layer 102, a plurality of first conductive plugs 103 are formed on the plurality of first electrodes 102a, and a plurality of second metal layers 104 are formed. The second metal layers 104 are also located on the first conductive plugs 103, and the plurality of second metal layers 104 are parallel to the second direction Y. After forming the first metal layer 102, a plurality of second conductive plugs 105 are formed on the plurality of second electrodes 102b, and a plurality of third metal layers 106 are formed. The third metal layers 106 are also located on the second conductive plugs 105, and the plurality of third metal layers 106 are parallel to the second direction Y.

[0051] Specifically, after forming the first metal layer 102, a second dielectric layer 101 is formed on the substrate 100 and the first metal layer 102. The first conductive plugs 103 and the second conductive plugs 105 are also located within the second dielectric layer 101.

[0052] It should be noted that Figure 4 the top view of

[0053] omits the second dielectric layer 101 and the substrate 100.

[0054] The method for forming the first conductive plug 103 includes: forming a first through hole (not marked in the figure) within the second dielectric layer 101, the first through hole exposing the surface of the first electrode 102a, forming a first conductive plug material layer (not marked in the figure) within the first through hole and on the surface of the second dielectric layer, and planarizing the first conductive plug material layer until the surface of the second dielectric layer 101 is exposed, thereby forming the first conductive plug 103.

[0055] In this embodiment, the first conductive plug 103 and the second conductive plug 105 are formed in the same process, reducing the number of processes and lowering the production cost.

[0056] A first MOM capacitor device is formed between the first electrode 102a and the second electrode 102b. Multiple first electrodes 102a are electrically connected through the second metal layer 104 that is in a different layer from the first electrode 102a; multiple second electrodes 102b are electrically connected through the third metal layer 106 that is in a different layer from the second electrode 102b. The electrode ends of each metal layer do not need to be connected through thick electrode plates, which can reduce the area of the electrode ends of each metal layer, thereby increasing the number of electrode plates and further improving the density of the MOM capacitor.

[0057] The second metal layer 104 and the third metal layer 106 are located above or below the first metal layer 102. In this embodiment, the second metal layer 104 and the third metal layer 106 are located above the first metal layer 102.

[0058] In this embodiment, the second metal layer 104 and the third metal layer 106 are in the same layer. In other embodiments, the second metal layer 104 and the third metal layer 106 are in different layers.

[0059] In other embodiments, the second metal layer 104 is higher than the first metal layer 102, and the third metal layer 106 is lower than the first metal layer 102; or the second metal layer 104 is lower than the first metal layer 102, and the third metal layer 106 is higher than the first metal layer 102.

[0060] In this embodiment, the first metal layer 102 includes a first region I and a second region II. The first region I and the second region II are arranged along the first direction X, and the first region I and the second region II are respectively located at opposite ends of the first metal layer 102.

[0061] In this embodiment, each second metal layer 104 is electrically connected to multiple first electrodes 102a in the first region I; each third metal layer 106 is electrically connected to multiple second electrodes 102b in the second region II.

[0062] The number of second metal layers 104 connected to the first electrode 102a is 2 or 3; the number of third metal layers 106 connected to the second electrode 102b is 2 or 3. In this embodiment, the number of second metal layers 104 connected to the first electrode 102a is 2; the number of third metal layers 106 connected to the second electrode 102b is 2.

[0063] Correspondingly, the technical solution of the present invention also provides an embodiment of a semiconductor structure formed by the above formation method. Please continue to refer to Figures 4 to 6, comprising: a substrate 100; a first metal layer 102 located on the substrate 100, the first metal layer 102 including a plurality of first electrodes 102a and a plurality of second electrodes 102b, the plurality of first electrodes 102a and the plurality of second electrodes 102b being parallel to a first direction X and arranged along a second direction Y, each of the second electrodes 102b being located between two adjacent first electrodes 102a, the first direction X being perpendicular to the second direction Y; a plurality of second metal layers 104 located on the substrate 100, the second metal layers 104 being located on the first metal layer 102 or the first metal layer 102 being located on the second metal layers 104, the plurality of second metal layers 104 being parallel to the second direction Y, and each of the second metal layers 104 being electrically connected to a plurality of the first electrodes 102a respectively; a plurality of third metal layers 106 located on the substrate, the third metal layers 106 being located on the first metal layer 102 or the first metal layer 102 being located on the third metal layers 106, the plurality of third metal layers 106 being parallel to the second direction Y, and each of the third metal layers 106 being electrically connected to a plurality of the second electrodes 102b respectively.

[0064] A first MOM capacitor device is formed between the first electrode 102a and the second electrode 102b, and the plurality of first electrodes 102a are electrically connected through the second metal layer 104 in a layer different from the first electrode 102a; the plurality of second electrodes 102b are electrically connected through the third metal layer 106 in a layer different from the second electrode 102b. The electrode ends of each metal layer do not need to be connected through a thicker electrode plate, which can reduce the area of the electrode ends of each metal layer, thereby increasing the number of electrode plates and further improving the density of the MOM capacitor.

[0065] The second metal layer 104 and the third metal layer 106 are located above or below the first metal layer 102. In this embodiment, the second metal layer 104 is located on the first metal layer 102, the third metal layer 106 is located on the first metal layer 102, and the second metal layer 104 and the third metal layer 106 are located on the same layer. In other embodiments, the second metal layer 104 and the third metal layer 106 may be located on different layers.

[0066] In other embodiments, the second metal layer 104 is higher than the first metal layer 102, and the third metal layer 106 is lower than the first metal layer 102; or the second metal layer 104 is lower than the first metal layer 102, and the third metal layer 106 is higher than the first metal layer 102.

[0067] In this embodiment, the first metal layer 102 includes a first region I and a second region II. The first region I and the second region II are arranged along the first direction X, and the first region I and the second region II are respectively located at opposite ends of the first metal layer 102.

[0068] In this embodiment, each second metal layer 104 is electrically connected to a plurality of the first electrodes 102a in the first region I; each third metal layer 106 is electrically connected to a plurality of the second electrodes 102b in the second region II.

[0069] The number of the second metal layers 104 connected to the first electrodes 102a is two or three; the number of the third metal layers 106 connected to the second electrodes 102b is two or three. In this embodiment, the number of the second metal layers 104 connected to the first electrodes 102a is two; the number of the third metal layers 106 connected to the second electrodes 102b is two.

[0070] Figures 7 to 9 It is a schematic structural diagram corresponding to each step in the method for forming a semiconductor structure according to another embodiment of the present invention.

[0071] Please continue to refer to Figure 4 on the basis of Figure 7 to form a fourth metal layer 202 on the substrate 100. The fourth metal layer 202 includes a plurality of third electrodes 202a and a plurality of fourth electrodes 202b. The plurality of third electrodes 202a and the plurality of fourth electrodes 202b are parallel to the second direction Y and arranged along the first direction X. Each of the fourth electrodes 202b is located between two adjacent third electrodes 202a.

[0072] Before forming the fourth metal layer 202, a plurality of fifth metal layers are formed on the substrate 100, and a plurality of third conductive plugs are formed on the fifth metal layers. A plurality of the third electrodes 202a are located on the third conductive plugs. Alternatively, after forming the fourth metal layer 202, a plurality of third conductive plugs are formed on a plurality of the third electrodes 202a, and a plurality of fifth metal layers are formed. The plurality of fifth metal layers are also located on the third conductive plugs. The plurality of fifth metal layers are parallel to the first direction X. Before forming the fourth metal layer 202, a plurality of sixth metal layers are formed on the substrate 100, and a plurality of fourth conductive plugs are formed on the sixth metal layers. A plurality of the fourth electrodes 202b are located on the fourth conductive plugs. Alternatively, after forming the fourth metal layer 202, a plurality of fourth conductive plugs are formed on a plurality of the fourth electrodes 202b, and a plurality of sixth metal layers are formed. The plurality of sixth metal layers are also located on the fourth conductive plugs. The plurality of sixth metal layers are parallel to the first direction X. In this embodiment, for the formation methods of the fifth metal layer and the sixth metal layer, please continue to refer to Figures 7 to 9 。

[0073] Please refer to Figures 7 to 9 , Figure 7 which is a top view, Figure 8 is Figure 7 a schematic cross-sectional structure diagram along the X1X2 direction in Figure 9 is Figure 7 a schematic cross-sectional structure diagram along the X3X4 direction in. Before forming the fourth metal layer 202, a plurality of fifth metal layers 204 are formed on the substrate 100, and a plurality of third conductive plugs 205 are formed on the fifth metal layers 204. A plurality of the third electrodes 202a are located on the third conductive plugs 205. Before forming the fourth metal layer 202, a plurality of sixth metal layers 206 are formed on the substrate 100, and a plurality of fourth conductive plugs 207 are formed on the sixth metal layers 206. A plurality of the fourth electrodes 202b are located on the fourth conductive plugs 207. The plurality of sixth metal layers 206 are parallel to the first direction X.

[0074] In this embodiment, specifically, the fifth metal layer 204 and the sixth metal layer 206 are formed in the first dielectric layer. The fifth metal layer 204, the sixth metal layer 206, and the first metal layer 102 are formed simultaneously to reduce the process steps and lower the production cost.

[0075] In this embodiment, specifically, the fourth metal layer 202 is formed on the second dielectric layer 101. The third conductive plug 203 and the fourth conductive plug 207 are located in the second dielectric layer 101.

[0076] It should be noted thatFigure 7 The top view of

[0077] A second MOM capacitor device is formed between the third electrode 202a and the fourth electrode 202b. Multiple third electrodes 202a are electrically connected through the fifth metal layer 204 which is in a different layer from the third electrode 202a; multiple fourth electrodes 202b are electrically connected through the sixth metal layer 206 which is in a different layer from the fourth electrode 202b. The electrode ends of each metal layer do not need to be connected through a thicker electrode plate, which can reduce the area of the electrode ends of each metal layer, thereby increasing the number of electrode plates, and further improving the density of the MOM capacitor.

[0078] In this embodiment, the fifth metal layer 204 and the sixth metal layer 206 are in the same layer. In other embodiments, the fifth metal layer 204 and the sixth metal layer 206 are in different layers.

[0079] The fifth metal layer 204 and the sixth metal layer 206 are located above or below the fourth metal layer 202. In this embodiment, the fifth metal layer 204 and the sixth metal layer 206 are located below the fourth metal layer 202.

[0080] In another embodiment, the fifth metal layer 204 is higher than the fourth metal layer 202, and the sixth metal layer 206 is lower than the fourth metal layer 202; or the fifth metal layer 204 is lower than the fourth metal layer 202, and the sixth metal layer 206 is higher than the fourth metal layer 202.

[0081] In this embodiment, the fourth metal layer 202 includes a third region III and a fourth region IV. The third region III and the fourth region IV are arranged along the second direction Y, and the third region III and the fourth region IV are respectively located at opposite ends of the fourth metal layer 202.

[0082] Each fifth metal layer 204 is electrically connected to multiple third electrodes 202a in the third region III; each sixth metal layer 206 is electrically connected to multiple fourth electrodes 202b in the fourth region IV.

[0083] The distance a between the second metal layer 104 and the fourth metal layer 202 in the direction parallel to the surface of the substrate 100 ranges from 10 nanometers to 80 nanometers; the distance b between the third metal layer 106 and the fourth metal layer 202 in the direction parallel to the surface of the substrate 100 ranges from 10 nanometers to 80 nanometers; the distance c between the fifth metal layer 204 and the first metal layer 102 in the direction parallel to the surface of the substrate 100 ranges from 10 nanometers to 80 nanometers; the distance d between the sixth metal layer 206 and the first metal layer 102 in the direction parallel to the surface of the substrate 100 ranges from 10 nanometers to 80 nanometers.

[0084] Any one of the fourth metal layer 202, the fifth metal layer 204, and the sixth metal layer 206 can be located in the same layer as one or more of the first metal layer 102, the second metal layer 104, and the third metal layer 106. In this embodiment, the fifth metal layer 204, the sixth metal layer 206, and the first metal layer 102 are located in the same layer; the second metal layer 104, the third metal layer 106, and the fourth metal layer 202 are located in the same layer.

[0085] The number of the fifth metal layers 204 electrically connected to the third electrode 202a is 2 or 3; the number of the sixth metal layers 206 electrically connected to the fourth electrode 202b is 2 or 3. In this embodiment, the number of the fifth metal layers 204 electrically connected to the third electrode 202a is 2; the number of the sixth metal layers 206 electrically connected to the fourth electrode 202b is 2.

[0086] Correspondingly, the technical solution of the present invention also provides an embodiment of a semiconductor structure formed by the above forming method. Please continue to refer to Figures 7 to 9, including: a fourth metal layer 202 located on a substrate 100, the fourth metal layer 202 including a plurality of third electrodes 202a and a plurality of fourth electrodes 202b, the plurality of third electrodes 202a and the plurality of fourth electrodes 202b being parallel to a second direction Y and arranged along a first direction X, each of the fourth electrodes 202b being located between two adjacent third electrodes 202a; a plurality of fifth metal layers 204 located on the substrate 100, the fifth metal layer 204 being located on the fourth metal layer 202 or the fourth metal layer 202 being located on the fifth metal layer 204, the plurality of fifth metal layers 204 being parallel to the first direction X, and each of the fifth metal layers 204 being electrically connected to a plurality of the third electrodes 202a respectively; a plurality of sixth metal layers 206 located on the substrate, the sixth metal layer 206 being located on the fourth metal layer 202 or the fourth metal layer 202 being located on the sixth metal layer 206, the plurality of sixth metal layers 206 being parallel to the first direction X, and each sixth metal layer 206 being electrically connected to a plurality of the fourth electrodes 202b respectively.

[0087] A second MOM capacitor device is formed between the third electrode 202a and the fourth electrode 202b, and a plurality of the third electrodes 202a are electrically connected through the fifth metal layer 204 in a layer different from the third electrode 202a; a plurality of the fourth electrodes 202b are electrically connected through the sixth metal layer 206 in a layer different from the fourth electrode 202b. The electrode ends of each metal layer do not need to be connected through a thick electrode plate, which can reduce the area of the electrode ends of each metal layer, thereby increasing the number of electrode plates, and further improving the density of the MOM capacitor.

[0088] In this embodiment, the fifth metal layer 204 and the sixth metal layer 206 are in the same layer. In other embodiments, the fifth metal layer 204 and the sixth metal layer 206 are in different layers.

[0089] The fifth metal layer 204 and the sixth metal layer 206 are located above or below the fourth metal layer 202. In this embodiment, the fifth metal layer 204 and the sixth metal layer 206 are located below the fourth metal layer 202.

[0090] In another embodiment, the fifth metal layer 204 is higher than the fourth metal layer 202, and the sixth metal layer 206 is lower than the fourth metal layer 202; or the fifth metal layer 204 is lower than the fourth metal layer 202, and the sixth metal layer 206 is higher than the fourth metal layer 202.

[0091] In this embodiment, the fourth metal layer 202 includes a third region III and a fourth region IV. The third region III and the fourth region IV are arranged along the second direction Y, and the third region III and the fourth region IV are respectively located at opposite ends of the fourth metal layer 202.

[0092] Each fifth metal layer 204 is electrically connected to a plurality of the third electrodes 202a in the third region III; each sixth metal layer 206 is electrically connected to a plurality of the fourth electrodes 202b in the fourth region IV.

[0093] The distance a between the second metal layer 104 and the fourth metal layer 202 in the direction parallel to the surface of the substrate 100 ranges from 10 nanometers to 80 nanometers; the distance b between the third metal layer 106 and the fourth metal layer 202 in the direction parallel to the surface of the substrate 100 ranges from 10 nanometers to 80 nanometers; the distance c between the fifth metal layer 204 and the first metal layer 102 in the direction parallel to the surface of the substrate 100 ranges from 10 nanometers to 80 nanometers; the distance d between the sixth metal layer 206 and the first metal layer 102 in the direction parallel to the surface of the substrate 100 ranges from 10 nanometers to 80 nanometers.

[0094] Any one of the fourth metal layer 202, the fifth metal layer 204, and the sixth metal layer 206 can be located in the same layer as one or more of the first metal layer 102, the second metal layer 104, and the third metal layer 106. In this embodiment, the fifth metal layer 204, the sixth metal layer 206, and the first metal layer 102 are located in the same layer; the second metal layer 104, the third metal layer 106, and the fourth metal layer 202 are located in the same layer.

[0095] The number of the fifth metal layers 204 electrically connected to the third electrodes 202a is 2 or 3; the number of the sixth metal layers 206 electrically connected to the fourth electrodes 202b is 2 or 3. In this embodiment, the number of the fifth metal layers 204 electrically connected to the third electrodes 202a is 2; the number of the sixth metal layers 206 electrically connected to the fourth electrodes 202b is 2.

[0096] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, it includes: a substrate; a first metal layer located on the substrate, the first metal layer includes a first region and a second region, the first region and the second region are arranged along a first direction, and the first region and the second region are respectively located at opposite ends of the first metal layer, the first metal layer further includes an intermediate region located between the first region and the second region, the first metal layer includes a plurality of first electrodes and a plurality of second electrodes, the plurality of first electrodes and the plurality of second electrodes are parallel to the first direction and arranged along a second direction, each of the second electrodes is located between two adjacent first electrodes, and the first direction is perpendicular to the second direction; a plurality of second metal layers located on the substrate, the number of the second metal layers is two or three, the second metal layers are located on the first metal layer or the first metal layer is located on the second metal layers, and the plurality of second metal layers are parallel to the second direction; a plurality of first conductive plugs located between the first region and the second metal layers, electrically connecting each of the second metal layers to the plurality of first electrodes in the first region, and the plurality of first conductive plugs are located at one end of the first metal layer; a plurality of third metal layers located on the substrate, the number of the third metal layers is two or three, the third metal layers are located on the first metal layer or the first metal layer is located on the third metal layers, and the plurality of third metal layers are parallel to the second direction; a plurality of second conductive plugs located between the second region and the third metal layers, electrically connecting each of the third metal layers to the plurality of second electrodes in the second region, and the plurality of second conductive plugs are located at the other end of the first metal layer.

2. The semiconductor structure according to claim 1, characterized in that, the second metal layer and the third metal layer are located on the same layer.

3. The semiconductor structure according to claim 2, characterized in that, the second metal layer and the third metal layer are located above or below the first metal layer.

4. The semiconductor structure according to claim 1, characterized in that, the second metal layer and the third metal layer are located on different layers.

5. The semiconductor structure according to claim 4, characterized in that, the second metal layer is higher than the first metal layer, and the third metal layer is lower than the first metal layer; or the second metal layer is lower than the first metal layer, and the third metal layer is higher than the first metal layer.

6. The semiconductor structure according to claim 1, characterized in that, the number of the second metal layers connected to the first electrodes is two or three; the number of the third metal layers connected to the second electrodes is two or three.

7. The semiconductor structure according to claim 1, characterized in that, it further includes: A fourth metal layer located on a substrate, the fourth metal layer including a plurality of third electrodes and a plurality of fourth electrodes, the plurality of third electrodes and the plurality of fourth electrodes being parallel to a second direction and arranged along a first direction, each of the fourth electrodes being located between two adjacent third electrodes; a plurality of fifth metal layers located on the substrate, the fifth metal layer being located on the fourth metal layer or the fourth metal layer being located on the fifth metal layer, the plurality of fifth metal layers being parallel to the first direction, and each of the fifth metal layers being electrically connected to a plurality of the third electrodes respectively; a plurality of sixth metal layers located on the substrate, the sixth metal layer being located on the fourth metal layer or the fourth metal layer being located on the sixth metal layer, the plurality of sixth metal layers being parallel to the first direction, and each sixth metal layer being electrically connected to a plurality of the fourth electrodes respectively.

8. The semiconductor structure according to claim 7, wherein, the fifth metal layer and the sixth metal layer are located on the same layer.

9. The semiconductor structure according to claim 8, wherein, the fifth metal layer and the sixth metal layer are located above or below the fourth metal layer.

10. The semiconductor structure according to claim 7, wherein, the fifth metal layer and the sixth metal layer are located on different layers.

11. The semiconductor structure according to claim 10, wherein, the fifth metal layer is higher than the fourth metal layer, and the sixth metal layer is lower than the fourth metal layer; or the fifth metal layer is lower than the fourth metal layer, and the sixth metal layer is higher than the fourth metal layer.

12. The semiconductor structure according to claim 7, wherein, the fourth metal layer includes a third region and a fourth region, the third region and the fourth region are arranged along the second direction, and the third region and the fourth region are respectively located at opposite ends of the fourth metal layer.

13. The semiconductor structure according to claim 12, wherein, each fifth metal layer is electrically connected to a plurality of the third electrodes in the third region respectively; each sixth metal layer is electrically connected to a plurality of the fourth electrodes in the fourth region respectively.

14. The semiconductor structure according to claim 13, wherein, the distance between the second metal layer and the fourth metal layer in a direction parallel to the surface of the substrate ranges from 10 nanometers to 80 nanometers; the distance between the third metal layer and the fourth metal layer in a direction parallel to the surface of the substrate ranges from 10 nanometers to 80 nanometers; the distance between the fifth metal layer and the first metal layer in a direction parallel to the surface of the substrate ranges from 10 nanometers to 80 nanometers; the distance between the sixth metal layer and the first metal layer in a direction parallel to the surface of the substrate ranges from 10 nanometers to 80 nanometers.

15. The semiconductor structure according to claim 7, wherein, any one of the fourth metal layer, the fifth metal layer, and the sixth metal layer can be located on the same layer as one or more of the first metal layer, the second metal layer, and the third metal layer.

16. The semiconductor structure according to claim 7, wherein, The number of the fifth metal layers electrically connected to the third electrode is two or three; the number of the sixth metal layers electrically connected to the fourth electrode is two or three.

17. A method for forming a semiconductor structure, characterized in that, comprising: providing a substrate; forming a first metal layer on the substrate, the first metal layer including a first region and a second region, the first region and the second region being arranged along a first direction, and the first region and the second region being respectively located at opposite ends of the first metal layer, the first metal layer further including an intermediate region between the first region and the second region, the first metal layer including a plurality of first electrodes and a plurality of second electrodes, the plurality of first electrodes and the plurality of second electrodes being parallel to the first direction and arranged along a second direction, each of the second electrodes being located between two adjacent first electrodes, the first direction being perpendicular to the second direction; before forming the first metal layer, forming a plurality of second metal layers on the substrate, the number of the second metal layers being two or three, and forming a plurality of first conductive plugs on the second metal layers, the plurality of first electrodes in the first region being located on the first conductive plugs, or after forming the first metal layer, forming a plurality of first conductive plugs on the plurality of first electrodes in the first region, and forming a plurality of second metal layers, the second metal layers further being located on the first conductive plugs, the plurality of second metal layers being parallel to the second direction; before forming the first metal layer, forming a plurality of third metal layers on the substrate, the number of the third metal layers being two or three, and forming a plurality of second conductive plugs on the third metal layers, the plurality of second electrodes in the second region being located on the second conductive plugs, or after forming the first metal layer, forming a plurality of second conductive plugs on the plurality of second electrodes in the second region, and forming a plurality of third metal layers, the third metal layers further being located on the second conductive plugs, the plurality of third metal layers being parallel to the second direction.

18. The method for forming a semiconductor structure according to claim 17, characterized in that, further comprising: A fourth metal layer is formed on the substrate. The fourth metal layer includes a plurality of third electrodes and a plurality of fourth electrodes. The plurality of third electrodes and the plurality of fourth electrodes are parallel to the second direction and arranged along the first direction. Each of the fourth electrodes is located between two adjacent third electrodes. Before forming the fourth metal layer, a plurality of fifth metal layers are formed on the substrate, and a plurality of third conductive plugs are formed on the fifth metal layers. A plurality of the third electrodes are located on the third conductive plugs. Alternatively, after forming the fourth metal layer, a plurality of third conductive plugs are formed on the plurality of third electrodes, and a plurality of fifth metal layers are formed. The plurality of fifth metal layers are also located on the third conductive plugs. The plurality of fifth metal layers are parallel to the first direction. Before forming the fourth metal layer, a plurality of sixth metal layers are formed on the substrate, and a plurality of fourth conductive plugs are formed on the sixth metal layers. A plurality of the fourth electrodes are located on the fourth conductive plugs. Alternatively, after forming the fourth metal layer, a plurality of fourth conductive plugs are formed on the plurality of fourth electrodes, and a plurality of sixth metal layers are formed. The plurality of sixth metal layers are also located on the fourth conductive plugs. The plurality of sixth metal layers are parallel to the first direction.

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