Power amplification module

Abstract

The present application realizes a power amplification module capable of inhibiting characteristic deterioration caused by asymmetry of a differential signal. A power amplification module, in which a plurality of differential amplification circuits are mounted on a substrate, wherein the differential amplification circuit includes: a chip device (100) including at least two amplifiers that respectively amplify a differential signal; a balun including a primary winding (41) and a secondary winding, both ends of the primary winding being connected to outputs of the chip device (100); and a capacitor (CB2) provided between a power supply point (P) of the primary winding (41) and a reference potential. In at least one of the plurality of differential amplification circuits, a distance from one end of the primary winding (41) to the power supply point (P) and a distance from the other end of the primary winding (41) to the power supply point (P) are different.

Description

TECHNICAL FIELD

[0001] The present application relates to a power amplification module. BACKGROUND

[0002] In a power amplifier mounted on a wireless communication terminal device, the power of a single-ended signal (unbalanced signal) is amplified and the single-ended signal is output. As one example of the structure of such a power amplifier, there is a differential amplification circuit that converts a single-ended signal into a pair of differential signals (balanced signals), amplifies the differential signals with two amplifiers, respectively, and converts the amplified differential signals into a single-ended signal. In this structure, the emitter inductance of a transistor with respect to the differential signals becomes zero, so the gain of the power amplifier can be easily increased. In Patent Literature 1 described below, a stable semiconductor integrated circuit that can well balance the differential signals is disclosed.

[0003] PRIOR ART LITERATURE

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Laid-Open No. 8-18005

[0006] In a differential amplification circuit, the asymmetry of differential signals caused by the characteristic deviation of amplifiers, the arrangement of components, and the like becomes a problem. In particular, in a structure in which differential amplification circuits for a plurality of communication bands are mounted on one module, the asymmetry of differential signals is easily generated due to interference between the differential amplification circuits and the like. SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] The present disclosure was completed in view of the above-described circumstances, and aims to realize a power amplification module that can suppress characteristic degradation caused by the asymmetry of differential signals.

[0009] TECHNICAL SOLUTION FOR SOLVING THE PROBLEM

[0010] The power amplification module of one aspect of the present disclosure is a power amplification module in which a plurality of differential amplification circuits are mounted on a substrate, wherein the differential amplification circuit includes: a chip device including at least two amplifiers that amplify differential signals, respectively; a balun including a primary winding and a secondary winding, both ends of the primary winding being connected to outputs of the chip device; and a capacitor provided between a power supply point of the primary winding and a reference potential, and in at least one of the plurality of differential amplification circuits, a distance from one end of the primary winding to the power supply point and a distance from the other end of the primary winding to the power supply point are different.

[0011] In this configuration, the gain difference and the phase difference of the differential signal can be reduced, and the asymmetry of the differential signal can be improved. Thus, the characteristic deterioration caused by the asymmetry of the differential signal can be suppressed.

[0012] Effects of Invention

[0013] According to the present disclosure, a power amplification module capable of suppressing the characteristic deterioration caused by the asymmetry of the differential signal can be implemented. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a schematic diagram showing one example of a circuit block configuration of a power amplification module to which the embodiments are related.

[0015] Figure 2 is a diagram showing a differential amplification circuit of a power amplification module to which the embodiments are related.

[0016] Figure 3A is a diagram showing a component configuration example for improving the asymmetry of a differential signal in a power amplification module to which Embodiment 1 is related.

[0017] Figure 3B is a diagram showing a component configuration example for improving the asymmetry of a differential signal in a power amplification module to which Embodiment 1 is related.

[0018] Figure 3C is a diagram showing a component configuration example for improving the asymmetry of a differential signal in a power amplification module to which Embodiment 1 is related.

[0019] Figure 4 is a diagram showing an asymmetry improvement example of a differential signal in a power amplification module to which Embodiment 1 is related.

[0020] Figure 5 is a diagram showing a component configuration example for improving the asymmetry of a differential signal in a power amplification module to which Modified Example 1 of Embodiment 1 is related.

[0021] Figure 6 is a diagram showing an asymmetry improvement example of a differential signal in a power amplification module to which Modified Example 1 of Embodiment 1 is related.

[0022] Figure 7 is a diagram showing a component configuration example for improving the asymmetry of a differential signal in a power amplification module to which Modified Example 2 of Embodiment 1 is related.

[0023] Figure 8 is a diagram showing an asymmetry improvement example of a differential signal in a power amplification module to which Modified Example 2 of Embodiment 1 is related.

[0024] Figure 9FIG. 2 is a diagram showing an example of the asymmetry improvement of the differential signal in the power amplification module according to Embodiment 1.

[0025] Figure 10A FIG. 3 is a diagram showing an example of the asymmetry improvement of the differential signal in the power amplification module according to Embodiment 2.

[0026] Figure 10B FIG. 4 is a diagram showing an example of the asymmetry improvement of the differential signal in the power amplification module according to Embodiment 2.

[0027] Figure 10C FIG. 5 is a diagram showing an example of the asymmetry improvement of the differential signal in the power amplification module according to Embodiment 2.

[0028] Figure 10D FIG. 6 is a diagram showing an example of the asymmetry improvement of the differential signal in the power amplification module according to Embodiment 2.

[0029] Figure 11A FIG. 7 is a diagram showing an example of the asymmetry improvement of the differential signal in the power amplification module according to Embodiment 2.

[0030] Figure 11B FIG. 8 is a diagram showing an example of the asymmetry improvement of the differential signal in the power amplification module according to Embodiment 2.

[0031] Figure 12 FIG. 9 is a diagram showing an example of the configuration of the plurality of differential amplification circuits on the power amplification module according to Embodiment 3.

[0032] Explanation of Reference Numerals

[0033] 1: Power amplification module

[0034] 2: Substrate

[0035] 4: Balun

[0036] 21, 22: Amplifier

[0037] 41, 41a, 41b: Inductor (primary winding)

[0038] 42: Inductor (secondary winding)

[0039] 100, 100a, 100b: Chip device

[0040] C1, C2, C3, C3a, CB1, CB1a, CB2, CB2a, CB2b: Capacitor

[0041] FP1, FP2: Mounting terminal

[0042] L: center line;

[0043] LB, LBa: inductor;

[0044] P: power supply point;

[0045] TH, TH1, TH2: through hole;

[0046] VCC: power supply potential;

[0047] WS: winding shaft. DETAILED DESCRIPTION

[0048] Hereinafter, a power amplification module according to the embodiment will be described in detail based on the drawings. In addition, the present disclosure is not limited to this embodiment.

[0049] Figure 1 is a schematic diagram showing one example of a circuit block structure of a power amplification module according to the embodiment. The power amplification module 1 according to the embodiment is an ultra-small integrated module in which a plurality of integrated circuits and various functional components are integrated on a substrate 2. As the substrate 2, for example, a ceramic laminated substrate such as an LTCC (Low Temperature Co-fired Ceramics) substrate can be exemplified. Hereinafter, first, the circuit block structure shown in Figure 1 will be described.

[0050] As shown in Figure 1 , as one example, the front-end module 1 according to the embodiment 1 is provided with a 1st power amplifier circuit (hereinafter, also referred to as "PA1"), a 2nd power amplifier circuit (hereinafter, also referred to as "PA2"), a 1st low noise amplifier (hereinafter, also referred to as "LNA1"), a 2nd low noise amplifier (hereinafter, also referred to as "LNA2"), a 3rd low noise amplifier (hereinafter, also referred to as "LNA3"), a 4th low noise amplifier (hereinafter, also referred to as "LNA4"), a 1st filter circuit (hereinafter, also referred to as "FIL1"), a 2nd filter circuit (hereinafter, also referred to as "FIL2"), a 3rd filter circuit (hereinafter, also referred to as "FIL3"), a 4th filter circuit (hereinafter, also referred to as "FIL4"), a 5th filter circuit (hereinafter, also referred to as "FIL5"), a transceiver switching circuit (hereinafter, also referred to as "TX / RX SW"), and an antenna switching circuit (hereinafter, also referred to as "ANT SW").

[0051] The PA1, the LNA1, the LNA2, the FIL1, the FIL3, and the FIL4 perform, for example, transceiving of the frequency band "n79". The PA2, the LNA3, the LNA4, the FIL2, the FIL5, and the TX / RX SW perform, for example, transceiving of the frequency band "n77". In addition, the PA1 and the PA2 are not limited to the frequency band "n79" and the frequency band "n77" as the transmission frequency band to be amplified.

[0052] The PA1 amplifies the first transmission signal input from the transmission signal input terminal TX1. The PA2 amplifies the second transmission signal input from the transmission signal input terminal TX2. In the present disclosure, the PA1 and the PA2 are differential amplification circuits that amplify a single-ended signal by converting it into a pair of differential signals (balanced signals) and convert the amplified differential signals into a single-ended signal.

[0053] The PA1 and the PA2 can include, for example, bipolar transistors or can include, for example, field effect transistors (FETs). In the case where the PA1 and the PA2 include bipolar transistors, a heterojunction bipolar transistor (HBT) can be exemplified, for example. The present disclosure is not limited to the specific structure of the PA1 and the PA2.

[0054] The LNA1 amplifies a reception signal input from the antenna terminals ANT1, ANT2 via the FIL3. For example, in the circuit block structure illustrated in FIG. 1, the reception signal amplified by the LNA1 is output from the reception signal output terminal RX1. Figure 1 The LNA1 amplifies a reception signal input from the antenna terminals ANT1, ANT2 via the FIL3. For example, in the circuit block structure illustrated in FIG. 1, the reception signal amplified by the LNA1 is output from the reception signal output terminal RX1.

[0055] The LNA2 amplifies a reception signal input from the antenna terminals ANT1, ANT2 via the FIL4. For example, in the circuit block structure illustrated in FIG. 1, the reception signal amplified by the LNA2 is output from the reception signal output terminal RX2. Figure 1 The LNA2 amplifies a reception signal input from the antenna terminals ANT1, ANT2 via the FIL4. For example, in the circuit block structure illustrated in FIG. 1, the reception signal amplified by the LNA2 is output from the reception signal output terminal RX2.

[0056] The LNA3 amplifies a reception signal input from the antenna terminals ANT1, ANT2 via the FIL5. For example, in the circuit block structure illustrated in FIG. 1, the reception signal amplified by the LNA3 is output from the reception signal output terminal RX3. Figure 1 The LNA3 amplifies a reception signal input from the antenna terminals ANT1, ANT2 via the FIL5. For example, in the circuit block structure illustrated in FIG. 1, the reception signal amplified by the LNA3 is output from the reception signal output terminal RX3.

[0057] In the circuit block structure illustrated in FIG. 1, the TX / RX SW switches the transmission signal input from the PA2 and the reception signal to the LNA4. Specifically, the TX / RX SW outputs the transmission signal input from the PA2 to the FIL2. In addition, the TX / RX SW outputs the reception signal input from the antenna terminals ANT1, ANT2 via the FIL2 to the LNA4. Figure 1 In the circuit block structure illustrated in FIG. 1, the TX / RX SW switches the transmission signal input from the PA2 and the reception signal to the LNA4. Specifically, the TX / RX SW outputs the transmission signal input from the PA2 to the FIL2. In addition, the TX / RX SW outputs the reception signal input from the antenna terminals ANT1, ANT2 via the FIL2 to the LNA4.

[0058] LNA4 amplifies a reception signal input from the TX / RX SW. For example, in the circuit block structure shown in FIG. 4, the reception signal amplified by the LNA4 is output from a reception signal output terminal RX4. Figure 1

[0059] FIL1 filters a transmission signal output from the PA1 and outputs to the ANTSW.

[0060] FIL2 filters a transmission signal input from the PA2 via the TX / RX SW and outputs to the ANTSW. In addition, FIL2 filters a reception signal input from the ANTSW and outputs to the LNA4 via the TX / RX SW.

[0061] ANTSW switches a transmission path and a reception path of a transmission signal and a reception signal. Specifically, ANTSW switches an output destination (antenna terminal ANT1, ANT2) of a transmission signal input from FIL1. In addition, ANTSW switches an output destination (antenna terminal ANT1, ANT2) of a transmission signal input from FIL2. In addition, ANTSW switches an output destination (FIL2, FIL3, FIL4, FIL5) of a reception signal input from the antenna terminal ANT1, ANT2. Further, although a structure having two antenna terminals ANT1, ANT2 is exemplified in FIG. 4, the number of antenna terminals is not limited thereto. Figure 1

[0062] The above-described Figure 1 The circuit block structure shown in FIG. 4 is one example, and the present disclosure is not limited to the structure of the power amplification module 1 involved in the embodiment.

[0063] Figure 2 is a diagram showing a differential amplification circuit of a power amplification module involved in the embodiment. Further, in the following description, in the case where the 1st power amplifier circuit PA1 and the 2nd power amplifier circuit PA2 are not particularly distinguished, it is simply referred to as "differential amplification circuit PA". In addition, in the case where the 1st power amplifier circuit PA1 and the 2nd power amplifier circuit PA2 are distinguished, the 1st power amplifier circuit PA1 is also referred to as "differential amplification circuit PA1", and the 2nd power amplifier circuit PA2 is also referred to as "differential amplification circuit PA2".

[0064] ​​In the present disclosure, the differential amplification circuit PA includes the chip device 100 mounted on the substrate 2. The chip device 100 includes, for example, an HBT. The chip device 100 includes amplifiers 21, 22. The amplifier 21 amplifies a differential signal RF_INP and outputs from an output OUTP of the chip device 100. The amplifier 22 amplifies a differential signal RF_INN and outputs from an output OUTN of the chip device 100.

[0065] The peripheral circuit components of the differential amplification circuit PA are mounted on the periphery of the chip device 100. In the example shown in FIG. 1, the inductor LB and the capacitors C1, C2, C3, CB1, CB2 are SMD components mounted on the surface layer of the substrate 2. Further, the balun 4 includes a conductor provided on the surface layer or the inner layer of the substrate 2. Figure 2

[0066] The balun 4 includes an inductor 41 as a winding of a primary side and an inductor 42 as a winding of a secondary side. The inductor 41 and the inductor 42 are magnetically coupled. One end of the inductor 41 is connected to the output OUTP of the amplifier 21. The other end of the inductor 41 is connected to the output OUTN of the amplifier 22.

[0067] At a power supply point P of the inductor 41, a power supply potential VCC is supplied via the inductor LB. The capacitors CB1, CB2 are provided between the supply path of the power supply potential VCC and a reference potential (here, a ground potential GND).

[0068] The capacitors C1, C2 are components that constitute an output matching circuit of the differential amplification circuit PA. Here, in a region where the transmission band is high like the frequency band "n79", there is a case where matching of the inductance value and the coupling coefficient of the balun 4 cannot be achieved. In the present disclosure, it is preferable to configure as shown in FIG. 2, outputting the transmission signal RF_OUT from one end of the inductor 42 connected to the output matching circuit, and providing the capacitor C3 between the other end of the inductor 42 and the reference potential (here, the ground potential GND), thereby achieving impedance matching. Note that, in the PA 2 (refer to FIG. 3) that amplifies the frequency band "n77" lower than the frequency band "n79", the capacitor C3 is not necessarily required. Further, as the PA 2 that amplifies "n77", the circuit structure shown in FIG. 4 can also be used. Figure 2 Figure 1 Figure 2

[0069] In such a differential amplification circuit, the asymmetry of the differential signal becomes a problem due to a characteristic deviation of the amplifier and the like. Hereinafter, a structure that suppresses characteristic degradation caused by the asymmetry of the differential signal in the power amplification module 1 according to the embodiment will be described. ​​​​

[0070] (Embodiment 1)

[0071] Figure 3A 、 Figure 3B 、 Figure 3C is a diagram showing a configuration example of a component that improves asymmetry of a differential signal in the power amplification module according to Embodiment 1. Figure 3A shows a surface layer pattern of the substrate 2 on which the chip component 100 and the SMD component are mounted, Figure 3B and Figure 3C shows an inner layer pattern of the substrate 2. Figure 3B and Figure 3C show inner layer patterns of different layers, respectively.

[0072] As shown in Figure 3A , in Embodiment 1, as the surface layer pattern of the substrate 2, the inductor 41 of the balun 4 is provided. Further, as shown in Figure 3B and Figure 3C , in Embodiment 1, as the inner layer pattern of the substrate 2, the inductor 42 of the balun 4 is provided. Figure 3B The inner layer pattern of the inductor 42 shown in Figure 3C and the inner layer pattern of the inductor 42 shown in are connected by a via TH.

[0073] In Embodiment 1, by adjusting a ratio of a distance from one end of the inductor 41 to the power supply point P of the power supply potential VCC and a distance from the other end of the inductor 41 to the power supply point P of the power supply potential VCC (hereinafter, also simply referred to as a "wiring length ratio"), the asymmetry of the differential signal is improved. Specifically, as shown in Figure 3A , the distance from one end of the inductor 41 to the power supply point P of the power supply potential VCC and the distance from the other end of the inductor 41 to the power supply point P of the power supply potential VCC are made different. In other words, the power supply point P of the power supply potential VCC is provided at a position deviated from the center line L that bisects the wiring length of the inductor 41. In addition, the "distance" referred to herein, for example, refers to "wiring length", and refers to the wiring length from one end of the inductor 41 to the power supply point P of the power supply potential VCC and the wiring length from the other end of the inductor 41 to the power supply point P of the power supply potential VCC.

[0074] Figure 4 is a diagram showing an example of improvement of asymmetry of a differential signal in the power amplification module according to Embodiment 1. In Figure 4 , the horizontal axis shows a wiring length ratio of the inductor 41, and the vertical axis shows a gain difference and a phase difference between differential signals. Figure 4 The solid line shown in shows a gain difference between differential signals, and the dashed line shows a phase difference between differential signals.

[0075] As Figure 4 indicated, by adjusting the wiring length ratio of the inductor 41, the gain difference and the phase difference of the differential signal can be reduced, and the asymmetry of the differential signal can be improved. Thus, the characteristic deterioration caused by the asymmetry of the differential signal can be suppressed.

[0076] In addition, Figure 3A the above-described manner is one example, and other manners can also be employed. Figure 5 is a diagram illustrating a component configuration example in which the asymmetry of the differential signal is improved in the power amplification module according to the modified example 1 of Embodiment 1. Figure 6 is a diagram illustrating an asymmetry improvement example of the differential signal in the power amplification module according to the modified example 1 of Embodiment 1. Figure 7 is a diagram illustrating a component configuration example in which the asymmetry of the differential signal is improved in the power amplification module according to the modified example 2 of Embodiment 1. Figure 8 is a diagram illustrating an asymmetry improvement example of the differential signal in the power amplification module according to the modified example 2 of Embodiment 1.

[0077] For example, as Figure 5 indicated, it can also be a manner in which the distance from the other end of the inductor 41 to the power supply point P of the power supply potential VCC is made shorter than the distance from one end of the inductor 41 to the power supply point P of the power supply potential VCC. Thus, as Figure 6 indicated, the gain difference and the phase difference of the differential signal can be reduced, and the asymmetry of the differential signal can be improved. Thus, the characteristic deterioration caused by the asymmetry of the differential signal can be suppressed.

[0078] Alternatively, as Figure 7 indicated, it can also be a manner in which the distance from one end of the inductor 41 to the power supply point P of the power supply potential VCC is made longer than the distance from the other end of the inductor 41 to the power supply point P of the power supply potential VCC. Thus, as Figure 8 indicated, the gain difference and the phase difference of the differential signal can be reduced, and the asymmetry of the differential signal can be improved. Thus, the characteristic deterioration caused by the asymmetry of the differential signal can be suppressed.

[0079] (Embodiment 2)

[0080] Figure 9 is a diagram illustrating an asymmetry improvement example of the differential signal in the power amplification module according to the modified example 1 of Embodiment 1. Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D is a diagram illustrating a component configuration example in which the asymmetry of the differential signal is improved in the power amplification module according to the modified example 1 of Embodiment 1. Figure 11A, Figure 11B is a diagram showing an example of improvement of the asymmetry of the differential signal in the power amplification module according to Embodiment 2.

[0081] Figure 10A shows the surface layer pattern of the substrate 2 on which the chip component 100 and the SMD component are mounted, Figure 10B , Figure 10C , Figure 10D shows the inner layer pattern of the substrate 2. Figure 10B , Figure 10C , Figure 10D shows the inner layer pattern of the inductor 42. In addition, Figure 10D may be the pattern of the back surface of the substrate 2 on which the chip component 100 and the SMD component are mounted.

[0082] As shown in Figure 10A , in Embodiment 2, as the surface layer pattern of the substrate 2, the inductor 41 of the balun 4 is provided. Further, as shown in Figure 10B and Figure 10C , in Embodiment 2, as the inner layer pattern of the substrate 2, the inductor 42 of the balun 4 is provided. Figure 10B The inner layer pattern of the inductor 42 shown in Figure 10C and the inner layer pattern of the inductor 42 shown in are connected by the via TH1.

[0083] Figure 9 In the comparative example shown in , the distance from one end of the inductor 41 to the power supply point P of the power supply potential VCC and the distance from the other end of the inductor 41 to the power supply point P of the power supply potential VCC are made equal, but the capacitor CB2 is disposed with respect to the center line L that bisects the wiring length of the inductor 41. Therefore, it is possible that the asymmetry of the differential signal occurs.

[0084] In Embodiment 2, by being disposed so that the two mounting terminals FP1, FP2 of the capacitor CB2 overlap on the center line L that bisects the wiring length of the inductor 41 when viewed from the surface layer side of the substrate 2, the asymmetry of the differential signal is improved.

[0085] Specifically, as shown in Figure 10A , one mounting terminal FP1 of the capacitor CB2 is disposed at a position overlapping the power supply point P of the power supply potential VCC of the inductor 41 when viewed from the surface layer side of the substrate 2. Further, as shown in Figure 10DAs shown, a reference potential pattern (in this case, a GND potential pattern) is provided at a position overlapping the winding axis WS of the inductor 41 when viewed from the surface layer side of the substrate 2 on the inner layer of the substrate 2, and the other mounting terminal FP2 of the capacitor CB2 is arranged so as to overlap the reference potential pattern (in this case, the GND potential pattern). In other words, the reference potential pattern and the other mounting terminal FP2 of the capacitor CB2 are electrically connected. In Embodiment 2, the reference potential pattern (in this case, the GND potential pattern) and Figure 10D The GND pattern of the inner layer of the substrate 2 or the back surface of the substrate 2 on which the chip component 100 and the SMD component are mounted is connected by the via hole TH2. In addition, the mounting terminal FP1 corresponds to the "first mounting terminal", and the mounting terminal FP2 corresponds to the "second mounting terminal".

[0086] Figure 11A Figure 11B is a graph showing an example of improvement of the asymmetry of the differential signal in the power amplification module according to Embodiment 2. In Figure 11A , the horizontal axis shows the output of the differential amplification circuit PA, and the vertical axis shows the gain difference between the differential signals. Figure 11A The dashed line shown in Figure 9 shows the gain difference between the differential signals of the comparative example shown in Figure 10A , and the solid line shows the gain difference between the differential signals of Embodiment 2 shown in Figure 11B . In Figure 11B , the horizontal axis shows the output of the differential amplification circuit PA, and the vertical axis shows the phase difference between the differential signals. Figure 9 The dashed line shown in Figure 11A shows the phase difference between the differential signals of the comparative example shown in , and the solid line shows the phase difference between the differential signals of Embodiment 2 shown in

[0087] . Figure 11A Figure 11B As shown in , by arranging the capacitor CB2 so as to be symmetrical on the center line L bisecting the wiring length of the inductor 41, the gain difference and the phase difference of the differential signal can be reduced, and the asymmetry of the differential signal can be improved. As a result, the characteristic deterioration caused by the asymmetry of the differential signal can be suppressed.

[0088] Figure 10A In addition, as shown in , in the case where the reference potential pattern (in this case, the GND potential pattern) is provided around the inductor 41, it is preferable to provide the reference potential pattern (the GND potential pattern) at a position at a distance D (for example, 0.2 mm) or more (for example, D ≥ 0.2 mm) from the inductor 41. As a result, the influence on the symmetry of the differential signal can be reduced.

[0089] (Embodiment 3)

[0090] Figure 12 is a view showing a configuration example of a plurality of differential amplification circuits on the power amplification module involved in Embodiment 3. In Figure 12 , a structure is shown in which the structure explained in Embodiment 1 is applied to the differential amplification circuit PA2 (2nd differential amplification circuit) and the structure explained in Embodiment 2 is applied to the differential amplification circuit PA1 (1st differential amplification circuit). PA1 takes, for example, the frequency band "n79" as an amplification target, and PA2 takes, for example, the frequency band "n77" as an amplification target.

[0091] In Figure 12 , the chip component 100a of the differential amplification circuit PA1, the inductor 41a, the inductor LBa, and the capacitors C3a, CB1a, CB2a are illustrated. Further, in Figure 12 , the chip component 100b of the differential amplification circuit PA2, the inductor 41b, and the capacitor CB2b are illustrated.

[0092] In a structure in which a plurality of differential amplification circuits different in amplification target frequency band are mounted on one power amplification module 1 as shown in Figure 12 , asymmetry of the differential signal is likely to occur due to interference between the differential amplification circuits and the like. Therefore, by arranging, for example, the SMD components such as the inductor LBa and the capacitors C3a, CB1a of the differential amplification circuit PA1 between the differential amplification circuit PA1 (1st differential amplification circuit) and the differential amplification circuit PA2 (2nd differential amplification circuit), it is possible to reduce the influence of the asymmetry of the differential signal caused by the interference between the differential amplification circuits and the like. The SMD components arranged between the differential amplification circuit PA1 and the differential amplification circuit PA2 are not limited to the inductor LBa and the capacitors C3a, CB1a of the differential amplification circuit PA1.

[0093] Further, in Figure 12In the above embodiment, a configuration is shown in which, in the differential amplification circuit PA1 (first differential amplification circuit), the distance from one end of the inductor 41a to the power supply point of the power supply potential VCC and the distance from the other end of the inductor 41a to the power supply point of the power supply potential VCC are made equal, and in the differential amplification circuit PA2 (second differential amplification circuit), the distance from one end of the inductor 41b to the power supply point of the power supply potential VCC and the distance from the other end of the inductor 41b to the power supply point of the power supply potential VCC are made different, but it can also be a configuration in which, in the differential amplification circuit PA1 (first differential amplification circuit), the distance from one end of the inductor 41a to the power supply point of the power supply potential VCC and the distance from the other end of the inductor 41a to the power supply point of the power supply potential VCC are made different. Even in this case, it can be a configuration in which, between the differential amplification circuit PA1 (first differential amplification circuit) and the differential amplification circuit PA2 (second differential amplification circuit), SMD components such as the inductor LBa and the capacitors C3a, CB1a, and the like of the differential amplification circuit PA1 are arranged.

[0094] Further, the configuration of the PA1 and the PA2 and the number of stages of the amplifiers are not limited to the configuration disclosed in the above-described embodiment. For example, the PA1 and the PA2 can also include a multi-stage amplifier.

[0095] Further, the above-described embodiment is used to make the present disclosure easy to understand, and is not used to limit the interpretation of the present invention. The present disclosure can be changed / modified without departing from the gist thereof, and the present disclosure also includes equivalents thereof.

[0096] The present disclosure can adopt the following configuration instead of the above-described configuration or in addition to the above-described configuration.

[0097] (1) A power amplification module of one aspect of the present disclosure is a power amplification module in which a plurality of differential amplification circuits are mounted on a substrate, wherein the differential amplification circuit includes: a chip device including at least two amplifiers that amplify differential signals respectively; a balun including a primary winding and a secondary winding, both ends of the primary winding being connected to outputs of the chip device; and a capacitor provided between a power supply point of the primary winding and a reference potential, and in at least one of the plurality of differential amplification circuits, the distance from one end of the primary winding to the power supply point and the distance from the other end of the primary winding to the power supply point are different.

[0098] In this configuration, it is possible to reduce the gain difference and the phase difference of the differential signal, and to improve the asymmetry of the differential signal. Thereby, it is possible to suppress the deterioration of characteristics caused by the asymmetry of the differential signal.

[0099] (2) In the power amplification module of (1) above, in at least one of the plurality of differential amplification circuits, the power supply point is provided at a position deviating from a center line that bisects the wiring length of the primary-side winding.

[0100] In this structure, the gain difference and the phase difference of the differential signal can be reduced, and the asymmetry of the differential signal can be improved. Thus, the characteristic deterioration caused by the asymmetry of the differential signal can be suppressed.

[0101] (3) In the power amplification module of (1) or (2) above, the capacitor has a first mounting terminal and a second mounting terminal that electrically connect the substrate and the capacitor, and at least one of the plurality of differential amplification circuits is configured so that, when viewed from the side of the surface of the substrate on which the differential amplification circuit is mounted, the first mounting terminal and the second mounting terminal overlap on a center line that bisects the wiring length of the primary-side winding.

[0102] In this structure, the gain difference and the phase difference of the differential signal can be reduced, and the asymmetry of the differential signal can be improved. Thus, the characteristic deterioration caused by the asymmetry of the differential signal can be suppressed.

[0103] (4) In the power amplification module of (3) above, further comprising: a reference potential pattern provided at a position overlapping the winding axis of the primary-side winding when viewed from the side of the surface of the substrate on which the differential amplification circuit is mounted, and in at least one of the plurality of differential amplification circuits, the first mounting terminal is provided at a position overlapping the power supply point of the primary-side winding when viewed from the side of the surface of the substrate on which the differential amplification circuit is mounted, and the second mounting terminal is electrically connected to the reference potential pattern.

[0104] In this structure, the gain difference and the phase difference of the differential signal can be reduced, and the asymmetry of the differential signal can be improved. Thus, the characteristic deterioration caused by the asymmetry of the differential signal can be suppressed.

[0105] (5) In the power amplification module of (1) above, the plurality of differential amplification circuits include a first differential amplification circuit and a second differential amplification circuit, and the first differential amplification circuit and the second differential amplification circuit each have the power supply point provided at a position deviating from a center line that bisects the wiring length of the primary-side winding.

[0106] In this structure, the gain difference and the phase difference of the differential signal can be reduced, and the asymmetry of the differential signal can be improved. Thus, the characteristic deterioration caused by the asymmetry of the differential signal can be suppressed.

[0107] (6) In the power amplification module described in (1) to (5) above, in at least one of the plurality of differential amplification circuits, one end of the secondary winding is connected to an output matching circuit, and a capacitor is provided between the other end of the secondary winding and a reference potential.

[0108] In this configuration, impedance matching of the inductance value and the coupling coefficient of the balun can be achieved.

[0109] (7) In the power amplification module described in (1) to (6) above, in at least one of the plurality of differential amplification circuits, a reference potential pattern is provided at a position that is a given distance or more from the primary winding.

[0110] In this configuration, the influence on the symmetry of the differential signal can be reduced.

[0111] (8) In the power amplification module described in (1) to (7) above, the plurality of differential amplification circuits include a first differential amplification circuit and a second differential amplification circuit, and a plurality of SMD components are disposed between the first differential amplification circuit and the second differential amplification circuit.

[0112] In this configuration, the influence on the symmetry of the differential signal caused by interference between the differential amplification circuits and the like can be reduced.

[0113] With the present disclosure, a power amplification module that can suppress characteristic degradation caused by the asymmetry of a differential signal can be implemented.

Claims

1. A power amplification module in which a plurality of differential amplification circuits are mounted on a substrate, wherein the differential amplification circuit comprises: a chip device including at least two amplifiers that amplify differential signals respectively; a balun including a primary winding and a secondary winding, both ends of the primary winding being connected to outputs of the chip device; and a capacitor provided between a power supply point of the primary winding and a reference potential, in at least one of the plurality of differential amplification circuits, a distance from one end of the primary winding to the power supply point and a distance from the other end of the primary winding to the power supply point are different, the capacitor has a first mounting terminal and a second mounting terminal that electrically connect the substrate and the capacitor, and at least one of the plurality of differential amplification circuits is configured such that the first mounting terminal and the second mounting terminal overlap on a center line that bisects a wiring length of the primary winding when viewed from a surface side of the substrate on which the differential amplification circuit is mounted.

2. The power amplification module according to claim 1, wherein in at least one of the plurality of differential amplification circuits, the power supply point is provided at a position deviated from the center line that bisects the wiring length of the primary winding.

3. The power amplification module according to claim 1 or 2, further comprising a reference potential pattern provided at a position overlapping a winding axis of the primary winding when viewed from the surface side of the substrate on which the differential amplification circuit is mounted, in at least one of the plurality of differential amplification circuits, the first mounting terminal is provided at a position overlapping the power supply point of the primary winding when viewed from the surface side of the substrate on which the differential amplification circuit is mounted, and the second mounting terminal is electrically connected to the reference potential pattern.

4. The power amplification module according to claim 1, wherein the plurality of differential amplification circuits include a first differential amplification circuit and a second differential amplification circuit, and the first differential amplification circuit and the second differential amplification circuit are each provided with the power supply point at a position deviated from the center line that bisects the wiring length of the primary winding.

5. The power amplification module according to claim 1 or 2, wherein in at least one of the plurality of differential amplification circuits, one end of the secondary winding is connected to an output matching circuit, and a capacitor is provided between the other end of the secondary winding and a reference potential.

6. The power amplification module according to claim 1 or 2, wherein in at least one of the plurality of differential amplification circuits, a reference potential pattern is provided at a position at a distance of a given distance or more from the primary winding.

7. The power amplification module according to claim 1 or 2, wherein the plurality of differential amplification circuits include a first differential amplification circuit and a second differential amplification circuit, and a plurality of SMD components are provided between the first differential amplification circuit and the second differential amplification circuit. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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