Display panel, display device and driving method

Abstract

Embodiments of the present disclosure provide a display panel, a display device and a driving method. By arranging a control signal line and a control unit in the display panel, and matching the control timing of the pixel island, the sub-pixel unit row in the pixel island can be independently controlled with the sub-pixel unit row in other pixel islands. Based on this, the display panel can be partitioned for image, and the important display area, or the gaze area where the human eye is focusing, and other display areas can be refreshed respectively. The important display area or the gaze area can be N times the frequency of other display areas. While meeting the driving requirements of high resolution, high refresh rate and high response speed of the important display area, the transmission data of other display areas can be compressed, the display resolution and refresh rate can be reduced, and the like, so as to allocate limited resources to the important display area preferentially, thereby solving the problems of high data transmission bandwidth, high device power consumption, insufficient pixel charging and the like.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel, display device, and driving method. Background Technology

[0002] With the development of the display industry, users have increasingly higher requirements for display quality, especially in specific display scenarios such as Virtual Reality (VR), Augmented Reality (AR), immersive games, and racing sports, where the requirements for display devices' screen refresh rate, high resolution, and other specifications are extremely high.

[0003] Currently, issues such as motion blur, display ghosting, and low clarity are quite serious at conventional display frequencies. Increasing the display refresh rate and resolution will directly lead to a doubling of the amount of data transmitted, which in turn increases the number of data transmission interfaces, data transmission bandwidth, and power consumption of the display device, seriously affecting the user's immersive experience in the display device. Summary of the Invention

[0004] A first aspect of this disclosure provides a display panel, including:

[0005] Substrate;

[0006] Multiple scan signal lines are located on the substrate, extending along a first direction and arranged along a second direction; the first direction and the second direction intersect.

[0007] Multiple data signal lines are located on the substrate, and the multiple data signal lines extend along the second direction and are arranged along the first direction;

[0008] Multiple sub-pixel units are respectively located in the regions divided by the multiple scan signal lines and the multiple data signal lines; at least two adjacent sub-pixel units along the first direction and the second direction constitute a pixel island;

[0009] Multiple control units are located between adjacent pixel islands in the first direction; each pixel island corresponds to n control units, where n is the number of sub-pixel unit rows included in the pixel island in the second direction; each control unit corresponds to one row of sub-pixel units in the pixel island in the first direction.

[0010] Multiple control signal lines are respectively located between adjacent pixel islands in the first direction, and the multiple control signal lines extend along the second direction and are arranged along the first direction; wherein,

[0011] The sub-pixel unit includes: a first transistor and a driving circuit; the first electrode of the first transistor is connected to the data signal line of the corresponding column of the sub-pixel unit, and the second electrode of the first transistor is connected to the driving circuit in the sub-pixel unit; the control electrode of the first transistor is interconnected with the control electrodes of the first transistors in each of the sub-pixel units located in the same row in the first direction within the pixel island.

[0012] The control unit includes a control terminal, an input terminal, and an output terminal; the control terminal of the control unit is connected to the control signal line of the corresponding column, the input terminal of the control unit is connected to the scan signal line of the corresponding row, and the output terminal of the control unit is connected to the control electrode of the first transistor in each sub-pixel unit of the corresponding row.

[0013] The control unit is configured to transmit the signal from the input terminal to the output terminal under the control of a first signal transmitted on the control signal line, and to stop transmitting the signal from the input terminal to the output terminal under the control of a second signal transmitted on the control signal line.

[0014] In some embodiments of this disclosure, the control unit includes: a second transistor and a third transistor; the display panel further includes:

[0015] Multiple fixed potential signal lines are respectively located between adjacent sub-pixel units in the second direction. The multiple fixed potential signal lines extend along the first direction and are arranged along the second direction.

[0016] The control electrode of the second transistor is connected to the control signal line of the column corresponding to the control unit, the first electrode of the second transistor is connected to the scan signal line of the row corresponding to the control unit, and the second electrode of the second transistor is connected to the control electrode of the first transistor in each sub-pixel unit of the row corresponding to the control unit.

[0017] The control electrode of the third transistor is connected to the control signal line of the column corresponding to the control unit, the first electrode of the third transistor is connected to the fixed potential signal line of the row corresponding to the control unit, and the second electrode of the third transistor is connected to the control electrode of the first transistor in each sub-pixel unit of the row corresponding to the control unit.

[0018] The second transistor is configured to turn on under the control of a first signal transmitted on the control signal line and turn off under the control of a second signal transmitted on the control signal line.

[0019] The third transistor is configured to turn off under the control of a first signal transmitted on the control signal line and turn on under the control of a second signal transmitted on the control signal line.

[0020] In some embodiments of this disclosure, the second transistor is an N-type transistor, and the third transistor is a P-type transistor; the first signal is a high-level signal, and the second signal is a low-level signal;

[0021] Alternatively, the second transistor is a P-type transistor, and the third transistor is an N-type transistor; the first signal is a low-level signal, and the second signal is a high-level signal.

[0022] In some embodiments of this disclosure, the control unit includes: a second transistor and a third transistor; the control signal line is a first control signal line; the display panel further includes:

[0023] Multiple second control signal lines are respectively located between adjacent pixel islands in the first direction, and the multiple second control signal lines extend along the second direction and are arranged along the first direction;

[0024] Multiple fixed potential signal lines are respectively located between adjacent sub-pixel units in the second direction. The multiple fixed potential signal lines extend along the first direction and are arranged along the second direction.

[0025] The control electrode of the second transistor is connected to the first control signal line of the column corresponding to the control unit, the first electrode of the second transistor is connected to the scan signal line of the row corresponding to the control unit, and the second electrode of the second transistor is connected to the control electrode of the first transistor in each sub-pixel unit of the row corresponding to the control unit.

[0026] The control electrode of the third transistor is connected to the second control signal line of the column corresponding to the control unit, the first electrode of the third transistor is connected to the fixed potential signal line of the row corresponding to the control unit, and the second electrode of the third transistor is connected to the control electrode of the first transistor in each sub-pixel unit of the row corresponding to the control unit.

[0027] The second transistor is configured to turn on under the control of a first signal transmitted on the first control signal line and turn off under the control of a second signal transmitted on the first control signal line.

[0028] The third transistor is configured to turn on under the control of a third signal transmitted on the second control signal line and turn off under the control of a fourth signal transmitted on the second control signal line.

[0029] In some embodiments of this disclosure, the second transistor is an N-type transistor, the first signal is a high-level signal, and the second signal is a low-level signal; or, the second transistor is a P-type transistor, the first signal is a low-level signal, and the second signal is a high-level signal.

[0030] The third transistor is an N-type transistor, the third signal is a high-level signal, and the fourth signal is a low-level signal; or, the third transistor is a P-type transistor, the third signal is a low-level signal, and the fourth signal is a high-level signal.

[0031] In some embodiments of this disclosure, the first transistor is an N-type transistor, and the fixed potential signal line is configured to transmit a low-level signal.

[0032] Alternatively, the first transistor is a P-type transistor, and the fixed-potential signal line is configured to transmit a high-level signal.

[0033] In some embodiments of this disclosure, the display panel is a liquid crystal display panel or an organic light-emitting diode display panel.

[0034] In some embodiments of this disclosure, the sub-pixel units included within a pixel island have the same display color;

[0035] The display panel includes multiple pixel islands, and the multiple pixel islands include at least a first pixel island displaying a first color and a second pixel island displaying a second color.

[0036] A second aspect of the present disclosure is to provide a display device, including any of the above-described display panels, microlens layers, and controllers;

[0037] The microlens layer is located on the light-emitting side of the display panel. The microlens layer includes a plurality of microlenses corresponding to the pixel islands of the display panel. The microlenses are used to modulate the emitted light from the pixel islands in the display panel so that the pixel islands are mapped into a pixel array to achieve image display.

[0038] The controller, connected to the display panel, is configured to provide drive signals to the display panel.

[0039] In some embodiments of this disclosure, it further includes:

[0040] A camera is positioned on the bezel of the display device and is configured to capture images of the user's eyes. This allows the controller to determine the user's gaze area on the display device based on the captured images and drive the gaze area and non-gaze area in the display panel to display images at different refresh rates.

[0041] A third aspect of this disclosure provides a driving method based on the above-described display device, comprising:

[0042] Real-time determination of the user's gaze area and non-gaze area on the display device;

[0043] The gaze area is driven to display an image at a first refresh rate, and the non-gaze area is driven to display an image at a second refresh rate; the first refresh rate is higher than the second refresh rate.

[0044] In some embodiments of this disclosure, the display device includes a camera;

[0045] The real-time determination of the user's gaze area and non-gaze area on the display device includes:

[0046] Control the camera to capture images of the user's eyes in real time;

[0047] Determine the area of ​​the user's gaze on the display device based on the captured image;

[0048] The areas in the display device other than the gaze area are defined as non-gaze areas.

[0049] In some embodiments of this disclosure, driving the gaze area to display an image at a first refresh rate and driving the non-gaze area to display an image at a second refresh rate includes:

[0050] Drive each sub-pixel unit within the gaze area to be refreshed a times;

[0051] Drive each sub-pixel unit in the non-focused area to be refreshed b times;

[0052] Where a and b are positive integers, and a is greater than b.

[0053] In some embodiments of this disclosure, driving the gaze area to display an image at a first refresh rate and driving the non-gaze area to display an image at a second refresh rate includes:

[0054] Drive each sub-pixel unit within the gaze area to be refreshed c times;

[0055] Drive each sub-pixel unit in the gaze region and the non-gaze region to be refreshed d times;

[0056] Where c and d are positive integers.

[0057] In some embodiments of this disclosure, the step of refreshing each sub-pixel unit within the gaze region includes:

[0058] The scanning signal lines corresponding to the gaze area are driven to transmit valid level signals sequentially.

[0059] The system controls the transmission of a first signal on each control signal line corresponding to the gaze area and controls the transmission of a second signal on each control signal line corresponding to the non-gaze area.

[0060] The process of refreshing each sub-pixel unit within the non-focused region includes:

[0061] The scanning signal lines within the display panel are driven to sequentially transmit valid level signals.

[0062] When the scan detects each sub-pixel unit row corresponding to the gaze region, it controls each control signal line corresponding to the gaze region to transmit a second signal, and controls each control signal line corresponding to the non-gaze region to transmit a first signal. Attached Figure Description

[0063] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments of this disclosure will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0064] Figure 1 This is a schematic diagram of the planar structure of a pixel island provided in an embodiment of this disclosure;

[0065] Figure 2 This is one of the schematic diagrams of the planar structure of the display panel provided in the embodiments of this disclosure;

[0066] Figure 3 This is a second schematic diagram of the planar structure of the display panel provided in an embodiment of the present disclosure;

[0067] Figure 4 This is the third schematic diagram of the planar structure of the display panel provided in the embodiments of this disclosure;

[0068] Figure 5 Fourth schematic diagram of the planar structure of the display panel provided in the embodiments of this disclosure;

[0069] Figure 6 Fifth schematic diagram of the planar structure of the display panel provided in the embodiments of this disclosure;

[0070] Figure 7 This is a schematic cross-sectional view of the display device provided in an embodiment of the present disclosure;

[0071] Figure 8 A flowchart of a driving method for a display device provided in an embodiment of this disclosure;

[0072] Figure 9 This is a schematic diagram of the planar structure of a display device provided in an embodiment of the present disclosure.

[0073] Wherein, 10-substrate, 20-scan signal line, 30-data signal line, 40-control signal line, 41-first control signal line, 42-second control signal line, 50-fixed potential signal line, 100-display panel, 200-microlens layer, 300-controller, Pi-pixel island, Pi-R-first pixel island, Pi-G-second pixel island, Pi-B-third pixel island, p-subpixel unit, c-control unit, T1-first transistor, T2-second transistor, T3-third transistor, dr-driving circuit. Detailed Implementation

[0074] To make the above-described objects, features, and advantages of this disclosure more apparent and understandable, the disclosure will be further described below in conjunction with the accompanying drawings and embodiments. However, the exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the disclosure more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms describing position and direction as described in this disclosure are illustrative of the accompanying drawings, but changes may be made as needed, and all such changes are included within the scope of protection of this disclosure. The accompanying drawings of this disclosure are for illustrative purposes only and do not represent actual scale.

[0075] Currently, the most commonly used displays are liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays.

[0076] LCD screens are currently the mainstream display technology, boasting advantages such as low power consumption, small size, and low radiation. However, LCD panels are non-self-emissive and require a backlight module for operation.

[0077] An LCD mainly consists of a backlight module and a liquid crystal display panel. The liquid crystal display panel itself does not emit light and relies on the light source provided by the backlight module to achieve brightness display.

[0078] The display principle of an LCD is to place liquid crystal between two conductive glass plates. Driven by the electric field between two electrodes, the liquid crystal molecules twist, which controls the transmission or blocking of the backlight, thereby displaying the image. If a color filter is added, color images can be displayed.

[0079] OLED displays are also known as organic light-emitting diode (OLED) displays or organic light-emitting semiconductor displays. OLED displays are self-emissive displays, so they do not require a backlight module. The overall thickness of the device is small, which is beneficial for miniaturizing near-eye display devices and making them easier to install.

[0080] The light-emitting device in an OLED display is an OLED device, which is a current-driven organic light-emitting device. It emits light through the injection and recombination of charge carriers, and the light intensity is proportional to the injected current.

[0081] In an OLED, holes generated at the anode and electrons generated at the cathode move under the influence of an electric field, injecting into the hole transport layer and electron transport layer respectively, and migrating to the emissive layer. When the two meet in the emissive layer, they generate excitons, which in turn excite the light-emitting molecules to ultimately produce visible light.

[0082] Regardless of the type of display used, display panels include sub-pixel units arranged in an array. The more sub-pixel units contained within a unit size, the higher the pixel density (Pixels Per Inch, or PPI) of the display panel, resulting in richer image details. However, current manufacturing processes cannot infinitely shrink the size of sub-pixel units; therefore, the PPI of display panels produced using traditional processes is limited. To overcome these limitations, this disclosure introduces a pixel island design and provides a normal display image after optical path integration by adding optical microlenses above the pixel islands.

[0083] Figure 1 This is a schematic diagram of the planar structure of a pixel island provided in an embodiment of this disclosure.

[0084] like Figure 1 As shown, the improvement of display PPI in LCD or OLED panels is limited by insufficient precision in the sub-pixel unit mask process. Therefore, embodiments of this disclosure can provide multiple pixel islands Pi in the display panel, with each pixel island Pi including multiple sub-pixel units. To illustrate the mapping relationship of sub-pixel units through optical microlenses, Figure 1 Only three pixel islands Pi are shown. In practical applications, the display panel may include multiple pixel islands distributed in an array. This disclosure does not limit the specific number of pixel islands contained in the display panel.

[0085] like Figure 1 As shown, a pixel island Pi includes multiple sub-pixel units, and in this embodiment, the sub-pixel units within the same pixel island Pi display the same color. To achieve color image display, the pixel island Pi includes at least a first pixel island displaying a first color and a second pixel island displaying a second color.

[0086] by Figure 1For example, pixel island Pi includes a first pixel island Pi-R displaying red, a second pixel island Pi-G displaying green, and a third pixel island Pi-B displaying blue. Each pixel island Pi includes 8 rows × 16 columns of sub-pixel units. When at least one microlens array is placed on the light-emitting side of each pixel island Pi, the light from the three pixel islands can be deflected in a set direction, thereby allowing the light from the three pixel islands to be mapped to the same position, forming... Figure 1 The lower part is a display block. For example, two adjacent rows × two columns of sub-pixel units in a pixel island Pi are used to display a pixel. Then, two rows × two columns of sub-pixel units located at the same position in three pixel islands Pi can be mapped to the same position after being modulated by the microlenses on their light-emitting side, in order to form a pixel. This pixel contains brightness information of three colors: red, green, and blue, so it can be displayed as a colored pixel. A frame of image is composed of multiple such pixels. Thus, the outgoing light from the pixel islands is mapped by the microlens array to achieve image display.

[0087] The three colors of sub-pixel units are designed as first pixel islands, second pixel islands, and third pixel islands. Multiple sub-pixel units of the same color can be designed in each pixel island, which can reduce the requirements for the precision of the mask process and improve the display resolution while reaching the physical arrangement limit of the sub-pixel units.

[0088] In addition, the microlens array can not only perform pixel mapping on the sub-pixel units in the pixel island, but also modulate the light field of the emitted light from the pixel island, so that the emitted light from the final pixel island forms multiple viewpoints, thereby realizing three-dimensional image display.

[0089] This disclosure provides a display panel based on the use of pixel islands. Figure 2 This is one of the planar structural schematic diagrams of a display panel provided in an embodiment of this disclosure.

[0090] like Figure 2 As shown, the display panel includes a substrate 10, which provides support and load-bearing function. The substrate 10 is typically made of glass, but when the display panel is a flexible display panel, the substrate 10 can also be made of a flexible substrate; this is not a limitation.

[0091] Multiple scan signal lines 20 are located on the substrate 10, extending along a first direction a1 and arranged along a second direction a2. The first direction a1 and the second direction a2 intersect; the first direction can be the direction of a row of sub-pixel units, and the second direction can be the direction of a column of sub-pixels.

[0092] Multiple data signal lines 30 are located on the substrate 10, extending along the second direction a2 and arranged along the first direction a1. Multiple scan signal lines 20 and multiple data signal lines 30 intersect each other, dividing multiple regions, which are the regions where sub-pixel units are located.

[0093] Multiple sub-pixel units p are located within regions defined by multiple scan signal lines 20 and multiple data signal lines 30, respectively; the multiple sub-pixel units p are arranged in an array along a first direction a1 and a second direction a2. Each sub-pixel unit p is connected to the scan signal line 20 corresponding to its sub-pixel row and to the data signal line 30 corresponding to its sub-pixel column.

[0094] When a scan signal line 20 transmits an effective level, the corresponding sub-pixel unit row can be written with a data signal, thereby enabling the sub-pixel units in that row to display an image according to the written data signal.

[0095] In this embodiment of the disclosure, at least two adjacent sub-pixel units p along the first direction a1 and the second direction a2 constitute a pixel island Pi. Figure 2 For example, two adjacent rows and two columns of sub-pixel units constitute a pixel island Pi. This disclosure is only for simplification. In practical applications, a pixel island contains at least two sub-pixel units. In addition, more sub-pixel units can be used to form a pixel island Pi. The embodiments of this disclosure do not limit the specific number of sub-pixel units contained in a pixel island Pi.

[0096] In this embodiment, the data signals loaded on each sub-pixel unit in a pixel island Pi can be the same or different, thereby achieving the switching of display resolution. For example, when all sub-pixel units in a pixel island are loaded with the same data signal, the pixel island is displayed as a single pixel, and the display resolution is the lowest. When each sub-pixel unit in a pixel island is loaded with a different data signal, the pixel island is displayed as the maximum number of pixels, and the display resolution is the highest. When the number of pixels displayed by a pixel island is greater than 1 and less than m, where m is the number of sub-pixel units contained in a pixel island, the sub-pixel units in the pixel island are grouped, with at least two adjacent sub-pixel units grouped together. The number of groups is the final number of pixels displayed. When the sub-pixel units in a group are loaded with the same data signal, while different groups are loaded with different data signals, a comparable image resolution can be achieved.

[0097] Therefore, by controlling the data signals loaded on each data signal line 30, the number of pixels that the pixel island can display can be controlled, thereby achieving different display resolutions.

[0098] Based on this, the display panel also includes: multiple control units c, located between adjacent pixel islands Pi in the first direction a1; one pixel island Pi corresponds to n control units, where n is the number of sub-pixel unit rows included in the pixel island Pi in the second direction a2; one control unit c corresponds to one row of sub-pixel units p in the pixel island Pi.

[0099] Multiple control signal lines 40 are located between adjacent pixel islands in the first direction a1, and the multiple control signal lines 40 extend along the second direction a2 and are arranged along the first direction a1.

[0100] Among them, such as Figure 2 As shown, the sub-pixel unit p includes: a first transistor T1 and a driving circuit dr; the first electrode of the first transistor T1 is connected to the data signal line 30 of the corresponding column of the sub-pixel unit p, and the second electrode of the first transistor T1 is connected to the driving circuit dr in the sub-pixel unit p; the control electrode of the first transistor is interconnected with the control electrodes of the first transistor T1 in each sub-pixel unit p located in the same row within the pixel island Pi.

[0101] The control unit c includes a control terminal s1, an input terminal s2, and an output terminal s3. The control terminal s1 of the control unit c is connected to the control signal line 40 of the corresponding column, the input terminal s2 of the control unit c is connected to the scan signal line 20 of the corresponding row, and the output terminal s3 of the control unit c is connected to the control electrode of the first transistor T1 in each sub-pixel unit p of the corresponding row.

[0102] The control unit c is configured to transmit the signal from the input terminal s2 to the output terminal s3 under the control of the first signal transmitted through the control signal line 40, and to stop transmitting the signal from the input terminal s2 to the output terminal s3 under the control of the second signal transmitted through the control signal line 40.

[0103] In this embodiment of the disclosure, n control units c are set to connect to each pixel island Pi, wherein each row of sub-pixel units of pixel island Pi is connected to one control unit c. Therefore, the number of control units c connected to a pixel island Pi is equal to the number of sub-pixel unit rows contained in the pixel island Pi.

[0104] by Figure 2 For example, a pixel island Pi may include 4 sub-pixel units in 2 rows × 2 columns. Then, a control unit c is connected to the first row of sub-pixel units and another control unit c is connected to the second row of sub-pixel units. The control unit c is controlled to be turned on or off by the control signal line 40 to which it is connected.

[0105] When the control signal line 40 connected to the pixel island transmits the first signal, the control unit c connected to the first row of sub-pixel units and the control unit c connected to the second row of sub-pixel units are turned on under the control of the first signal. At this time, the control unit c connected to the first row of sub-pixel units can transmit the signal transmitted by the first row of scan signal line 20 to the first row of sub-pixel units, and the control unit c connected to the second row of sub-pixel units can transmit the signal transmitted by the second row of scan signal line 20 to the second row of sub-pixel units. Since the scan signal line 20 outputs valid level signals sequentially, if the first row of scan signal line 20 transmits a valid level signal, then the first transistor T1 of the first row of sub-pixel units is turned on, and the data signals loaded by each data signal line 30 are written into the first row of sub-pixel units. After the first row of sub-pixel units finish scanning, the scan signal line 20 corresponding to the second row of sub-pixel units transmits a valid level signal again, and the same rule as above can be used to write data signals for the second sub-pixel units.

[0106] When the control signal line 40 connected to the pixel island transmits the second signal, the control unit c connected to the first row of sub-pixel units and the control unit c connected to the second row of sub-pixel units are disconnected under the control of the second signal. At this time, the signals transmitted by the scan signal lines 20 connected to the first row of sub-pixel units and the second row of sub-pixel units cannot be transmitted to the first transistor T1 of the corresponding row of pixel units through the control unit c. At this time, neither the first row of sub-pixel units nor the second row of sub-pixel units can write data signals.

[0107] Therefore, by setting control signal lines 40 and control unit c in the display panel, and coordinating with the control timing of the pixel islands, the sub-pixel unit rows within a pixel island can be controlled independently from the sub-pixel unit rows within other pixel islands. Based on this, the display panel can be partitioned into image zones. For important display areas, or areas of focus, the image can be refreshed separately from other display areas. Important display areas or areas of focus can have a refresh rate N times higher than other display areas. While ensuring high resolution, high refresh rate, and high response speed for important display areas, the transmitted data for other display areas can be compressed, and the display resolution and refresh rate reduced, prioritizing limited resources for important display areas. This solves the limitations of high data transmission bandwidth, high device power consumption, and insufficient pixel charging.

[0108] like Figure 2 As shown, the control unit c can be a transistor. The control electrode of the transistor is connected to the control signal line 40, the first electrode is connected to the scan signal line 20 of the corresponding row, and the second electrode is connected to the control electrode of the first transistor T1 in the sub-pixel unit of the corresponding row.

[0109] In addition, control unit c can also adopt other structures. Figure 3This is a second schematic diagram of the planar structure of the display panel provided in an embodiment of this disclosure.

[0110] like Figure 3 As shown, the control unit c includes a second transistor T2 and a third transistor T3; the display panel also includes multiple fixed potential signal lines 50, which are located between adjacent sub-pixel units p in the second direction a2, and the multiple fixed potential signal lines 50 extend along the first direction a1 and are arranged along the second direction a2.

[0111] The fixed potential signal line 50 can extend in the same direction as the scan signal line 20, and one fixed potential line 50 can be grouped with one scan signal line 20. A group of signal lines is set between two adjacent sub-pixel unit rows.

[0112] The control electrode of the second transistor T2 is connected to the control signal line 40 of the column corresponding to the control unit c. The first electrode of the second transistor T2 is connected to the scan signal line 20 of the row corresponding to the control unit c. The second electrode of the second transistor T2 is connected to the control electrode of the first transistor T1 in each sub-pixel unit of the row corresponding to the control unit c.

[0113] The control electrode of the third transistor T3 is connected to the control signal line 40 of the column corresponding to the control unit c. The first electrode of the third transistor T3 is connected to the fixed potential signal line 50 of the row corresponding to the control unit c. The second electrode of the third transistor T3 is connected to the control electrode of the first transistor T1 in each sub-pixel unit of the row corresponding to the control unit c.

[0114] like Figure 3 As shown, the control terminals of the second transistor T2 and the third transistor T3 in the same control unit c are connected to the same control signal line 40. Therefore, the control signal line 40 controls both the second transistor T2 and the third transistor T3 simultaneously.

[0115] The second transistor T2 is configured to turn on under the control of the first signal transmitted through the control signal line 40 and turn off under the control of the second signal transmitted through the control signal line 40; the third transistor T3 is configured to turn off under the control of the first signal transmitted through the control signal line 40 and turn on under the control of the second signal transmitted through the control signal line 40.

[0116] In this embodiment, the control signal line 40 outputs a set timing sequence according to a set rule. The transmitted signals include a first signal and a second signal. The first signal is an active level signal for the second transistor T2 and an inactive level signal for the third transistor T3; the second signal is an inactive level signal for the second transistor T2 and an active level signal for the third transistor T3. Therefore, when the control electrodes of the second transistor T2 and the third transistor T3 are connected to the same control signal line 40, the types of the second transistor T2 and the third transistor T3 are opposite.

[0117] by Figure 3 For example, a pixel island Pi still includes 2 rows × 2 columns of sub-pixel units p. When the control signal line 40 transmits the first signal, the second transistor T2 in the control unit connected to the first row of sub-pixel units and the control unit connected to the second row of sub-pixel units are turned on, and the third transistor T3 is turned off. The second transistor T2 corresponding to the first row of sub-pixel units can transmit the signal of the first row of scan signal line 20 to the control electrode of the first transistor T1 in the first row of sub-pixel units, and the second transistor T2 corresponding to the second row of sub-pixel units can transmit the signal of the second row of scan signal line 20 to the control electrode of the first transistor T1 in the second row of sub-pixel units. Since the scan signal line 20 outputs valid level signals sequentially, if the first row of scan signal line 20 transmits a valid level signal, then the first transistor T1 of the first row of sub-pixel units is turned on, and the data signals loaded by each data signal line 30 are written into the first row of sub-pixel units. After the first row of sub-pixel units finishes scanning, the scan signal line 20 corresponding to the second row of sub-pixel units transmits a valid level signal again, and the same rule as above can be used to write data signals for the second sub-pixel units. The third transistor T3 is turned off under the control of the first signal, so the fixed potential transmitted by the fixed potential signal line 50 cannot be transmitted to the control electrode of the first transistor T1 of the corresponding row of sub-pixel units.

[0118] When the control signal line 40 transmits the second signal, the second transistor T2 in the control unit connected to the first row of sub-pixel units and the control unit connected to the second row of sub-pixel units are turned off, and the third transistor T3 is turned on. In the off state, the second transistor T2 cannot transmit the scan signal of the corresponding row to the control electrode of the first transistor T1 in the corresponding row of sub-pixel units. In the on state, the third transistor T3 transmits a fixed potential signal to the control electrode of the first transistor T1 in the corresponding row of sub-pixel units. The first transistor T1 is in the off state under the control of the fixed potential, thus ensuring that the first transistor T1 is off. Under this condition, no data signal can be written to the sub-pixel units of the corresponding row.

[0119] When using Figure 3The structure shown allows for partitioned refresh of the display panel. For important display areas, or areas the viewer is currently focusing on, when the sub-pixel row corresponding to the important display area is scanned, the corresponding control signal lines 40 can transmit a first signal. This turns on the second transistor T2 and turns off the third transistor T3 corresponding to each sub-pixel unit row in the important display area. The scan signal for the corresponding row is then transmitted to the control electrode of the first transistor T1 of the corresponding sub-pixel unit, thus refreshing the image data of each sub-pixel unit within the important display area. Simultaneously, when a non-important display area is scanned, the corresponding control signal lines 40 can transmit a second signal. This turns off the second transistor T2 and turns on the third transistor T3 corresponding to each sub-pixel unit row in the non-important display area. A fixed potential signal is then transmitted to the control electrode of the first transistor T1 of the corresponding sub-pixel unit, keeping each first transistor T1 in the off state, preventing data signals from being written to the sub-pixel units in the non-important display area.

[0120] This allows image data to be refreshed in important display areas while not in non-important display areas. Conversely, when image data is refreshed in non-important display areas, important display areas can be prevented from refreshing, thus enabling important and non-important display areas to refresh image data independently.

[0121] Figure 3 The structure shown is a planar structure of an OLED panel. The driving circuit (dr) includes components such as storage capacitors, driving transistors, and organic light-emitting diodes. Figure 3 The diagram shows only the simplest pixel circuit structure of an OLED display panel. In practical applications, other OLED pixel circuit structures can also be used, and no limitation is made here.

[0122] In addition to OLED panels, which can use the control unit provided in this embodiment to select and control the sub-pixel rows in the corresponding pixel islands, LCD panels can also be equipped with a control unit. Figure 4 This is the third schematic diagram of the planar structure of the display panel provided in the embodiments of this disclosure.

[0123] like Figure 4 As shown, the sub-pixel unit p includes a first transistor T1 and a driving circuit dr. The driving circuit dr includes at least a storage capacitor. One terminal of the storage capacitor is connected to the pixel electrode of the sub-pixel unit, and the other terminal is connected to a common electrode. The voltage between the pixel electrode and the common electrode can drive the liquid crystal to flip, thereby allowing the sub-pixel units to have different transmittances. In the LCD panel, the specific structure of the control unit c, and the connection relationship between the first transistor T1 and the scan signal line 20 and the data signal line 30 are the same as in the OLED panel. For specific connection relationships and driving methods, please refer to [reference needed]. Figure 3 The relevant parts will not be elaborated here.

[0124] In practical applications, the first transistor T1, the second transistor T2, and the third transistor T3 mentioned above can all be Metal-Oxide-Semiconductor Field-Effect Transistors (MOS), Complementary Metal-Oxide-Semiconductor Transistors (CMOS), or Thin Film Transistors (TFTs). Furthermore, these three transistors can be either P-type or N-type transistors.

[0125] In the display panel, such as Figure 3 or Figure 4 In the circuit structure shown, the second transistor T2 and the third transistor T3 are controlled by the same control signal line 40, and the functions of the second transistor T2 and the third transistor T3 are opposite. Therefore, the types of the second transistor T2 and the third transistor T3 should be opposite.

[0126] For example, the second transistor T2 can be an N-type transistor, and the third transistor T3 can be a P-type transistor. For an N-type transistor, a high-level signal is an effective level signal, and for a P-type transistor, a low-level signal is an effective level signal. Therefore, the first signal transmitted by the control signal line 40 is a high-level signal, and the second signal is a low-level signal.

[0127] Alternatively, the second transistor T2 can be a P-type transistor, and the third transistor T3 can be an N-type transistor; in this case, the first signal transmitted by the control signal line 40 is a low-level signal, and the second signal is a high-level signal.

[0128] Furthermore, the first transistor T1 can be either a P-type transistor or an N-type transistor. When the first transistor T1 is a P-type transistor, it turns on when a low-level signal is transmitted on the corresponding row's scan signal line 20, and turns off when a high-level signal is transmitted on the corresponding row's scan signal line 20. The fixed-level signal transmitted on the fixed-level signal line 50 is used to control the first transistor T1 to turn off; therefore, when the first transistor T1 is a P-type transistor, the fixed-level signal transmitted on the fixed-level signal line 50 is a high-level signal.

[0129] When the first transistor T1 is an N-type transistor, it turns on when a high-level signal is transmitted on the corresponding row's scan signal line 20, and turns off when a low-level signal is transmitted on the corresponding row's scan signal line 20. The fixed-level signal transmitted on the fixed-level signal line 50 is used to control the first transistor T1 to turn off; therefore, when the first transistor T1 is an N-type transistor, the fixed-level signal transmitted on the fixed-level signal line 50 is a low-level signal.

[0130] Figure 5 This is a fourth schematic diagram of the planar structure of the display panel provided in an embodiment of this disclosure. Optionally, the control unit c may also employ... Figure 5 Configure the structure shown.

[0131] like Figure 5 As shown, the control unit c includes: a second transistor T2 and a third transistor T3; the control signal lines are divided into a first control signal line 41 and a second control signal line 42.

[0132] Multiple first control signal lines 41 are located between adjacent pixel islands Pi in the first direction a1. The first control signal lines 41 extend along the second direction a2 and are arranged along the first direction a1.

[0133] Multiple second control signal lines 42 are located between adjacent pixel islands Pi in the first direction a1. The second control signal lines 42 extend along the second direction a2 and are arranged along the first direction a1.

[0134] The first control signal line 41 and the second control signal line 42 extend in the same direction as the data signal line 30. One first control signal line 41 and one second control signal line 42 form a group, and a group of control signal lines is set between two adjacent columns of pixel islands.

[0135] The display panel also includes: multiple fixed potential signal lines 50, which are located between adjacent sub-pixel units p in the second direction a2, and the multiple fixed potential signal lines extend along the first direction a1 and are arranged along the second direction a2.

[0136] The fixed potential signal line 50 can extend in the same direction as the scan signal line 20, and one fixed potential line 50 can be grouped with one scan signal line 20. A group of signal lines is set between two adjacent sub-pixel unit rows.

[0137] The control electrode of the second transistor T2 is connected to the first control signal line 41 of the column corresponding to the control unit c, the first electrode of the second transistor T2 is connected to the scan signal line 20 of the row corresponding to the control unit c, and the second electrode of the second transistor T2 is connected to the control electrode of the first transistor T1 in each sub-pixel unit of the row corresponding to the control unit c.

[0138] The control electrode of the third transistor T3 is connected to the second control signal line 42 of the column corresponding to the control unit c, the first electrode of the third transistor T3 is connected to the fixed potential signal line 50 of the row corresponding to the control unit c, and the second electrode of the third transistor T3 is connected to the control electrode of the first transistor T1 in each sub-pixel unit of the row corresponding to the control unit c.

[0139] like Figure 5 As shown, the control electrode of the second transistor T2 in the same control unit c is connected to the first control signal line 41, and the control electrode of the third transistor T3 is connected to the second control signal line 42. Therefore, two control signal lines are used to control the second transistor T2 and the third transistor T3 respectively.

[0140] The second transistor T2 is configured to turn on under the control of a first signal transmitted through the first control signal line 41 and turn off under the control of a second signal transmitted through the first control signal line 42; the third transistor T3 is configured to turn on under the control of a third signal transmitted through the second control signal line 42 and turn off under the control of a fourth signal transmitted through the second control signal line 42.

[0141] In this embodiment, the first control signal line 41 and the second control signal line 42 output a set timing sequence according to a set rule. The second terminals of the second transistor T2 and the third transistor T3 are both connected to the control terminal of the first transistor T1 in each sub-pixel unit of the corresponding row. Therefore, when the second transistor T2 is turned on, the third transistor T3 is turned off; when the third transistor T3 is turned on, the second transistor T2 is turned off.

[0142] by Figure 5For example, a pixel island Pi still includes 2 rows × 2 columns of sub-pixel units p. When the first control signal line 41 transmits the first signal, the second control signal line 42 transmits the fourth signal. The second transistor T2 in the control unit connecting the first row of sub-pixel units and the control unit connecting the second row of sub-pixel units is turned on, and the third transistor T3 is turned off. The second transistor T2 corresponding to the first row of sub-pixel units can transmit the signal of the first row of scan signal line 20 to the control electrode of the first transistor T1 in the first row of sub-pixel units, and the second transistor T2 corresponding to the second row of sub-pixel units can transmit the signal of the second row of scan signal line 20 to the control electrode of the first transistor T1 in the second row of sub-pixel units. Since the scan signal line 20 outputs valid level signals sequentially, if the first row of scan signal line 20 transmits a valid level signal, then the first transistor T1 of the first row of sub-pixel units is turned on, and the data signals loaded by each data signal line 30 are written into the first row of sub-pixel units. After the first row of sub-pixel units finishes scanning, the scan signal line 20 corresponding to the second row of sub-pixel units transmits a valid level signal again, and the same rule as above can be used to write data signals for the second sub-pixel units. The third transistor T3 is turned off under the control of the fourth signal, so the fixed potential transmitted by the fixed potential signal line 50 cannot be transmitted to the control electrode of the first transistor T1 of the corresponding row sub-pixel unit.

[0143] When the first control signal line 41 transmits the second signal, the second control signal line 42 transmits the third signal. The second transistor T2 in the control unit connecting the first row of sub-pixel units and the control unit connecting the second row of sub-pixel units is turned off, and the third transistor T3 is turned on. When the second transistor T2 is off, it cannot transmit the scan signal of the corresponding row to the control electrode of the first transistor T1 in the corresponding row of sub-pixel units. When the third transistor T3 is on, it transmits a fixed potential signal to the control electrode of the first transistor T1 in the corresponding row of sub-pixel units. The first transistor T1 is in a closed state under the control of the fixed potential, thus ensuring that the first transistor T1 is off. Under this condition, no data signal can be written to the sub-pixel units of the corresponding row.

[0144] When using Figure 5The structure shown allows for partitioned refresh of the display panel. For important display areas, or areas the viewer is currently focusing on, when the sub-pixel row corresponding to the important display area is scanned, the corresponding first control signal line 41 can transmit a first signal, and the corresponding second control signal line 42 can transmit a fourth signal. This causes the second transistor T2 corresponding to each sub-pixel unit row in the important display area to turn on, and the third transistor T3 to turn off. The scan signal for the corresponding row is then transmitted to the control electrode of the first transistor T1 of the corresponding sub-pixel unit, thereby refreshing the image data of each sub-pixel unit in the important display area. Simultaneously, when a non-important display area is scanned, the corresponding first control signal line 41 can transmit a second signal, and the corresponding second control signal line 42 can transmit a third signal. This causes the second transistor T2 corresponding to each sub-pixel unit row in the non-important display area to turn off, and the third transistor T3 to turn on. A fixed potential signal is then transmitted to the control electrode of the first transistor T1 of the corresponding sub-pixel unit, keeping the first transistor T1 in the off state, preventing data signals from being written to the sub-pixel units in the non-important display area.

[0145] This allows image data to be refreshed in important display areas while not in non-important display areas. Conversely, when image data is refreshed in non-important display areas, important display areas can be prevented from refreshing, thus enabling important and non-important display areas to refresh image data independently.

[0146] Using two control signal lines can prevent data writing errors caused by timing abnormalities in the control signal lines.

[0147] Figure 5 The structure shown is a planar structure of an OLED panel. The driving circuit (dr) includes components such as storage capacitors, driving transistors, and organic light-emitting diodes. Figure 5 The diagram shows only the simplest pixel circuit structure of an OLED display panel. In practical applications, other OLED pixel circuit structures can also be used, and no limitation is made here.

[0148] In addition to OLED panels, which can use the control unit provided in this embodiment to select and control the sub-pixel rows in the corresponding pixel islands, LCD panels can also be equipped with a control unit. Figure 6 Fifth schematic diagram of the planar structure of the display panel provided in the embodiments of this disclosure.

[0149] like Figure 6 As shown, the sub-pixel unit p includes a first transistor T1 and a driving circuit dr. The driving circuit dr includes at least a storage capacitor, and... Figure 4 The difference in the structure shown is that, Figure 6In the described structure, the first control signal line 41 and the second control signal line 42 are used to independently control the second transistor T2 and the third transistor T3. Other structures are similar to... Figure 4 Same as above, see details. Figure 4 The relevant content will not be repeated here.

[0150] In practical applications, the first transistor T1, the second transistor T2, and the third transistor T3 mentioned above can all be MOS, CMOS, or TFT. Furthermore, these three transistors can be either P-type or N-type transistors.

[0151] In the display panel, such as Figure 5 or Figure 6 In the circuit structure shown, the second transistor T2 and the third transistor T3 are controlled independently using different control signal lines. It is only necessary to keep the second transistor T2 and the third transistor T3 having opposite effects at the same time.

[0152] The second transistor T2 and the third transistor T3 can be of the same type or different types. For example, both the second transistor T2 and the third transistor T3 can be N-type transistors; or both the second transistor T2 and the third transistor T3 can be P-type transistors; or both the second transistor T2 and the third transistor T3 can be P-type transistors; or both the second transistor T2 and the third transistor T3 can be N-type transistors. In practice, the choice can be made according to actual needs, and no limitation is made here.

[0153] For N-type transistors, a high-level signal is an effective signal, while for P-type transistors, a low-level signal is an effective signal.

[0154] When the second transistor T2 is an N-type transistor, the first signal transmitted by the first control signal line 41 is a high-level signal and the second signal is a low-level signal. When the second transistor T2 is a P-type transistor, the first signal transmitted by the first control signal line 41 is a low-level signal and the second signal is a high-level signal.

[0155] When the third transistor T3 is an N-type transistor, the third signal transmitted by the second control signal line 42 is a high-level signal, and the fourth signal is a low-level signal. When the third transistor T3 is a P-type transistor, the third signal transmitted by the second control signal line 42 is a low-level signal, and the fourth signal is a high-level signal.

[0156] Furthermore, the first transistor T1 can be either a P-type transistor or an N-type transistor. When the first transistor T1 is a P-type transistor, it turns on when a low-level signal is transmitted on the corresponding row's scan signal line 20, and turns off when a high-level signal is transmitted on the corresponding row's scan signal line 20. The fixed-level signal transmitted on the fixed-level signal line 50 is used to control the first transistor T1 to turn off; therefore, when the first transistor T1 is a P-type transistor, the fixed-level signal transmitted on the fixed-level signal line 50 is a high-level signal.

[0157] When the first transistor T1 is an N-type transistor, it turns on when a high-level signal is transmitted on the corresponding row's scan signal line 20, and turns off when a low-level signal is transmitted on the corresponding row's scan signal line 20. The fixed-level signal transmitted on the fixed-level signal line 50 is used to control the first transistor T1 to turn off; therefore, when the first transistor T1 is an N-type transistor, the fixed-level signal transmitted on the fixed-level signal line 50 is a low-level signal.

[0158] Based on the same inventive concept, this disclosure also provides a display device. Figure 7 This is a schematic cross-sectional view of the display device provided in an embodiment of the present disclosure.

[0159] like Figure 7 As shown, the display device includes any of the above-mentioned display panels 100, microlens layer 200, and controller 300.

[0160] The microlens layer 200 is located on the light-emitting side of the display panel 100. The microlens layer 200 includes a plurality of microlenses corresponding to the pixel islands of the display panel. The microlenses are used to modulate the emitted light from the pixel islands in the display panel so that the pixel islands are mapped into a pixel array to achieve image display.

[0161] The controller 300 is connected to the display panel 100 and is configured to provide drive signals to the display panel.

[0162] The specific structure of the pixel islands included in the display panel 100 can be adopted. Figure 1The structure is shown. The microlens layer 200 is composed of a microlens array. The microlens layer 200 can modulate the outgoing light from the pixel islands, thereby mapping the pixel islands into a pixel array for image display. By using a structure of pixel islands in conjunction with the microlens layer 200, the imaging resolution can be improved while reaching the physical arrangement limit of the sub-pixel units. The display panel 100 also has a driver chip in the non-display area on one side of the sub-pixel unit column, and cascaded gate driving units are arranged on one or both sides of the sub-pixel unit row. Data signal lines can be connected to the driver chip through multiple multiplexers, and the gates are respectively connected to the corresponding gate driving units. The gate driving units are finally connected to the driver chip, and the controller 300 is connected to the driver chip in the display panel 100. The controller 300 can be a graphics processing unit (GPU) installed in the display device, or it can be a processing device external to the display device; there is no limitation here.

[0163] The controller 300 is configured to provide drive signals to the driver chip of the display panel. If the display area of ​​the display device is divided into an important display area for displaying important image details and other display areas, the controller 300 compresses the image data of the non-important display areas and then transmits the image data of the important and non-important display areas to the driver chip. The driver chip then controls the image data refresh of the important and non-important display areas separately. While ensuring high resolution, high refresh rate, and high response speed in the important display areas, the controller can compress the transmitted data of other non-important display areas, reduce the display resolution and refresh rate, and prioritize the allocation of limited resources to the important display areas. This solves the limitations of high data transmission bandwidth, high device power consumption, and insufficient pixel charging.

[0164] The display device provided in this embodiment may further include a camera (not shown in the figure), which is disposed at the edge of the display device and configured to capture images of the user's eyes, so that the controller 300 determines the user's gaze area on the display device based on the captured images and drives the gaze area and non-gaze area in the display panel 100 to display images at different refresh rates.

[0165] Based on the above-described display device structure, this disclosure also provides a driving method for a display device. Figure 8 A flowchart of a driving method for a display device provided in an embodiment of this disclosure.

[0166] like Figure 8 As shown, the driving method for the display device includes:

[0167] S10. Real-time determination of the user's gaze area and non-gaze area on the display device;

[0168] S20. Drive the gaze area to display the image at a first refresh rate, and drive the non-gaze area to display the image at a second refresh rate.

[0169] The first refresh rate is higher than the second refresh rate.

[0170] This embodiment of the disclosure defines the viewing area and non-viewing area of ​​the image displayed by the display device, drives the viewing area to display the image at a high refresh rate, and drives the non-viewing area to display the image at a low refresh rate, thereby ensuring the image display quality of the viewing area. While driving the viewing area to meet the requirements of high resolution, high refresh rate, and high response speed, the transmission data of the non-viewing area can be compressed, and the display resolution and refresh rate can be reduced, so that limited resources are allocated to the viewing area first. This solves the limitations of high data transmission bandwidth, high device power consumption, and insufficient pixel charging.

[0171] The gaze area can be a fixed region defined by the system. For example, the center area of ​​the display screen can be set as the gaze area, while the edge areas can be set as non-gaze areas. This allows for different image rendering for the gaze and non-gaze areas. While ensuring that the non-gaze areas can fully display the image, the image data in the non-gaze areas is appropriately compressed to reduce their display resolution, thus providing a better display effect in the gaze area. This reduces the overall power consumption of the display device and avoids resource waste.

[0172] In addition, a camera can be installed on the display device, which can then be used to determine the area where the user is looking at the display device.

[0173] Specifically, this includes controlling the camera to capture images of the user's eyes in real time;

[0174] Determine the area of ​​the user's gaze on the display device based on the captured image;

[0175] Areas in the display device other than the gaze area will be defined as non-gaze areas.

[0176] In practical implementation, the displayed image of the display device is usually large, and the human eye will only focus on a local area of ​​the displayed image. Therefore, the embodiments of this disclosure solve the limitations of high data transmission bandwidth, high device power consumption, and insufficient pixel charging by setting a camera on the display device or connecting an external camera to track the human eye's gaze area on the display device in real time.

[0177] To achieve a higher image refresh rate in the gaze area than in the non-gaze area, embodiments of this disclosure can employ the following two methods to refresh the display screen.

[0178] In one feasible approach, each sub-pixel unit within the gaze region can be refreshed a times; and each sub-pixel unit within the non-gaze region can be refreshed b times. Here, a and b are both positive integers, and a is greater than b.

[0179] In other words, the image is refreshed independently for the gaze area and the non-gaze area. When the image data is refreshed in the gaze area, the image data in the non-gaze area is not refreshed; conversely, when the image data is refreshed in the non-gaze area, the image data in the gaze area is not refreshed. This way, by ensuring that the number of image refreshes in the gaze area per unit time is greater than the number of image refreshes in the non-gaze area, the image refresh rate of the gaze area can be higher than that of the non-gaze area, resulting in a more detailed and smoother display image within the gaze area.

[0180] In another feasible approach, each sub-pixel unit within the gaze region can be refreshed c times first; then, each sub-pixel unit within both the gaze region and the non-gaze region can be refreshed d times. Here, c and d are both positive integers.

[0181] In other words, when refreshing the display screen, the image of the gaze area can be refreshed multiple times first. After completing the above refresh operations, the entire display screen can then be refreshed multiple times. This ensures that the number of refreshes in the gaze area is greater than the number of refreshes in the non-gaze area, thus making the image refresh rate of the gaze area higher than that of the non-gaze area. Using this method, the image of the gaze area can be refreshed more times per unit time, which is beneficial for optimizing the display effect of the gaze area.

[0182] Regardless of which image refresh method is used, independent driving control of the gaze area is required. The embodiments of this disclosure can achieve independent refresh control of the gaze area and non-gaze area by using any of the above display panel structures.

[0183] Figure 9 This is a schematic diagram of the planar structure of a display device provided in an embodiment of the present disclosure.

[0184] like Figure 9 As shown, the display area can be divided into multiple regions along the extension direction of the gate drive circuit, so as to... Figure 9 The structure shown in this embodiment can divide the display area into 16 zones, each driven independently by 16 gate driving units (GOA1-GOA16). If the user's gaze area on the display device is determined by a camera or other device... Figure 9 The area corresponding to the black box in the middle is the viewing area, which is driven by the gate driving units GOA5-GOA9.

[0185] When refreshing the image only on the gaze area, combine Figure 3 or Figure 4 Taking the display panel structure shown as an example, the control gate driving units GOA5-GOA9 sequentially transmit valid level signals and control the control signal lines 40 corresponding to the viewing area to transmit first signals, and control the fixed potential signal lines 50 corresponding to the viewing area to transmit fixed potential signals. The second transistor T2 corresponding to each pixel island within the viewing area is turned on, and the third transistor T3 is turned off. The scan signal transmitted by the scan signal line 20 is transmitted through the second transistor T2 to the control electrode of the first transistor T1 of each row of sub-pixel units. The first transistor T1 is turned on under the control of the valid level signal of the scan signal line 20, so that the data signal loaded on the data signal line 30 corresponding to each sub-pixel unit within the viewing area is written into each sub-pixel unit. Simultaneously, the control signal lines 40 corresponding to the non-viewing areas in the sub-pixel rows corresponding to the control gate driving units GOA5-GOA9 transmit second signals, and control the fixed potential signal lines 50 corresponding to the non-viewing areas to transmit fixed potential signals. In the non-focused area, the second transistor T2 corresponding to each pixel island is turned off, and the third transistor T3 is turned on. The fixed potential signal transmitted by the fixed potential signal line 50 is transmitted to the control electrode of the first transistor T1 of each row of sub-pixel units through the third transistor T3. The first transistor T1 remains off under the control of the fixed potential signal, so image data in the non-focused area cannot be written to each sub-pixel unit. This achieves independent image data refresh for the focused area.

[0186] Combined Figure 5 or Figure 6Taking the display panel structure shown as an example, the control gate driving units GOA5-GOA9 sequentially transmit valid level signals and control the first control signal lines 41 corresponding to the viewing area to transmit first signals, control the second control signal lines 42 corresponding to the viewing area to transmit fourth signals, and control the fixed potential signal lines 50 corresponding to the viewing area to transmit fixed potential signals. The second transistor T2 corresponding to each pixel island within the viewing area is turned on, and the third transistor T3 is turned off. The scan signal transmitted by the scan signal line 20 is transmitted through the second transistor T2 to the control electrode of the first transistor T1 of each row of sub-pixel units. The first transistor T1 is turned on under the control of the valid level signal of the scan signal line 20, so that the data signal loaded on the data signal line 30 corresponding to each sub-pixel unit within the viewing area is written into each sub-pixel unit. Simultaneously, the control gate driving units GOA5-GOA9 control the first control signal lines 41 corresponding to the non-viewing areas in the sub-pixel rows to transmit second signals, control the second control signal lines 42 corresponding to the non-viewing areas to transmit third signals, and control the fixed potential signal lines 50 corresponding to the non-viewing areas to transmit fixed potential signals. In the non-focused area, the second transistor T2 corresponding to each pixel island is turned off, and the third transistor T3 is turned on. The fixed potential signal transmitted by the fixed potential signal line 50 is transmitted to the control electrode of the first transistor T1 of each row of sub-pixel units through the third transistor T3. The first transistor T1 remains off under the control of the fixed potential signal, so image data in the non-focused area cannot be written to each sub-pixel unit. This achieves independent image data refresh for the focused area.

[0187] When only the non-focused region is refreshed individually, combined with Figure 3 or Figure 4Taking the displayed panel structure as an example, the gate driving units GOA1-GOA16 sequentially transmit valid level signals. When the sub-pixel unit row corresponding to gate driving units GOA1-GOA4 is scanned, all control signal lines 40 are controlled to transmit the first signal, and all fixed potential signal lines are controlled to transmit fixed potential signals, so that image data can be written to each row of sub-pixel units corresponding to gate driving units GOA1-GOA4. When the sub-pixel unit row corresponding to gate driving units GOA5-GOA9 is scanned, the control signal lines 40 corresponding to the non-focused area are controlled to transmit the first signal, and the control signal lines 40 corresponding to the focused area are controlled to transmit the second signal, thereby ensuring that image data is written to the non-focused area corresponding to gate driving units GOA5-GOA9, and no image data is written to the focused area. When the sub-pixel unit row corresponding to gate driving units GOA10-GOA16 is scanned, all control signal lines 40 are controlled to transmit the first signal, and all fixed potential signal lines are controlled to transmit fixed potential signals, so that image data can be written to each row of sub-pixel units corresponding to gate driving units GOA1-GOA16. This enables the individual refreshing of image data for non-focused regions.

[0188] Combined Figure 5 or Figure 6 Taking the display panel structure shown as an example, the gate driving units GOA1-GOA16 sequentially transmit valid level signals. When the sub-pixel unit row corresponding to gate driving units GOA1-GOA4 is scanned, all first control signal lines 41 are controlled to transmit the first signal, all second control signal lines 42 are controlled to transmit the fourth signal, and all fixed potential signal lines are controlled to transmit the fixed potential signal, so that image data can be written to each row of sub-pixel units corresponding to gate driving units GOA1-GOA4. When the sub-pixel unit row corresponding to gate driving units GOA5-GOA9 is scanned, the first control signal lines 41 corresponding to the non-focused area are controlled to transmit the first signal, the second control signal lines 42 corresponding to the non-focused area are controlled to transmit the fourth signal, and the first control signal lines 41 corresponding to the focused area are controlled to transmit the second signal, and the second control signal lines 42 corresponding to the focused area are controlled to transmit the third signal, thereby ensuring that image data is written to the non-focused areas corresponding to gate driving units GOA5-GOA9, and no image data is written to the focused areas. When the scan reaches the sub-pixel unit row corresponding to gate driving units GOA10-GOA16, all first control signal lines 41 are controlled to transmit the first signal, all second control signal lines 42 are controlled to transmit the fourth signal, and all fixed potential signal lines are controlled to transmit the fixed potential signal, so that image data can be written to each row of sub-pixel units corresponding to gate driving units GOA1-GOA16. This achieves individual image data refresh for non-focused areas.

[0189] When refreshing the entire display area, all control signal lines can be controlled to transmit the first signal, and all fixed potential signal lines can transmit the fixed potential signal line, so that all sub-pixel units are scanned in the conventional way and image data is written to complete the refresh of the entire display screen.

[0190] In practice, the system (i.e., the controller 300) prioritizes refreshing the image of the gaze area, which is refreshed with uncompressed, high-resolution images. Then, the images of the non-gaze area are refreshed, which are refreshed with high-compression, low-resolution images.

[0191] The controller 300 transmits image data from the gaze area and the non-gaze area to the driver chip of the display panel 100. The driver chip first receives the image data and drives the refresh of each sub-pixel unit in the gaze area. After the gaze area is refreshed, the driver chip decompresses the image data in the non-gaze area and drives the refresh of each sub-pixel unit in the non-gaze area.

[0192] In addition, the driver chip can first drive and refresh each sub-pixel unit in the gaze area, and then drive and refresh all sub-pixel units in both the gaze and non-gaze areas. No further limitations are specified here.

[0193] The display panel, display device, and driving method provided in this disclosure, by setting control signal lines and control units in the display panel and coordinating the control timing of pixel islands, enable independent control of sub-pixel unit rows within a pixel island from those within other pixel islands. Based on this, the display panel can be partitioned into image zones, allowing for separate image refreshes between important display areas or areas of focus and other display areas. Important display areas or areas of focus can have a refresh rate N times higher than other display areas. While meeting the requirements of high resolution, high refresh rate, and high response speed for important display areas, the transmitted data for other display areas can be compressed, and the display resolution and refresh rate reduced, prioritizing limited resources for important display areas. This solves the limitations of high data transmission bandwidth, high device power consumption, and insufficient pixel charging.

[0194] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0195] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Therefore, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A display panel, comprising: a substrate substrate; a plurality of scan signal lines located on the substrate substrate, the plurality of scan signal lines extending along a first direction and arranged along a second direction; the first direction and the second direction intersecting; a plurality of data signal lines located on the substrate substrate, the plurality of data signal lines extending along the second direction and arranged along the first direction; a plurality of sub-pixel units respectively located in regions divided by the plurality of scan signal lines and the plurality of data signal lines; at least two sub-pixel units adjacent along the first direction and the second direction constitute a pixel island; a plurality of control units located between adjacent pixel islands in the first direction; one pixel island is connected to n control units, n being the number of rows of sub-pixel units included in the pixel island in the second direction; one control unit corresponds to a row of sub-pixel units in the first direction in the pixel island; each row of sub-pixel units in the pixel island in the second direction is independent of each other; a plurality of control signal lines respectively located between adjacent pixel islands in the first direction, the plurality of control signal lines extending along the second direction and arranged along the first direction; wherein the sub-pixel unit comprises a first transistor and a drive circuit; the first electrode of the first transistor is connected to the data signal line of the corresponding column of the sub-pixel unit, the second electrode of the first transistor is connected to the drive circuit in the sub-pixel unit; the control electrode of the first transistor is connected to the control electrode of the first transistor in each sub-pixel unit located in the same row in the first direction in the pixel island; the control unit comprises a control end, an input end and an output end; the control end of the control unit is connected to the control signal line of the corresponding column, the input end of the control unit is connected to the scan signal line of the corresponding row, and the output end of the control unit is connected to the control electrode of the first transistor in the corresponding row of each sub-pixel unit; the control unit is configured to transmit the signal of the input end to the output end under the control of a first signal transmitted by the control signal line, and cut off the transmission of the signal of the input end to the output end under the control of a second signal transmitted by the control signal line; the control unit comprises a second transistor and a third transistor; the display panel further comprises: a plurality of fixed potential signal lines respectively located between adjacent sub-pixel units in the second direction, the plurality of fixed potential signal lines extending along the first direction and arranged along the second direction; the control electrode of the second transistor is connected to the control signal line of the corresponding column of the control unit, the first electrode of the second transistor is connected to the scan signal line of the corresponding row of the control unit, and the second electrode of the second transistor is connected to the control electrode of the first transistor in the corresponding row of each sub-pixel unit of the control unit. The control electrode of the third transistor is connected to the control signal line corresponding to the column of the control unit, the first electrode of the third transistor is connected to the fixed potential signal line corresponding to the row of the control unit, and the second electrode of the third transistor is connected to the control electrode of the first transistor in each of the sub-pixel units corresponding to the row of the control unit. The second transistor is configured to be turned on under the control of a first signal transmitted by the control signal line and turned off under the control of a second signal transmitted by the control signal line. The third transistor is configured to be turned off under the control of a first signal transmitted by the control signal line and turned on under the control of a second signal transmitted by the control signal line.

2. The display panel of claim 1, wherein, The second transistor is an N-type transistor, and the first signal is a high-level signal and the second signal is a low-level signal; or the second transistor is a P-type transistor, and the first signal is a low-level signal and the second signal is a high-level signal. The second transistor is an N-type transistor, and the first signal is a high-level signal and the second signal is a low-level signal; or the second transistor is a P-type transistor, and the first signal is a low-level signal and the second signal is a high-level signal.

3. The display panel of claim 1, wherein, The control unit comprises a second transistor and a third transistor, the control signal line is a first control signal line, and the display panel further comprises: a plurality of second control signal lines located between adjacent pixel islands in the first direction, the plurality of second control signal lines extending along the second direction and arranged along the first direction; a plurality of fixed potential signal lines located between adjacent sub-pixel units in the second direction, the plurality of fixed potential signal lines extending along the first direction and arranged along the second direction; The control electrode of the second transistor is connected to the first control signal line corresponding to the column of the control unit, the first electrode of the second transistor is connected to the scan signal line corresponding to the row of the control unit, and the second electrode of the second transistor is connected to the control electrode of the first transistor in each of the sub-pixel units corresponding to the row of the control unit. The control electrode of the third transistor is connected to the second control signal line corresponding to the column of the control unit, the first electrode of the third transistor is connected to the fixed potential signal line corresponding to the row of the control unit, and the second electrode of the third transistor is connected to the control electrode of the first transistor in each of the sub-pixel units corresponding to the row of the control unit. The second transistor is configured to be turned on under the control of a first signal transmitted by the first control signal line and turned off under the control of a second signal transmitted by the first control signal line. The third transistor is configured to be turned on under the control of a third signal transmitted by the second control signal line and turned off under the control of a fourth signal transmitted by the second control signal line.

4. The display panel of claim 3, wherein, The second transistor is an N-type transistor, and the first signal is a high-level signal and the second signal is a low-level signal; or the second transistor is a P-type transistor, and the first signal is a low-level signal and the second signal is a high-level signal. The third transistor is an N-type transistor, the third signal is a high-level signal, and the fourth signal is a low-level signal; or, the third transistor is a P-type transistor, the third signal is a low-level signal, and the fourth signal is a high-level signal.

5. The display panel of any of claims 1-3, wherein, The first transistor is an N-type transistor, and the fixed potential signal line is configured to transmit a low-level signal. Or, the first transistor is a P-type transistor, and the fixed potential signal line is configured to transmit a high-level signal.

6. The display panel of claim 1, wherein, The display panel is a liquid crystal display panel or an organic light-emitting diode display panel.

7. The display panel of claim 1, wherein, The display colors of the sub-pixel units included in one pixel island are the same. The display panel includes a plurality of pixel islands, and the plurality of pixel islands at least include a first pixel island displaying a first color and a second pixel island displaying a second color.

8. A display device, comprising the display panel of any one of claims 1-6, a microlens layer, and a controller. The microlens layer is located on the light-emitting side of the display panel, and the microlens layer includes a plurality of microlenses corresponding to the pixel islands of the display panel; the microlenses are used to modulate the outgoing light rays of the pixel islands in the display panel, so that the pixel islands are mapped to a pixel array to realize image display. The controller is connected to the display panel and is configured to provide driving signals to the display panel.

9. The display device of claim 8, further comprising: a camera disposed at a frame position of the display device, the camera being configured to capture images of the user's eyes, so that the controller determines the gaze area of the user on the display device according to the captured images, and drives the gaze area and the non-gaze area in the display panel to display images at different refresh rates.

10. A driving method based on the display device of claim 8 or 9, comprising: determining the gaze area and the non-gaze area of the user on the display device in real time; driving the gaze area to display images at a first refresh rate, and driving the non-gaze area to display images at a second refresh rate; the first refresh rate is higher than the second refresh rate.

11. The driving method of claim 10, wherein, The display device includes a camera; The real-time determination of the gaze area and the non-gaze area of the user on the display device comprises: controlling the camera to capture images of the user's eyes in real time; determining the gaze area of the user on the display device according to the captured images; determining other areas of the display device except the gaze area as the non-gaze area.

12. The driving method according to claim 10 or 11, wherein The driving of the gaze area to display images at a first refresh rate and the driving of the non-gaze area to display images at a second refresh rate comprise: driving each sub-pixel unit in the gaze area a times; driving each sub-pixel unit in the non-gaze area b times; wherein a and b are positive integers, and a is greater than b.

13. The driving method according to claim 10 or 11, wherein The driving of the gaze area to display images at a first refresh rate and the driving of the non-gaze area to display images at a second refresh rate comprise: driving each sub-pixel unit in the gaze area c times; driving each sub-pixel unit in the gaze area and the non-gaze area d times; Wherein, c and d are positive integers.

14. The driving method according to claim 12 or 13, wherein The driving the sub-pixel units in the gaze area to refresh includes: Driving each scanning signal line corresponding to the gaze area to transmit an effective level signal in turn; Controlling each control signal line corresponding to the gaze area to transmit a first signal, and controlling each control signal line corresponding to the non-gaze area to transmit a second signal; The driving the sub-pixel units in the non-gaze area to refresh includes: Driving each scanning signal line in the display panel to transmit an effective level signal in turn; When scanning each sub-pixel unit row corresponding to the gaze area, controlling each control signal line corresponding to the gaze area to transmit the second signal, and controlling each control signal line corresponding to the non-gaze area to transmit the first signal.

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