Wafer abnormality early warning method

Abstract

The application provides a wafer abnormality early warning method. When an abnormality occurs in an exposure process station, repeated abnormal points usually occur at the same position of multiple exposure regions on a wafer. The wafer test image of the wafer that needs to be analyzed for abnormality in the exposure test station is obtained first, and then the wafer test image is divided into a plurality of sub-test images, each of which corresponds to an exposure region on the wafer. Then, the proportion between the maximum number of the sub-test images with repeated abnormal points at the same position and the total number of the sub-test images is obtained. Whether wafer abnormality early warning is needed can be determined based on the proportion. In this way, once an abnormality occurs in the exposure process station, it can be found in time and accurately, wafer abnormality can be effectively warned, and batch defective products can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a wafer abnormality early warning method. BACKGROUND

[0002] The manufacturing process of an integrated circuit chip is very complex, and the production cycle is long. The final shipment generally goes through several hundred or even thousands of steps, involves several hundred machines, and the machines performing the same process step are usually divided into a process station. The wafer is sequentially processed in each process station. In order to ensure that the final product performance is qualified, stable and reliable, and the yield is high, strict requirements are required for all process steps. Therefore, a detection station is set at the end of each process station to detect wafer abnormalities (such as defects and other abnormalities) and monitor each process step to early warn wafer abnormalities, so as to timely find out whether the current process station is abnormal, thereby avoiding the production of batch defective products.

[0003] The exposure process station is one of the most critical process stations in chip manufacturing. It uses a mask on an exposure machine to expose different areas on a wafer, thereby forming a pattern on the wafer. An exposure detection station is provided after the exposure process station and can be used to detect exposure quality. However, since the wafer has passed through other process stations before the exposure process station, the wafer abnormalities detected at the exposure detection station are not necessarily caused by the exposure process station, but may also be caused by the process stations before the exposure process station. Therefore, how to timely and accurately find out whether the exposure process station is abnormal is a problem to be solved at present. SUMMARY

[0004] The present application aims to provide a wafer abnormality early warning method to solve the problem that the exposure process station cannot be timely and accurately found out whether it is abnormal.

[0005] In order to achieve the above-mentioned purpose, the present application provides a wafer abnormality early warning method, comprising:

[0006] Obtaining a wafer test pattern that needs to be analyzed for abnormalities at an exposure test station;

[0007] Dividing the wafer test pattern into a plurality of sub-test patterns, each of the sub-test patterns corresponding to an exposure area on the wafer;

[0008] Obtaining the proportion between the maximum number of sub-test patterns with repeated abnormal points at the same position and the total number of sub-test patterns; and

[0009] Determining whether wafer abnormality early warning is needed based on the proportion.

[0010] Optionally, the wafer test map is a wafer defect test map, and the abnormal points in the wafer test map are positions of defects; or the wafer test map is a wafer electrical property test map, and the abnormal points in the wafer test map are positions of defective dies; or the wafer test map is a wafer parameter test map, and the abnormal points in the wafer test map are positions of abnormal parameters.

[0011] Optionally, when the number of abnormal points in the wafer test map is less than a first threshold, it is determined that the wafer test map needs to be analyzed for abnormalities.

[0012] Optionally, the step of obtaining the maximum number of sub-test maps having repeated abnormal points at the same position comprises:

[0013] In each of the sub-test maps having abnormal points, a circle is drawn with the center of each abnormal point as the center and half of a preset tolerance as the radius to obtain a corresponding first abnormal tolerance map; and,

[0014] All the first abnormal tolerance maps are superimposed, and the maximum number of overlapping circles is the maximum number of sub-test maps having repeated abnormal points at the same position.

[0015] Optionally, in the first abnormal tolerance map, the area within the circle has a gray value of 1, and other areas have a gray value of 0; and,

[0016] When all the first abnormal tolerance maps are superimposed, all the first abnormal tolerance maps are added to obtain a first abnormal tolerance superimposed map, and the maximum gray value in the first abnormal tolerance superimposed map is the maximum number of sub-test maps having abnormal points at the same position.

[0017] Optionally, after it is determined that wafer abnormality early warning is needed, the method further comprises:

[0018] Obtaining the positions of the repeated abnormal points.

[0019] Optionally, the step of obtaining the positions of the repeated abnormal points comprises:

[0020] In each of the sub-test maps having abnormal points, a circle is drawn with the center of each abnormal point as the center and a preset tolerance as the radius to obtain a corresponding second abnormal tolerance map;

[0021] All the second abnormal tolerance maps are superimposed, and the area with the maximum number of overlapping circles is a repeated abnormal area; and,

[0022] The repeated abnormal area and all the abnormal points in the sub-test maps are superimposed, and the abnormal points overlapping the repeated abnormal area are the repeated abnormal points.

[0023] Optionally, in the second abnormal tolerance map, the gray value of the area within the circle is 1, and the gray value of other areas is 0.

[0024] When all the second abnormal tolerance maps are superimposed, all the second abnormal tolerance maps are added to obtain a second abnormal tolerance superposition map, and the area with the maximum gray value in the second abnormal tolerance superposition map is the repeated abnormal area; and,

[0025] The gray value of the abnormal point in the sub-test map is 1, and the gray value of other areas is 0. When the repeated abnormal area and all the abnormal points in the sub-test map are superimposed, the gray value of the repeated abnormal area in the second abnormal tolerance superposition map is set to 1, and the gray value of other areas is set to 0. Then, the second abnormal tolerance superposition map is multiplied by the sum of all the sub-test maps with abnormal points to obtain a repeated abnormal map. The position with the gray value of 1 in the repeated abnormal map is the repeated abnormal point.

[0026] Optionally, when the proportion is greater than a second threshold value, it is determined that wafer abnormality warning is needed.

[0027] In the wafer abnormality warning method provided by the present application, when an abnormality occurs in the exposure process station, a repeated abnormal point usually occurs at the same position of a plurality of exposure areas on the wafer. The present application first acquires a wafer test map that needs to be analyzed for abnormality at the exposure test station, then divides the wafer test map into a plurality of sub-test maps, each of which corresponds to an exposure area on the wafer. Then, the maximum number of sub-test maps with repeated abnormal points at the same position and the total number of sub-test maps are obtained. The proportion between the maximum number and the total number is obtained. Based on the proportion, it can be determined whether wafer abnormality warning is needed. In this way, once an abnormality occurs in the exposure process station, it can be timely and accurately found out, which can effectively warn the wafer abnormality and avoid the production of a large number of defective products. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 The flowchart of the wafer abnormality warning method provided by the present application is shown in the figure.

[0029] Figure 2a The schematic diagram of the wafer test map that needs to be analyzed for abnormality provided by the present application is shown in the figure.

[0030] Figure 2b The schematic diagram of the wafer test map that needs to be analyzed for abnormality provided by the present application is shown in the figure.

[0031] Figure 3 The schematic diagram of the five first abnormal tolerance maps provided by the present application is shown in the figure.

[0032] Figure 4A schematic diagram of a first abnormal tolerance overlay provided for an embodiment of the present application;

[0033] Figure 5 A schematic diagram of five second abnormal tolerance maps provided for an embodiment of the present application;

[0034] Figure 6 A schematic diagram of a second abnormal tolerance overlay provided for an embodiment of the present application;

[0035] Figure 7 A schematic diagram of a processed second abnormal tolerance overlay provided for an embodiment of the present application;

[0036] Figure 8 A schematic diagram of a sum of all sub-test maps with abnormal points provided for an embodiment of the present application;

[0037] Figure 9 A schematic diagram of a sum of all abnormal points in a wafer test map and a repeated abnormal area provided for an embodiment of the present application;

[0038] Figure 10 A schematic diagram of a product of a processed second abnormal tolerance overlay and a sum of all sub-test maps with abnormal points provided for an embodiment of the present application;

[0039] Wherein, the reference signs are:

[0040] A-wafer test map; a1, a2, a3, a4, a5-abnormal points; A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15-sub-test maps; A21, A41, A81, A91, A131-first abnormal tolerance maps; A22, A42, A82, A92, A132-second abnormal tolerance maps;

[0041] a11, a21, a31, a41, a51, a12, a22, a32, a42, a52-circles; B1-first abnormal tolerance overlay; B2, B2'-second abnormal tolerance overlay; q-repeated abnormal area; C-abnormal point overlay; D-repeated abnormal map. DETAILED DESCRIPTION

[0042] The specific embodiments of the present application will be described in more detail below with reference to the accompanying schematic diagrams. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the accompanying schematic diagrams are all in a very simplified form and all use non-precise proportions, only for the purpose of conveniently and clearly assisting the description of the embodiments of the present application.

[0043] Figure 1 A flowchart of a wafer abnormality early warning method provided for the present embodiment. As shown in FIG. 1, the wafer abnormality early warning method provided for the present embodiment includes the following steps. Figure 1As shown, the wafer anomaly early warning method comprises:

[0044] Step S100: Obtain a wafer test graph of a wafer that needs to be analyzed for anomaly at an exposure test site;

[0045] Step S200: Divide the wafer test graph into a plurality of sub-test graphs, each of which corresponds to an exposure area on the wafer;

[0046] Step S300: Obtain a proportion between a maximum number of the sub-test graphs with repeated anomaly points at the same position and a total number of the sub-test graphs; and

[0047] Step S400: Determine whether wafer anomaly early warning is needed based on the proportion.

[0048] In this embodiment, the wafer test graph is a wafer defect test graph, and the anomaly points in the wafer test graph are positions of defects, but this should not be limited. The wafer test graph can also be other wafer test graphs, for example, the wafer test graph can also be a wafer electrical test graph, at this time, the anomaly points in the wafer test graph are positions of defective dies; or the wafer test graph can also be a wafer parameter test graph (thickness measurement graph, size measurement graph, alignment offset graph, etc.), at this time, the anomaly points in the wafer test graph are positions of parameter anomalies.

[0049] Specifically, step S100 is performed to obtain all wafer test graphs of the exposure test site. The wafer test graphs can have anomaly points (i.e., positions of defects) or can have no anomaly points. The number of anomaly points in each wafer test graph is obtained, and the number of anomaly points in each wafer test graph is compared with a preset first threshold value. When the number of anomaly points in the wafer test graph is less than the first threshold value, it indicates that the number of anomaly points in the wafer test graph is small, and there is a possibility of misplacement, and it is determined that the wafer test graph needs to be analyzed for anomaly. Conversely, when the number of anomaly points in the wafer test graph is greater than or equal to the first threshold value, it indicates that the number of anomaly points in the wafer test graph is large and will be stuck by other systems, and it is determined that the wafer test graph does not need to be analyzed for anomaly.

[0050] It should be understood that the present embodiment is not limited to determining whether the wafer test graph needs to be analyzed for anomaly based on the number of anomaly points in the wafer test graph, but can also be determined in other ways, such as based on the sum of areas of the anomaly points or the size of the largest anomaly point in the wafer test graph. Here, it will not be illustrated one by one.

[0051] It should be noted that the exposure test station is a test station arranged after the exposure process station, that is, the wafer is tested after exposure through the exposure test station, so as to obtain the wafer test map.

[0052] Figure 2a A schematic diagram of the wafer test map needing to be analyzed abnormally is provided for the embodiment. As shown in the figure, Figure 2a In the embodiment, the wafer test map A has five abnormal points, which are abnormal points a1, a2, a3, a4 and a5.

[0053] Step S200 is performed, and the wafer test map is divided into a plurality of sub-test maps, each of which corresponds to an exposure area on the wafer. That is, when the wafer passes through the exposure process station, the different areas on the wafer are exposed in turn by using the mask (MASK) on the exposure machine, until the whole wafer is exposed. The area exposed each time is an exposure area, and the sub-test map corresponds to the exposure area one by one.

[0054] It should be noted that the mask on the exposure machine and the exposure field are usually rectangular, so each exposure area on the wafer is also usually rectangular, and the sub-test map is also rectangular, but it should not be limited thereto. Since the wafer is circular, when the edge area of the wafer is exposed, the exposure field of the exposure machine will exceed the wafer, so the sub-test map located at the edge of the wafer test map is not a complete rectangle. At this time, the sub-test map located at the edge of the wafer test map can be filled into a complete rectangle, or it can not be filled and directly used in the subsequent steps, which does not affect the implementation of the present application.

[0055] Figure 2b A schematic diagram of dividing the wafer test map A into a plurality of sub-test maps is provided for the embodiment. As shown in the figure, Figure 2b In the embodiment, the wafer test map A is divided into 15 sub-test maps, which are A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14 and A15. Among them, the abnormal point a1 is located in the sub-test map A2, the abnormal point a2 is located in the sub-test map A4, the abnormal point a3 is located in the sub-test map A8, the abnormal point a4 is located in the sub-test map A9, and the abnormal point a5 is located in the sub-test map A13. There is no abnormal point in the remaining sub-test maps.

[0056] Step S300 is executed to obtain the maximum number of sub-test patterns with repeated anomalies at the same location. A repeated anomaly is an anomaly present at the same location in at least two of the sub-test patterns. Since an anomaly occurs at the exposure process station, multiple exposure areas on the wafer will have repeated anomalies at the same location. Furthermore, this embodiment obtains wafer test patterns from the exposure test station; therefore, it can be assumed that the repeated anomalies are generated by the exposure process station, specifically by the exposure machine.

[0057] Specifically, in each subtest map with anomalies, a circle is drawn with the center of each anomaly as the center and half the preset tolerance as the radius to obtain the corresponding first anomaly tolerance map.

[0058] Optionally, the preset tolerance is an empirical value, and the specific value of the preset tolerance will not be given as an example here.

[0059] Figure 3 This is a schematic diagram of the five first anomaly tolerance diagrams provided in this embodiment. (See diagram below.) Figure 3 As shown, the preset tolerance is γ. The first anomaly tolerance maps A21, A41, A81, A91, and A131 are obtained by drawing circles around the sub-test maps A2, A4, A8, A9, and A13, respectively. Since each sub-test map A2, A4, A8, A9, and A13 has only one anomaly point, the first anomaly tolerance maps A21, A41, A81, A91, and A131 also each have only one circle. The circles in A81, A91, and A131 are circles a11, a21, a31, a41, and a51, respectively. The center of circle a11 is the abnormal point a1, and its radius is γ / 2; the center of circle a21 is the abnormal point a2, and its radius is γ / 2; the center of circle a31 is the abnormal point a3, and its radius is γ / 2; the center of circle a41 is the abnormal point a4, and its radius is γ / 2; and the center of circle a51 is the abnormal point a5, and its radius is γ / 2.

[0060] Next, all the first anomaly tolerance maps are superimposed, and the maximum number of overlapping circles is the maximum number of sub-test maps with duplicate anomalies at the same location. Specifically, in this embodiment, in all the first anomaly tolerance maps, the grayscale value of the area inside the circle is 1, and the grayscale value of other areas (areas outside the circle) is 0. When superimposing all the first anomaly tolerance maps, all the first anomaly tolerance maps are added together to obtain a first anomaly tolerance superimposed map. The maximum grayscale value in the first anomaly tolerance superimposed map is the maximum number of sub-test maps with anomalies at the same location.

[0061] It should be understood that adding all the first abnormal tolerance maps together means adding the gray values ​​of each pixel in all the first abnormal tolerance maps together to obtain the first grayscale map, which is the first abnormal tolerance overlay map.

[0062] For example, Figure 3 In the diagram, the grayscale value inside circles a11, a21, a31, a41, and a51 (the gray area) is 1, while the grayscale value outside circles a11, a21, a31, a41, and a51 (the white area) is 0.

[0063] Figure 4 This is a schematic diagram of the first abnormal tolerance overlay diagram B1 provided in this embodiment. Figure 4 As shown, the first abnormal tolerance maps A21, A41, A81, A91, and A131 are added together to obtain the first abnormal tolerance overlay map B1. The maximum gray value in the first abnormal tolerance overlay map B1 is 2. Figure 4 As can be seen from this, the maximum number of overlapping circles is 2, which means the maximum number of sub-test images with anomalies at the same position is 2 (at most 2 sub-test images have anomalies at the same position).

[0064] Furthermore, after obtaining the maximum number of sub-test maps with duplicate anomalies at the same location, it is also necessary to obtain the ratio between the maximum number of sub-test maps with duplicate anomalies at the same location and the total number of sub-test maps. Specifically, the ratio can be obtained by dividing the maximum number of sub-test maps with duplicate anomalies at the same location by the total number of sub-test maps.

[0065] For example, according to Figure 4 The maximum number of sub-test maps with duplicate anomalies at the same location is 2, and the total number of sub-test maps is 15. Therefore, the proportion can be calculated to be approximately 0.13.

[0066] Step S400 is executed, determining whether a wafer anomaly warning is needed based on the percentage. In this embodiment, after obtaining the percentage, the percentage is compared with a preset second threshold. When the percentage is greater than the second threshold, it indicates that there are many sub-test patterns with repeated anomalies at the same location, and it is determined that a wafer anomaly warning is needed; conversely, when the percentage is less than or equal to the second threshold, it indicates that there are few sub-test patterns with repeated anomalies at the same location, and it is determined that a wafer anomaly warning is not needed.

[0067] For example, if the second threshold is 0.6, and the percentage is 0.13, it can be determined that no wafer anomaly warning is required.

[0068] Furthermore, after determining that a wafer anomaly warning is needed, the location of the repeated anomaly point can be obtained, thereby facilitating subsequent anomaly analysis. It should be noted that although the repeated anomaly point is ideally considered to be an anomaly point at the same location on at least two of the sub-test patterns, due to the existence of positional deviations, the repeated anomaly point is often not necessarily at the same location on at least two of the sub-test patterns in practice, but rather has a certain offset within the error range.

[0069] Based on this, in this embodiment, firstly, in the sub-test map with anomalies, a circle is drawn with the center of each anomaly as the center and the preset tolerance as the radius to obtain the corresponding second anomaly tolerance map.

[0070] Figure 5 This is a schematic diagram of the five second anomaly tolerance diagrams provided in this embodiment. (See diagram below.) Figure 5 As shown, the preset tolerance is γ. The second anomaly tolerance maps A22, A42, A82, A92, and A132 are obtained by drawing circles on the sub-test maps A2, A4, A8, A9, and A13, respectively. Since each sub-test map A2, A4, A8, A9, and A13 has only one anomaly point, the second anomaly tolerance maps A22, A42, A82, A92, and A132 also have only one circle. A22, A42, A82, A92, and A132 are circles a12, a22, a32, a42, and a52, respectively. The center of circle a12 is the abnormal point a1, and its radius is γ; the center of circle a22 is the abnormal point a2, and its radius is γ; the center of circle a32 is the abnormal point a3, and its radius is γ; the center of circle a42 is the abnormal point a4, and its radius is γ / 2; and the center of circle a52 is the abnormal point a5, and its radius is γ.

[0071] Next, all the second anomaly tolerance maps are superimposed. The region with the most overlapping circles is the repeating anomaly region, which is used to characterize the possible locations of the repeating anomaly points. Specifically, in this embodiment, in all the second anomaly tolerance maps, the grayscale value of the area inside the circle is 1, and the grayscale value of other areas (areas outside the circle) is 0. When superimposing all the second anomaly tolerance maps, all the second anomaly tolerance maps are added together to obtain the second anomaly tolerance overlay map. The region with the most overlapping circles in the second anomaly tolerance overlay map is the repeating anomaly region.

[0072] It should be understood that adding all the second abnormal tolerance maps together means adding the gray values ​​of each pixel in all the second abnormal tolerance maps together to obtain the second grayscale map, which is the second abnormal tolerance overlay map.

[0073] For example, Figure 5 In the diagram, the grayscale value inside the circles a12, a22, a32, a42, and a52 (the gray area) is 1, while the grayscale value outside the circles a12, a22, a32, a42, and a52 (the white area) is 0.

[0074] Figure 6 This is a schematic diagram of the second abnormal tolerance overlay diagram B2 provided in this embodiment. (See diagram below.) Figure 6 As shown, the second abnormal tolerance maps A22, A42, A82, A92, and A132 are added together to obtain the second abnormal tolerance overlay map B2. The region with the largest gray value (the region with a gray value of 2) in the second abnormal tolerance overlay map B2 is the repeated abnormal region q.

[0075] Next, the repeated abnormal region is superimposed with all abnormal points in the sub-test image, and the abnormal points overlapping with the repeated abnormal region are the repeated abnormal points. Specifically, in this embodiment, the grayscale value of the abnormal points in the sub-test image is 1, and the grayscale value of other areas is 0. When superimposing the repeated abnormal region with all abnormal points in the sub-test image, the second abnormal tolerance overlay image is processed first. The grayscale value of the repeated abnormal region in the second abnormal tolerance overlay image is set to 1, and the grayscale value of other areas is set to 0. Then, the processed second abnormal tolerance overlay image is multiplied by the sum of all sub-test images with abnormal points to obtain a repeated abnormal image. The position with a grayscale value of 1 in the repeated abnormal image is the repeated abnormal point.

[0076] It should be understood that multiplying the processed second anomaly tolerance overlay image with the sum of all the sub-test images with anomalies involves first adding the corresponding grayscale values ​​of each pixel in all the sub-test images with anomalies to obtain a third grayscale image, and then multiplying the processed second anomaly tolerance overlay image with the corresponding grayscale values ​​of each pixel in the third grayscale image to obtain the duplicate anomaly image.

[0077] Figure 7 This is a schematic diagram of the processed second anomaly tolerance overlay diagram B2' provided in this embodiment. (See diagram below.) Figure 7 As shown, after setting the gray value of the repeated abnormal region q in the second abnormal tolerance overlay B2 to 1 and the gray value of other regions (regions outside the repeated abnormal region q) to 0, the processed second abnormal tolerance overlay B2' is obtained.

[0078] like Figure 2a As shown, in the sub-test images A2, A4, A8, A9, and A13, the grayscale values ​​of outlier points a1, a2, a3, a4, and a5 are 1, while the grayscale values ​​of other areas are 0. Figure 8 This is a schematic diagram showing the sum of all the sub-test graphs with anomalies provided in this embodiment. For example...Figure 8 As shown in the figure, after adding the sub-test images A2, A4, A8, A9 and A13, an abnormal point overlay C (i.e., the third gray scale image mentioned above) is obtained, in which all abnormal points in the sub-test images A2, A4, A8, A9 and A13 (i.e., all abnormal points in the wafer test image) are collected, and the gray scale values of the abnormal points a1, a2, a3, a4 and a5 in the abnormal point overlay C are 1, and the gray scale values of other regions are 0.

[0079] Figure 9 The figure provided in this embodiment shows the wafer test image after the repeated abnormal region is superimposed on all abnormal points in the wafer test image. As shown in the figure, Figure 9 As shown in the figure, after superimposing the second abnormal tolerance overlay B2' and the abnormal point overlay C, it can be seen that there are two abnormal points overlapping with the repeated abnormal region q, which are abnormal points a1 and a2, and it can be seen that the abnormal points a1 and a2 are the repeated abnormal points.

[0080] Figure 10 The figure provided in this embodiment shows the wafer test image after the repeated abnormal region is superimposed on all abnormal points in the wafer test image. As shown in the figure, Figure 10 As shown in the figure, after superimposing the second abnormal tolerance overlay B2' and the abnormal point overlay C, it can be seen that there are two abnormal points overlapping with the repeated abnormal region q, which are abnormal points a1 and a2, and it can be seen that the abnormal points a1 and a2 are the repeated abnormal points.

[0081] It can be understood that, compared with traversing all abnormal points in the wafer test image one by one, the present embodiment adopts the image processing method to find the repeated abnormal points, which is faster, more efficient and more reliable. Especially when the number of masks increases, the advantage of the present application is more obvious.

[0082] After obtaining the position of the repeated abnormal point, wafer early warning information can be issued to remind the user that the exposure process site has occurred abnormally, so as to timely and accurately find out whether the exposure process site has occurred abnormally, effectively warn the wafer abnormality, and the user can repair or correct the exposure machine according to the wafer early warning information, so as to avoid batch defective products.

[0083] To sum up, in the wafer abnormality early warning method provided by the embodiment of the present application, when the exposure process station is abnormal, repeated abnormal points usually appear at the same position of the plurality of exposure regions on the wafer. The wafer test image that needs to be analyzed for abnormality at the exposure test station is first acquired, and then the wafer test image is divided into a plurality of sub-test images, each of which corresponds to an exposure region on the wafer. Then, the proportion between the maximum number of the sub-test images with repeated abnormal points at the same position and the total number of the sub-test images is acquired. Based on the proportion, it can be determined whether the wafer abnormality early warning is needed. In this way, once the exposure process station is abnormal, it can be found in time and accurately, and the wafer abnormality can be effectively warned, so that the batch of defective products can be avoided.

[0084] It should be noted that the embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the system disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part.

[0085] It should also be noted that, although the present application has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present application. For any skilled person in the art, many possible changes and modifications of the technical solutions of the present application can be made, or equivalent embodiments of equivalent changes can be made, without departing from the scope of the technical solutions of the present application. Therefore, any simple modification, equivalent change and modification of the above embodiments made according to the technical essence of the present application, without departing from the content of the technical solutions of the present application, still belongs to the protection scope of the technical solutions of the present application.

[0086] It should also be understood that, unless specifically described or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish the components, elements, steps and the like in the specification, and not to indicate the logical relationship or sequence relationship between the components, elements, steps and the like.

[0087] It is also to be appreciated that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the scope of the present application. It must be noted that, as used herein, the articles "a", "an" and "the" are intended to include both singular and plural references unless the context clearly dictates otherwise. For example, the references "a step" or "an element" can mean one or more steps or elements, and the references "the first step" or "the first element" can mean one or more steps or elements. Also, the use of the term "about" is intended to encompass variations, for example, due to manufacturing or processing tolerances, or variations in the natural properties of a given material. In addition, the use of the term "or" is intended to encompass both exclusive and inclusive meanings of the term, unless the context clearly indicates otherwise. Furthermore, the embodiments of methods and / or apparatuses can be implemented in hardware, software, or a combination thereof.

Claims

1. A wafer abnormality early warning method, characterized by, The method comprises the following steps: obtaining wafer test images that need to be analyzed for abnormalities at an exposure test site; dividing the wafer test images into a plurality of sub-test images, each of which corresponds to an exposure area on a wafer; obtaining a proportion between the maximum number of sub-test images with repeated abnormal points at the same position and the total number of sub-test images; the step of obtaining the maximum number of sub-test images with repeated abnormal points at the same position comprises: in each sub-test image with abnormal points, drawing a circle with the center of each abnormal point as the center and half of the preset tolerance as the radius to obtain a corresponding first abnormal tolerance image; and superimposing all the first abnormal tolerance images, the maximum number of overlapping circles being the maximum number of sub-test images with repeated abnormal points at the same position; and determining whether wafer abnormality warning is needed based on the proportion; in the first abnormal tolerance image, the gray value of the area within the circle is 1, and the gray value of other areas is 0; when all the first abnormal tolerance images are superimposed, all the first abnormal tolerance images are added to obtain a first abnormal tolerance superimposed image, and the maximum gray value in the first abnormal tolerance superimposed image is the maximum number of sub-test images with abnormal points at the same position; when it is determined that wafer abnormality warning is needed, the method further comprises the following steps: obtaining the positions of the repeated abnormal points, which comprises: in each sub-test image with abnormal points, drawing a circle with the center of each abnormal point as the center and the preset tolerance as the radius to obtain a corresponding second abnormal tolerance image; superimposing all the second abnormal tolerance images, the area with the maximum number of overlapping circles being a repeated abnormal area; and superimposing the repeated abnormal area and all the abnormal points in the sub-test images, the abnormal points overlapping the repeated abnormal area being the repeated abnormal points; in the second abnormal tolerance image, the gray value of the area within the circle is 1, and the gray value of other areas is 0; when all the second abnormal tolerance images are superimposed, all the second abnormal tolerance images are added to obtain a second abnormal tolerance superimposed image, and the area with the maximum gray value in the second abnormal tolerance superimposed image is the repeated abnormal area; the gray value of the abnormal points in the sub-test images is 1, and the gray value of other areas is 0; when the repeated abnormal area and all the abnormal points in the sub-test images are superimposed, the gray value of the repeated abnormal area in the second abnormal tolerance superimposed image is set to 1, and the gray value of other areas is set to 0, then the second abnormal tolerance superimposed image is multiplied by the sum of all the sub-test images with abnormal points to obtain a repeated abnormal image, and the positions with a gray value of 1 in the repeated abnormal image are the repeated abnormal points.

2. The wafer abnormality early warning method according to claim 1, wherein The wafer test images are wafer defect test images, the abnormal points in the wafer test images are the positions of defects; or the wafer test images are wafer electrical test images, the abnormal points in the wafer test images are the positions of defective dies; or the wafer test images are wafer parameter test images, the abnormal points in the wafer test images are the positions of parameter abnormalities.

3. The wafer abnormality early warning method according to claim 1, wherein When the number of abnormal points in the wafer test map is less than a first threshold value, it is determined that the wafer test map needs to be analyzed for abnormalities.

4. The wafer abnormality early warning method according to claim 1, wherein When the proportion is greater than a second threshold value, it is determined that a wafer abnormality warning is needed.

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