Data processing method, device, electronic device and computer-readable storage medium

Abstract

The embodiments of the present application provide a data processing method, device, electronic device and computer-readable storage medium, which relate to the field of computer technology. By responding to a data request, it is determined whether the target data requested by the data request exists in the data cache of the processor; when the target data exists in the data cache and the target data meets the preset status update conditions, the data status information of the target data is updated. Because the data status information is stored in a pre-expanded register stack. In this way, on the one hand, since the register stack has multiple read ports and multiple write ports, when writing updated data status information, there is no need to arbitrate with other read data requests; on the other hand, the material properties of the register stack are relatively stable, and if the material properties are stable, the stored data is not prone to errors, so there is no need to generate corresponding verification information when writing data status information. Therefore, the timing of updating the data status information is shorter, thereby improving CPU performance.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and more specifically, to a data processing method, device, electronic device, and computer-readable storage medium. Background Art

[0002] In computer technology, cache is typically divided into three levels: Level 1 (L1), Level 2 (L2), and Level 3 (L3). L1 is the fastest, L2 is the second fastest, and L3 is the slowest. L1 has the smallest capacity, L2 has the largest, and L3 has the largest. These three levels of cache serve as a high-speed data buffer between the CPU and main memory.

[0003] In the secondary cache, multiple data requests for reading / writing data are usually received. For each data request, the last processing operation of executing the data request is to update the data status of the requested data, that is, to update the consistency status of the cache line. The data status is used to indicate whether the requested data has been modified during the execution of the data request. For example, during the execution of the data request, if the requested data has been modified, the data status of the requested data is dirty data; if the requested data has not been modified, the data status of the requested data is clean data.

[0004] In the prior art, data status is usually stored in a tag random access memory (tag-RAM). The tag-RAM usually has only one port through which read and write operations are performed. In this way, the timing for updating the data status is long, which affects CPU performance. Summary of the Invention

[0005] The purpose of this application is to solve at least one of the above-mentioned technical defects, especially the technical defect that the updating time sequence of data status in the secondary cache of computer devices is long, which affects the CPU performance.

[0006] According to one aspect of the present application, a data processing method is provided, the method comprising:

[0007] In response to a data request, determining whether target data requested by the data request exists in a data cache of a processor;

[0008] When the target data exists in the data cache and the target data meets a preset status update condition, updating the data status information of the target data;

[0009] The data status information is stored in a pre-extended register stack of the processor; the updated target status information includes first indication information, and the first indication information indicates whether the target data is modified during the execution of the data request.

[0010] Optionally, determining whether the target data requested by the data request exists in the data cache of the processor includes:

[0011] Obtaining a first data address carried in the data request, and obtaining data address information of data in the data cache;

[0012] In a case where a second data address that is consistent with the first data address exists in the data address information, it is determined that the target data requested by the data request exists in the data cache.

[0013] Optionally, the data address information and the data status information are stored separately;

[0014] The data address information is stored in a random access memory, and the data status information is stored in a register file.

[0015] Optionally, the method further includes:

[0016] Obtaining verification information corresponding to each data address in the data address information;

[0017] Verifying the data address and its corresponding verification information;

[0018] When a preset data relationship is satisfied between the data address and the verification information, the processing step of determining whether the target data requested by the data request exists in the data cache when a second data address consistent with the first data address exists in the data address information is executed.

[0019] Optionally, the status update condition includes at least one of the following:

[0020] The target data does not exist in the core of the processor;

[0021] The target data does not exist on the data bus connected to the processor;

[0022] There is no conflicting request for operating the target data, and the conflicting request is a request other than the data request.

[0023] Optionally, the register file includes at least two read / write ports.

[0024] According to another aspect of the present application, a data processing device is provided, the device comprising:

[0025] an information determination module, configured to determine, in response to a data request, whether target data requested by the data request exists in a data cache of the processor;

[0026] an information updating module, configured to update data status information of the target data when the target data exists in the data cache and the target data meets a preset status update condition;

[0027] The data status information is stored in a pre-extended register stack of the processor; the updated target status information includes first indication information, and the first indication information indicates whether the target data is modified during the execution of the data request.

[0028] According to another aspect of the present application, a processor is provided, including:

[0029] an information determining unit, configured to determine, in response to a data request, whether target data requested by the data request exists in a data cache of the processor;

[0030] an information updating unit, configured to update data status information of the target data when the target data exists in the data cache and the target data meets a preset status update condition;

[0031] a pre-extended register file, which is used to store the data status information;

[0032] The updated target status information includes first indication information, and the first indication information indicates whether the target data is modified during the execution of the data request.

[0033] According to another aspect of the present application, an electronic device is provided, the electronic device comprising:

[0034] one or more processors;

[0035] Memory;

[0036] One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more programs are configured to: execute the data processing method described in any one of the first aspects of the present application.

[0037] For example, a third aspect of the present application provides a computing device, including: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus;

[0038] The memory is used to store at least one executable instruction, and the executable instruction enables the processor to perform operations corresponding to the data processing method shown in the first aspect of the present application.

[0039] According to another aspect of the present application, a computer-readable storage medium is provided, and when the computer program is executed by a processor, the data processing method described in any one of the first aspects of the present application is implemented.

[0040] For example, the fourth aspect of the embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the data processing method shown in the first aspect of the present application is implemented.

[0041] According to one aspect of the present application, a computer program product or computer program is provided, comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the methods provided in various optional implementations of the first aspect described above.

[0042] The beneficial effects of the technical solution provided by this application are:

[0043] In an embodiment of the present application, data status information is stored in a pre-extended register stack. When the target data exists in the data cache and the target data meets the preset status update conditions, the updated data status information of the target data is written to the register stack. In this way, on the one hand, since the register stack has multiple read ports and multiple write ports, when writing the updated data status information (i.e., updating the data status information), there is no need to arbitrate with other read data requests; on the other hand, the material properties of the register stack are relatively stable. If the material properties are stable, the stored data is not prone to errors, so there is no need to generate corresponding verification information when writing the data status information. Therefore, the time for the above-mentioned arbitration and generation of verification information is saved, so that the timing of updating the data status information is shorter, thereby shortening the locking time of the cache line where the target data is located when updating the data status information, which is beneficial for other requests to access the cache line, thereby improving CPU performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments of the present application.

[0045] Figure 1 One of the flow charts of a data processing method provided in an embodiment of the present application;

[0046] Figure 2A second flow chart of a data processing method provided in an embodiment of the present application;

[0047] Figure 3 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application;

[0048] Figure 4 A schematic diagram of the structure of a processor provided in an embodiment of the present application;

[0049] Figure 5 A schematic diagram of the structure of an electronic device for data processing provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0051] Those skilled in the art will understand that, unless otherwise stated, the singular forms "a", "an", "said", and "the" used herein may also include plural forms. It should be further understood that the terms "including" and "comprising" used in the embodiments of the present application mean that the corresponding features can be implemented as the presented features, information, data, steps, operations, elements, and / or components, but do not exclude implementation as other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the present technical field. It should be understood that when we say that an element is "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or it can refer to the element and the other element establishing a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used here can include wireless connection or wireless coupling. The term "and / or" used here indicates at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or as "B", or as "A and B".

[0052] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0053] First, several terms involved in this application are introduced and explained:

[0054] L2 cache: Second level cache, integrated on the motherboard or CPU.

[0055] Cache: A small, high-speed memory located between the CPU and main memory (DRAM), typically composed of SRAM (Static Random Access Memory). It's a small, high-speed memory located between the CPU and main memory. The CPU is much faster than main memory. Direct access to data from main memory requires a certain period of time. However, cache can store data that the CPU has just used or is reusing. If the CPU needs to use that data again, it can directly retrieve it from the cache. This avoids repeated data access, reduces CPU wait time, and thus improves system efficiency.

[0056] Cache line: The data in the cache is read in blocks. When the CPU accesses a piece of data, it assumes that the data near it will be accessed later. Therefore, when this area is accessed for the first time, the data will be read into the cache together with the data in the surrounding area (a total of 64 bytes). Then this block of data is called a cache line.

[0057] In the secondary cache, multiple data requests for reading / writing data are usually received. For each data request, the last processing operation of executing the data request is to update the data status of the target data corresponding to the data request, that is, to update the consistency status of the cache line. The data status is reflected by the status bits of the random access memory (RAM) that stores the data status. The status bits usually include a valid bit (Valid, V), a used bit (Used, U), and a modified bit (Dirty, D, also known as a dirty bit). The V bit indicates whether the corresponding tag is a valid tag; the U bit indicates whether the corresponding tag is the least recently used tag in the S path; and the D bit indicates whether the current tag has been modified and has not been written back to the main memory.

[0058] In the prior art, the data status and data address of the target data are usually stored in a random access memory (tag-RAM). The tag-RAM usually has only one port, and read and write operations are performed through one port. In this way, when updating the data status, that is, when writing the data status to the tag-RAM through this port, since both read and write operations need to be performed through this port, the operation of updating the data status needs to be sequenced and executed with multiple other read and write requests (that is, the operation of updating the data status needs to be arbitrated with multiple other read and write requests to determine the execution order), which results in a longer timing for updating the data status and affects the CPU performance.

[0059] In response to the above technical problems, this application provides a data processing method, combining Figure 1 As shown, after receiving a data request, it can be determined whether the target data requested by the data request exists in the secondary cache (an example of "data cache" in this application) during the tArb to t2 stages. When the target data exists in the secondary cache and the data status information of the target data meets the preset status update conditions, the data status information of the target data is updated in the pre-extended register stack during the t3 stage.

[0060] That is to say, in the present application, the data status information of the data in the secondary cache is stored in a pre-extended register stack. Since the register stack has multiple ports, when updating the data status information, the updated data status information can be written to the register stack through a separate write port, without performing arbitration processing caused by sharing a port with other data read requests. Therefore, the timing of updating the data status is shorter.

[0061] The following describes several exemplary embodiments to illustrate the technical solutions of the embodiments of the present application and the technical effects produced by the technical solutions of the present application. It should be noted that the following embodiments can refer to, draw on, or combine with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0062] See also Figure 2 The embodiment of the present application provides a data processing method. Optionally, the method is applied to a processor, which may be a CPU or a graphics processing unit (GPU). Specifically, the method may include the following steps:

[0063] S201: In response to a data request, determine whether target data requested by the data request exists in a data cache of a processor.

[0064] Optionally, the embodiments of the present application can be applied to the field of computer technology, and specifically can be applied to application scenarios in which the consistency state of a cache line is updated in a data cache. Updating the consistency state of a cache line means updating the data state information of the data in the cache line.

[0065] In actual scenarios, a data request can be any request for performing a data operation on target data in a data cache, such as reading, writing, modifying, or invalidating the target data. A data cache may be, for example, a Level 2 cache (L2 cache) or a Level 3 cache (L3 cache).

[0066] After receiving the data request, it is necessary to determine whether the target data requested by the data request exists in the data cache, that is, to determine whether the data request is a hit in the data cache. If the target data exists in the data cache, the judgment result is a hit; if the target data does not exist in the data cache, the judgment result is a miss.

[0067] When determining whether the data request hits the data cache, the determination may be based on the data address carried in the data request.

[0068] Specifically, after receiving a data request, the data address carried in the data request can be obtained. The data address is the address of the target data requested by the data request. To facilitate distinguishing other data addresses involved in this application, this address will be referred to as the first data address in the following.

[0069] In addition, data address information of the data in the data cache needs to be obtained. In an embodiment of the present application, the data address information is information of the cache line where the data is located in the data cache. For example, the cache line information can be an identifier of the cache line.

[0070] The data address information is stored in a random access memory (RAM). For example, the RAM can be a static random access memory (SRAM). SRAM is fast and is typically used as a temporary data storage medium for operating systems or other running programs.

[0071] A random access memory (RAM) typically has a read / write port through which data stored in the RAM can be read from the RAM or written to the RAM. Since both the read and write operations are performed through a single port, when multiple read and write operations are performed on the RAM, an arbitration process is typically required to determine whether the port is idle and the order in which the multiple read and write operations are performed.

[0072] Optionally, since the data address information is part of the data tag information (the data tag information includes the data address information and the data status information), in the embodiment of the present application, the random access memory storing the data address information may be a tag random access memory (tag-RAM).

[0073] Furthermore, after obtaining the first data address and the data address information, it is determined whether a second data address identical to the first data address exists in the data address information. If the second data address identical to the first data address exists, it indicates that the target data requested by the data request exists in the data cache, i.e., the data request is a hit in the data cache. If the second data address identical to the first data address does not exist, it indicates that the target data requested by the data request does not exist in the data cache, i.e., the data request is a miss in the data cache.

[0074] S202: When the target data exists in the data cache and the target data meets a preset status update condition, update the data status information of the target data.

[0075] The data status information is stored in a pre-extended register stack of the processor; the updated target status information includes first indication information, and the first indication information indicates whether the target data is modified during the execution of the data request.

[0076] Specifically, when the target data exists in the data cache, the data request can be executed. Executing the data request means performing a data operation on the target data in the data cache, such as reading, writing, modifying, or invalidating the target data.

[0077] The last processing action in executing the data request is to update the data status information of the target data, that is, to update the consistency state of the cache line. Specifically, the data status information is used to indicate whether the target data has been modified during the execution of the data request. For example, if the target data has been modified during the execution of the data request, the data status of the target data is dirty data; if the target data has not been modified, the data status of the target data is clean data.

[0078] In an embodiment of the present application, when the target data meets a preset status update condition, the data status information of the target data may be updated in a pre-extended register file.

[0079] The register file is an array of multiple registers in the CPU, typically implemented as fast static random access memory (SRAM). It has dedicated read and write ports, enabling multiple concurrent accesses to different registers. In specific implementations, the register file has multiple read ports and multiple write ports. For example, in some embodiments, the register file has nine read ports and four write ports.

[0080] In addition, the preset status update conditions may include that the target data does not exist in the CPU core, the target data does not exist on the data bus connected to the CPU, there is no data request for other operations on the target data (ie, conflicting request), etc.

[0081] In summary, in an embodiment of the present application, data status information is stored in a pre-extended register stack. When the target data exists in the data cache and the target data meets the preset status update conditions, the updated data status information of the target data is written to the register stack. In this way, on the one hand, since the register stack has multiple read ports and multiple write ports, when writing the updated data status information (i.e., updating the data status information), there is no need to arbitrate with other read data requests; on the other hand, the material properties of the register stack are relatively stable, and if the material properties are stable, the stored data is less prone to errors, so there is no need to generate corresponding verification information when writing the data status information. Therefore, the time for the above-mentioned arbitration and generation of verification information is saved, so that the timing of updating the data status information is shorter, thereby shortening the locking time of the cache line where the target data is located when updating the data status information, which is beneficial for other requests to access the cache line, thereby improving CPU performance.

[0082] In one embodiment of the present application, determining whether the target data requested by the data request exists in the data cache of the processor includes:

[0083] Obtaining a first data address carried in the data request, and obtaining data address information of data in the data cache;

[0084] In a case where a second data address that is consistent with the first data address exists in the data address information, it is determined that the target data requested by the data request exists in the data cache.

[0085] Specifically, after receiving the data request, the first data address carried in the data request may be obtained, where the first data address is the address of the target data requested by the data request.

[0086] In addition, data address information of the data in the data cache needs to be obtained. The data address information is information of the cache line where the data is located in the data cache. For example, the cache line information may be an identifier of the cache line.

[0087] Furthermore, after obtaining the first data address and the data address information, it is determined whether a second data address identical to the first data address exists in the data address information. If the second data address identical to the first data address exists, it indicates that the target data requested by the data request exists in the data cache, i.e., the data request is a hit in the data cache. If the second data address identical to the first data address does not exist, it indicates that the target data requested by the data request does not exist in the data cache, i.e., the data request is a miss in the data cache.

[0088] In one embodiment of the present application, the method further includes:

[0089] Obtaining verification information corresponding to each data address in the data address information;

[0090] Verifying the data address and its corresponding verification information;

[0091] When a preset data relationship is satisfied between the data address and the verification information, the processing step of determining whether the target data requested by the data request exists in the data cache when a second data address consistent with the first data address exists in the data address information is executed.

[0092] In an embodiment of the present application, the data address information is stored in a random access memory. Since the random access memory is sensitive to environmental influences, such as electrostatic influences, radiation influences, etc., static electricity may interfere with the charge of the capacitor in the memory, resulting in data loss, etc. Therefore, after obtaining the data address information from the random access memory, it is necessary to verify the accuracy of the data address information.

[0093] Specifically, when obtaining data address information, it is also necessary to obtain verification information of each data address from the random access memory, the verification information being, for example, an Error Correcting Code (ECC).

[0094] Then, the data address and its corresponding verification information are verified. The verification is to verify whether the data address and its corresponding verification information satisfy a preset data relationship (a preset data relationship, such as a preset function relationship). If the preset data relationship is satisfied between the data address and the verification information, the accuracy of the data address information can be confirmed.

[0095] The following combination Figure 1 , taking the data cache as the second-level cache as an example, the overall implementation process of the embodiment of the present application is described:

[0096] After receiving the data request, the first data address carried by the data request can be obtained, and the data address information and checksum information (ECC) of the data in the secondary cache can be obtained from the random access memory (tag-RAM), that is, Figure 1 In the actual scenario, during the tArb and t1 phases, while reading the data address information and the checksum information (ECC), the data state information can also be read from the register file (tag state reg).

[0097] Then, each data address in the data address information is verified with its corresponding verification information to ensure the accuracy of the data address. And it is determined whether there is a second data address in the data address information that is consistent with the first data address, that is, whether the data request is a hit or a miss in the secondary cache. Figure 1 The treatment at stage t2 is shown in FIG.

[0098] When the data request hit is determined, the data request can be executed. In the final stage of the data request execution, when the target data meets the preset status update condition, the data status information of the target data is updated in the register file. Figure 1 The treatment at stage t3 is shown in FIG.

[0099] In an embodiment of the present application, data status information is stored in a pre-extended register stack. When the target data exists in the data cache and the target data meets the preset status update conditions, the updated data status information of the target data is written to the register stack. In this way, on the one hand, since the register stack has multiple read ports and multiple write ports, when writing the updated data status information (i.e., updating the data status information), there is no need to arbitrate with other read data requests; on the other hand, the material properties of the register stack are relatively stable. If the material properties are stable, the stored data is not prone to errors, so there is no need to generate corresponding verification information when writing the data status information. Therefore, the time for the above-mentioned arbitration and generation of verification information is saved, so that the timing of updating the data status information is shorter, thereby shortening the locking time of the cache line where the target data is located when updating the data status information, which is beneficial for other requests to access the cache line, thereby improving CPU performance.

[0100] The present application embodiment provides a data processing device, such as Figure 3 As shown, the data processing device 30 may include: an information determination module 301, an information update module 302, wherein:

[0101] An information determination module 301 is configured to determine, in response to a data request, whether target data requested by the data request exists in a data cache of a processor;

[0102] An information updating module 302 is configured to update data status information of the target data when the target data exists in the data cache and the target data meets a preset status update condition;

[0103] The data status information is stored in a pre-extended register stack of the processor; the updated target status information includes first indication information, and the first indication information indicates whether the target data is modified during the execution of the data request.

[0104] In one embodiment of the present application, the information determination module is configured to:

[0105] Obtaining a first data address carried in the data request, and obtaining data address information of data in the data cache;

[0106] In a case where a second data address that is consistent with the first data address exists in the data address information, it is determined that the target data requested by the data request exists in the data cache.

[0107] In one embodiment of the present application, the data address information and the data status information are stored separately;

[0108] The data address information is stored in a random access memory, and the data status information is stored in a register file.

[0109] In one embodiment of the present application, the apparatus further comprises a verification module, configured to obtain verification information corresponding to each data address in the data address information;

[0110] Verifying the data address and its corresponding verification information;

[0111] When a preset data relationship is satisfied between the data address and the verification information, the processing step of determining whether the target data requested by the data request exists in the data cache when a second data address consistent with the first data address exists in the data address information is executed.

[0112] In one embodiment of the present application, the status update condition includes at least one of the following:

[0113] The target data does not exist in the core of the processor;

[0114] The target data does not exist on the data bus connected to the processor;

[0115] There is no conflicting request for operating the target data, and the conflicting request is a request other than the data request.

[0116] In one embodiment of the present application, the register file includes at least two read / write ports.

[0117] The embodiment of the present application provides a processor, such as Figure 4 As shown, the processor 40 may include: an information determination unit 401, an information update unit 402, and a pre-extended register file 403, wherein:

[0118] An information determining unit 401 is configured to determine, in response to a data request, whether target data requested by the data request exists in a data cache of a processor;

[0119] An information updating unit 402 is configured to update data status information of the target data when the target data exists in the data cache and the target data meets a preset status update condition;

[0120] A pre-extended register file 403, which is used to store the data status information;

[0121] The updated target status information includes first indication information, and the first indication information indicates whether the target data is modified during the execution of the data request.

[0122] The device of the embodiment of the present application can execute the method provided by the embodiment of the present application, and its implementation principle is similar. The actions performed by each module in the device of each embodiment of the present application correspond to the steps in the method of each embodiment of the present application. For the detailed functional description of each module of the device, please refer to the description in the corresponding method shown in the previous text, and will not be repeated here.

[0123] In an embodiment of the present application, data status information is stored in a pre-extended register stack. When the target data exists in the data cache and the target data meets the preset status update conditions, the updated data status information of the target data is written to the register stack. In this way, on the one hand, since the register stack has multiple read ports and multiple write ports, when writing the updated data status information (i.e., updating the data status information), there is no need to arbitrate with other read data requests; on the other hand, the material properties of the register stack are relatively stable. If the material properties are stable, the stored data is not prone to errors, so there is no need to generate corresponding verification information when writing the data status information. Therefore, the time for the above-mentioned arbitration and generation of verification information is saved, so that the timing of updating the data status information is shorter, thereby shortening the locking time of the cache line where the target data is located when updating the data status information, which is beneficial for other requests to access the cache line, thereby improving CPU performance.

[0124] In an embodiment of the present application, an electronic device is provided, comprising: a memory and a processor; at least one program stored in the memory for execution by the processor. Compared with the prior art, the following can be achieved: in an embodiment of the present application, data state information is stored in a pre-extended register file. When the target data exists in the data cache and the target data meets a preset state update condition, the updated data state information of the target data is written to the register file. In this way, on the one hand, because the register file has multiple read ports and multiple write ports, when writing the updated data state information (i.e., updating the data state information), there is no need to arbitrate with other read data requests; on the other hand, the material properties of the register file are relatively stable. If the material properties are stable, the stored data is less prone to errors, thereby eliminating the need to generate corresponding check information when writing the data state information. Therefore, the time for the above arbitration and generation of check information is saved, making the timing of updating the data state information shorter, thereby shortening the lock time of the cache line where the target data is located when updating the data state information, which is beneficial for other requests to access the cache line, thereby improving CPU performance.

[0125] In an alternative embodiment, an electronic device is provided, such as Figure 5 As shown, Figure 5 The electronic device 4000 shown includes: a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, for example, via a bus 4002. Optionally, the electronic device 4000 may further include a transceiver 4004, which may be used for data exchange between the electronic device and other electronic devices, such as data transmission and / or data reception. It should be noted that in actual applications, the number of transceivers 4004 is not limited to one, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present application.

[0126] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 4001 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0127] Bus 4002 may include a path for transmitting information between the above components. Bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. Bus 4002 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0128] The memory 4003 may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, optical disk storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to these.

[0129] The memory 4003 is used to store the application code (computer program) for executing the solution of the present application, and the execution is controlled by the processor 4001. The processor 4001 is used to execute the application code stored in the memory 4003 to implement the content shown in the above method embodiment.

[0130] Electronic devices include but are not limited to mobile phones, laptops, multimedia players, desktop computers, etc.

[0131] An embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer-readable storage medium is run on a computer, the computer can execute the corresponding contents of the aforementioned method embodiment.

[0132] In an embodiment of the present application, data status information is stored in a pre-extended register stack. When the target data exists in the data cache and the target data meets the preset status update conditions, the updated data status information of the target data is written to the register stack. In this way, on the one hand, since the register stack has multiple read ports and multiple write ports, when writing the updated data status information (i.e., updating the data status information), there is no need to arbitrate with other read data requests; on the other hand, the material properties of the register stack are relatively stable. If the material properties are stable, the stored data is not prone to errors, so there is no need to generate corresponding verification information when writing the data status information. Therefore, the time for the above-mentioned arbitration and generation of verification information is saved, so that the timing of updating the data status information is shorter, thereby shortening the locking time of the cache line where the target data is located when updating the data status information, which is beneficial for other requests to access the cache line, thereby improving CPU performance.

[0133] The terms "first," "second," "third," "fourth," "1," "2," and the like (if any) in the specification and claims of this application and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the application described herein can be implemented in an order other than that shown or described in the drawings.

[0134] It should be understood that, although each operation step is indicated by arrows in the flowchart of the embodiment of the present application, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless otherwise clearly stated herein, in some implementation scenarios of the embodiment of the present application, the implementation steps in each flowchart can be performed in other orders according to demand. In addition, some or all of the steps in each flowchart can include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage in these sub-steps or stages can also be executed at different times respectively. Under different scenarios at the execution time, the execution order of these sub-steps or stages can be flexibly configured according to demand, and the embodiment of the present application does not limit this.

[0135] The above description is only an optional implementation method for some implementation scenarios of this application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of this application, the use of other similar implementation methods based on the technical ideas of this application also falls within the protection scope of the embodiments of this application.

Claims

1. A data processing method, characterized in that: include: In response to a data request, determining whether target data requested by the data request exists in a data cache of a processor; When the target data exists in the data cache and the target data meets a preset status update condition, updating the data status information of the target data; Wherein, the data state information is stored in a pre-extended register file of the processor; The register stack has multiple ports. When writing updated data status information, the updated data status information is written to the register stack through a separate write port, without performing arbitration processing caused by sharing a port with other data read requests; the updated data status information includes first indication information, and the first indication information indicates whether the target data is modified during the execution of the data request.

2. The data processing method according to claim 1, wherein: Determining whether the target data requested by the data request exists in the data cache of the processor includes: Obtaining a first data address carried in the data request, and obtaining data address information of data in the data cache; In a case where a second data address that is consistent with the first data address exists in the data address information, it is determined that the target data requested by the data request exists in the data cache.

3. The data processing method according to claim 2, characterized in that: The data address information and the data status information are stored separately; The data address information is stored in a random access memory, and the data status information is stored in a register file.

4. The data processing method according to claim 2, wherein: The method further comprises: Obtaining verification information corresponding to each data address in the data address information; Verifying the data address and its corresponding verification information; When a preset data relationship is satisfied between the data address and the verification information, the processing step of determining whether the target data requested by the data request exists in the data cache when a second data address consistent with the first data address exists in the data address information is executed.

5. The data processing method according to claim 1, wherein: The status update condition includes at least one of the following: The target data does not exist in the core of the processor; The target data does not exist on the data bus connected to the processor; There is no conflicting request for operating the target data, and the conflicting request is a request other than the data request.

6. The data processing method according to claim 1, wherein: The register file includes at least two read / write ports.

7. A data processing device, characterized in that: include: an information determination module, configured to determine, in response to a data request, whether target data requested by the data request exists in a data cache of the processor; an information updating module, configured to update data status information of the target data when the target data exists in the data cache and the target data meets a preset status update condition; Wherein, the data state information is stored in a pre-extended register file of the processor; The register stack has multiple ports. When writing updated data status information, the updated data status information is written to the register stack through a separate write port, without performing arbitration processing caused by sharing a port with other data read requests; the updated data status information includes first indication information, and the first indication information indicates whether the target data is modified during the execution of the data request.

8. A processor, characterized in that: include: an information determining unit, configured to determine, in response to a data request, whether target data requested by the data request exists in a data cache of the processor; an information updating unit, configured to update data status information of the target data when the target data exists in the data cache and the target data meets a preset status update condition; a pre-extended register file, which is used to store the data status information; In which, the register stack has multiple ports. When writing updated data status information, the updated data status information is written to the register stack through a separate write port, without performing arbitration processing caused by sharing a port with other data read requests; the updated data status information includes first indication information, and the first indication information indicates whether the target data is modified during the execution of the data request.

9. An electronic device, characterized in that: The electronic device comprises: one or more processors; Memory; One or more application programs, wherein the one or more application programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs are configured to: execute the data processing method according to any one of claims 1 to 6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data processing method according to any one of claims 1 to 6 is implemented.

Images