Display panel

Abstract

A display panel is disclosed. The display panel includes a display area including at least one module area, wherein a pixel array is disposed in the display area; and a frame area located outside the display area, wherein the at least one module area is formed as a light-transmissive area.

Description

[0001] This application is a divisional application of the original invention patent application No. 201811055808.4 (filed on September 11, 2018, invention title: display panel and display device). Technical Field

[0002] This disclosure relates to a display panel and a display device including the display panel. Background Technology

[0003] With the development of the information society, the demand for display devices used to display images in various forms is increasing. For example, flat panel displays (FPDs), which are thinner, lighter, and larger than bulky cathode ray tubes (CRTs) and can replace CRTs, are rapidly developing. As such FPDs, various types of FPDs, such as liquid crystal displays (LCDs), plasma displays (PDPs), electroluminescent displays (ELs), field emission displays (FEDs), and electrophoretic displays (EDs), are being developed and used.

[0004] Such a display device includes: a display panel including display elements for displaying information; a driver for driving the display panel; and a power supply for generating power to be supplied to the display panel and the driver.

[0005] These display devices can have various designs depending on the usage environment or purpose. Therefore, display panels with free-form components such as partially curved parts or notches are widely used because of their aesthetic appeal, in addition to the traditional single quadrilateral shape.

[0006] In recent years, various components such as cameras, speakers, and sensors for multimedia functions have been introduced in modular form. These components are typically located in the area where the display panel is formed, that is, in the area formed by removing a portion of the edge of the display panel.

[0007] However, in order to fix the notch, the entire cross-section of part of the display panel must be cut off. Therefore, an additional mask must be used to achieve the cutting process, which complicates the manufacturing process. Summary of the Invention

[0008] One aspect of this disclosure is to provide a display panel in which various components such as cameras, speakers, sensors, etc., can be disposed in the display area of ​​the display panel without removing a portion of the display panel.

[0009] According to an aspect of the disclosure, a display panel includes a display area including at least one module area in which a pixel array is disposed, and a bezel area outside the display area, wherein the at least one module area is formed as a light-transmissive area.

[0010] The at least one module area can be located in the display area such that information is displayed in at least two of the upper side, the lower side, the left side, and the right side of the at least one module area.

[0011] The display panel further includes a first voltage supply electrode disposed in the bezel area to supply a first voltage to the pixel array of the display area, a second voltage supply electrode disposed in the bezel area to supply a second voltage less than the first voltage to the pixel array of the display area, and a first voltage supply line connected to the first voltage supply electrode, extending to the display area, and disposed to avoid the at least one module area.

[0012] The display panel further includes a gate line and a data line disposed in the display area to provide a gate signal and a data signal to the pixel array, respectively, wherein the gate line and the data line are disposed to avoid the at least one module area.

[0013] The display panel further includes another first voltage supply electrode disposed on the bezel area to supply the first voltage to the pixel array.

[0014] The first voltage supply electrode and the other first voltage supply electrode are connected by a link line disposed in the bezel area.

[0015] The display panel further includes a shift register of a gate driver disposed in the bezel area, which is located on both sides or one side of the display area to generate a gate signal to be supplied to the pixel array.

[0016] Each pixel in the pixel array can include a light emitting diode (LED), a driving thin film transistor (TFT), at least one switching TFT, and at least one storage capacitor.

[0017] The gate line, the data line, the power line, and the electrode are not formed in the at least one module area.

[0018] According to another aspect of the disclosure, a display apparatus includes a display panel, a data driver, a gate driver, a power supply, and a timing controller. The display panel includes a display area including at least one module area in which a pixel array is disposed, and a bezel area located outside the display area, in which the at least one module area is formed as a light-transmissive area. According to the display panel and display apparatus of the disclosure, a module area allowing light to be transmitted therein can be formed in the bezel area of the display panel through a display panel manufacturing process without using a separate mask, thus a complicated manufacturing process can be avoided, and manufacturing time and cost can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0019] The above and other aspects, features, and advantages of the disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 is a block diagram illustrating a display apparatus according to an embodiment of the disclosure.

[0021] Figure 2 is a plan view specifically illustrating Figure 1 an upper area of the display panel shown in FIG. 1.

[0022] Figure 3 is a cross-sectional view illustrating Figure 2 a single layer structure of the area R2 in FIG. 1. DETAILED DESCRIPTION

[0023] Advantages and features of the disclosure and a method of achieving the same will be clarified by embodiments described below with reference to the accompanying drawings. The disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Furthermore, the disclosure is only defined by the scope of the claims.

[0024] The shapes, sizes, ratios, angles, numbers, and the like disclosed in the accompanying drawings for describing the embodiments of the disclosure are illustrative and are not limited to those shown in the disclosure. Throughout the specification, like drawing reference numerals refer to like elements. Also, in the description of the disclosure, if it is determined that the subject matter of the disclosure can become unnecessarily unclear, a detailed description of known related art will be omitted. In the case where the terms "include", "have", and the like are used in the disclosure, other parts can be added unless "only" is used. The plural includes the singular unless the context clearly indicates otherwise.

[0025] In analyzing structural elements, the elements are interpreted to include a margin of error, although not explicitly described.

[0026] In describing a position relationship, for example, when two parts are described as "on", "above", "below", or "on the side of", one or more other parts can be located between the two parts, unless "directly" or "exactly" is used.

[0027] It is to be understood that the terms "first", "second", and the like, can be used herein to describe various elements, but these elements should not be limited by these terms. The terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element without departing from the scope of the present disclosure.

[0028] As can be fully understood by those skilled in the art, the features of various embodiments of the present disclosure can be partially or wholly coupled or combined with each other, and can be technically inter-operable and driven in various forms with each other. Embodiments of the present disclosure can be executed independently of each other or together in interdependent relationships.

[0029] Hereinafter, a display apparatus according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. Throughout the specification, like reference numerals denote like elements. In the following description, when it is determined that a detailed description of related known functions or configurations will unnecessarily obscure the gist of the present disclosure, the detailed description or a brief description will be omitted.

[0030] Hereinafter, a display apparatus according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. Throughout the specification, like reference numerals denote like elements. In the following description, when it is determined that a detailed description of related known functions or configurations will unnecessarily obscure the gist of the present disclosure, the detailed description or a brief description will be omitted. Figures 1 to 3 Hereinafter, a display apparatus according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. Throughout the specification, like reference numerals denote like elements. In the following description, when it is determined that a detailed description of related known functions or configurations will unnecessarily obscure the gist of the present disclosure, the detailed description or a brief description will be omitted.

[0031] Figure 1 is a block diagram illustrating a display apparatus according to an embodiment of the present disclosure. Figure 2 is a plan view schematically showing Figure 1 the shape of the display panel shown. Figure 3 is a cross-sectional view along Figure 2 line I-I' in

[0032] Referring to Figure 1 and Figure 2 , a display apparatus according to an embodiment of the present disclosure can include a display panel 10, a data driver, a gate driver, a power supply PS, a timing controller TC, etc.

[0033] The display panel 10 includes a display area AA for displaying information and a bezel area BA which does not display information.

[0034] The display area AA is an area in which an input image is displayed and is provided with a pixel array in which a plurality of pixels P are arranged in a matrix form.

[0035] The bezel area BA is an area in which shift registers SRa and SRb of a gate drive circuit, various link signal lines (e.g., DL1 to DLm), link power supply lines VDL1, VDL2, VSL1, and VSL2, power supply electrodes VDL a and VDLb, and the like are provided. The pixel array arranged in the display area AA includes a plurality of data lines D1 to Dm and a plurality of gate lines G1 to Gn arranged to cross each other, and pixels P arranged in a matrix form at the intersection points.

[0036] Each pixel P includes a light emitting diode LED, a drive thin film transistor (hereinafter referred to as a drive TFT DT) for controlling the amount of current flowing in the light emitting diode LED, and a programming portion SC for setting a gate-source voltage of the drive TFT DT. A first voltage Vdd is supplied to the pixels P of the pixel array from the power supply PS via first link power supply lines VDL1 to VDL2 as a high-level voltage, and a second voltage Vss is supplied to the pixels P of the pixel array via second link power supply lines VSL1 to VSL2 as a low-level voltage.

[0037] The first voltage Vdd from the power supply PS at both sides is supplied to the first power lines VD1 to VDm through the lower first power supply electrode VDL a in the bezel area BA on one side to which the chip on film 30 is bonded and the upper first power supply electrode VDLb provided on the opposite bezel area. The both ends of the lower first power supply electrode VDL a and the upper first power supply electrode VDLb can be connected to each other through the first link power supply lines VDL1 and VDL2. Accordingly, it is possible to minimize the deterioration of the display quality due to an increase in resistance capacitance (RC) according to the position of the pixel provided in the display area AA.

[0038] The programming portion SC can include at least one switching TFT and at least one storage capacitor. The switching TFT is turned on in response to a gate signal from the gate line GL, thereby applying a data voltage from the data line DL to one electrode of the storage capacitor. The drive TFT DT controls the amount of current supplied to the light emitting diode LED according to the magnitude of the voltage charged in the storage capacitor, to adjust the light intensity of the light emitting diode LED. The light intensity of the light emitting diode LED is proportional to the amount of current supplied from the drive TFT DT.

[0039] The TFTs constituting the pixel P can be implemented as p-type or n-type. Also, the semiconductor layer of the TFT constituting the pixel can include amorphous silicon or polysilicon, or an oxide. The LED includes an anode, a cathode, and a light emitting structure disposed between the anode and the cathode. The anode is connected with the driving TFT DT. The light emitting structure includes a light emitting layer (EML), a hole injection layer (HIL) and a hole transport layer (HTL) formed on one side of the light emitting layer, and an electron transport layer (ETL) and an electron injection layer (EIL) disposed on the other side of the light emitting layer (EML).

[0040] The data driver includes a chip on film 30 on which a data IC SD is mounted. One side of the chip on film 30 is connected to one end of the source PCB 20, and the other side of the chip on film 30 is bonded to the bezel area BA of the display panel 10.

[0041] The data IC SD converts digital video data input from the timing controller TC into an analog gamma compensation voltage to generate a data voltage. The data voltage output from the data IC SD is supplied to the data lines D1 to Dm.

[0042] The gate driver can be a type in which a chip on film on which a gate IC is mounted is provided on one side of the display panel, or can be a GIP type in which a gate IC is formed on the display panel. In the present disclosure, the GIP type gate driver will be described as an example.

[0043] The GIP type gate driver includes level shifters LSa and LSb mounted on the source PCB 20 and shift registers SRa and SRb formed in the bezel area BA of the display panel 10 and receiving signals supplied from the level shifters LSa and LSb.

[0044] The level shifters LSa and LSb receive signals such as a start pulse ST, a gate shift clock GCLK, a flicker signal FLK, etc. from the timing controller TC, and receive driving voltages such as a gate high voltage VGH, a gate low voltage VGL, etc. The start pulse ST, the gate shift clock GCLK, and the flicker signal FLK are signals that swing between about 0V to 3.3V. The gate shift clock GCLK1-n is an n-phase clock signal having a predetermined phase difference. The gate high voltage VGH is a voltage equal to or greater than the threshold voltage of the TFT formed in the TFT array of the display panel 10, and is about 28V. The gate low voltage VGL is a voltage less than the threshold voltage of the TFT formed in the TFT array of the display panel 10, and is about -5V.

[0045] The level shifter LS performs level shifting of the start pulse ST and the gate shift clock GCLK input from the timing controller TC with the gate high voltage VGH and the gate low voltage VGL to output a shift clock signal CLK. Accordingly, the start pulse VST and the shift clock signal CLK output from the level shifter LS swing between the gate high voltage VGH and the gate low voltage VGL. The level shifter LS can lower the gate high voltage according to the flicker signal FLK to lower the kickback voltage ΔVp of the liquid crystal cell to reduce flicker.

[0046] The output signals of the level shifter LS can be supplied to the shift register SR through lines formed in the film on which the source driving IC SD is disposed in the film on chip 30 and LOG (on glass) lines formed at the substrate of the display panel 10. The shift register SR can be directly formed on the bezel area BA of the display panel 10 through a GIP process.

[0047] The shift register SR sequentially shifts the gate pulses swinging between the gate high voltage VGH and the gate low voltage VGL by shifting the start pulse VST input from the level shifter LS according to the gate shift clock signals CLK1 to CLKn. The gate pulses output from the shift register SR are sequentially supplied to the gate lines G1 to Gn.

[0048] The timing controller TC synchronizes the operation timing of the data IC SD and the gate drivers LSa, LSb, SRa, and SRb upon receiving timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a master clock input from a host system (not shown). The data timing control signals for controlling the data IC SD can include a source sampling clock (SSC), a source output enable (SOE) signal, and the like. The gate timing control signals for controlling the gate drivers LSa, LSb, SRa, and SRb can include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE) signal, and the like.

[0049] In Figure 1 Such a configuration is shown in which the shift registers SRa and SRb are disposed at both sides of the display area AA outside the display area AA to supply the gate pulses to the gate lines G1 to Gn from both sides of the display area AA. However, the present disclosure is not limited thereto, and the shift registers can be disposed at only one side of the display area AA to supply the gate pulses to the gate lines G1 to Gn from one side of the display area AA. When the shift registers SRa and SRb are disposed at both sides outside the display area AA, the gate pulses having the same phase and the same amplitude are supplied to the gate lines arranged in the same horizontal line of the pixel array.

[0050] Referring to Figure 2The display panel 10 of the present disclosure includes a display area AA and a bezel area BA outside the display area AA.

[0051] The display area AA is an area in which a pixel array for displaying information such as characters, graphics, pictures, photos, and images is arranged. The display area AA can include at least one module area MA in a region adjacent to a corner of the display area AA or in a side of the display area AA. The module area MA is an area in which a camera, a speaker, a sensor, or the like is provided. In the module area MA, signal lines including gate lines G1 to Gn and data lines D1 to Dm for supplying signals to the pixel array, power lines VD1 to VDm, or the like are not provided.

[0052] The module area MA can be disposed at any position in the display area AA, and information can be displayed on at least one of the upper side, the left side, the right side, and the lower side of the module area MA according to the arrangement position of the module area MA.

[0053] The bezel area BA is an area surrounding the display area AA from the outside of the display area AA. Shift registers SRa and SRb for generating a gate pulse to be supplied to the pixel array of the display area AA, signal lines for supplying various signals, and power supply lines for supplying various power are provided in the bezel area BA.

[0054] Hereinafter, a cross-sectional structure of a display apparatus according to the present disclosure will be described with reference to Figure 3 Figure 3 Examples in which information is displayed on the upper side and the lower side of the module area MA are illustrated, and the examples are used to help understanding of the present disclosure. Accordingly, the present disclosure should not be construed as being limited to Figure 3 and related descriptions.

[0055] Referring to Figure 3 , a buffer layer BUF having a single layer structure or a multi-layer structure can be disposed on the substrate SUB. The substrate SUB can be formed of a flexible reflective-transmissive material. When the substrate SUB is formed of a material such as polyimide, the buffer layer BUF can be formed of any one of an inorganic material and an organic material to prevent damage to the light emitting device due to impurities such as alkali ions flowing from the substrate SUB during a subsequent process. The inorganic material can include any one of silicon oxide (SiO2) and silicon nitride (SiNx), and the organic material can include photoacrylic acid.

[0056] ​A semiconductor layer A is provided on the buffer layer BUF at each pixel in the display region AA. The semiconductor layer A includes a source region SA and a drain region DA spaced apart from each other, and a channel region CA is provided between the source region SA and the drain region DA. The source region SA and the drain region DA are conductive regions. The semiconductor layer A can be formed using amorphous silicon or polycrystal silicon crystallized from amorphous silicon. Alternatively, the semiconductor layer A can be formed of any one of zinc oxide (ZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO), and zinc tin oxide (ZnSnO). Further, the semiconductor layer A can be formed of a low-molecular or high-molecular organic material such as melocyanine, phthalocyanine, pentacene, or thiophene polymer.

[0057] A gate insulating film GI is provided on the buffer layer BUF on which the semiconductor layer A is provided, so as to cover the semiconductor layer A. The gate insulating film GI can be formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a double layer thereof.

[0058] A gate electrode GE of the TFT and a gate line (not shown) connected to the gate electrode are provided on the gate insulating film GI in the display region AA, so that at least a part of the gate insulating film GI overlaps with the channel layer CA of the semiconductor layer A. The gate electrode GE and the gate line can be formed of any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), copper (Cu), or an alloy thereof, and can be formed in a single layer or multiple layers.

[0059] First and second interlayer insulating films INT1 and INT2 are sequentially provided on the gate insulating film GI on which the gate electrode GE and the gate line are provided, so as to cover the gate electrode GE and the gate line. The first and second interlayer insulating films INT1 and INT2 can be formed of a silicon oxide film (SiOx) or a silicon nitride film (SiNx). One of the first and second interlayer insulating films INT1 and INT2 can be omitted.

[0060] A source electrode SE and a drain electrode DE of the TFT and a data line (not shown) connected to the source electrode SE are provided on the second interlayer insulating film INT2 in the display region AA. The source electrode SE and the drain electrode DE are connected to the source region SA and the drain region DA of the semiconductor layer, respectively, which are exposed through a contact hole that penetrates the gate insulating film GI and the first and second interlayer insulating films INT1 and INT2.

[0061] The first planarization film PNL1 can be located on the passivation film PAS covering the source electrode SE and the drain electrode DE. The first planarization film PNL1 serves to protect the lower structure while mitigating step coverage of the lower structure, and can be formed of a silicon oxide film (SIOx) or a silicon nitride film (SiNx).

[0062] On the first planarization film PNL1, a connection electrode CN (to be described later) for connecting the anode ANO to the drain electrode DE is provided in the display area AA.

[0063] A second planarization film PNL2 is provided on the first planarization film PNL1 to cover the connection electrode CN. The second planarization film PNL2 can be a planarization film for additionally protecting the lower structure while also mitigating step coverage of the lower structure due to the connection electrode CN on the first planarization film PNL1. The second planarization film PNL2 can be formed of a silicone-based organic material.

[0064] The anode ANO is located on the second planarization film PNL2 in the display area AA. The anode ANO is connected to the connection electrode CN exposed through a contact hole penetrating the second planarization film PNL2. The anode ANO can be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

[0065] On the second planarization film PNL2, a bank BN having an opening OL exposing the anode ANO is formed in the display area AA. The opening of the bank BN is a region defining a light emitting region LA.

[0066] A light emitting stack LES and a cathode CAT are sequentially disposed on the anode ANO exposed through the emission region of the bank BN. The light emitting stack LES can be formed on the anode ANO in the order of a hole-related layer, an organic light emitting layer, and an electron-related layer, or in the reverse order. The cathode CAT can be provided on the second planarization film PNL2 to cover the bank BN and the light emitting stack LES in the entire region of the display area AA. Preferably, the cathode CAT is not located in the module area MA. The cathode CAT can be formed of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof having a low work function.

[0067] An encapsulation layer ENC can be located on the second planarization film PNL2 to cover the cathode CAT and the bank BN in the display area AA and the bezel area BA. The encapsulation layer ENC can serve to minimize penetration of moisture or oxygen from the outside into the light emitting stack LES located inside the encapsulation layer ENC, and can have a multi-layer structure in which inorganic layers and organic layers are alternately disposed.

[0068] A polarizer POL can be located on the encapsulation layer ENC to reduce an external light factor, for example, surface reflection of external light reflected from a surface of the display panel or electrode reflection of external light traveling inside the display panel reflected from an electrode inside the display panel.

[0069] On a lower surface of the substrate SUB corresponding to the module area MA of the display area AA, elements such as a camera module, a speaker module, and a sensor module, which are difficult to integrate into the display panel, can be disposed.

[0070] The module area MA is a light transmission area TA through which light can be transmitted. The module area MA is an area in which an opaque material such as a signal line including a gate line and a data line, a power line, an electrode, etc. or a material having no good light transmittance is removed. In Figure 3 In an example, for simplicity of description, TFT1 and a light emitting diode LED disposed in a pixel above the module area MA shown in FIG. 1A and TFT2 and a light emitting diode LED2 disposed in a pixel below the module area MA are shown. Figure 2

[0071] As described above, according to the display apparatus of the embodiment of the disclosure, since the module area MA allowing light transmission can be formed in the display area AA of the display panel through a display panel manufacturing process without using a separate mask, a complicated manufacturing process can be avoided, and manufacturing time and cost can be reduced.

[0072] Further, since the module area MA can be located at any desired position in the display area AA, and all remaining display areas except the module area MA can be used as a display area, a degree of freedom in design can be increased.

[0073] It will be apparent to those skilled in the art that various modifications and changes can be made in the present disclosure without departing from the spirit or scope thereof. In the examples shown in the present disclosure, an electroluminescent display apparatus has been described, but the present disclosure is not limited thereto, and can be applied to various flat panel display apparatuses such as a liquid crystal display apparatus (LCD), a plasma display panel (PDP), a field emission display apparatus (FED), and an electrophoretic display apparatus (ED). Accordingly, the technical scope of the present disclosure should not be limited to what has been described in the detailed description of the present disclosure, but should be defined by the appended claims.​

Claims

1. A display panel comprising: a display area including at least one module area; and a bezel area outside the display area, wherein the display area includes a pixel array, wherein each pixel in the pixel array includes a light emitting diode, a thin film transistor, and a connection electrode connecting the light emitting diode to the thin film transistor, wherein the at least one module area is configured to be a light-transmissive area including at least one insulating layer between adjacent pixels in the pixel array, wherein the light emitting diode includes an anode, a cathode, and a light emitting structure between the anode and the cathode, wherein neither the cathode nor the anode is located in the at least one module area, wherein the at least one insulating layer includes a first planarization film provided between the thin film transistor and the connection electrode, and wherein the first planarization film is provided in the light-transmissive area and adjacent pixels of the pixel array. The anode is connected to the thin film transistor through the connection electrode.

2. The display panel of claim 1, wherein, The cathode is formed of magnesium, calcium, aluminum, silver, or an alloy thereof.

3. The display panel of claim 1, wherein, 4. The display panel according to claim 1, further comprising a polarizer on the cathode, the polarizer is not located in the at least one module area. wherein The connection electrode is directly on the first planarization film, and the first planarization film is continuously provided in the light-transmissive area and adjacent pixels of the pixel array.

5. The display panel of claim 1, wherein, The at least one insulating layer further includes a second planarization film provided between the connection electrode and the light emitting diode, 6. The display panel of claim 1, wherein, wherein the second planarization film is provided in the light-transmissive area and adjacent pixels of the pixel array. The second planarization film is directly on the connection electrode, and is continuously provided in the light-transmissive area and adjacent pixels of the pixel array.

7. The display panel of claim 6, wherein, 8. The display panel according to claim 1, further comprising: a gate line and a data line provided in the display area to supply a gate signal and a data signal to the pixel array, wherein the gate line and the data line are provided to avoid the at least one module area.

9. The display panel according to claim 1, further comprising: a first potential supply electrode provided in the bezel area to supply a first potential to the pixel array of the display area; a second potential supply electrode provided in the bezel area to supply a second potential smaller than the first potential to the pixel array of the display area; and a first potential supply line connected to the first potential supply electrode, extending to the display area, and provided to avoid the at least one module area. The at least one module area includes only the at least one insulating layer between adjacent pixels of the pixel array. ​ 10. The display panel of claim 1, wherein, ​ 11. The display panel of claim 1, wherein, The at least one module region transmits light incident on one surface of the display panel to at least one module provided on the other surface of the display panel so as to overlap the at least one module region.

12. The display panel of claim 1, wherein, One of a camera, a speaker, or a sensor is provided on the other surface of the display panel so as to overlap the at least one module region.

13. A display panel, the display panel comprising: a display region including at least one module region; and a bezel region outside the display region, wherein the display region includes an array of pixels, wherein each pixel in the array of pixels includes a light emitting diode, a thin film transistor, and a connection electrode connecting the light emitting diode to the thin film transistor, wherein the at least one module region is configured as a light-transmissive region between adjacent pixels in the array of pixels including at least one insulating layer, wherein the bezel region includes a first potential supply electrode supplying a first potential to the array of pixels and a second potential supply electrode supplying a second potential less than the first potential to the array of pixels, wherein the first potential supply electrode is between the display region and the second potential supply electrode, wherein the at least one insulating layer includes a first planarization film provided between the thin film transistor and the connection electrode, and wherein the first planarization film is provided in the light-transmissive region and in adjacent pixels of the array of pixels.

14. The display panel of claim 13, wherein, The bezel region further includes a shift register of a gate driver generating a gate signal to be supplied to the array of pixels, wherein at least one of the shift register is between the display region and the second potential supply electrode.

15. The display panel of claim 14, wherein, The bezel region further includes another first potential supply electrode supplying the first potential to the array of pixels, wherein the display region is between the first potential supply electrode and the another first potential supply electrode, wherein both an end of the first potential supply electrode and an end of the another first potential supply electrode are connected by a link line provided in the bezel region.

16. The display panel of claim 15, wherein, One of the link lines is between at least one of the shift register and the second potential supply electrode.

17. The display panel of claim 13, wherein, Each pixel in the array of pixels includes a light emitting diode having an anode, a cathode, and a light emitting structure between the anode and the cathode, wherein the cathode is not in the at least one module region.

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