Impedance calibration circuit and memory

Abstract

The embodiment of the present disclosure provides an impedance calibration circuit, a first control signal is output based on the difference between the initial calibration code and the first impedance calibration code, and the counting frequency of a counting module is adjusted based on the first control signal, so that the time for the counting value generated by the counting module to reach a preset value is controlled, random changes caused by external factors are avoided, the calibration control module can stop outputting the first calibration clock signal within a set time, that is, the impedance calibration circuit can stop calibration in time, the calibration time of the impedance calibration circuit meets the design requirement, power consumption is effectively reduced, and the reliability of the impedance calibration circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, and in particular, to an impedance calibration circuit and a memory. BACKGROUND

[0002] As the operating speed of electronic devices increases, the swing width of a signal transmitted between semiconductor memory devices within the electronic device decreases to minimize the delay time taken to transmit the signal. However, as the signal swing width of the transmitted signal decreases, the signal transmission is more affected by external noise. If there is an impedance mismatch at the interface, the external noise can affect the reflection characteristics of the output signal. The impedance mismatch is caused by external noise or by variations in the supply voltage, operating temperature, and manufacturing process, etc. If the impedance mismatch occurs, it is difficult to transmit data at high speed because the impedance mismatch can distort the data from the semiconductor device. Therefore, problems such as setup / hold failure or misjudgment of the signal level can occur in the semiconductor device that receives the distorted data.

[0003] To alleviate these adverse situations, a memory device can include on-die termination (ODT, also referred to as "on-die termination resistance") that can be used to provide adjustable termination impedance values. For example, when a signal (e.g., a command, data, etc.) is provided to the memory device, the impedance value of the on-die termination can be adjusted to reduce impedance mismatch.

[0004] In high-speed DRAMs, impedance calibration is typically performed periodically to adjust the impedance value of the on-die termination, thereby facilitating impedance matching, maintaining and calibrating signal integrity and data eye in real time. The integrated circuit design specification requires that the impedance calibration circuit ends the calibration within a set time, however, the existing impedance calibration circuit is affected by external factors such as variations in the supply voltage, operating temperature, and manufacturing process, and there is a situation where the calibration period randomly changes, which can cause the impedance calibration circuit to fail to end the calibration within the set time, failing to meet the design requirements. SUMMARY

[0005] The technical problem to be solved by the present disclosure is to provide an impedance calibration circuit and a memory that can make the calibration time of the impedance calibration circuit meet the design requirements, effectively reduce power consumption, and improve the reliability of the impedance calibration circuit.

[0006] To solve the above problems, the impedance calibration circuit comprises a comparison module, which receives an initial calibration code and a first impedance calibration code, and outputs a first control signal based on the difference between the initial calibration code and the first impedance calibration code; a counting module, which receives the first control signal, adjusts the counting frequency based on the first control signal, and outputs a counting value; a calibration module, which receives a first calibration clock signal, generates the first impedance calibration code based on the first calibration clock signal, performs impedance calibration according to the first impedance calibration code, and outputs a first stop signal when the calibration is completed; and a calibration control module, which receives the counting value and the first stop signal, and outputs the first calibration clock signal; when the counting value is greater than or equal to a preset value or the calibration control module receives the first stop signal, the output of the first calibration clock signal is stopped.

[0007] In an embodiment, the comparison module comprises a difference unit, which receives the initial calibration code and the first impedance calibration code, and obtains the difference between the initial calibration code and the first impedance calibration code; and a plurality of adjustment units, which are connected to the difference unit respectively, receive the difference, and output the first control signal according to the difference selected by the corresponding adjustment unit, wherein each adjustment unit corresponds to a numerical range.

[0008] In an embodiment, the numerical ranges of each adjustment unit do not overlap.

[0009] In an embodiment, the impedance calibration circuit further comprises a latch module connected to the comparison module, which latches the initial calibration code.

[0010] In an embodiment, the counting module comprises a clock signal generation unit connected to the comparison module, which generates an initial clock signal, receives the first control signal, and changes the period of the initial clock signal according to the first control signal; and a counting unit, which counts the period of the initial clock signal, and outputs the counting value.

[0011] In an embodiment, the clock signal generation unit comprises a plurality of switch modes, and the clock signal generation unit selects the corresponding switch mode according to the first control signal to change the period of the initial clock signal.

[0012] In an embodiment, the clock signal generation unit is a ring oscillator composed of a plurality of first and last connected inverters, and the clock signal generation unit further comprises at least one selection switch connected in parallel with at least one inverter to control whether the corresponding inverter is connected to the circuit.

[0013] In an embodiment, when the count value is greater than or equal to a preset value, the calibration control module generates a second stop signal, and stops outputting the first calibration clock signal according to the second stop signal.

[0014] In an embodiment, the calibration control module comprises a first logic gate circuit, which is configured to receive the first stop signal and the second stop signal, and perform a logic operation to output a first output signal, and the calibration control module stops outputting the first calibration clock signal according to the first output signal.

[0015] In an embodiment, the calibration module comprises a first calibration unit, which is calibrated by the first impedance calibration code; the first calibration unit comprises: a first resistance unit, a first end of which is connected to a first power supply end; a reference resistance, a first end of which is connected to a second end of the first resistance unit, and a second end of which is connected to a second power supply end; a first comparison unit, which is configured to compare a voltage at the second end of the first resistance unit with a first reference voltage, and output a first comparison signal; and a first detection unit, which takes the first comparison signal as an input signal, and records a change of the first comparison signal; when the change of the first comparison signal meets a preset condition, the first detection unit outputs the first stop signal.

[0016] In an embodiment, the first calibration unit further comprises a first calibration code generation unit, which updates the first impedance calibration code according to the first comparison signal, and the first impedance calibration code is used to control an equivalent resistance value of the first resistance unit.

[0017] In an embodiment, the calibration control module is further configured to output a second calibration clock signal, and the calibration module is further configured to receive the second calibration clock signal, and when the calibration control module receives the first stop signal or the second stop signal, the calibration control module stops outputting the first calibration clock signal and starts outputting the second calibration clock signal.

[0018] In an embodiment, the calibration module generates a second impedance calibration code based on the second calibration clock signal, the calibration module further comprises a second calibration unit, and the calibration module performs impedance calibration on the second calibration unit according to the second impedance calibration code, the second calibration unit comprises: a second resistance unit, a second end of which is connected to a second power supply end; a third resistance unit, a first end of which is connected to the first power supply end, and a second end of which is connected to a first end of the second resistance unit, the first calibration code further being used to control an equivalent resistance value of the third resistance unit; a second comparison unit, configured to compare a voltage at the first end of the second resistance unit with a second reference voltage, and output a second comparison signal; and a second detection unit, configured to take the second comparison signal as an input signal, and record a change of the second comparison signal, and output a third stop signal when the change of the second comparison signal meets a preset condition; and the calibration control module stops outputting the second calibration clock signal when the calibration control module receives the third stop signal or the second stop signal.

[0019] In an embodiment, the comparison module is further configured to receive an initial calibration code and a second impedance calibration code, and output a second control signal based on a difference between the initial calibration code and the second impedance calibration code, and the counting module receives the second control signal, and adjusts a counting frequency and outputs the counting value based on the second control signal, and stops outputting the second calibration clock signal when the counting value is greater than or equal to a preset value or the calibration control module receives the third stop signal.

[0020] In an embodiment, the calibration control module further comprises a reset module, and the reset module resets the first control signal when the calibration control module receives the first stop signal or the second stop signal.

[0021] The embodiments of the present disclosure further provide a memory comprising the impedance calibration circuit as described above.

[0022] The impedance calibration circuit and memory provided in this disclosure stop the output of the first calibration clock signal and halt the impedance calibration process when the count value output by the counting module is greater than or equal to a preset value. The counting module generates the count value; if the counting module is affected by changes in external factors (e.g., changes in power supply voltage, operating temperature, and manufacturing process), the counting frequency decreases, which prolongs the time it takes for the count value to reach the preset value. This may prevent the calibration control module from stopping the output of the first calibration clock signal within the set time, thus lengthening the calibration cycle of the impedance calibration circuit and failing to meet design requirements. Therefore, the impedance calibration circuit provided in this disclosure outputs a first control signal based on the difference between the initial calibration code and the first impedance calibration code, and adjusts the counting frequency of the counting module based on the first control signal to change the time it takes for the count value generated by the counting module to reach the preset value. This makes the time for the count value generated by the counting module to reach the preset value controllable, avoiding random changes due to external factors. This allows the calibration control module to stop outputting the first calibration clock signal within the set time, enabling the impedance calibration circuit to stop calibration promptly. The calibration time of the impedance calibration circuit meets design requirements, effectively reducing power consumption and improving the reliability of the impedance calibration circuit. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of an impedance calibration circuit provided in an embodiment of the present disclosure;

[0024] Figure 2 This is a schematic diagram of an impedance calibration circuit provided in another embodiment of this disclosure;

[0025] Figure 3 This is a schematic diagram of a clock signal generation unit provided in an embodiment of this disclosure;

[0026] Figure 4 This is a schematic diagram of an impedance calibration circuit provided in another embodiment of the present disclosure;

[0027] Figure 5 This is a schematic diagram of an impedance calibration circuit provided in another embodiment of the present disclosure. Detailed Implementation

[0028] The specific implementation of the impedance calibration circuit and memory provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0029] Figure 1 This is a schematic diagram of an impedance calibration circuit provided in one embodiment of this disclosure. Please refer to... Figure 1 The impedance calibration circuit includes a comparison module 40, a counting module 20, a calibration module 10, and a calibration control module 30. The comparison module 40 receives the initial calibration code INcode. <n:0>and a first impedance calibration code Pcode <n:0>and based on the initial calibration code INcode <n:0>and a first impedance calibration code Pcode <n:0>The difference between the two outputs outputs a first control signal Ctr1. The counting module 20 receives the first control signal Ctr1 and adjusts the counting frequency and outputs a counting value C1 based on the first control signal Ctr1. The calibration module 10 is configured to receive a first calibration clock signal Pclk and generate a first impedance calibration code Pcode based on the first calibration clock signal Pclk <n:0>, the calibration module 10 calibrates the first impedance calibration code Pcode <n:0>The impedance calibration is performed, and when the calibration is completed, a first stop signal Stop1 is output. The calibration control module 30 is configured to receive the count value C1, the first stop signal Stop1, and output a first calibration clock signal Pclk; when the count value C1 is greater than or equal to a preset value or the calibration control module 30 receives the first stop signal Stop1, the output of the first calibration clock signal Pclk is stopped.

[0030] In the impedance calibration circuit provided by the embodiments of the present disclosure, after the calibration is completed, the calibration module 10 outputs the first stop signal Stop1, and due to the design limitation of the calibration module 10, there is a case that the calibration module 10 cannot output the valid first stop signal Stop1 in time, which causes the impedance calibration circuit to fail to stop outputting the first calibration clock signal Pclk in time, i.e., the calibration cannot be stopped in time, the calibration time of the impedance calibration circuit exceeds the design requirement, cannot meet the demand, and has large power consumption. Therefore, the impedance calibration circuit provided by the embodiments of the present disclosure further provides another setting for stopping the calibration, i.e., when the count value C1 output by the count module 20 is greater than or equal to a preset value, the calibration control module 30 stops outputting the first calibration clock signal Pclk, and the impedance calibration process is stopped. The count module 20 is configured to generate the count value C1, and if the count module 20 is affected by external factors (for example, changes in supply voltage, operating temperature, and manufacturing process), the count frequency is reduced, which will make the time for the count value C1 to reach the preset value longer, and may cause the calibration control module 30 to fail to stop outputting the first calibration clock signal Pclk within the set time, i.e., the calibration period of the impedance calibration circuit is lengthened, which cannot meet the design requirement. Therefore, the impedance calibration circuit provided by the embodiments of the present disclosure is based on the initial calibration code INcode <n:0>and a first impedance calibration code Pcode <n:0>The difference between the two outputs the first control signal Ctr1, and adjusts the counting frequency of the counting module 20 based on the first control signal Ctr1, to change the time for the counting value C1 generated by the counting module 20 to reach the preset value, so that the time for the counting value C1 generated by the counting module 20 to reach the preset value is controllable, avoiding random changes due to external factors, enabling the calibration control module 30 to stop outputting the first calibration clock signal Pclk within a set time, i.e., enabling the impedance calibration circuit to stop calibration in time, so that the calibration time of the impedance calibration circuit meets the design requirements, effectively reduces power consumption, and improves the reliability of the impedance calibration circuit.

[0031] In the impedance calibration circuit provided in the embodiments of the present disclosure, the initial calibration code INcode <n:0>The preset value can be the first impedance calibration code Pcode generated when the impedance calibration circuit performs calibration for the first time <n:0>, or the impedance calibration circuit generates a first impedance calibration code Pcode after a plurality of clock cycles <n:0>For example, in one embodiment, the design specification requires that the calibration period of the impedance calibration circuit be 40 clock cycles, and the initial calibration code INcode <n:0>Pcode is the first impedance calibration code generated after 20 clock cycles for impedance calibration circuit <n:0>.

[0032] In some embodiments, the initial calibration code INcode <n:0>and a first impedance calibration code Pcode <n:0>the difference between the output of the first control signal Ctr1, if the initial calibration code INcode <n:0>and a first impedance calibration code Pcode <n:0>If the difference is too large, the counting module 20 increases the counting frequency based on the first control signal Ctr1, i.e. reduces the time length of the clock cycle, the time for the counting value C1 output by the counting module 20 to reach the preset value becomes shorter, the time for the calibration control module 30 to stop outputting the first calibration clock signal Pclk is advanced, the time for the impedance calibration circuit to calibrate to the same target is reduced, i.e. the impedance calibration circuit calibrates to the same target, the total calibration time from starting to stopping calibration of the impedance calibration circuit is reduced, the calibration time of the impedance calibration circuit meets the design requirement, the power consumption is effectively reduced, and the reliability of the impedance calibration circuit is improved. If the initial calibration code INcode <n:0>and a first impedance calibration code Pcode <n:0>If the difference is within the allowed range, the counting module 20 keeps the current counting frequency based on the first control signal Ctr1.

[0033] Please refer to Figure 2 Fig. 6 is a schematic diagram of an impedance calibration circuit provided by another embodiment of the present disclosure. In some embodiments, the comparison module 40 includes a difference unit 41 and a plurality of adjustment units.

[0034] The difference unit 41 is configured to receive the initial calibration code INcode <n:0>and a first impedance calibration code Pcode <n:0>and obtain an initial calibration code INcode <n:0>and a first impedance calibration code Pcode <n:0>the difference Dl. The difference unit 41 can be a comparator or a subtractor. For example, in the present embodiment, the difference unit 41 is a subtractor, and the initial calibration code INcode <n:0>and a first impedance calibration code Pcode <n:0>As an input signal of the subtractor, the subtractor subtracts the initial calibration code INcode <n:0>and a first impedance calibration code Pcode <n:0>The subtraction operation is performed, and the difference D1 between the two is output as an output signal.

[0035] The plurality of adjustment units are respectively connected to the difference unit 41, and are configured to receive the difference D1 and output a first control signal Ctr1 according to the difference D1. Each adjustment unit corresponds to a range of values. It can be understood that the first control signal Ctr1 output by different adjustment units has different values, which are used as the basis for adjusting the counting frequency of the counting module 20.

[0036] As an example, in the embodiment, the comparison module 40 includes three adjustment units, i.e., a first adjustment unit 42, a second adjustment unit 43, and a third adjustment unit 44, which respectively correspond to a range of values. The first adjustment unit 42, the second adjustment unit 43, and the third adjustment unit 44 receive the difference D1. If the difference D1 is within the range of values corresponding to the first adjustment unit 42, the first adjustment unit 42 outputs the first control signal Ctr1, and the second adjustment unit 43 and the third adjustment unit 44 do not output signals. Similarly, if the difference D1 is within the range of values corresponding to the second adjustment unit 43 or the third adjustment unit 44, the second adjustment unit 43 or the third adjustment unit 44 outputs the first control signal Ctr1, and the other adjustment units do not output signals.

[0037] In some embodiments, the ranges of values of each adjustment unit do not overlap, so as to avoid the difference D1 falling within the ranges of values of multiple adjustment units and causing the output first control signal Ctr1 to be unreliable. The ranges of values do not overlap includes that the ranges of values and the endpoints of the ranges of values do not overlap.

[0038] As an example, in an embodiment, the range of values corresponding to the first adjustment unit 42 is [-10, 10], the range of values corresponding to the second adjustment unit 43 is [-20, -10) and (10, 20], and the range of values corresponding to the second adjustment unit 43 is greater than 20 or less than -20. If the difference D1 is 15, the difference D1 is within the range of values corresponding to the second adjustment unit 43, and the second adjustment unit 43 outputs the first control signal Ctr1, and the first adjustment unit 42 and the third adjustment unit 44 do not output signals.

[0039] In the embodiment, the first adjustment unit 42, the second adjustment unit 43, and the third adjustment unit 44 can be circuit structures such as comparators, so as to realize the comparison between the difference D1 and the range of values.

[0040] Please continue to refer to Figure 2 In some embodiments, the impedance calibration circuit further includes a latch module 50 connected to the comparison module 40, and configured to latch the initial calibration code INcode <n:0>. When the difference Dl is required to be obtained, the comparison module 40 can obtain the initial calibration code INcode from the latch module 50 <n:0>and then the difference D1 is obtained.

[0041] The counting module 20 receives the first control signal Ctr1 and adjusts the counting frequency based on the first control signal Ctr1 and outputs the counting value C1. This embodiment also provides an example of the counting module 20.

[0042] Please continue to refer to Figure 2 The counting module 20 includes a clock signal generation unit 21 and a counting unit 22. The clock signal generation unit 21 is connected to the comparison module 40 and is configured to generate an initial clock signal CLK-0. The clock signal generation unit 21 is configured to receive the first control signal Ctr1 and change the period of the initial clock signal CLK-0 according to the first control signal Ctr1. The counting unit 22 counts the period of the initial clock signal CLK-0 and outputs the counting value C1. The counting value C1 is the number of periods of the initial clock signal CLK-0.

[0043] Since the values of the first control signals Ctr1 output by different adjustment units are different, the period of the initial clock signal CLK-0 can be changed according to the first control signal Ctr1, for example, the time length of the period of the initial clock signal CLK-0 is increased or decreased, so that the time for the counting module 20 to output the counting value C1 to reach the preset value is lengthened or shortened.

[0044] In an embodiment, the clock signal generation unit 21 includes a plurality of switch modes. The clock signal generation unit 21 selects a corresponding switch mode according to the first control signal Ctr1 to change the period of the initial clock signal CLK-0. Each switch mode corresponds to a period of the initial clock signal CLK-0, and different switch modes correspond to different periods of the initial clock signal CLK-0. For example, the first control signal generated by the first adjustment unit 42 corresponds to the first switch mode, the first control signal generated by the second adjustment unit 43 corresponds to the second switch mode, and the first control signal generated by the third adjustment unit 44 corresponds to the third switch mode. The clock signal generation unit 21 selects the first switch mode, the second switch mode, or the third switch mode according to the first control signal Ctr1, so that the clock signal generation unit 21 can output the initial clock signal CLK-0 with different periods.

[0045] In some embodiments, the clock signal generation unit 21 is a ring oscillator composed of a plurality of first and last connected inverters. The clock signal generation unit 21 further includes at least one selection switch in parallel with at least one inverter to control whether the corresponding inverter is connected to the circuit. Each selection switch corresponds to a switch mode.

[0046] As an example, please refer to Figure 3 The clock signal generation unit 21 includes seven inverters P1, P2, P3, P4, P5, P6 and P7 connected in a ring, and the inverters P1, P2, P3, P4, P5, P6 and P7 form a ring oscillator. The clock signal generation unit 21 includes two selection switches S1 and S2. The selection switch S1 is connected in parallel with the inverters P2 and P3 to control whether the inverters P2 and P3 are connected in the circuit, and the selection switch S2 is connected in parallel with the inverters P4 and P5 to control whether the inverters P4 and P5 are connected in the circuit. The selection switches S1 and S2 are turned on and off in response to a first control signal Ctr1 to control the number of inverters connected in the circuit. As an example, in some embodiments, a first switch mode is that the selection switch S1 and the selection switch S2 are both turned off, a second switch mode is that the selection switch S1 is turned on and the selection switch S2 is turned off, and a third switch mode is that the selection switch S1 and the selection switch S2 are both turned on.

[0047] Since each inverter has a delay, the total delay time of the ring oscillator is different when the number of inverters connected in the circuit is different, so that an initial clock signal CLK-0 with a corresponding clock period can be generated according to the number of inverters. That is, the clock signal generation unit 21 changes the period of the initial clock signal CLK-0 by changing the number of inverters connected in the circuit. It can be understood that the number of inverters and selection switches is only an example, and is not the actual number of inverters and selection switches included in the clock signal generation unit 21.

[0048] In some embodiments, when the count value C1 output by the counting module 20 is greater than or equal to a preset value, the calibration control module 30 generates a second stop signal Stop2 and stops outputting the first calibration clock signal Pclk according to the second stop signal Stop2, and the impedance calibration circuit stops the impedance calibration process. In some embodiments, the calibration control module 30 further includes a judging module 31, which receives the count value C1 and judges whether the count value C1 is greater than or equal to the preset value, and outputs the second stop signal Stop2 when the count value C1 is greater than or equal to the preset value.

[0049] The calibration control module 30 stops outputting the first calibration clock signal Pclk according to the second stop signal Stop2 in addition to the first stop signal Stop1. The second stop signal Stop2 is generated when the count value C1 output by the counting module 20 is greater than or equal to a preset value. If the first stop signal Stop1 is still an invalid signal when the count value C1 output by the counting module 20 is greater than or equal to the preset value, the impedance calibration circuit stops outputting the first calibration clock signal Pclk according to the second stop signal Stop2. If the first stop signal Stop1 is a valid signal when the count value C1 output by the counting module 20 is greater than or equal to the preset value or before the count value C1 reaches the preset value, the impedance calibration circuit stops outputting the first calibration clock signal Pclk according to the first stop signal Stop1. Thus, the impedance calibration circuit can be stopped in time, the calibration time of the impedance calibration circuit can meet the design requirement, the power consumption can be effectively reduced, and the reliability of the impedance calibration circuit can be improved.

[0050] The preset value can be determined according to the design requirement. For example, in an embodiment, the calibration time of the impedance calibration circuit is required to be no more than 40 clock periods of the initial clock signal CLK-0, and the preset value is less than or equal to 40 clock periods of the initial clock signal CLK-0. For example, in the embodiment, the preset value is 40 clock periods of the initial clock signal CLK-0, the counting unit 22 counts the clock periods of the initial clock signal CLK-0, and outputs the second stop signal Stop2 when the count value C1 is 40. The calibration control module 30 stops outputting the first calibration clock signal Pclk according to the second stop signal Stop2.

[0051] It can be understood that in other embodiments, in order to ensure that the impedance calibration circuit can stop outputting the first calibration clock signal Pclk in time, the preset value can also be other values less than the design requirement, for example, the preset value is less than 40, so as to ensure that the impedance calibration circuit can stop outputting the first calibration clock signal Pclk in time.

[0052] In some embodiments, the calibration control module 30 can achieve the purpose of stopping output of the first calibration clock signal Pclk when receiving the first stop signal Stop1 or the second stop signal Stop2 by logical operation. Specifically, the calibration control module 30 comprises a first logic gate circuit 32 configured to receive the first stop signal Stop1 and the second stop signal Stop2 and perform logical operation processing to output a first output signal Out1, and the calibration control module 30 stops output of the first calibration clock signal Pclk according to the first output signal Out1. For example, in the present embodiment, the first logic gate circuit 32 comprises an OR gate, the first stop signal Stop1 and the second stop signal Stop2 are input signals of the OR gate, the OR gate outputs the first output signal Out1, and the calibration control module 30 stops output of the first calibration clock signal Pclk according to the first output signal Out1.

[0053] Please continue to refer to Figure 2 In some embodiments, the calibration control module 30 is further configured to receive an initial clock signal CLK-0 of the clock signal generation unit 21 and generate the first calibration clock signal Pclk according to the initial clock signal CLK-0. Since the clock signal generation unit 21 can change the period of the initial clock signal CLK-0 according to the first control signal Ctr1, the period of the first calibration clock signal Pclk is also changed accordingly, so that the calibration time of the calibration module 10 can be changed, for example, the calibration time of the calibration module 10 can be accelerated, and the calibration time exceeding the set time can be avoided. When the calibration control module 30 receives the first stop signal Stop1 and the second stop signal Stop2, the calibration control module 30 is further configured to output a fourth stop signal Stop4 to the clock signal generation unit 21 to stop the clock signal generation unit 21 from outputting the initial clock signal CLK-0.

[0054] Please refer to Figure 4 which is a schematic diagram of an impedance calibration circuit provided by another embodiment of the present disclosure. In this embodiment, the calibration module 10 comprises a first calibration unit 11, and the calibration module 10 generates the first calibration clock signal Pclk according to the first impedance calibration code Pcode <n:0>Impedance calibration is performed on the first calibration unit 11.

[0055] The first calibration unit 11 includes a first resistance unit 111, a reference resistance R1, a first comparison unit 112, and a first detection unit 113.

[0056] The first end of the first resistance unit 111 is connected to a first power supply end VDD; the first end of the reference resistance R1 is connected to the second end of the first resistance unit 111, and the second end of the reference resistance R1 is connected to a second power supply end VSS; the first comparison unit 112 is configured to compare the voltage Vp1 at the second end of the first resistance unit 111 with a first reference voltage Vref1 and output a first comparison signal Comp1; the first detection unit 113 takes the first comparison signal Comp1 as an input signal and records the change of the first comparison signal Comp1, and outputs a first stop signal Stop1 when the change of the first comparison signal Comp1 meets a preset condition. The change of the first comparison signal Comp1 refers to the change of the logic level of the first comparison signal Comp1. The preset condition can include whether the logic level of the first comparison signal Comp1 changes from a first value to a second value and then continues to change from the second value to the first value. In some embodiments, the first value can represent a logic high level, and its truth value can be "1"; the second value can represent a logic low level, and its truth value can be "0"; in other embodiments, the first value can represent a logic low level, and its truth value can be "0"; the second value can represent a logic high level, and its truth value can be "1". If the logic level of the first comparison signal Comp1 changes from the first value to the second value and then continues to change from the second value to the first value, i.e., the logic level of the first comparison signal Comp1 is dithered between the high level and the low level, then the change of the first comparison signal Comp1 meets the preset condition, and at this time, the first detection unit 113 outputs the first stop signal Stop1.

[0057] In this embodiment, the first resistance unit 111 can include a plurality of parallel MOS transistors, which include but are not limited to PMOS transistors. The first calibration code Pcode <n:0>The on or off of the MOS transistor is adjusted, and thus the equivalent resistance value of the first resistance unit 111 is controlled. The second end voltage Vp1 of the first resistance unit 111 changes with the change of the equivalent resistance value of the first resistance unit 111. The reference resistance R1 is a fixed resistance with an accurate resistance value, for example, 240 ohms. The equivalent resistance value of the first resistance unit 111 can be calibrated according to the reference resistance R1. In this embodiment, the first reference voltage Vref1 can be set as VDD / 2, and in other embodiments, the first reference voltage Vref1 can be set as other values.

[0058] In this embodiment, the first comparison unit 112 can be a comparator. The positive input end of the comparator receives the first reference voltage Vref1, and the negative input end of the comparator is connected to the first resistance unit 111 and receives the second end voltage Vp1 of the first resistance unit 111. The comparator outputs the first comparison signal Comp1 in response to the second end voltage Vp1 of the first resistance unit 111 and the first reference voltage Vref1. If the second end voltage Vp1 of the first resistance unit 111 is less than the first reference voltage Vref1, the logic level of the first comparison signal Comp1 output by the output end of the comparator is high. If the second end voltage Vp1 of the first resistance unit 111 is greater than the first reference voltage Vref1, the logic level of the first comparison signal Comp1 output by the output end of the comparator is low.

[0059] The first detection unit 113 takes the first comparison signal Comp1 as an input signal and outputs the first stop signal Stop1. That is, the first stop signal Stop1 is generated based on the first comparison signal Comp1. When the sensitivity of the first comparison unit 112 is low, the first comparison unit 112 cannot output the first comparison signal Comp1 or outputs an incorrect first comparison signal. When the second end voltage Vp1 of the first resistance unit 111 is close to the first reference voltage Vref1, the first comparison unit 112 cannot distinguish the size of the two, and cannot output an effective first comparison signal Comp1. This makes the impedance calibration circuit fail to generate the first stop signal Stop1 in time, and thus the impedance calibration circuit fails to stop calibration in time. As described above, in addition to stopping the impedance calibration process according to the first stop signal Stop1, the calibration control module 30 also stops the impedance calibration process according to the second stop signal Stop2. Thus, the impedance calibration circuit can stop calibration in time, the calibration time of the impedance calibration circuit meets the design requirements, the power consumption is effectively reduced, and the reliability of the impedance calibration circuit is improved.

[0060] As an example, the present embodiment provides a structure of the first detection unit 113. The first detection unit 113 includes an odd number of flip-flop cascades and a second logic gate circuit, the first output end of the flip-flop at an odd stage is connected with the input end of the second logic gate circuit, the second input end of the flip-flop at an even stage is connected with the input end of the second logic gate circuit, and the first stop signal Stop1 is output after the logic processing of the second logic gate circuit.

[0061] The present embodiment also provides another structure of the first detection unit 113. The first detection unit 113 includes an odd number of flip-flop cascades and a second logic gate circuit, the second output end of the flip-flop at an odd stage is connected with the input end of the second logic gate circuit, the first input end of the flip-flop at an even stage is connected with the input end of the second logic gate circuit, and the first stop signal Stop1 is output after the logic processing of the second logic gate circuit.

[0062] In an embodiment, the first calibration unit further includes a first calibration code generating unit, the first calibration code generating unit updates the first impedance calibration code Pcode <n:0>, a first impedance calibration code Pcode <n:0>for controlling the equivalent resistance value of the first resistance unit. In particular, please refer to Figure 4 The first calibration unit 11 further includes a first calibration code generating unit 114 which updates the first impedance calibration code Pcode <n:0>, a first impedance calibration code Pcode <n:0>The first calibration code generating unit 114 is configured to generate a first calibration code Pcode for controlling the equivalent resistance value of the first resistance unit 111. In some embodiments, the first calibration code generating unit 114 can be a counter. The comparison module 40 receives the first impedance calibration code Pcode <n:0>and based on the initial calibration code INcode <n:0>and a first impedance calibration code Pcode <n:0>The difference D1 between the two values outputs a first control signal Ctr1.

[0063] The above only lists the case where the calibration module 10 includes one calibration unit (the first calibration unit 11). In the case where the calibration module 10 includes multiple calibration units, the multiple calibration units can perform calibration individually. For example, when one calibration unit finishes calibration, another calibration unit can start performing calibration. Each calibration unit corresponds to a stop signal, so that the calibration control module 30 stops outputting the calibration clock signal corresponding to the calibration unit according to the stop signal after the calibration unit finishes calibration.

[0064] Specifically, refer to Figure 5 The impedance calibration circuit provided by still another embodiment of the disclosure is shown in the figure. In this embodiment, the calibration control module 30 is further configured to output a second calibration clock signal Nclk. When the calibration control module 30 receives the first stop signal Stop1 or the second stop signal Stop2, it stops outputting the first calibration clock signal Pclk and starts outputting the second calibration clock signal Nclk. The calibration module 10 performs impedance calibration on the second calibration unit 12 when it receives the second calibration clock signal Nclk. The calibration module 10 includes the first calibration unit 11 and the second calibration unit 12. When the first calibration unit 11 finishes calibration, the calibration control module 30 stops outputting the first calibration clock signal Pclk corresponding to the first calibration unit 11 according to the first stop signal Stop1 or the second stop signal Stop2. Due to the influence of the response time of the impedance calibration circuit and the external environment, the calibration control module 30 starts outputting the second calibration clock signal Nclk corresponding to the second calibration unit 12 after a certain period of time, and the second calibration unit 12 can start performing impedance calibration. In some embodiments, when the first calibration unit 11 finishes calibration, the calibration control module 30 can start outputting the second calibration clock signal Nclk corresponding to the second calibration unit 12 without waiting for a certain period of time. In some embodiments, the calibration control module 30 is further configured to generate the second calibration clock signal Nclk based on the initial clock signal CLK-0. Since the clock signal generation unit 21 can change the period of the initial clock signal CLK-0 according to the first control signal Ctr1, the period of the second calibration clock signal Nclk is also changed accordingly, so that the calibration time of the calibration module 10 can be changed, and the calibration time exceeding the set time can be avoided.

[0065] When the second calibration unit 12 performs impedance calibration, the counting unit 22 re-counts the period of the initial clock signal CLK-0 and outputs the second stop signal Stop2 when the counting value C1 is greater than or equal to a preset value.

[0066] The second calibration unit 12 can output a third stop signal Stop3, and the calibration control module 30 stops outputting the second calibration clock signal Nclk corresponding to the second calibration unit 12 according to the third stop signal Stop3 or the second stop signal Stop2.

[0067] Please continue to refer to Figure 5 The calibration control module 30 comprises a third logic gate circuit 33, which is configured to receive the second stop signal Stop2 and the third stop signal Stop3, and perform logic operation processing to output a second output signal Out2. The calibration control module 30 stops outputting the second calibration clock signal Nclk according to the second output signal Out2. The structure and principle of the third logic gate circuit 33 are the same as those of the first logic gate circuit 32, and will not be described again.

[0068] Please continue to refer to Figure 5 In this embodiment, the second calibration unit 12 comprises a second resistance unit 121, a third resistance unit 125, a second comparison unit 122, and a second detection unit 123.

[0069] The second end of the second resistance unit 121 is connected to the first power supply end VDD; the first end of the third resistance unit 125 is connected to the first power supply end VDD, the second end of the third resistance unit 125 is connected to the first end of the second resistance unit 121, and the first impedance calibration code Pcode <n:0>The second comparison unit 122 is also used to control the equivalent resistance value of the third resistance unit 125; the second comparison unit 122 is used to compare the first end voltage Vp2 of the second resistance unit 121 with a second reference voltage Vref2, and output a second comparison signal Comp2; the second detection unit 123 takes the second comparison signal Comp2 as an input signal, and records the change of the second comparison signal Comp2; when the change of the second comparison signal Comp2 meets a preset condition, a third stop signal Stop3 is output. The change of the second comparison signal Comp2 and the preset condition are defined in the same way as the change of the first comparison signal Comp1 and the preset condition, which will not be described here.

[0070] In the embodiment, the second resistance unit 121 can include a plurality of parallel MOS transistors, which include but are not limited to NMOS transistors. The second resistance unit 121 can be calibrated by a second impedance calibration code Ncode <n:0>The on or off of the MOS transistor is adjusted, thereby controlling the equivalent resistance value of the second resistance unit 121. The first end voltage Vp2 of the second resistance unit 121 is changed with the change of the equivalent resistance value of the second resistance unit 121. The third resistance unit 125 can have the same structure as the first resistance unit 111, and can adopt the first impedance calibration code Pcode <n:0>The equivalent resistance of the third resistance unit 125 is controlled, and then the second resistance unit 121 is calibrated by the third resistance unit 125.

[0071] In the embodiment, the second comparison unit 122 is a comparator, which has the same structure as the first comparison unit 112. The positive input terminal of the comparator receives the second reference voltage Vref2, and the negative input terminal of the comparator is connected to the second resistance unit 121 to receive the first terminal voltage Vp2 of the second resistance unit 121. The comparator outputs the second comparison signal Comp2 in response to the first terminal voltage Vp2 of the second resistance unit 121 and the second reference voltage Vref2. If the first terminal voltage Vp2 of the second resistance unit 121 is less than the second reference voltage Vref2, the logic level of the second comparison signal Comp2 output by the output terminal of the comparator is high. If the first terminal voltage Vp2 of the second resistance unit 121 is greater than the second reference voltage Vref2, the logic level of the second comparison signal Comp2 output by the output terminal of the comparator is low.

[0072] The second detection unit 123 takes the second comparison signal Comp2 as the input signal and outputs the third stop signal Stop3. That is, the third stop signal Stop3 is generated based on the second comparison signal Comp2. When the sensitivity of the second comparison unit 122 is low, the second comparison unit 122 cannot output the second comparison signal Comp2 or outputs an incorrect second comparison signal. When the first terminal voltage Vp2 of the second resistance unit 121 is close to the second reference voltage Vref2, the second comparison unit 122 cannot distinguish the size of the two, and cannot output the valid second comparison signal Comp2. This makes the impedance calibration circuit fail to generate the third stop signal Stop3 in time, and the impedance calibration circuit fails to stop calibration in time. As described above, in addition to stopping the impedance calibration process according to the third stop signal Stop3, the calibration control module 30 also stops the impedance calibration process according to the second stop signal Stop2, so that the impedance calibration circuit can stop calibration in time, the calibration time of the impedance calibration circuit meets the design requirement, the power consumption is effectively reduced, and the reliability of the impedance calibration circuit is improved.

[0073] In an embodiment, the second detection unit 123 has the same structure as the first detection unit 113, which will not be described here.

[0074] In the embodiment, the second calibration unit 12 further includes a second calibration code generation unit 124. The second calibration code generation unit 124 updates the second impedance calibration code Ncode2 according to the second comparison signal Comp2. <n:0>, a second impedance calibration code Ncode <n:0>Used to control the equivalent resistance value of the second resistor unit 121. In some embodiments, the second calibration code generation unit 124 may be a counter.

[0075] In one embodiment, the comparison module 40 is further configured to receive the initial calibration code INcode. <n:0>and a second impedance calibration code, and based on the initial calibration code INcode <n:0>The difference between the first impedance calibration code and the second impedance calibration code outputs a second control signal Ctr2, the count module 20 receives the second control signal Ctr2, and adjusts the count frequency based on the second control signal Ctr2 and outputs a count value C1, when the count value C1 is greater than or equal to a preset value or the calibration control module 30 receives a third stop signal Stop3, the output of the second calibration clock signal Nclk is stopped.

[0076] In some embodiments, the calibration control module 30 further comprises a reset module 34, when the calibration control module 30 receives the first stop signal Stop1 or the second stop signal Stop2, the reset module 34 resets the first control signal Ctr1, so that it no longer acts on the count module 20, thereby avoiding the count module 20 being disturbed by the first control signal Ctr1 when responding to the second control signal Ctr2, and improving the reliability of the impedance calibration circuit.

[0077] The embodiments of the present disclosure also provide a memory comprising the impedance calibration circuit as above. The memory can output a first control signal based on the difference between the initial calibration code and the first impedance calibration code, and adjust the count frequency of the count module based on the first control signal, so as to change the time for the count value generated by the count module to reach a preset value, thereby making the time for the count value generated by the count module to reach the preset value controllable, avoiding random changes due to external factors, enabling the calibration control module to stop outputting the first calibration clock signal within a set time, i.e. enabling the impedance calibration circuit to stop calibration in time, the calibration time of the memory meeting the design requirements, effectively reducing power consumption, and improving the reliability of the memory.

[0078] The above only describes the preferred embodiments of the present application, and it should be noted that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. An impedance calibration circuit, characterized by, include: The comparison module receives an initial calibration code and a first impedance calibration code, and outputs a first control signal based on the difference between the initial calibration code and the first impedance calibration code. A counting module receives the first control signal, and the counting module adjusts the counting frequency and outputs a counting value based on the first control signal. The calibration module is used to receive a first calibration clock signal and generate a first impedance calibration code based on the first calibration clock signal. The calibration module performs impedance calibration according to the first impedance calibration code and outputs a first stop signal when the calibration is completed. The calibration control module is used to receive the count value, the first stop signal, and output the first calibration clock signal; when the count value is greater than or equal to a preset value or the calibration control module receives the first stop signal, it stops outputting the first calibration clock signal.

2. The impedance calibration circuit of claim 1, wherein, The comparison module includes: a difference unit, used to receive the initial calibration code and the first impedance calibration code, and to obtain the difference between the initial calibration code and the first impedance calibration code; Multiple adjustment units are connected to the difference unit respectively, for receiving the difference, and selecting the corresponding adjustment unit to output the first control signal according to the difference, with each adjustment unit corresponding to a numerical range.

3. The impedance calibration circuit of claim 2, wherein, The numerical ranges of each adjustment unit do not overlap.

4. The impedance calibration circuit of claim 1, wherein, It also includes a latching module, connected to the comparison module, for latching the initial calibration code.

5. The impedance calibration circuit of claim 1, wherein, The counting module includes: a clock signal generation unit connected to the comparison module, which generates an initial clock signal. The clock signal generation unit is used to receive the first control signal and change the period of the initial clock signal according to the first control signal. The counting unit counts the period of the initial clock signal and outputs the count value.

6. The impedance calibration circuit of claim 5, wherein, The clock signal generation unit includes multiple switching modes. The clock signal generation unit selects the corresponding switching mode according to the first control signal to change the period of the initial clock signal.

7. The impedance calibration circuit of claim 6, wherein, The clock signal generation unit is a ring oscillator composed of multiple inverters connected end to end. The clock signal generation unit also includes at least one selection switch, which is connected in parallel with at least one of the inverters to control whether the corresponding inverter is connected to the circuit.

8. The impedance calibration circuit of claim 1, wherein, When the count value is greater than or equal to a preset value, the calibration control module generates a second stop signal and stops outputting the first calibration clock signal according to the second stop signal.

9. The impedance calibration circuit of claim 8, wherein, The calibration control module includes a first logic gate circuit, which is used to receive the first stop signal and the second stop signal, and perform logical operations to output a first output signal. The calibration control module stops outputting the first calibration clock signal according to the first output signal.

10. The impedance calibration circuit of claim 8, wherein, The calibration module includes a first calibration unit, and the calibration module performs impedance calibration on the first calibration unit according to the first impedance calibration code. The first calibration unit includes: The first resistor unit has its first end connected to the first power supply terminal; A reference resistor, the first end of which is connected to the second end of the first resistor unit, and the second end of which is connected to the second power supply terminal; a first comparison unit configured to compare a second end voltage of the first resistance unit with a first reference voltage and output a first comparison signal; a first detection unit configured to take the first comparison signal as an input signal and record a change of the first comparison signal, and output the first stop signal when the change of the first comparison signal meets a preset condition.

11. The impedance calibration circuit of claim 10, wherein, The first calibration unit further comprises a first calibration code generation unit configured to update the first impedance calibration code according to the first comparison signal, and the first impedance calibration code is used to control an equivalent resistance value of the first resistance unit.

12. The impedance calibration circuit of claim 11, wherein, The calibration control module is further configured to output a second calibration clock signal, and the calibration module is further configured to receive the second calibration clock signal, and stop outputting the first calibration clock signal and start outputting the second calibration clock signal when the calibration control module receives the first stop signal or the second stop signal.

13. The impedance calibration circuit of claim 12, wherein, The calibration module generates a second impedance calibration code based on the second calibration clock signal, and the calibration module further comprises a second calibration unit, and the calibration module performs impedance calibration on the second calibration unit according to the second impedance calibration code, and the second calibration unit comprises: a second resistance unit, a second end of which is connected to a second power supply end; a third resistance unit, a first end of which is connected to the first power supply end, and a second end of which is connected to a first end of the second resistance unit, and the first calibration code is further used to control an equivalent resistance value of the third resistance unit; a second comparison unit configured to compare a first end voltage of the second resistance unit with a second reference voltage and output a second comparison signal; a second detection unit configured to take the second comparison signal as an input signal and record a change of the second comparison signal, and output a third stop signal when the change of the second comparison signal meets a preset condition; The calibration control module is further configured to output a second calibration clock signal, and the calibration module is further configured to receive the second calibration clock signal, and stop outputting the first calibration clock signal and start outputting the second calibration clock signal when the calibration control module receives the first stop signal or the second stop signal.

14. The impedance calibration circuit of claim 13, wherein, The comparison module is further configured to receive an initial calibration code and a second impedance calibration code, and output a second control signal based on a difference between the initial calibration code and the second impedance calibration code, and the counting module receives the second control signal and adjusts a counting frequency based on the second control signal and outputs the counting value, and stops outputting the second calibration clock signal when the counting value is greater than or equal to a preset value or the calibration control module receives the third stop signal.

15. The impedance calibration circuit of claim 14, wherein, The calibration control module further comprises a reset module, and the reset module resets the first control signal when the calibration control module receives the first stop signal or the second stop signal.

16. A memory, comprising: An impedance calibration circuit comprising any one of claims 1-15. An impedance calibration circuit comprising any one of claims 1-15.

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