Test circuit and test method for semiconductor memory

Abstract

The application provides a test circuit and a test method for a semiconductor memory, which comprises a counting module and a control module. An input end of the counting module receives a refresh pulse signal, and the refresh pulse signal indicates that the semiconductor memory performs a self-refresh operation. The counting module counts the refresh pulse signal and outputs a counting value when the semiconductor memory frequently enters a self-refresh mode at a minimum self-refresh interval. An input end of the control module is coupled to an output end of the counting module to obtain the counting value output by the counting module. If an optimized refresh mode of the semiconductor memory is in a normal state, and the semiconductor memory frequently enters the self-refresh mode at the minimum refresh interval, since the minimum self-refresh interval is smaller than a refresh time interval, the self-refresh operation is not performed every time the semiconductor memory enters the self-refresh mode. Therefore, the counting value obtained by the control module changes every time, and the control module can determine whether the optimized refresh mode of the semiconductor memory is in the normal state according to the counting value.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a test circuit and a test method of a semiconductor memory. BACKGROUND

[0002] A dynamic random access memory (DRAM) is a kind of semiconductor memory, which includes a plurality of memory cells, each of which can represent a binary bit (bit) is 1 or 0 by using the amount of storage charge stored in a storage capacitor. Due to the existence of leakage current in the transistor in the memory cell, the storage charge in the storage capacitor is affected by the leakage current and changes, resulting in data loss. Therefore, the dynamic random access memory needs to constantly refresh the memory cells to maintain the charge amount of the storage charge in the storage capacitor in the memory cell.

[0003] At present, the semiconductor memory can use optimized refresh to refresh the memory cells, and the optimized refresh mode is a kind of power saving mode. However, due to the small power saving range of the optimized refresh mode, it is difficult to accurately determine the working state of the optimized refresh. SUMMARY

[0004] The present application provides a test circuit and a test method of a semiconductor memory to determine whether the optimized refresh mode is in a normal state.

[0005] In a first aspect, the present application provides a semiconductor memory, comprising:

[0006] a counting module, an input end of which receives a refresh pulse signal, for outputting a counting value after counting the refresh pulse signal when the semiconductor memory frequently enters a self-refresh mode at a minimum self-refresh interval, the refresh pulse signal being used to instruct the semiconductor memory to perform a self-refresh operation;

[0007] a control module, an input end of which is coupled to an output end of the counting module, for determining whether an optimized refresh mode of the semiconductor memory is in a normal state according to the counting value.

[0008] Optionally, the control module is used to acquire a first counting value output by the counting module when the semiconductor memory exits the self-refresh mode and a second counting value output by the counting module when the semiconductor memory enters the self-refresh mode again.

[0009] When the first counting value is the same as the second counting value, it is determined that the optimized refresh mode is in a normal state, and when the first counting value is different from the second counting value, it is determined that the optimized refresh mode is in an abnormal state.

[0010] Optionally, the counting module is configured to output a third count value after counting the refresh pulse signals in a preset time interval.

[0011] The control module is configured to obtain the third count value, and determine that the optimized refresh mode is in a normal state when the third count value is less than a preset count threshold, and determine that the self-refresh mode is in an abnormal state when the third count value is greater than or equal to the preset count threshold.

[0012] Optionally, the preset count threshold is positively correlated with the number of times of entering the self-refresh mode in the preset time interval.

[0013] Optionally, the test circuit further comprises:

[0014] an interval adjustment module configured to adjust an interval between entering the self-refresh mode and exiting the self-refresh mode of the semiconductor memory.

[0015] Optionally, the test circuit further comprises:

[0016] a pulse adjustment module configured to receive an original refresh signal at an input end, and output the refresh pulse signal after pulse adjustment on the original refresh signal;

[0017] The pulse adjustment module comprises:

[0018] a first inverter configured to receive the original refresh signal at an input end;

[0019] a delay circuit configured to be coupled with an output end of the first inverter at an input end, and perform delay processing on an output signal of the first inverter to output a delay signal;

[0020] a NAND gate circuit configured to be coupled with the output end of the first inverter at a first input end, and coupled with the output end of the delay circuit at a second input end, and configured to perform NAND operation on the original refresh signal and the delay signal;

[0021] a second inverter configured to be coupled with an output end of the NAND gate circuit at an input end, and configured to output the refresh pulse signal.

[0022] Optionally, the counting module comprises a plurality of output ends; the count value comprises a plurality of count signals; the counting module comprises a plurality of counting circuits; each of the counting circuits comprises an input end and an output end.

[0023] The input end of a first-stage counting circuit receives the refresh pulse signal, and the output end of an upper-stage counting circuit is coupled with the input end of a lower-stage counting circuit; the output end of each of the counting circuits serves as one of the output ends of the counting module, and is configured to output one of the count signals.

[0024] In a second aspect, the application provides a testing method for a semiconductor memory, the method comprising:

[0025] counting a refresh pulse signal for outputting a count value after the semiconductor memory frequently enters a self-refresh mode at a minimum self-refresh interval, the refresh pulse signal being used to indicate the semiconductor memory to enter a self-refresh operation;

[0026] determining whether an optimized refresh mode of the semiconductor memory is in a normal state according to the count value.

[0027] Optionally, the determining whether the optimized refresh mode of the semiconductor memory is in the normal state according to the count value specifically comprises:

[0028] acquiring a first count value output by a counting module when the semiconductor memory exits the self-refresh mode and a second count value output by the counting module when the semiconductor memory re-enters the self-refresh mode;

[0029] determining that the optimized refresh mode is in the normal state when the first count value is the same as the second count value;

[0030] determining that the optimized refresh mode is in an abnormal state when the first count value is different from the second count value.

[0031] Optionally, the counting the refresh pulse signal for outputting the count value after the semiconductor memory frequently enters the self-refresh mode at the minimum self-refresh interval specifically comprises:

[0032] counting the refresh pulse signal for outputting a third count value within a preset time interval when the semiconductor memory frequently enters the self-refresh mode at a minimum time interval;

[0033] determining whether the optimized refresh mode of the semiconductor memory is in the normal state according to the count value, specifically comprising:

[0034] determining that the optimized refresh mode is in the normal state when the third count value is less than a preset count threshold, and determining that the optimized refresh mode is in the abnormal state when the third count value is greater than or equal to the preset count threshold.

[0035] The test circuit of the semiconductor memory provided by the application comprises a counting module and a control module. The input end of the counting module receives a refresh pulse signal. The refresh pulse signal indicates that the semiconductor memory performs a self-refresh operation. The counting module counts the refresh pulse signal and outputs a counting value when the semiconductor memory frequently enters the self-refresh mode at a minimum self-refresh interval. The input end of the control module is coupled to the output end of the counting module to obtain the counting value output by the counting module. When the optimized refresh mode of the semiconductor memory is in a normal state and the semiconductor memory frequently enters the self-refresh mode at the minimum refresh interval, the self-refresh operation is not performed every time the self-refresh mode is entered because the minimum self-refresh interval is smaller than a refresh time interval, which is the interval between two self-refresh operations. Therefore, the counting value obtained by the control module changes every time. Thus, the control module can determine whether the optimized refresh mode of the semiconductor memory is in the normal state according to the counting value. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the application or the prior art, the following will briefly introduce the drawings needed in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0037] Figure 1 A circuit diagram of a test circuit of a semiconductor memory provided by an embodiment of the application;

[0038] Figure 2 A circuit diagram of a counting circuit provided by an embodiment of the application;

[0039] Figure 3 A circuit diagram of a test circuit of a semiconductor memory provided by an embodiment of the application;

[0040] Figure 4 Another circuit diagram of a counting circuit provided by an embodiment of the application;

[0041] Figure 5 Another circuit diagram of a test circuit of a semiconductor memory provided by an embodiment of the application;

[0042] Figure 6 A circuit diagram of a pulse width modulation module provided by an embodiment of the application;

[0043] Figure 7 A flowchart of a test method of a semiconductor memory provided by an embodiment of the application. DETAILED DESCRIPTION

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the foregoing claims.

[0046] Figure 1 This application provides a test circuit for a semiconductor memory according to one embodiment. Figure 1 As shown, an embodiment of this application provides a test circuit for a semiconductor memory, including a counting module 100 and a control module 200. The input terminal of the counting module 100 receives a refresh pulse signal `selfclk`, which instructs the semiconductor memory to perform a self-refresh operation. The counting module 100 counts the refresh pulse signal `selfclk` and outputs a count value when the semiconductor memory frequently enters self-refresh mode with the minimum self-refresh interval. The input terminal of the control module 200 is coupled to the output terminal of the counting module 100, and is used to determine whether the optimized refresh mode of the semiconductor memory is in a normal state based on the count value.

[0047] When a semiconductor memory is in optimized refresh mode, it does not perform a self-refresh operation on the memory cells every time it enters self-refresh mode. After entering self-refresh mode, the semiconductor memory needs to continue timing based on the previous exit from self-refresh operation, and perform a self-refresh operation when the accumulated timing in self-refresh mode reaches the self-refresh interval.

[0048] For example, the semiconductor memory enters the self-refresh mode for the first time, and performs the first self-refresh operation, and exits the self-refresh operation for the first time after the self-refresh is completed. Then, the semiconductor memory enters the self-refresh mode for the second time, and continues to accumulate the time period in the self-refresh mode since the last self-refresh is completed. If the accumulated time period has not reached the self-refresh time interval before the semiconductor memory exits the self-refresh mode for the second time, the counting continues until the accumulated time period in the self-refresh mode reaches the self-refresh time interval, and then the self-refresh operation is performed. That is, the counter for accumulating the time period in the self-refresh mode stops counting after the current self-refresh mode is exited, and before the semiconductor memory enters the self-refresh mode next time.

[0049] Therefore, when the semiconductor memory is in the optimized refresh mode and the optimized refresh mode is in the normal state, if the semiconductor memory frequently enters the self-refresh mode with the minimum self-refresh interval, since the time period for entering the self-refresh mode each time is less than the self-refresh time interval, the accumulated time period in the self-refresh mode needs to meet the time interval requirement of the self-refresh operation once. Therefore, the self-refresh operation is not performed each time the self-refresh operation is entered. That is, the number of times the self-refresh operation is actually performed should be much less than the frequency of entering the self-refresh mode. By comparing the number of times the self-refresh operation is actually performed with the frequency of entering the self-refresh mode, it can be determined whether the optimized refresh mode of the semiconductor memory is in the normal state.

[0050] When the semiconductor memory enters the self-refresh mode and performs the self-refresh operation, the refresh pulse signal selfclk is sent to the input end of the counting module 100. The counting module 100 receives the refresh pulse signal selfclk, counts the refresh pulse signal selfclk, and outputs the counting value. When the semiconductor memory enters the self-refresh mode but does not perform the self-refresh operation, the refresh pulse signal selfclk is not sent to the input end of the counting module 100. At this time, the counting module 100 does not count.

[0051] In some embodiments, the control module 200 acquires a first count value output by the count module 100 when the semiconductor memory exits the self-refresh mode, and acquires a second count value output by the count module 100 when the semiconductor memory re-enters the self-refresh mode. Since the count module 100 stops counting in the optimized refresh mode, when the first count value is the same as the second count value, i.e., the count value when the semiconductor memory exits the self-refresh mode is the same as the count value when the semiconductor memory re-enters the self-refresh mode, it indicates that the semiconductor memory does not perform the self-refresh operation when it re-enters the self-refresh mode, and it is determined that the optimized refresh mode is in the normal state. When the first count value is different from the second count value, it indicates that the semiconductor memory performs the self-refresh operation when it re-enters the self-refresh mode, and it is determined that the optimized refresh mode is in the abnormal state. That is, whether the optimized refresh mode is in the normal state or not can be determined according to the first count value when the semiconductor memory exits the self-refresh mode and the second count value when the semiconductor memory re-enters the self-refresh mode.

[0052] In other embodiments, when the semiconductor memory is in the optimized refresh mode and the optimized refresh mode is in the normal state, if the semiconductor memory frequently enters the self-refresh mode with the minimum self-refresh interval, the self-refresh operation is not performed every time the semiconductor memory enters the self-refresh mode. Therefore, the count module 100 counts the refresh pulse signal selfclk in a preset time interval and outputs a third count value, which is used to indicate the number of times of the self-refresh operation in the preset time interval. The control module 200 acquires the third count value. When the third count value is less than a preset count threshold, it indicates that the self-refresh operation is not performed every time the semiconductor memory enters the self-refresh mode, and it is determined that the optimized refresh mode is in the normal state. When the third count value is greater than or equal to the preset count threshold, it indicates that the self-refresh operation is performed every time the semiconductor memory enters the self-refresh mode, or the number of times of the self-refresh operation is large, and it is determined that the optimized refresh mode is in the abnormal state.

[0053] The preset count threshold can be positively correlated with the number of times of entering the self-refresh mode in the preset time interval, so as to determine whether the optimized refresh mode is in the normal state in different time intervals, thereby more accurately determining the working state of the optimized refresh mode. The more the number of times of entering the self-refresh mode in the preset time interval, the greater the preset count threshold, and the more the number of times of the self-refresh operation. The less the number of times of entering the self-refresh mode in the preset time interval, the smaller the preset count threshold, and the less the number of times of the self-refresh operation. The preset time interval can be determined according to specific conditions, and is not limited herein.

[0054] As an implementation manner, the control module 200 can also acquire the first count value and the second count value for multiple times within the preset time interval, i.e., acquire the first count value when exiting the self-refresh mode multiple times, and acquire the second count value when entering the self-refresh mode again after exiting the self-refresh mode each time, so as to acquire multiple pairs of the first count value and the second count value within the preset time interval.

[0055] After acquiring multiple pairs of the first count value and the second count value within the preset time interval, the last acquired first count value and the last acquired second count value can be compared first, and if the last acquired first count value and the last acquired second count value are the same, the intermediate acquired first count value and the intermediate acquired second count value are compared, and if the intermediate acquired first count value and the intermediate acquired second count value are the same, it is determined that the optimized refresh mode is in the normal state, so as to more accurately determine whether the optimized refresh mode is in the normal state. The intermediate time can be any time between the first time and the last time.

[0056] For the convenience of description, the last time is recorded as the Nth time, N is a positive integer greater than 1, if the first count value acquired in the Nth time and the second count value acquired in the Nth time are different, the first count value acquired in the (N-1)th time and the second count value acquired in the (N-1)th time are compared, if the first count value acquired in the (N-1)th time and the second count value acquired in the (N-1)th time are different, it is determined that the optimized refresh mode is in the abnormal state, if the first count value acquired in the (N-1)th time and the second count value acquired in the (N-1)th time are the same, the first count value acquired in the Mth time and the second count value acquired in the Mth time are compared, if the first count value acquired in the Mth time and the second count value acquired in the Mth time are the same, it is determined that the optimized refresh mode is in the normal state, M is a positive integer greater than or equal to 1, which can be any value from 1 to N-1, for example, N / 2.

[0057] In some embodiments, the test circuit can include an interval adjustment module, which is configured to adjust the interval between the semiconductor memory entering the self-refresh mode and exiting the self-refresh mode, so as to determine whether the optimized refresh mode is in the normal state under different conditions.

[0058] The control module 200 can include an enable terminal, which is configured to receive an enable signal MRSelfNum, and the enable signal MRSelfNum is configured to instruct the control module 200 to acquire the count value output by the count module 100.

[0059] In some embodiments, with reference to Figure 3 and Figure 5As shown, the counting module 100 includes a plurality of outputs, and the counting value includes a plurality of counting signals. The counting module 100 includes a plurality of counting circuits 110, and each counting circuit 110 includes an input and an output. The input of the first counting circuit 110 receives the refresh pulse signal selfclk, the output of the previous counting circuit 110 is coupled to the input of the next counting circuit 110, the output of each counting circuit 110 is an output of the counting module 100, and is used to output a counting signal. The control module 200 is coupled to the output of each counting circuit 110, acquires the counting signal of each counting circuit 110, and forms the counting value of the counting module 100.

[0060] As an implementation manner, refer to Figure 2 As shown, each counting circuit 110 includes a third inverter 111, a fourth inverter 113, a fifth inverter 114, and a first flip-flop 112. The input of the third inverter 111 is the input of the counting circuit 110, and the output of the third inverter 111 is coupled to the first flip-flop 112. The clock end CK of the first flip-flop 112 is coupled to the output of the third inverter 111, the enable end CKN of the first flip-flop 112 is coupled to the input of the third inverter 111, the output end Q of the first flip-flop 112 is coupled to the input of the fourth inverter 113, and the input end D of the first flip-flop 112 is coupled to the output of the fourth inverter 113. The input of the fifth inverter 114 is coupled to the output of the fourth inverter 113, and the output of the fifth inverter 114 is the output of the counting circuit 110.

[0061] As another implementation manner, refer to Figure 4 As shown, each counting circuit 110 includes a sixth inverter 121, a seventh inverter 123, and a second flip-flop 122. The input of the sixth inverter 121 is the input of the counting circuit 110, and the output of the sixth inverter 121 is coupled to the second flip-flop 122. The clock end CK of the second flip-flop 122 is coupled to the output of the sixth inverter 121, the enable end CKN of the second flip-flop 122 is coupled to the input of the sixth inverter 121, the output end Q of the second flip-flop 122 is coupled to the input of the seventh inverter 123, the input end D of the second flip-flop 122 is coupled to the output of the seventh inverter 123, and the output end Q of the second flip-flop 122 is the output of the counting circuit 110.

[0062] Refer to Figure 3 and Figure 5As shown, n counting circuits 110 form a counting module 100, n is a positive integer greater than 1, the input end of the first-stage counting circuit receives a refresh pulse signal selfclk, the output end Q1 of the first-stage counting circuit is coupled to the input end of the second-stage counting circuit, the output end Q2 of the second-stage counting circuit is coupled to the input end of the third-stage counting circuit, and so on, the output end of the n-1th-stage counting circuit is coupled to the input end of the nth-stage counting circuit. The control module 200 is coupled to the output end Q1 of the first-stage counting circuit, the output end Q2 of the second-stage counting circuit, the output end Q3 of the third-stage counting circuit, and so on, and the output end Qn of the nth-stage counting circuit, to obtain the counting signal of each stage of counting circuit, and form a counting value.

[0063] For example, the active signal of the clock end CK of the first flip-flop 112 is a high-level signal, and the active signal of the enable end CKN is a low-level signal. Referring to Figure 3As shown, when the refresh pulse signal selfclk is a first data signal (a low-level signal), for the first-stage counting circuit, the CKN of the first flip-flop 112 receives the first data signal, the third inverter 111 converts the first data signal into a second data signal and transmits the second data signal to the clock end CK of the first flip-flop 112, then the clock end CK and the enable end CKN of the first flip-flop 112 both receive valid signals, the output end of the first flip-flop 112 receives the first data signal of the input end of the first flip-flop 112 and outputs the first data signal, the fourth inverter 113 converts the first data signal into a second data signal and outputs the second data signal to the input end of the first flip-flop 112, and the fifth inverter 114 converts the second data signal into the first data signal, which is used as a trigger signal of the second-stage counting circuit 110, and the control module 200 obtains the first data signal of the first-stage counting circuit 110. The first data signal and the second data signal are data signals with opposite levels, for example, the first data signal is a low-level signal 0 and the second data signal is a high-level signal 1. The input end of the second-stage counting circuit receives the first data signal, for the second-stage counting circuit, the enable end CKN of the first flip-flop 112 receives the first data signal, the third inverter 111 converts the first data signal into a second data signal and transmits the second data signal to the clock end CK of the first flip-flop 112, then the clock end CK and the enable end CKN of the first flip-flop 112 receive valid signals, the output end of the first flip-flop 112 receives the first data signal of the input end of the first flip-flop 112 and outputs the first data signal, the fourth inverter 113 converts the first data signal into a second data signal and outputs the second data signal to the input end of the first flip-flop 112, and the fifth inverter 114 converts the second data signal into the first data signal, which is used as a trigger signal of the third-stage counting circuit, and the control module 200 obtains the first data signal output by the second-stage counting circuit. By analogy, the control module 200 obtains the first data signal or the second data signal output by each stage of the counting circuit, and forms a counting value.

[0064] Reference Figure 5As shown, when the refresh pulse signal selfclk is a first data signal (a low-level signal), for the first-stage counting circuit, the enable end CKN of the second flip-flop 122 receives the first data signal, the sixth inverter 121 converts the first data signal into a second data signal and transmits the second data signal to the clock end CK of the second flip-flop 122, then the clock end CK and the enable end CKN of the second flip-flop 122 both receive valid signals, the output end of the second flip-flop 122 receives the first data signal of the input end of the second flip-flop 122 and outputs the first data signal, the seventh inverter 123 converts the first data signal into a second data signal and outputs the second data signal to the input end of the second flip-flop 122, and the output end of the second flip-flop 122 outputs the first data signal as a trigger signal of the second-stage counting circuit, while the control module 200 acquires the first data signal output by the output end of the second flip-flop 122. The first data signal and the second data signal are data signals with opposite levels, for example, the first data signal is a low-level signal 0 and the second data signal is a high-level signal 1. The input end of the second-stage counting circuit 110 receives the first data signal, for the second-stage counting circuit, the enable end CKN of the second flip-flop 122 receives the first data signal, the sixth inverter 121 converts the first data signal into a second data signal and transmits the second data signal to the clock end CK of the second flip-flop 122, then the clock end CK and the enable end CKN of the second flip-flop 122 receive valid signals, the output end of the second flip-flop 122 receives the first data signal of the input end of the second flip-flop 122 and outputs the first data signal, the seventh inverter 123 converts the first data signal into a second data signal and outputs the second data signal to the input end of the second flip-flop 122, and the output end of the second flip-flop 122 outputs the first data signal as a trigger signal of the second-stage counting circuit, while the control module 200 acquires the first data signal output by the output end of the second flip-flop 122. By analogy, the control module 200 acquires the first data signal or the second data signal output by each counting circuit to form a counting value.

[0065] In some embodiments, with reference to Figure 6 As shown, the test circuit further includes a pulse adjustment module 300, and the input end of the pulse adjustment module 300 receives an original refresh signal. The original refresh signal can be understood as a state signal, for example, a low-level signal changes into a high-level signal and lasts for a high-level signal. After the pulse adjustment module 300 receives the original refresh signal, the pulse adjustment module 300 outputs a refresh pulse signal selfclk after pulse adjustment on the original refresh signal, so as to provide the refresh pulse signal selfclk for the counting module 100. The refresh pulse signal selfclk can be a high-level signal or a low-level signal.

[0066] The pulse adjustment module 300 can include a first inverter 301, a delay circuit 302, a NAND gate circuit 303, and a second inverter 304. The input end of the first inverter 301 receives an original refresh signal, and the first inverter 301 can perform level inversion on the original refresh signal, for example, converting a high-level signal into a low-level signal. The input end of the delay circuit 302 is coupled with the output end of the first inverter 301, and the delay circuit 302 performs delay processing on the output signal of the first inverter 301 to output a delay signal. The first input end In1 of the NAND gate circuit 303 is coupled with the output end of the first inverter 301, and the second input end In1 of the NAND gate circuit 303 is coupled with the output end of the delay circuit 302, for performing NAND operation on the original refresh signal and the delay signal. The input end of the second inverter 304 is coupled with the output end Out of the NAND gate circuit 303, for outputting a refresh pulse signal selfclk.

[0067] Figure 7 A test method of a semiconductor memory is provided for an embodiment of the present application. Referring to Figure 7 as shown, comprising:

[0068] S101, counting the refresh pulse signal and outputting a count value when the semiconductor memory frequently enters the self-refresh mode at the minimum self-refresh interval.

[0069] The refresh pulse signal is used to instruct the semiconductor memory to perform a self-refresh operation, and the count value is outputted after counting the refresh pulse signal. The count value can be used to indicate the number of times of performing the self-refresh operation.

[0070] When the semiconductor memory enters the self-refresh mode and performs the self-refresh operation, the refresh pulse signal is sent to the input end of the counting module, and the counting module receives the refresh pulse signal, counts the refresh pulse signal, and outputs a count value. When the semiconductor memory enters the self-refresh mode but does not perform the self-refresh operation, the refresh pulse signal is not sent to the input end of the counting module, and the counting module does not count at this time.

[0071] As an implementation manner, a first count value outputted by the counting module when the semiconductor memory exits the self-refresh mode and a second count value outputted by the counting module when the semiconductor memory enters the self-refresh mode again can be acquired. As another implementation manner, a third count value outputted after counting the refresh pulse signal s in a preset time interval when the semiconductor memory frequently enters the self-refresh mode at the minimum refresh interval can be acquired.

[0072] S102, determining whether the optimized refresh mode of the semiconductor memory is in a normal state according to the count value.

[0073] When the semiconductor is in the optimized refresh mode, if the semiconductor memory frequently enters the self-refresh mode with the minimum self-refresh interval, since the duration of the self-refresh mode is less than the refresh time interval, the self-refresh operation is not performed every time the semiconductor memory enters the self-refresh mode, and thus the count value can be used to determine whether the optimized refresh mode of the semiconductor memory is in a normal state.

[0074] As an implementation manner, the first count value output by the counting module when the semiconductor memory exits the self-refresh mode and the second count value output by the counting module when the semiconductor memory reenters the self-refresh mode are acquired, and then the first count value and the second count value are compared. When the first count value and the second count value are the same, it is determined that the optimized refresh mode is in a normal state, and when the first count value and the second count value are different, it is determined that the optimized refresh mode is in an abnormal state.

[0075] As another implementation manner, a third count value output after counting the refresh pulse signals in a preset time interval is acquired, and then the third count value is compared with a preset count threshold. When the third count value is less than the preset count threshold, it is determined that the optimized refresh mode is in a normal state, and when the third count value is greater than or equal to the preset count threshold, it is determined that the optimized refresh mode is in an abnormal state.

[0076] The test circuit and the test method of the semiconductor memory provided in the present application are described in detail above. When the optimized refresh mode of the semiconductor memory is in a normal state, if the semiconductor memory frequently enters the self-refresh mode with the minimum refresh interval, and the minimum self-refresh interval is less than the refresh time interval, the self-refresh operation is not performed every time the semiconductor memory enters the self-refresh mode. Thus, the count value can be used to determine whether the optimized refresh mode of the semiconductor memory is in a normal state.

[0077] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or equivalently replace some or all of the technical features. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A test circuit for a semiconductor memory, characterized in that, include: The counting module receives a refresh pulse signal at its input terminal and is used to count the refresh pulse signal and output a count value when the semiconductor memory frequently enters the self-refresh mode with the minimum self-refresh interval. The refresh pulse signal is used to instruct the semiconductor memory to perform a self-refresh operation. The control module, whose input is coupled to the output of the counting module, is used to determine whether the optimized refresh mode of the semiconductor memory is in a normal state based on the count value.

2. The test circuit according to claim 1, characterized in that, The control module is used to acquire the first count value output by the counting module when the semiconductor memory exits the self-refresh mode and the second count value output by the counting module when the semiconductor memory re-enters the self-refresh mode. When the first count value and the second count value are the same, the optimized refresh mode is determined to be in a normal state; when the first count value and the second count value are different, the optimized refresh mode is determined to be in an abnormal state.

3. The test circuit according to claim 1 or 2, characterized in that, The counting module is used to count the refresh pulse signal within a preset time interval and then output a third count value; The control module is used to obtain the third count value, and when the third count value is less than a preset count threshold, it determines that the optimized refresh mode is in a normal state, and when the third count value is greater than or equal to the preset count threshold, it determines that the self-refresh mode is in an abnormal state.

4. The test circuit according to claim 3, characterized in that, The preset counting threshold is positively correlated with the number of times the self-refresh mode is entered within the preset time interval.

5. The test circuit according to claim 1, characterized in that, The test circuit also includes: An interval adjustment module is used to adjust the interval between the semiconductor memory entering and exiting the self-refresh mode.

6. The test circuit according to claim 3, characterized in that, The test circuit also includes: The pulse adjustment module receives the original refresh signal at its input terminal, performs pulse adjustment on the original refresh signal, and outputs the refresh pulse signal. The pulse adjustment module includes: The first inverter receives the original refresh signal at its input terminal; The delay circuit has its input terminal coupled to the output terminal of the first inverter, and performs delay processing on the output signal of the first inverter to output a delayed signal; A NAND gate circuit, whose first input terminal is coupled to the output terminal of the first inverter and whose second input terminal is coupled to the output terminal of the delay circuit, is used to perform NAND operation on the original refresh signal and the delay signal; The second inverter, whose input is coupled to the output of the NAND gate circuit, is used to output the refresh pulse signal.

7. The test circuit according to claim 3, characterized in that, The counting module includes multiple output terminals; the counting value includes multiple counting signals; the counting module includes multiple counting circuits; each counting circuit includes an input terminal and an output terminal; The input terminal of the first-stage counting circuit receives the refresh pulse signal, and the output terminal of the previous-stage counting circuit is coupled to the input terminal of the next-stage counting circuit; the output terminal of each counting circuit serves as an output terminal of the counting module, used to output a counting signal.

8. A method for testing a semiconductor memory, characterized in that, The method includes: When the semiconductor memory frequently enters the self-refresh mode with the minimum self-refresh interval, the refresh pulse signal is counted and the count value is output. The refresh pulse signal is used to indicate that the semiconductor memory enters the self-refresh operation. The optimized refresh mode of the semiconductor memory is determined based on the count value to determine whether it is in a normal state.

9. The test method according to claim 8, characterized in that, Determining whether the optimized refresh mode of the semiconductor memory is in a normal state based on the count value specifically includes: The first count value output by the counting module when the semiconductor memory exits the self-refresh mode and the second count value output by the counting module when the semiconductor memory re-enters the self-refresh mode are obtained. When the first count value and the second count value are the same, it is determined that the optimized refresh mode is in a normal state; When the first count value is different from the second count value, it is determined that the optimized refresh mode is in an abnormal state.

10. The test method according to claim 8 or 9, characterized in that, When the semiconductor memory frequently enters self-refresh mode with the minimum refresh interval, the refresh pulse signal is counted and a count value is output, specifically including: When the semiconductor memory frequently enters the self-refresh mode with the minimum time interval, the refresh pulse signal is counted within a preset time interval and a third count value is output. Determining whether the optimized refresh mode of the semiconductor memory is in a normal state based on the count value specifically includes: When the third count value is less than a preset count threshold, the optimized refresh mode is determined to be in a normal state; when the third count value is greater than or equal to the preset count threshold, the optimized refresh mode is determined to be in an abnormal state.

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