Word line resistance testing method, device, equipment, storage medium and program product

Abstract

Embodiments of the present application provide a word line resistance testing method, apparatus, device, storage medium, and program product. The word line resistance testing method includes: writing first data into a memory cell connected to a word line to be tested, and reading the data stored in the memory cell after the word line to be tested is activated for a preset time, wherein the preset time is less than the standard row address activation time corresponding to the memory cell; and determining whether the resistance of the word line to be tested is qualified based on the data stored in the memory cell. After writing the data to the memory cell, the stored data is read using a shorter row address activation valid time, and the word line resistance is tested based on whether the read data is consistent with the written data. The test is low in cost and high in accuracy. Through word line resistance testing, DRAM read and write failures caused by excessively large word line resistance are effectively avoided.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a word line resistance testing method, apparatus, device, storage medium, and program product. Background Art

[0002] DRAM (Dynamic Random Access Memory) is an internal memory that includes one or more memory arrays. Each memory array consists of M×N memory cells. Each memory cell is located at the intersection of a WL (Word Line) and a BL (Bit Line) and is used to store data.

[0003] As DRAM sizes continue to shrink, the impact of WL resistance on read and write failures in DRAM memory cells is becoming increasingly significant. To improve DRAM yield, it is often necessary to use low-resistance materials or increase the current during DRAM read and write operations by increasing voltage.

[0004] However, the above method has limited effect on improving the DRAM yield. Therefore, there is an urgent need for an effective WL resistance testing method to perform WL maintenance based on the test results and improve the yield of DRAM read and write operations. Summary of the Invention

[0005] The embodiments of the present application provide a word line resistance testing method, apparatus, device, storage medium and program product, which realize the detection of excessively large WL resistance, avoid affecting the effectiveness of DRAM read and write operations due to excessively large WL resistance, and improve the yield of DRAM.

[0006] In a first aspect, an embodiment of the present application provides a word line resistance testing method, the method comprising:

[0007] Writing first data into a memory cell connected to a word line to be tested, and reading data stored in the memory cell after the word line to be tested is activated for a preset time, wherein the preset time is less than a standard row address activation time corresponding to the memory cell;

[0008] Whether the resistance of the word line to be tested is qualified is determined according to the data stored in the memory cell.

[0009] In some embodiments, writing first data into a memory cell connected to a word line to be tested, and reading data stored in the memory cell after the word line to be tested is activated for a preset time, includes:

[0010] issuing an activation instruction to activate the word line to be tested, and writing first data into a storage unit connected to the word line to be tested;

[0011] The data stored in the storage unit is read at a preset time after the activation instruction is issued.

[0012] In some embodiments, issuing an activation instruction to activate the word line to be tested and writing the first data into a memory cell connected to the word line to be tested includes:

[0013] When the bit line corresponding to the memory cell connected to the word line to be tested remains open, an activation instruction is issued to activate the word line to be tested, and first data is written into the memory cell connected to the word line to be tested.

[0014] In some embodiments, the method further comprises:

[0015] turning off the sense amplifier corresponding to the storage unit;

[0016] A bit line precharge voltage between the bit line corresponding to the memory cell and a reference bit line is maintained at a preset voltage, so that the bit line corresponding to the memory cell remains open.

[0017] In some embodiments, before reading the data stored in the storage unit, the method further includes:

[0018] Turning on the sense amplifier corresponding to the storage unit;

[0019] The bit line precharge voltage is maintained at the preset voltage.

[0020] In some embodiments, before issuing the activation instruction, the method further includes:

[0021] Second data is written into a memory cell connected to a word line to be tested, and the word line to be tested is turned off.

[0022] In some embodiments, before issuing the activation instruction, the method further includes:

[0023] The row address activation time timer corresponding to the word line to be tested is turned off.

[0024] In some embodiments, the activation instruction when writing data to the storage unit is a falling edge valid instruction, and the activation instruction when reading data stored in the storage unit is a rising edge valid instruction.

[0025] In some embodiments, issuing an activation instruction to write first data into a memory cell connected to a word line to be tested includes:

[0026] At least two activation instructions are issued at intervals, and the first data is written into the storage unit at least twice, wherein the preset times corresponding to the at least two activation instructions are different.

[0027] Accordingly, determining whether the resistance of the word line to be tested is qualified according to the data stored in the storage unit includes:

[0028] If the data in the storage unit read after the preset time corresponding to the issuance of at least one activation instruction is the second data, it is determined that the resistance of the word line to be tested is unqualified.

[0029] In some embodiments, the method further comprises:

[0030] The abnormality level of the resistance of the word line to be tested is determined according to data in the storage unit read after a preset period corresponding to each activation instruction of the at least two activation instructions is issued.

[0031] In some embodiments, the word line to be tested includes multiple word lines of a memory chip, and the method further includes:

[0032] The memory chip test report is generated and outputted according to the word lines with unqualified resistance among the plurality of word lines.

[0033] In some implementations, the preset time is 5-20 ns.

[0034] In a second aspect, an embodiment of the present application provides a word line resistance testing device, comprising:

[0035] a read / write module, configured to write first data into a storage cell connected to a word line to be tested, and read the data stored in the storage cell after the word line to be tested is activated for a preset time, wherein the preset time is less than a standard row address activation time corresponding to the storage cell;

[0036] The resistance testing module is used to determine whether the resistance of the word line to be tested is qualified according to the data stored in the storage unit.

[0037] In some implementations, the read / write module includes:

[0038] a first data writing unit, configured to issue an activation instruction to activate the word line to be tested, and write first data into a storage unit connected to the word line to be tested;

[0039] The data reading module unit is used to read the data stored in the storage unit at a preset time after the activation instruction is issued.

[0040] In some implementations, the first data writing unit is specifically configured to:

[0041] When the bit line corresponding to the memory cell connected to the word line to be tested remains open, an activation instruction is issued to activate the word line to be tested, and first data is written into the memory cell connected to the word line to be tested.

[0042] In some embodiments, the device further comprises:

[0043] The bit line holding module is used to turn off the sensitive amplifier corresponding to the storage unit; maintain the bit line precharge voltage between the bit line corresponding to the storage unit and the reference bit line at a preset voltage, so that the bit line corresponding to the storage unit remains open.

[0044] In some embodiments, the device further comprises:

[0045] The cancellation module is used to turn on the sense amplifier corresponding to the storage unit before reading the data stored in the storage unit; and cancel the maintenance of the bit line pre-charge voltage at the preset voltage.

[0046] In some embodiments, the device further comprises:

[0047] The storage unit initialization module is used to write second data into the storage unit connected to the word line to be tested and close the word line to be tested before issuing the activation instruction.

[0048] In some embodiments, the method further comprises:

[0049] The timer closing module is used to close the row address activation time timer corresponding to the word line to be tested before issuing the activation instruction.

[0050] In some implementations, the data reading module is specifically configured to:

[0051] At least two activation instructions are issued at intervals, and the first data is written into the storage unit at least twice, wherein the preset times corresponding to the at least two activation instructions are different.

[0052] Accordingly, the resistance test module is specifically used for:

[0053] If the data in the storage unit read after the preset time corresponding to the issuance of at least one activation instruction is the second data, it is determined that the resistance of the word line to be tested is unqualified.

[0054] In some embodiments, the device further comprises:

[0055] The abnormality level determination module is used to determine the abnormality level of the word line resistance to be tested according to the data in the storage unit read after the corresponding preset period of time of each activation instruction in the at least two activation instructions.

[0056] In some embodiments, the word lines to be tested include multiple word lines of a memory chip, and the apparatus method further includes:

[0057] A test report output module is used to generate and output the memory chip test report according to the word lines with unqualified resistance among the multiple word lines.

[0058] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: at least one processor and a memory;

[0059] The memory stores computer-executable instructions;

[0060] The at least one processor executes the computer-executable instructions stored in the memory, so that the electronic device implements the method described in the first aspect.

[0061] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions. When a processor executes the computer-executable instructions, the method described in the first aspect is implemented.

[0062] In a fifth aspect, an embodiment of the present application further provides a computer program product, comprising a computer program, which implements the method described in the first aspect when executed by a processor.

[0063] The word line resistance testing method, apparatus, device, storage medium, and program product provided in the embodiments of the present application write first data, such as corresponding to digital signal 1, into a storage cell connected to a word line, and read the data stored in the storage cell after the word line is activated for a preset time. Because the preset time is less than the corresponding standard row address strobe time (tRAS), the word line activation time is relatively short. If the read data is the first data to be written, the resistance of the word line is determined to be qualified. Specifically, if the read data is the first data, the resistance of the word line is qualified; otherwise, it is unqualified. By using a shorter word line activation time when writing data, the word line resistance is tested, with low test cost and high accuracy. The word line resistance test effectively avoids DRAM read and write failures due to excessively large word line resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the embodiments of the present application, and together with the description, are used to explain the principles of the embodiments of the present application.

[0065] Figure 1 This is a schematic diagram of a DRAM layout provided in an embodiment of the present application;

[0066] Figure 2 is a schematic diagram of a memory cell of a DRAM provided in an embodiment of the present application;

[0067] Figure 31 is a flow chart of a word line resistance testing method provided in an embodiment of the present application;

[0068] Figure 4 A flow chart of another word line resistance testing method provided in an embodiment of the present application;

[0069] Figure 5 A circuit diagram of a DRAM provided in an embodiment of the present application;

[0070] Figure 6 For this application Figure 4 The working timing diagram of writing first data provided by the illustrated embodiment;

[0071] Figure 7 A flowchart of a method for testing resistance of multiple word lines provided in an embodiment of the present application;

[0072] Figure 8 A flow chart of another word line resistance testing method provided in an embodiment of the present application;

[0073] Figure 9 1 is a structural diagram of a word line resistance testing device provided in an embodiment of the present application;

[0074] Figure 10 This is a structural block diagram of an electronic device provided in an embodiment of the present application.

[0075] The above drawings illustrate specific embodiments of the present invention, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the present invention in any way, but rather to illustrate the concepts of the present invention for those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0076] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numbers in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible implementations consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present invention, as detailed in the appended claims.

[0077] Figure 1 is a schematic diagram of a DRAM layout provided in an embodiment of the present application. Figure 2 Schematic diagram of a DRAM memory cell provided by an embodiment of the present application. Figure 1 and Figure 2 As shown, DRAM is provided with a corresponding number of bit lines (such as Figure 1 BL1 to BLM) and word lines (such as Figure 1 WL1 to WLN in the figure), the bit lines and word lines are crossed in batches, and a memory cell is formed at each intersection (such as Figure 1 P11 to PMN in the memory cell form a memory array, wherein each memory cell stores at least one bit of data.

[0078] In a DRAM integrated circuit device, the memory array is typically arranged in rows and columns so that a particular memory cell can be addressed by specifying its row and column of the array.

[0079] Reference Figure 2 The memory cell 10 includes a storage capacitor 11 and a transistor 12. The storage capacitor 11 is used to store charge. The drain of the transistor 12 is connected to the storage capacitor 11. The transistor 12 is used to access the storage capacitor 11 and can read the charge stored in the storage capacitor 11 or store new charge in the storage capacitor 11. The bit line BL is connected to the source of the transistor 12 and can read the charge stored in the storage capacitor 11 or provide capacitance when writing a new value to the storage capacitor 11. The word line WL is connected to the gate of the transistor 12. The voltage signal on the word line WL is used to control the opening or closing of the transistor 12, thereby controlling access to the storage capacitor 11, that is, reading the information stored in the storage capacitor 11 through the bit line BL, or writing information into the storage capacitor 11 for storage through the bit line BL.

[0080] It should be noted that the source of the transistor 12 may also be connected to the storage capacitor 11 , and correspondingly, the drain of the transistor 12 is connected to the bit line BL.

[0081] With the advancement of process technology, the size of memory chips, such as DRAM, is shrinking. The problem of DRAM read and write failure due to the large word line WL resistance is becoming more and more prominent. The method of only using low-resistance materials to improve the word line WL resistance or adding additional voltage to produce a larger read and write current has limited effect on improving the DRAM yield. In order to ensure the reliability of DRAM read and write operations and improve the DRAM yield, the present application provides a word line resistance testing method, which determines whether the word line resistance is qualified through testing, thereby effectively avoiding the DRAM from working when the word line resistance is large and improving the DRAM yield.

[0082] Figure 3 FIG. 1 is a flow chart of a word line resistance testing method provided by an embodiment of the present application. Figure 3 As shown, the word line resistance testing method includes the following steps S301 to S302.

[0083] S301, writing first data into a storage cell connected to a word line to be tested, and reading data stored in the storage cell after the word line to be tested is activated for a preset time, wherein the preset time is less than a standard row address activation time corresponding to the storage cell.

[0084] The word line to be tested may be any one or more word lines WL in the DRAM.

[0085] Before testing, the data stored in the memory cell connected to the word line to be tested is the second data. The second data is different from the first data. If the first data is a digital signal "1", the second data is a digital signal "0". If the first data is a digital signal "0", the second data is a digital signal "1". For ease of description, the following embodiments use the example of the first data being "1" and the second data being "0".

[0086] The standard row address activation time corresponding to a memory cell is the default setting of the DRAM for writing data to the corresponding memory cell after the word line is activated. The preset time is any period of time that is less than the standard row address activation time.

[0087] In some embodiments, the preset time may be 5-20 ns, such as 10 ns.

[0088] In some embodiments, the preset time may be a product of the row standard address activation time and a first coefficient that is less than 1 and greater than 0. The first coefficient may be 0.3, 0.5, 0.8, or the like.

[0089] Specifically, the preset time may be determined based on the row address activation time tRAS corresponding to successful read / write operations in the DRAM historical time period, for example, the preset time may be determined as the product of the average value of tRAS corresponding to successful read / write operations in the DRAM historical time period and the first coefficient.

[0090] Specifically, when writing the first data into the memory cell, the memory cell needs to be activated first, and then the write operation is performed on the memory cell. Activating the memory cell includes activating the word line WL and the bit line BL corresponding to the memory cell.

[0091] To facilitate the test of word line resistance, the bit line corresponding to the word line to be tested can be set to remain open through DFT (Design for Test) technology, so that the first data can be directly written to the corresponding memory cell after the word line to be tested is opened.

[0092] S302 : Determine whether the resistance of the word line to be tested is qualified according to the data stored in the storage unit.

[0093] If the data stored in the read memory cell is the first data, the resistance of the word line to be tested is determined to be qualified; otherwise, that is, the data read is the second data, the resistance of the word line to be tested is determined to be unqualified, specifically, the resistance of the word line to be tested is too large.

[0094] The above test process can be performed on each word line of the DRAM by traversing each word line as a word line to be tested, thereby determining whether the resistance of each word line of the DRAM is qualified.

[0095] The word line resistance testing method provided in this embodiment writes first data, such as corresponding to digital signal 1, into a memory cell connected to a word line. After the word line is activated for a preset time, the data stored in the memory cell is read. Because the preset time is shorter than the corresponding standard row address strobe time (tRAS), the word line activation time is relatively short. The word line resistance is determined to be qualified based on whether the read data is the first data to be written. Specifically, if the read data is the first data, the word line resistance is qualified; otherwise, it is unqualified. By using a shorter word line activation time when writing data, word line resistance testing is achieved with low testing cost and high accuracy. The word line resistance test effectively avoids DRAM read and write failures due to excessively large word line resistance.

[0096] In some embodiments, writing first data into a memory cell connected to a word line to be tested, and reading data stored in the memory cell after the word line to be tested is activated for a preset time, includes:

[0097] An activation instruction is issued to activate the word line to be tested, and first data is written into a storage unit connected to the word line to be tested; and data stored in the storage unit is read a preset time after the activation instruction is issued.

[0098] The activation instruction (ACT, Activate), specifically a word line activation instruction, is used to activate a word line, thereby activating a memory cell corresponding to the word line, so as to perform read and write operations on the memory cell.

[0099] After issuing the activation instruction ACT, there is no need to wait for a complete cycle corresponding to the standard tRAS. Instead, after a preset time less than the standard tRAS, the corresponding storage unit is read to read the data stored in the storage unit, and the resistance of the word line to be tested is tested based on the read data.

[0100] In some embodiments, issuing an activation instruction to activate the word line to be tested and writing first data into a memory cell connected to the word line to be tested includes:

[0101] When the bit line corresponding to the memory cell connected to the word line to be tested remains open, an activation instruction is issued to activate the word line to be tested, and first data is written into the memory cell connected to the word line to be tested.

[0102] The bit line remains open, maintaining the level corresponding to when the first data is written. For example, if the first data is "1," the corresponding bit line remains high. This eliminates the need to open the bit line during testing; the word line can be directly opened to write the first data to the corresponding memory cell, simplifying the test process and improving test efficiency.

[0103] In some embodiments, the activation instruction when writing data to the storage unit is a falling edge valid instruction, and the activation instruction when reading data stored in the storage unit is a rising edge valid instruction.

[0104] Figure 4 A flow chart of another word line resistance testing method provided in an embodiment of the present application. Figure 3 Based on the embodiment shown, step S301 is further refined, and steps related to second data writing, test mode start and test exit are added before step S301. Figure 4 As shown, the word line resistance testing method includes the following steps S401 to S406.

[0105] S401 , writing second data into a memory cell connected to a word line to be tested, and closing the word line to be tested.

[0106] To ensure the accuracy of the resistance test results, before the test, the memory cells corresponding to the word lines to be tested are written with data different from the data written during the test process, that is, a second data, such as "0", is written. After the writing is completed, the word lines to be tested are closed and precharged to prepare for subsequent writing. The test process includes steps S402 to S406.

[0107] In some embodiments, second data, such as “0”, may be written into each memory cell connected to the word line to be tested.

[0108] S402 , starting a test mode: maintaining a bit line precharge voltage between a bit line corresponding to the memory cell and a reference bit line at a preset voltage, so as to enable the bit line corresponding to the memory cell and turn off a sense amplifier corresponding to the memory cell.

[0109] After the second data is written, the word line to be tested is closed and pre-charge is completed, the test mode is activated or turned on. In this test mode, the memory cell corresponding to the word line to be tested, that is, the memory cell written with the second data, is closed; the bit line pre-charge voltage (BL Pre-charge Voltage) V BLP is the preset voltage, such as the maximum voltage V ary , so that the corresponding bit line remains open, that is, in the "1" state.

[0110] In some embodiments, starting the test mode further includes:

[0111] The row address activation time timer corresponding to the word line to be tested is turned off; and the activation instruction when reading and writing data to the storage unit is set to a falling edge valid instruction.

[0112] By disabling the row address activation timer (tRAS timer) inside the memory chip, the opening time of the word line to be tested can be controlled according to the set preset time, and the preset time can be flexibly configured to realize the test of various types of DRAM word line resistance.

[0113] S403 , after the test mode is turned on, issuing an activation instruction to activate the word line to be tested, and writing first data into a memory cell connected to the word line to be tested.

[0114] Figure 5 The circuit diagram of the DRAM provided in the embodiment of the present application is as follows: Figure 5 As shown, the DRAM includes a memory cell 10, an equalizer BLEQ, a sense amplifier SA, a bit line selector module 20, a bit line BL, a reference bit line / BL, and a word line WL. The equalizer BLEQ is located between the bit line BL and the reference bit line / BL and is used to provide an equalizing voltage to restore the bit line BL and the reference bit line / BL to the same potential. The bit line selector module 20 is used to rotate the bit line BL for read and write operations and control whether the bit line is turned on or off. The sense amplifier SA is used to amplify small voltage changes on the bit line BL during the process of reading data from the memory cell and convert them into digital signals.

[0115] When V BLP When the voltage is preset, the bit line BL is in a high level state, that is, the state is "1", so after the activation instruction is issued to open the word line to be tested, that is, after the word line WL is opened, data "1" can be written into the memory cell 10.

[0116] The word line to be tested is turned on, thereby turning on the memory cell connected to the test word line, so that the data in the memory cell is shared with the potential of the bit line BL. Since the potential on the reference bit line / BL is a preset voltage, the data stored in the memory cell 10 is 0, so that the potential of the bit line BL is lower than the potential on the reference bit line / BL, and the voltage difference between the bit line BL and the reference bit line / BL is the highest potential Vary, thereby realizing the writing of the first data "1" into the memory cell 10.

[0117] Figure 6 For this application Figure 4 The working timing diagram of writing the first data provided by the embodiment shown is as follows: Figure 6 As shown, while maintaining V BLP It is a preset voltage, that is, in the "1" state, the bit line BL remains at "1", the reference bit line / BL remains at "0", and an activation instruction ACT is issued to turn on the word line to be tested (word line WL). After the word line to be tested is turned on (WL ON), the sensitive amplifier is turned off. Since the activation time of the word line to be tested is the preset time, which is shorter than its corresponding standard tRAS, the time for the word line to be tested to be turned on is shorter, so it enters the pre-charge state (PRE), and the word line to be tested is turned off (WL OFF). When the resistance of the word line to be tested is large, the written data "1" may not be written into the corresponding storage unit, resulting in the subsequent read data not being "1".

[0118] S404 , exiting the test mode: turning on the sense amplifier corresponding to the memory cell, and canceling the maintenance of the bit line precharge voltage at the preset voltage.

[0119] After the first data is written, the test mode is exited, the sense amplifier SA is turned on, and the bit line precharge voltage is canceled from being maintained at the preset voltage, so as to facilitate subsequent read operations.

[0120] In some embodiments, exiting the test mode further comprises:

[0121] The row address activation time timer corresponding to the word line to be tested is started; and the activation instruction when reading and writing data to the storage unit is set to a rising edge valid instruction.

[0122] S405: Read the data stored in the storage unit at a preset time after the activation instruction is issued.

[0123] S406 , determining whether the resistance of the word line to be tested is qualified according to the data stored in the storage unit.

[0124] In this embodiment, "1" is written into the storage cell corresponding to the word line to be tested when the test mode is turned on, and then the test mode is turned off, and the data in the storage cell written with "1" is read to see if it is "1". If not, it is determined that the resistance of the word line to be tested is too large, that is, the resistance is unqualified. The test complexity is low, and it is easy to implement and highly portable.

[0125] Figure 7 A flowchart of a method for testing resistance of multiple word lines provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, taking the memory chip including n word lines to be tested as an example, i.e., the 1st to nth word lines, the following loop can be used to traverse the n word lines of the memory chip to implement the test of the resistance of the n word lines:

[0126] S701, obtaining the next word line to be tested.

[0127] S702 , turning on the word line to be tested and writing “0” into all the memory cells connected to the word line to be tested, and then turning off the word line to be tested.

[0128] S703, turn on the test mode: maintain the bit line pre-charge voltage between the bit line corresponding to the storage cell and the reference bit line at a preset voltage to make the bit line corresponding to the storage cell; turn off the sensitive amplifier corresponding to the storage cell; turn off the row address activation time timer; set the activation instruction when reading and writing data to the storage cell to a falling edge valid instruction.

[0129] S704 , opening the word line to be tested again, and writing “1” into all the memory cells connected to the word line to be tested, with the precharge time being a preset time.

[0130] S705, exit the test mode: turn on the sense amplifier corresponding to the memory cell, cancel maintaining the bit line precharge voltage at the preset voltage; turn on the row address activation time timer; set the activation instruction when reading and writing data to the memory cell to a rising edge valid instruction.

[0131] S706 , reading data in a memory cell connected to the word line.

[0132] S707 , determining whether the resistance of the word line is qualified based on the read data in the memory cell connected to the word line.

[0133] If the data read from the memory cells connected to the word line are all "1", the word line resistance is qualified. If the data read from at least one memory cell connected to the word line is "0", the word line resistance is unqualified.

[0134] Steps S701 to S707 are executed in a loop until all the word lines to be tested of the memory chip are tested.

[0135] In this embodiment, resistance testing of multiple word lines to be tested in a memory chip is achieved by traversing multiple word lines to be tested.

[0136] In some embodiments, the word lines to be tested include multiple word lines of a memory chip, and the method further includes:

[0137] The memory chip test report is generated and outputted according to the word lines with unqualified resistance among the plurality of word lines.

[0138] Specifically, a test report for the memory chip can be generated based on the position of the word line with unqualified resistance in the corresponding array, so that relevant personnel can quickly locate the unqualified word line based on the visual test report, thereby improving the efficiency of word line maintenance.

[0139] Figure 8 This is a flow chart of another word line resistance testing method provided in an embodiment of the present application. This embodiment is aimed at the scenario where the bit lines to be tested are multiple bit lines of a memory chip. Figure 3 Based on the embodiment shown, step S301 and step S302 are further refined to implement multiple tests corresponding to multiple different preset times to determine the abnormal level of the bit line resistance, and to add a step of outputting a test report after step S302. Figure 8 As shown, the word line resistance testing method includes the following steps S801 to S805.

[0140] S801 , issuing at least two activation instructions at intervals, and writing first data into memory cells of a word line to be tested at least twice.

[0141] The activation instructions are both used to activate the word line to be tested, and the preset times corresponding to the activation instructions of at least two activation instructions are different.

[0142] In some embodiments, at least two activation instructions may have corresponding activation instructions with the same preset time, for example, the activation times corresponding to the activation instructions may be 5ns, 10ns, 15ns, 5ns, 10ns, and 15ns, respectively.

[0143] Exemplarily, the number of activation instructions may be 3, 5, or another number.

[0144] In some embodiments, the preset times corresponding to the activation instructions may form an arithmetic progression, or may be other irregular progressions, which is not limited in this application.

[0145] S802 : For each activation instruction, read the data stored in the storage unit at a preset time after the activation instruction is issued.

[0146] S803: If the data in the storage unit read after the preset time corresponding to at least one activation instruction is issued is the second data, it is determined that the resistance of the word line to be tested is unqualified.

[0147] By performing multiple tests on word line resistance based on multiple activation instructions and using different preset times for the tests, the accuracy of the word line resistance test is improved.

[0148] In some embodiments, the method further comprises:

[0149] The abnormality level of the resistance of the word line to be tested is determined according to data in the storage unit read after a preset period corresponding to each activation instruction of the at least two activation instructions is issued.

[0150] If the preset time corresponding to the activation instructions issued in chronological order shows a decaying trend, the abnormal level of the word line resistance to be tested can be determined based on the preset time corresponding to the first time the test result of the word line resistance to be tested is unqualified, or the maximum value of the preset times when the test result of the word line resistance to be tested is unqualified, which is recorded as the maximum abnormal preset time.

[0151] The longer the preset time corresponding to the first failure, or the longer the corresponding maximum abnormal preset time, the higher the abnormality level of the word line resistance to be tested.

[0152] The word lines to be tested are sorted according to abnormality levels of resistance of the word lines to be tested, so that the word lines to be tested are replaced in sequence based on the sorting results.

[0153] By setting the abnormality level, word lines can be sorted based on the abnormality level. Therefore, when there are a large number of unqualified word lines, the word lines that have a greater impact on DRAM can be replaced first based on the sorting results, thereby improving the quality of DRAM maintenance.

[0154] Corresponding to the above method embodiment, Figure 9 Schematic diagram of a word line resistance test device provided in an embodiment of the present application. Figure 9 As shown, the word line resistance testing device includes: a read / write module 910 and a resistance testing module 920 .

[0155] Among them, the read-write module 910 is used to write the first data into the storage cell connected to the word line to be tested, and read the data stored in the storage cell after the word line to be tested is activated for a preset time, wherein the preset time is less than the standard row address activation time corresponding to the storage cell; the resistance testing module 920 is used to determine whether the resistance of the word line to be tested is qualified based on the data stored in the storage cell.

[0156] In some implementations, the reader / writer module 910 includes:

[0157] a first data writing unit, configured to issue an activation instruction to activate the word line to be tested, and write first data into a storage unit connected to the word line to be tested;

[0158] The data reading module unit is used to read the data stored in the storage unit at a preset time after the activation instruction is issued.

[0159] In some implementations, the first data writing unit is specifically configured to:

[0160] When the bit line corresponding to the memory cell connected to the word line to be tested remains open, an activation instruction is issued to activate the word line to be tested, and first data is written into the memory cell connected to the word line to be tested.

[0161] In some embodiments, the apparatus further comprises:

[0162] The bit line holding module is used to turn off the sensitive amplifier corresponding to the storage unit; maintain the bit line precharge voltage between the bit line corresponding to the storage unit and the reference bit line at a preset voltage, so that the bit line corresponding to the storage unit remains open.

[0163] In some embodiments, the apparatus further comprises:

[0164] The cancellation module is used to turn on the sense amplifier corresponding to the storage unit before reading the data stored in the storage unit; and cancel the maintenance of the bit line pre-charge voltage at the preset voltage.

[0165] In some embodiments, the apparatus further comprises:

[0166] The storage unit initialization module is used to write second data into the storage unit connected to the word line to be tested and close the word line to be tested before issuing the activation instruction.

[0167] In some embodiments, the method further comprises:

[0168] The timer closing module is used to close the row address activation time timer corresponding to the word line to be tested before issuing the activation instruction.

[0169] In some implementations, the data reading module is specifically configured to:

[0170] At least two activation instructions are issued at intervals, and the first data is written into the storage unit at least twice, wherein the preset times corresponding to the at least two activation instructions are different.

[0171] Accordingly, the resistance testing module 920 is specifically configured to:

[0172] If the data in the storage unit read after the preset time corresponding to the issuance of at least one activation instruction is the second data, it is determined that the resistance of the word line to be tested is unqualified.

[0173] In some embodiments, the apparatus further comprises:

[0174] The abnormality level determination module is used to determine the abnormality level of the word line resistance to be tested according to the data in the storage unit read after the corresponding preset period of time of each activation instruction in the at least two activation instructions.

[0175] In some embodiments, the word lines to be tested include multiple word lines of a memory chip, and the apparatus method further includes:

[0176] A test report output module is used to generate and output the memory chip test report according to the word lines with unqualified resistance among the multiple word lines.

[0177] The above device embodiment is an embodiment corresponding to the above method embodiment and has the same technical effects as the method embodiment. The detailed description of the device embodiment can refer to the detailed description of the above method embodiment and will not be repeated here.

[0178] An embodiment of the present application also provides an electronic device, including: at least one processor and a memory.

[0179] The memory stores computer-executable instructions.

[0180] The at least one processor executes the computer-executable instructions stored in the memory, so that the electronic device implements the above-mentioned word line resistance testing method.

[0181] Figure 10 10 is a block diagram of an electronic device provided in an embodiment of the present application. The electronic device includes a memory 1010 and at least one processor 1020.

[0182] The memory 1010 stores computer-executable instructions.

[0183] At least one processor 1020 executes the computer-executable instructions stored in the memory 1010 , so that the electronic device implements the aforementioned word line resistance testing method.

[0184] The memory 1010 and the processor 1020 are connected via a bus 1030 .

[0185] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions. When a processor executes the computer-executable instructions, the processor implements the word line resistance testing method provided in any embodiment of the present application.

[0186] An embodiment of the present application further provides a computer program product, including a computer program, which, when executed by a processor, implements the word line resistance testing method provided in any embodiment of the present application.

[0187] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0188] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0189] The above are only preferred embodiments of the embodiments of the present application, and do not limit the patent scope of the embodiments of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of the embodiments of the present application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the embodiments of the present application.

Claims

1. A word line resistance testing method, characterized in that: include: Writing first data into a memory cell connected to a word line to be tested, and reading data stored in the memory cell after the word line to be tested is activated for a preset time, wherein the preset time is less than a standard row address activation time corresponding to the memory cell; determining whether the resistance of the word line to be tested is qualified according to whether the data stored in the read storage unit is the first data; Writing first data into a memory cell connected to a word line to be tested, and reading data stored in the memory cell after the word line to be tested is activated for a preset time, comprising: issuing an activation instruction to activate the word line to be tested, and writing first data into a storage unit connected to the word line to be tested; Reading the data stored in the storage unit at a preset time after issuing the activation instruction; Issuing an activation instruction to activate the word line to be tested, and writing first data into a storage unit connected to the word line to be tested, comprises: When the bit line corresponding to the memory cell connected to the word line to be tested remains open, an activation instruction is issued to activate the word line to be tested, and first data is written into the memory cell connected to the word line to be tested.

2. The method according to claim 1, characterized in that The method further comprises: turning off the sense amplifier corresponding to the storage unit; A bit line precharge voltage between the bit line corresponding to the memory cell and a reference bit line is maintained at a preset voltage, so that the bit line corresponding to the memory cell remains open.

3. The method according to claim 2, characterized in that Before reading the data stored in the storage unit, the method further includes: Turning on the sense amplifier corresponding to the storage unit; The bit line precharge voltage is maintained at the preset voltage.

4. The method according to claim 1, wherein Before issuing the activation instruction, the method further includes: Second data is written into a memory cell connected to a word line to be tested, and the word line to be tested is turned off.

5. The method according to claim 1, wherein Before issuing the activation instruction, the method further includes: The row address activation time timer corresponding to the word line to be tested is turned off.

6. The method according to claim 1, characterized in that The activation instruction when writing data to the storage unit is a falling edge valid instruction, and the activation instruction when reading data stored in the storage unit is a rising edge valid instruction.

7. The method according to claim 1, characterized in that Issuing an activation instruction to write first data into a memory cell connected to a word line to be tested includes: issuing at least two activation instructions at intervals, and writing the first data into the storage unit at least twice, wherein the preset times corresponding to the at least two activation instructions are different; Determining whether the resistance of the word line to be tested is qualified according to the data stored in the memory cell includes: If the data in the storage unit read after the preset time corresponding to the issuance of at least one activation instruction is the second data, it is determined that the resistance of the word line to be tested is unqualified.

8. The method according to claim 7, characterized in that The method further comprises: The abnormality level of the resistance of the word line to be tested is determined according to data in the storage unit read after a preset period corresponding to each activation instruction of the at least two activation instructions is issued.

9. The method according to any one of claims 1 to 8, characterized in that The word lines to be tested include multiple word lines of a memory chip, and the method further includes: The memory chip test report is generated and outputted according to the word lines with unqualified resistance among the plurality of word lines.

10. A word line resistance testing device, characterized in that: include: a read / write module, configured to write first data into a storage cell connected to a word line to be tested, and read the data stored in the storage cell after the word line to be tested is activated for a preset time, wherein the preset time is less than a standard row address activation time corresponding to the storage cell; Writing first data into a memory cell connected to a word line to be tested, and reading data stored in the memory cell after the word line to be tested is activated for a preset time, comprising: issuing an activation instruction to activate the word line to be tested, and writing first data into a storage unit connected to the word line to be tested; Reading the data stored in the storage unit at a preset time after issuing the activation instruction; Issuing an activation instruction to activate the word line to be tested, and writing first data into a storage unit connected to the word line to be tested, comprises: In a state where a bit line corresponding to a memory cell connected to a word line to be tested remains open, issuing an activation instruction to activate the word line to be tested, and writing first data into the memory cell connected to the word line to be tested; The resistance testing module is used to determine whether the resistance of the word line to be tested is qualified according to whether the data stored in the read storage unit is the first data.

11. An electronic device, characterized in that: include: at least one processor and memory; The memory stores computer-executable instructions; The at least one processor executes the computer-executable instructions stored in the memory, so that the electronic device implements the method according to any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, and when a processor executes the computer-executable instructions, the method according to any one of claims 1 to 9 is implemented.

13. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.

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