A novel high-reliability GaN HEMT device and a preparation method thereof

Abstract

The application discloses a novel high-reliability GaN HEMT device and a preparation method thereof, and belongs to the technical field of semiconductor devices. The novel high-reliability GaN HEMT device comprises the following steps: providing a substrate; forming a nucleation layer, a transition layer and a barrier layer on one side surface of the substrate, and preparing a source electrode and a drain electrode on the side of the barrier layer away from the substrate; etching both ends of the barrier layer and the transition layer to form a mesa, and depositing an HfO2 film on the side of the source electrode, the drain electrode and the barrier layer away from the substrate to form an insulating dielectric layer; preparing a gate electrode on the side of the insulating dielectric layer away from the substrate; depositing a passivation layer on the side of the insulating dielectric layer and the gate electrode away from the substrate; after etching the surface of the passivation layer away from the substrate, depositing oxygen-doped semi-insulating polycrystalline silicon to form a gate field plate; the orthogonal projection of the gate field plate in the direction perpendicular to the plane where the substrate is located is approximately S-shaped; forming a protective layer on the side of the gate field plate and the passivation layer away from the substrate to obtain the prepared GaN HEMT device. The application can make the electric field distribution between the gate and the drain more uniform, thereby greatly improving the long-term reliability and breakdown efficiency of the device.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor power devices, and particularly relates to a novel high-reliability GaN HEMT device and a preparation method thereof. BACKGROUND

[0002] In recent years, the research on traditional Si-based devices has gradually approached the physical limit, and in order to further reduce the chip area, improve the breakdown voltage and reduce the on-resistance, GaN material has been widely used due to its advantages of large band gap, high breakdown field, radiation resistance and high temperature resistance.

[0003] The voltage resistance and reliability of the GaN-based HEMT device are often restricted by multiple factors. The electric field intensity near the drain of the GaN-based HEMT device reaches a peak value, and then the device is degraded under the action of long-time high-field stress, or even directly breaks down. In order to solve this problem, different types of field plate structures are used in the related technology to homogenize the drain-source electric field and reduce the peak electric field, so as to improve the breakdown voltage of the device.

[0004] However, the existing field plate structure is to connect a metal field plate at the drain end, and the field plate is located above the passivation layer. Such structure has certain limitations, especially for GaN material with high breakdown field strength, and its effect on the homogenization of the surface electric field is very limited. Therefore, improving the long-term reliability of the GaN HEMT device is still a problem to be solved by those skilled in the art. SUMMARY

[0005] In order to solve the above problems existing in the prior art, the application provides a novel high-reliability GaN HEMT device and a preparation method thereof. The technical problems to be solved by the application are solved by the following technical scheme:

[0006] In the first aspect, the application provides a preparation method of a novel high-reliability GaN HEMT device, comprising:

[0007] providing a substrate;

[0008] epitaxially growing AlN material on one side surface of the substrate to form a nucleation layer;

[0009] epitaxially growing GaN material on the side surface of the nucleation layer away from the substrate to form a transition layer;

[0010] epitaxially growing AlGaN material on the side surface of the transition layer away from the substrate to form a barrier layer, and preparing a source electrode and a drain electrode on the side of the barrier layer away from the substrate;

[0011] Etching both ends of the barrier layer and the transition layer to form a mesa, and depositing a HfO2 film on the side of the source, drain and barrier layer away from the substrate to form an insulating medium layer;

[0012] Preparing a gate on the side of the insulating medium layer away from the substrate;

[0013] Depositing a passivation layer on the side of the insulating medium layer and the gate away from the substrate; the orthogonal projection of the passivation layer in the direction perpendicular to the plane where the substrate is located coincides with the orthogonal projection of the barrier layer;

[0014] After etching the surface of the passivation layer away from the substrate, depositing oxygen-doped semi-insulating polysilicon to form a gate field plate; the orthogonal projection of the gate is located between the orthogonal projections of the source and the drain in the direction perpendicular to the plane where the substrate is located, the orthogonal projection of the gate field plate is approximately S-shaped, and the orthogonal projections of the first end and the second end of the gate field plate respectively overlap with the orthogonal projections of the gate and the drain;

[0015] Forming a protective layer on the side of the passivation layer and the gate field plate away from the substrate to obtain a prepared GaN HEMT device.

[0016] In an embodiment of the present application, the step of depositing a HfO2 film on the side of the source, drain and barrier layer away from the substrate to form an insulating medium layer comprises:

[0017] Preparation of the HfO2 film on the side of the source, drain and barrier layer away from the substrate by atomic layer deposition to form an insulating medium layer; the thickness of the HfO2 film in the direction perpendicular to the plane where the substrate is located is 20 nm.

[0018] In an embodiment of the present application, the step of depositing oxygen-doped semi-insulating polysilicon to form a gate field plate after etching the surface of the passivation layer away from the substrate comprises:

[0019] After making a mask on the surface of the passivation layer away from the substrate, etching is performed by inductively coupled plasma dry etching technology to form a groove;

[0020] Oxygen-doped semi-insulating polysilicon is deposited in the groove by electron beam evaporation technology to form a gate field plate.

[0021] In an embodiment of the present application, the first end of the gate field plate is electrically connected to the gate, and the second end of the gate field plate is electrically connected to the drain.

[0022] In an embodiment of the present application, the step of epitaxially growing an AlN material on the surface of the substrate to form a nucleation layer comprises:

[0023] The low-temperature AlN nucleation layer is epitaxially grown on one side surface of the substrate by metal organic compound chemical vapor deposition (MOCVD) technology, and the high-temperature AlN nucleation layer is epitaxially grown on the side surface of the low-temperature AlN nucleation layer away from the substrate.

[0024] The thickness of the low-temperature AlN nucleation layer is 30 nm in the direction perpendicular to the plane where the substrate is located, and the thickness of the high-temperature AlN nucleation layer is 170 nm.

[0025] In one embodiment of the present application, the step of epitaxially growing AlGaN material on the side surface of the transition layer away from the substrate to form the barrier layer comprises:

[0026] The undoped AlGaN barrier layer is deposited on the side surface of the transition layer away from the substrate by MOCVD technology with trimethylaluminum as the aluminum source, trimethylgallium as the gallium source and ammonia as the ammonia source. 0.2 Ga 0.8 The thickness of the barrier layer is 10 nm in the direction perpendicular to the plane where the substrate is located.

[0027] In a second aspect, the present application provides a novel high-reliability GaN HEMT device, which comprises:

[0028] a substrate;

[0029] a nucleation layer on one side of the substrate;

[0030] a transition layer on the side of the nucleation layer away from the substrate;

[0031] a barrier layer on the side of the transition layer away from the substrate;

[0032] a source electrode and a drain electrode on the side of the barrier layer away from the substrate, and the source electrode and the drain electrode are located at two ends of the barrier layer;

[0033] an insulating medium layer on the side of the barrier layer and the source electrode and the drain electrode away from the substrate;

[0034] a gate electrode on the side of the insulating medium layer away from the substrate;

[0035] a passivation layer on the side of the insulating medium layer away from the substrate;

[0036] a gate field plate on the side of the passivation layer away from the substrate; the orthographic projection of the passivation layer coincides with the orthographic projection of the barrier layer in the direction perpendicular to the plane where the substrate is located, the orthographic projection of the gate electrode is located between the orthographic projections of the source electrode and the drain electrode, the orthographic projection of the gate field plate is approximately S-shaped, and the orthographic projections of the first end and the second end of the gate field plate respectively overlap the orthographic projections of the gate electrode and the drain electrode.

[0037] A protective layer is located on the side of the passivation layer and the gate field plate away from the substrate.

[0038] Compared with the prior art, the present application has the following beneficial effects:

[0039] The present application provides a novel high-reliability GaN HEMT device and a preparation method thereof, which optimizes the surface electric field by using a resistance field plate, and the resistance field plate can prevent external harmful impurity ions from contaminating and mitigate the influence of ion-induced electric field on the electric field distribution of the device.

[0040] In addition, in the direction perpendicular to the plane where the substrate is located, the orthogonal projection of the gate field plate is approximately S-shaped, and such an approximately S-shaped field plate structure can make full use of the drift region area, thereby optimizing the electric field distribution of the entire channel, making the distribution of the electric field more uniform, and greatly improving the breakdown efficiency of the lateral device; on the other hand, the bending density of the S-shaped structure field plate can be modulated according to the actual channel electric field distribution, for example, the bending of the field plate is dense at the electric field peak, and the bending of the field plate is sparse at the electric field flat, so that the role of the field plate in uniformly distributing the channel electric field can be maximized, and the breakdown characteristics of the device are improved.

[0041] The present application will be further described in detail below with reference to the accompanying drawings and examples. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 is a flowchart of the preparation method of the novel high-reliability GaN HEMT device provided by the embodiment of the present application;

[0043] Figure 2 is a schematic diagram of the preparation method of the novel high-reliability GaN HEMT device provided by the embodiment of the present application;

[0044] Figure 3 is a schematic diagram of the preparation method of the novel high-reliability GaN HEMT device provided by the embodiment of the present application;

[0045] Figure 4 is a schematic diagram of the preparation method of the novel high-reliability GaN HEMT device provided by the embodiment of the present application;

[0046] Figure 5 is a schematic diagram of the preparation method of the novel high-reliability GaN HEMT device provided by the embodiment of the present application;

[0047] Figure 6 is a schematic diagram of the preparation method of the novel high-reliability GaN HEMT device provided by the embodiment of the present application;

[0048] Figure 7 is a schematic diagram of the preparation method of the novel high-reliability GaN HEMT device provided by the embodiment of the present application;

[0049] Figure 8 is a schematic diagram of a new high-reliability GaN HEMT device preparation method provided by an embodiment of the application;

[0050] Figure 9 is a schematic diagram of a new high-reliability GaN HEMT device preparation method provided by an embodiment of the application;

[0051] Figure 10 is a schematic diagram of a new high-reliability GaN HEMT device preparation method provided by an embodiment of the application;

[0052] Figure 11 is a schematic diagram of a new high-reliability GaN HEMT device preparation method provided by an embodiment of the application;

[0053] Figure 12 is a schematic diagram of a new high-reliability GaN HEMT device preparation method provided by an embodiment of the application;

[0054] Figure 13 is a schematic diagram of a new high-reliability GaN HEMT device preparation method provided by an embodiment of the application. DETAILED DESCRIPTION

[0055] The application will be further described in detail below with specific embodiments, but the embodiments of the application are not limited thereto.

[0056] Figure 1 is a flowchart of a new high-reliability GaN HEMT device and a preparation method thereof provided by an embodiment of the application, Figures 2-13 is a schematic diagram of a new high-reliability GaN HEMT device preparation method provided by an embodiment of the application. As shown in Figures 1-13 , the embodiment provides a preparation method of a new high-reliability GaN HEMT device, comprising:

[0057] S1, providing a substrate;

[0058] S2, epitaxially growing AlN material on one side surface of the substrate to form a nucleation layer;

[0059] S3, epitaxially growing GaN material on the side surface of the nucleation layer away from the substrate to form a transition layer;

[0060] S4, epitaxially growing AlGaN material on the side surface of the transition layer away from the substrate to form a barrier layer, and preparing a source electrode and a drain electrode on the side of the barrier layer away from the substrate;

[0061] S5, etching the two ends of the barrier layer and the transition layer to form a mesa, and depositing a HfO2 film on the side of the source, the drain and the barrier layer away from the substrate to form an insulating medium layer;

[0062] S6, preparing a gate on the side of the insulating medium layer away from the substrate;

[0063] S7, depositing a passivation layer on the side of the insulating medium layer and the gate away from the substrate; the orthogonal projection of the passivation layer in the direction perpendicular to the plane of the substrate coincides with the orthogonal projection of the barrier layer;

[0064] S8, after etching the surface of the passivation layer away from the substrate, depositing oxygen-doped semi-insulating polysilicon to form a gate field plate; the orthogonal projection of the gate is located between the orthogonal projections of the source and the drain in the direction perpendicular to the plane of the substrate, the orthogonal projection of the gate field plate is approximately S-shaped, and the orthogonal projections of the first end and the second end of the gate field plate respectively overlap with the orthogonal projections of the gate and the drain;

[0065] S9, forming a protective layer on the side of the passivation layer and the gate field plate away from the substrate to obtain a prepared GaN HEMT device.

[0066] Specifically, in the process of making the GaN HEMT device, first, a Si substrate is provided, and an AlN nucleation layer, a GaN transition layer and an AlGaN barrier layer are epitaxially grown on one side surface of the Si substrate in sequence; then, a mask is made on the barrier layer, and metal Ti / Al / Ni / Au is deposited on the barrier layer using electron beam evaporation technology, and ohmic contact is formed after rapid thermal annealing in N2, so that the source and the drain are prepared on the left and right ends of the barrier layer. Figure 2 In this embodiment, the Ti, Al, Ni and Au metals are arranged from bottom to top, and the thicknesses are 0.02 μm, 0.133 μm, 0.04 μm and 0.06 μm respectively.

[0067] Further, as shown in Figure 7 , a mask is made on the barrier layer, and the barrier layer and the transition layer on the left side of the source and the right side of the drain are etched using reactive ion etching technology to form a mesa. It should be noted that the etching depth in step S5 should be at least greater than the thickness of the barrier layer, Figure 7 Although only the case where the mesa is formed on the nucleation layer is shown in the above embodiment, in some other embodiments of the present application, the mesa can also be formed on the transition layer, which is not limited in the present application.

[0068] For example, the etching depth when making the mesa is 1.01 μm.

[0069] In steps S5-S6, HfO2 films are deposited above the source, drain and the barrier layer to form an insulating medium layer, and then a mask is formed above the insulating medium layer, and Ni / Au metal is deposited using electron beam evaporation technology to prepare a gate electrode, the orthographic projection of which in the direction perpendicular to the plane of the substrate is located between the orthographic projections of the source and drain. Optionally, the Ni metal is located on the side of the Au metal close to the substrate, i.e., the Ni metal is located on the lower layer and the Au metal is located on the upper layer, which not only ensures strong adhesion of the gate electrode, but also reduces the gate resistance and improves the frequency characteristics of the device.

[0070] Illustratively, the thickness of the Ni metal is 0.026 μm and the thickness of the Au metal is 0.11 μm in the direction perpendicular to the plane of the substrate.

[0071] In step S7, a 2-μm-thick SiN layer is deposited on the upper part of the gate electrode and the remaining area of the insulating medium layer using PECVD technology to form a passivation layer. It should be understood that the remaining area of the insulating medium layer refers to the area of the insulating medium layer other than the orthographic projection of the gate electrode in the direction perpendicular to the plane of the substrate. In addition, in order to ensure that the device surface is not damaged during the manufacturing process, a thin SiN passivation layer can be first deposited at a low power, and then a thick SiN passivation layer can be deposited at a high power.

[0072] In steps S8-S9, after etching the surface of the passivation layer away from the substrate, oxygen-doped semi-insulating polysilicon is deposited to form a gate field plate, the first end of which is located above the gate electrode and the second end of which is located above the drain electrode, and the first end is electrically connected to the gate electrode and the second end is electrically connected to the drain electrode. Further, in order to weaken the influence of the ambient atmosphere on the electrical characteristics of the gate field plate, an insulating medium material, which can be selectively SiO2, is deposited on the passivation layer and the gate field plate using PECVD technology to form a protective layer, and the thickness of the insulating medium material is 3.0 μm. Thus, a new high-reliability GaN HEMT power device shown in the figure can be obtained. Figure 13

[0073] It should be noted that the gate field plate is made of oxygen-doped semi-insulating polysilicon in the manufacturing process of the embodiment, and thus the field plate is a resistive field plate, which can prevent external harmful impurity ions from contaminating and mitigate the influence of ion-induced electric field on the electric field distribution of the device. In addition, since the gate field plate is in an approximate S shape, the approximate S-shaped field plate structure can make full use of the drift region area and thus optimize the electric field distribution of the entire channel, so that the electric field distribution is more uniform, greatly improving the breakdown efficiency of the lateral device. On the other hand, the bending density of the S-shaped structure field plate can be modulated according to the actual channel electric field distribution, for example, the bending of the field plate is dense at the peak of the electric field, and the bending of the field plate is sparse at the flat part of the electric field, so that the role of the field plate in uniformly distributing the channel electric field can be maximized, and the breakdown characteristics of the device are improved.​

[0074] As shown in Figure 3 , the step of epitaxially growing AlN material on one side surface of the substrate to form a nucleation layer in step S2 above comprises:

[0075] The low-temperature AlN nucleation layer is epitaxially grown on one side surface of the substrate by metal organic chemical vapor deposition (MOCVD) technology, and the high-temperature AlN nucleation layer is epitaxially grown on the side surface of the low-temperature AlN nucleation layer away from the substrate.

[0076] In the direction perpendicular to the plane where the substrate is located, the thickness of the low-temperature AlN nucleation layer is 30 nm, and the thickness of the high-temperature AlN nucleation layer is 170 nm.

[0077] Optionally, the transition layer as shown in Figure 4 is hetero-epitaxially grown in step S3 in a high-temperature hydrogen environment. The lateral epitaxial overgrowth (ELOG) technology can be used to obtain a GaN transition layer with low defect density. Exemplarily, in the direction perpendicular to the plane where the substrate is located, the thickness of the GaN transition layer is 1 μm.

[0078] As shown in Figure 5 , the step of epitaxially growing AlGaN material on the side surface of the transition layer away from the substrate to form a barrier layer in step S4 above comprises:

[0079] The undoped Al 0.2 Ga 0.8 N barrier layer is deposited on the side surface of the transition layer away from the substrate by MOCVD technology using trimethylaluminum as an aluminum source, trimethylgallium as a gallium source, and ammonia as an ammonia source. In the direction perpendicular to the plane where the substrate is located, the thickness of the barrier layer is 10 nm.

[0080] It should be noted that the ratio of the incorporated group III-V element impurities needs to be controlled in the above process.

[0081] As shown in Figure 8 , the step of depositing a HfO2 film on the side of the source, the drain, and the barrier layer away from the substrate to form an insulating medium layer in step S5 above comprises:

[0082] The HfO2 film is prepared on the side of the source, the drain, and the barrier layer away from the substrate by atomic layer deposition technology to form an insulating medium layer. In the direction perpendicular to the plane where the substrate is located, the thickness of the HfO2 film is 20 nm.

[0083] As shown in Figures 11-12 , the step of depositing oxygen-doped semi-insulating polysilicon to form a gate field plate after etching the side surface of the passivation layer away from the substrate in step S8 above comprises:

[0084] After making a mask on the side surface of the passivation layer far from the substrate, etching is performed by using a reactive ion etching technique to form a groove;

[0085] Oxygen-doped semi-insulating polysilicon is deposited in the groove by using an electron beam evaporation technique to form a gate field plate.

[0086] In this embodiment, a mask is first made on the side surface of the passivation layer far from the substrate, and then the passivation layer between the gate and the drain is etched by using a reactive ion etching technique to form a groove, wherein the depth of the groove is 0.14 μm, the width of the groove is 0.47 μm, and the length of the groove is 4.52 μm. The groove is curved from above the gate to above the drain, approximately in an S shape.

[0087] Next, oxygen-doped semi-insulating polysilicon is deposited in the groove to make a drain field plate. Specifically, oxygen-doped semi-insulating polysilicon is deposited in the groove by using an electron beam evaporation technique. The deposited semi-insulating polysilicon should completely fill the groove, and the first end of the gate field plate is placed above the gate and the second end is placed above the drain. To ensure that the gate field plate has a proper resistance value, the oxygen-doping amount of the semi-insulating polysilicon is determined by the actual length of the device. The oxygen content is generally between 0.3% and 20%, and preferably, the oxygen-doping amount is 0.5%.

[0088] It should be noted that the actual curved shape of the gate field plate can be flexibly adjusted according to the electric field distribution, for example, the field plate is curved densely at the peak of the electric field, and the field plate is curved sparsely at the flat electric field.

[0089] As shown in FIG. 1, the present embodiment also provides a novel high-reliability GaN HEMT device, which comprises: Figure 13

[0090] a substrate;

[0091] a nucleation layer located on one side of the substrate;

[0092] a transition layer located on the side of the nucleation layer far from the substrate;

[0093] a barrier layer located on the side of the transition layer far from the substrate;

[0094] a source and a drain located on the side of the barrier layer far from the substrate, and the source and the drain are located at two ends of the barrier layer;

[0095] an insulating dielectric layer located on the side of the barrier layer and the source and the drain far from the substrate;

[0096] a gate located on the side of the insulating dielectric layer far from the substrate;

[0097] a passivation layer located on the side of the insulating dielectric layer far from the substrate;

[0098] ​The gate field plate is located on the side of the passivation layer away from the substrate, and in the direction perpendicular to the plane in which the substrate is located, the orthogonal projection of the passivation layer coincides with the orthogonal projection of the barrier layer, the orthogonal projection of the gate electrode is located between the orthogonal projections of the source electrode and the drain electrode, the orthogonal projection of the gate field plate is approximately S-shaped, and the orthogonal projections of the first end and the second end of the gate field plate overlap with the orthogonal projections of the gate electrode and the drain electrode, respectively.

[0099] The protection layer is located on the side of the passivation layer and the gate field plate away from the substrate.

[0100] In the embodiment, the new high-reliability GaN HEMT device includes, from bottom to top, a substrate, a nucleation layer, a transition layer, a barrier layer, an insulating dielectric layer, a passivation layer, a gate field plate, and a protection layer. The source electrode and the drain electrode are located at two ends of the barrier layer, i.e., on the left and right sides of the insulating dielectric layer. The gate electrode is located on the side of the insulating dielectric layer away from the barrier layer. The source electrode and the drain electrode are led out through a contact hole. The first end of the gate field plate is located above the gate electrode, and the second end is located above the drain electrode and electrically connected to the drain electrode. The gate field plate is approximately S-shaped.

[0101] As can be seen from the above embodiments, the present application has the following beneficial effects:

[0102] The present application provides a new high-reliability GaN HEMT device and a preparation method thereof. The surface electric field is optimized by using a resistance field plate. The resistance field plate can prevent external harmful impurity ions from contaminating and mitigate the influence of ion-induced electric field on the electric field distribution of the device.

[0103] In addition, in the direction perpendicular to the plane in which the substrate is located, the orthogonal projection of the gate field plate is approximately S-shaped. This S-shaped field plate structure can make full use of the drift region area, thereby optimizing the electric field distribution of the entire channel, making the distribution of the electric field more uniform, and greatly improving the breakdown efficiency of the lateral device. On the other hand, the bending density of the S-shaped structure field plate can be adjusted according to the actual channel electric field distribution, for example, the bending of the field plate is dense at the peak of the electric field, and the bending of the field plate is sparse at the flat part of the electric field. In this way, the role of the field plate in uniformly distributing the channel electric field can be maximized, and the breakdown characteristics of the device can be improved.

[0104] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0105] Furthermore, the terms "first", "second", etc. are used herein only to describe different instances, and do not imply or suggest relative importance or a number of the indicated technical features. Thus, the features defined with "first", "second", etc. can include one or more of the features explicitly or implicitly. In the description of the present application, the meaning of "a plurality" is two or more, unless otherwise explicitly and specifically limited.

[0106] In the present application, unless otherwise explicitly specified and limited, "on" or "under" of a first feature to a second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, "on", "above" and "over" of a first feature to a second feature includes that the first feature is directly above and obliquely above the second feature, or only means that the first feature is horizontally higher than the second feature. "Under", "below" and "underneath" of a first feature to a second feature includes that the first feature is directly below and obliquely below the second feature, or only means that the first feature is horizontally lower than the second feature.

[0107] In the description of the present application, the description referring to the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in one or more embodiments or examples. In addition, a person skilled in the art can combine and integrate different embodiments or examples described in the present specification.

[0108] Although the present application is described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from the appended claims, the disclosure and the accompanying drawings. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite articles "a" or "an" do not exclude a plurality. A single processor or other unit can fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0109] The above is further detailed description of the present application in combination with specific preferred embodiments, and cannot be deemed as limitation of the specific implementation of the present application to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, and all of them shall be deemed as falling within the protection scope of the present application.

Claims

1. A method for fabricating a novel high-reliability GaN HEMT device, characterized in that, The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof.

2. The method of fabricating a novel high reliability GaN HEMT device according to claim 1, wherein, The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof.

3. The method of fabricating a novel high reliability GaN HEMT device according to claim 1, wherein, The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof.

4. The method of fabricating a novel high reliability GaN HEMT device according to claim 3, wherein, The application relates to a GaN HEMT device and a preparation method thereof.

5. The method of fabricating a novel high reliability GaN HEMT device according to claim 1, wherein, The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof.

6. The method of fabricating a novel high reliability GaN HEMT device according to claim 1, wherein, The application relates to a GaN HEMT device and a preparation method thereof. Using trimethylaluminum as the aluminum source, trimethylgallium as the gallium source, and ammonia as the ammonia source, undoped Al was deposited on the surface of the transition layer away from the substrate using MOCVD technology. 0.2 Ga 0.8 N-type barrier layer; wherein, along the direction perpendicular to the plane of the substrate, the thickness of the barrier layer is 10 nm.

7. A novel high reliability GaN HEMT device characterized by, The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. The application relates to a GaN HEMT device and a preparation method thereof. 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The application relates to a GaN H a source and a drain located on the side of the barrier layer away from the substrate, and the source and the drain are located at two ends of the barrier layer; an insulating medium layer located on the side of the barrier layer and the source and the drain away from the substrate; a gate located on the side of the insulating medium layer away from the substrate; a passivation layer located on the side of the insulating medium layer away from the substrate; a gate field plate located on the side of the passivation layer away from the substrate; in the direction perpendicular to the plane in which the substrate is located, the orthographic projection of the passivation layer coincides with the orthographic projection of the barrier layer, the orthographic projection of the gate is located between the orthographic projections of the source and the drain, the orthographic projection of the gate field plate is approximately S-shaped, and the orthographic projections of the first end and the second end of the gate field plate respectively overlap with the orthographic projections of the gate and the drain; a protective layer located on the side of the passivation layer and the gate field plate away from the substrate.

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