A method for preparing a ferroelectric 3D stacked gate-all-around transistor

Abstract

The present invention discloses a method for preparing a ferroelectric 3D stacked gate-all-around transistor, comprising the following steps: epitaxially growing multiple first Si layer / channel material layer / second Si layer stacked structures on a substrate, and forming an isolation layer between each first Si layer / channel material layer / second Si layer stacked structure; performing photolithography and etching on the first Si layer / channel material layer / second Si layer stacked structure to form a nanocolumn structure; performing atomic layer etching on the channel material to form a channel, and controlling the channel thickness by adjusting the etching depth; preparing a hafnium-based ferroelectric thin film around the channel by using an atomic layer deposition method and anisotropic etching, forming a metal electrode on the surface of the hafnium-based ferroelectric thin film, and controlling the channel length by adjusting the thickness of the hafnium-based ferroelectric thin film; and performing rapid thermal annealing in an N2 environment to transform the hafnium-based ferroelectric thin film into a ferroelectric phase, thereby obtaining a ferroelectric 3D stacked gate-all-around transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a ferroelectric 3D stacked ring-gate transistor. Background Art

[0002] Perovskite, as a ferroelectric material, requires a thickness of tens of nanometers to exhibit good ferroelectric properties. However, this thickness limits the scaling of memory cells, making them incompatible with mainstream CMOS technology. It wasn't until 2011 that TS Boscke discovered that HfO2-doped Si exhibits ferroelectricity. Subsequently, ferroelectric properties were observed when HfO2 was doped with elements such as Al, Zr, and La. Subsequently, FeFET research shifted to hafnium-based ferroelectric transistors, which are compatible with mainstream CMOS.

[0003] However, after integrated circuits enter the 5nm technology node, the gate length of logic devices will be miniaturized to below 18nm. However, FeFET is limited by the thickness of ferroelectric films. FinFET and GAA (gate all around) FeFET cannot be miniaturized synchronously with logic devices, which limits the increase in integration density and hinders the development of FeFTE memory. Summary of the Invention

[0004] The present invention discloses a method for preparing a ferroelectric 3D stacked gate-all-around transistor, comprising the following steps: epitaxially growing multiple first Si layer / channel material layer / second Si layer stacked structures on a substrate, and forming an isolation layer between each first Si layer / channel material layer / second Si layer stacked structure; performing photolithography and etching on the first Si layer / channel material layer / second Si layer stacked structure to form a nanocolumn structure; atomically etching the channel material layer to form a channel, and controlling the channel thickness by adjusting the etching depth; preparing a hafnium-based ferroelectric thin film around the channel by atomic layer deposition and anisotropic etching, forming a metal electrode on the surface of the hafnium-based ferroelectric thin film, and controlling the channel length by adjusting the thickness of the hafnium-based ferroelectric thin film; and performing rapid thermal annealing in an N2 atmosphere to transform the hafnium-based ferroelectric thin film into a ferroelectric phase, thereby obtaining a ferroelectric 3D stacked gate-all-around transistor.

[0005] In the preparation method of the ferroelectric 3D stacked ring-gate transistor of the present invention, preferably, the thickness of the first Si layer is 200-400 nm, the thickness of the channel material layer is 40-80 nm, and the thickness of the second Si layer is 120-160 nm.

[0006] In the method for preparing the ferroelectric 3D stacked gate-all-around transistor of the present invention, preferably, the temperature of the rapid thermal annealing treatment is 350° C. to 750° C., and the time is 30 seconds.

[0007] In the method for preparing the ferroelectric 3D stacked ring-gate transistor of the present invention, preferably, the channel material layer is SiGe, graphene or MoS2.

[0008] In the preparation method of the ferroelectric 3D stacked ring-gate transistor of the present invention, preferably, when the channel material layer is SiGe, the channel is oxidized by oxygen plasma to form a thin oxide layer as an interface layer before forming the hafnium-based ferroelectric film, so as to improve the interface quality and reduce the interface state density.

[0009] In the method for preparing the ferroelectric 3D stacked ring-gate transistor of the present invention, preferably, the isolation layer is SiO2, HfO2, ZrO2 or Al2O3.

[0010] In the method for preparing the ferroelectric 3D stacked gate-all-around transistor of the present invention, preferably, the channel thickness is 12 nm to 27 nm.

[0011] In the method for preparing the ferroelectric 3D stacked gate-all-around transistor of the present invention, preferably, the channel length is 40 to 80 nm. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a flow chart of a method for preparing a ferroelectric 3D stacked gate-all-around transistor.

[0013] Figures 2 to 5 It is a flow chart of the various stages of the method for preparing a ferroelectric 3D stacked gate-all-around transistor. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical solutions and advantages of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. The described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0015] In the description of the present invention, it should be noted that the terms "upper," "lower," "vertical," and "horizontal," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0016] In addition, many specific details of the present invention are described below, such as device structure, materials, dimensions, processing techniques, and technologies, to facilitate a clearer understanding of the present invention. However, as will be appreciated by those skilled in the art, the present invention may be practiced without following these specific details. Unless otherwise noted below, various components of the device may be constructed from materials known to those skilled in the art, or materials with similar functions developed in the future may be used.

[0017] Figure 1 This is a flow chart of the method for preparing a ferroelectric 3D stacked gate-all-around transistor. Figure 1 As shown, the method for preparing a ferroelectric 3D stacked gate-all-around transistor includes the following steps:

[0018] In step S1, multiple (cycles) of Si101 / MoS2102 / Si103 stacked structures are epitaxially grown on a Si substrate 100, and an isolation layer 104 such as SiO2, HfO2, ZrO2 and Al2O3 is formed between each of the Si101 / MoS2102 / Si103 stacked structures. The resulting structure is as shown in FIG. Figure 2 The number of layers in the 3D stack of the device can be determined based on the number of layers required. In this embodiment, MoS2 is used as the channel material, but the present invention is not limited thereto. Other materials include SiGe and graphene.

[0019] In step S2, the multi-layered Si101 / MoS2102 / Si103 structure is photolithographically and etched to form a nanopillar structure. Specifically, first, a photoresist is spin-coated on the surface of the structure, and an electron beam is used to etch out a specified shape; then, a reactive ion etching method (RIE) is used to etch out the nanopillar structure; finally, the photoresist is removed in acetone, and the resulting structure is as shown. Figure 3 shown.

[0020] In step S3, the MoS2102 layers are etched by atomic layer etching to form channels, so that the Si101 / MoS2102 / Si103 stacked structure is in the shape of an "I". The resulting structure is as follows: Figure 4 By adjusting the etching depth of the MoS2102 layer to control the channel thickness, preferably between 12nm and 27nm, this channel thickness range will effectively avoid the narrow channel effect of the device.

[0021] In step S4, an atomic layer deposition method and anisotropic etching are used to prepare a hafnium-based ferroelectric film 105 around the channel 102, and a metal electrode 106 is formed on its surface as a gate to achieve self-alignment between the gate and the channel. The resulting structure is as follows: Figure 5 By adjusting the thickness of the hafnium-based ferroelectric film, the channel length is controlled to be 40 to 80 nm, which effectively reduces the short channel effect of the device.

[0022] In step S5, a rapid thermal annealing treatment is performed in a nitrogen atmosphere to transform the hafnium-based ferroelectric thin film into a ferroelectric phase. The rapid thermal annealing treatment temperature is 500° C. and the time is 30 seconds to obtain a ferroelectric 3D stacked ring-gate transistor.

[0023] In another preferred embodiment, the difference from the above implementation is that the channel material is selected as SiGe, and step S6 is also included before step S4, in which a thin oxide layer is formed as an interface layer by oxidizing the channel by oxygen plasma before forming the hafnium-based ferroelectric film to improve the interface quality and reduce the interface state density.

[0024] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with this technical field within the technical scope disclosed in the present invention should be covered by the scope of protection of the present invention.

Claims

1. A method for preparing a ferroelectric 3D stacked gate-all-around transistor, characterized in that: The following steps are involved: Epitaxially growing multiple first Si layer / channel material layer / second Si layer stacked structures on a substrate, and forming an isolation layer between each of the multiple first Si layer / channel material layer / second Si layer stacked structures; Performing photolithography and etching on the first Si layer / channel material layer / second Si layer stacked structure to form a nano-column structure; Atomic layer etching of the channel material layer forms a channel, and the channel thickness is controlled by adjusting the etching depth; A hafnium-based ferroelectric film is prepared around the channel by atomic layer deposition and anisotropic etching, and a metal electrode is formed on the surface thereof. The channel length is controlled by adjusting the thickness of the hafnium-based ferroelectric film. Rapid thermal annealing treatment is performed in an N2 atmosphere to transform the hafnium-based ferroelectric film into a ferroelectric phase, thereby obtaining a ferroelectric 3D stacked ring-gate transistor.

2. The method for preparing a ferroelectric 3D stacked gate-all-around transistor according to claim 1, wherein: The thickness of the first Si layer is 200-400 nm, the thickness of the channel material layer is 40-80 nm, and the thickness of the second Si layer is 120-160 nm.

3. The method for preparing a ferroelectric 3D stacked gate-all-around transistor according to claim 1, wherein: The temperature of the rapid thermal annealing treatment is 350° C. to 750° C., and the time is 30 seconds.

4. The method for preparing a ferroelectric 3D stacked gate-all-around transistor according to claim 1, wherein: The channel material layer is SiGe, graphene or MoS2.

5. The method for preparing a ferroelectric 3D stacked gate-all-around transistor according to claim 4, wherein: When the channel material layer is SiGe, the channel material layer is oxidized by oxygen plasma before forming the hafnium-based ferroelectric film to form a thin oxide layer as an interface layer to improve interface quality and reduce interface state density.

6. The method for preparing a ferroelectric 3D stacked gate-all-around transistor according to claim 1, wherein: The isolation layer is SiO2, HfO2, ZrO2 or Al2O3.

7. The method for preparing a ferroelectric 3D stacked gate-all-around transistor according to claim 1, wherein: The channel thickness is 12nm to 27nm.

8. The method for preparing a ferroelectric 3D stacked gate-all-around transistor according to claim 1, wherein: The channel length is 40 to 80 nm.

Images