A packaging method and a package

Abstract

The application discloses a packaging method and a packaging body. The packaging method comprises the following steps: obtaining a to-be-processed plate, the to-be-processed plate comprising a packaging substrate, at least one first copper column and a first chip arranged on a first surface of the packaging substrate; forming a first insulating medium layer; the first insulating medium layer is arranged around the first copper column and covers the first chip and the first surface of the packaging substrate; attaching at least one second copper column and a second chip on a second surface of the packaging substrate; the second surface is arranged opposite to the first surface; forming a second insulating medium layer; the second insulating medium layer is arranged around the second copper column and covers the second chip and the second surface of the packaging substrate. The application solves the problem of poor heat dissipation performance in the existing stacked packaging structure.

Description

Technical Field

[0001] This application relates to the field of encapsulation technology, and in particular to an encapsulation method and an encapsulation body. Background Technology

[0002] With the development of 5G technology, electronic products are becoming increasingly feature-rich and smaller, placing higher demands on packaging and driving the PCB industry towards high density, high integration, and multi-layering. As IC (integrated circuit) packaging rapidly evolves towards high density, multi-functionality, and miniaturization, the current method of chip-flattened, few-layer stacked chip packaging can no longer meet the demands.

[0003] In the existing technology, most functional integrated module ICs adopt stacked packaging, whether it is PiP (package in package) or POP (package on package), which utilizes the vertical space of the IC package to achieve the requirements of high density, multi-functionality and miniaturization.

[0004] However, currently, chips with stacked packaging structures in the industry generally dissipate heat through epoxy resin, which has poor heat dissipation performance. Stacked packaging structures are prone to poor heat dissipation due to increased internal temperature, resulting in low reliability. Summary of the Invention

[0005] The main technical problem addressed by this application is to provide a packaging method and a package that can solve the problem of poor heat dissipation performance in existing stacked packaging structures.

[0006] To solve the above-mentioned technical problems, the first technical solution adopted in this application is to provide a packaging method, comprising: obtaining a substrate to be processed, the substrate including a packaging substrate and at least one first copper pillar and a first chip disposed on a first surface of the packaging substrate; obtaining a first insulating material, and pressing the first insulating material with the first surface of the packaging substrate, the first copper pillar and the first chip to form a first insulating dielectric layer; wherein the first insulating dielectric layer is located around the first copper pillar and covers the first chip and the first surface of the packaging substrate; attaching at least one second copper pillar and a second chip to a second surface of the packaging substrate; wherein the second surface is disposed opposite to the first surface; obtaining a second insulating material, and pressing the second insulating material with the second surface of the packaging substrate, the second copper pillar and the second chip to form a second insulating dielectric layer; wherein the second insulating dielectric layer is located around the second copper pillar and covers the second chip and the second surface of the packaging substrate.

[0007] The step of obtaining a first insulating material and pressing the first insulating material with the first surface of the packaging substrate, the first copper pillar, and the first chip to form a first insulating dielectric layer specifically includes: obtaining the first insulating material and pressing the first insulating material with the first surface of the packaging substrate, the first copper pillar, and the first chip, so that the first insulating material covers the side surface of the first copper pillar away from the first surface, the side surface of the first chip away from the first surface, and the first surface; grinding the first insulating material until the side surface of the first copper pillar away from the first surface is exposed to form a first insulating dielectric layer; wherein the first insulating dielectric layer is located around the first copper pillar and covers the first chip and the first surface of the packaging substrate.

[0008] The step of obtaining a second insulating material and pressing the second insulating material with the second surface of the packaging substrate, the second copper pillar, and the second chip to form a second insulating dielectric layer specifically includes: obtaining a second insulating material and pressing the second insulating material with the second surface of the packaging substrate, the second copper pillar, and the second chip, so that the second insulating material covers the side surface of the second copper pillar away from the second surface, the side surface of the second chip away from the second surface, and the second surface; grinding the second insulating material until the side surface of the second copper pillar away from the second surface is exposed to form a second insulating dielectric layer; wherein the second insulating dielectric layer is located around the second copper pillar and covers the second chip and the second surface of the packaging substrate.

[0009] The first insulating material and the second insulating material include one or more of epoxy resin, phenolic resin, polyimide, BT, ABF and ceramic matrix.

[0010] The step of obtaining the second insulating material and pressing the second insulating material with the second surface of the packaging substrate, the second copper pillar and the second chip to form the second insulating dielectric layer includes: plating tin or gold on the side surface of the first copper pillar away from the first surface and the side surface of the second copper pillar away from the second surface to form a tin oxide layer.

[0011] The step of plating tin or gold on the side of the first copper pillar away from the first surface and on the side of the second copper pillar away from the second surface to form a tin-plated layer includes: welding an inductor element on the side of the first copper pillar away from the first surface.

[0012] The step of welding the inductor on the side of the first copper pillar away from the first surface includes filling the side of the inductor in contact with the first copper pillar with conductive adhesive.

[0013] The step of filling conductive adhesive on the surface of the inductor that contacts the first copper pillar includes: implanting a ball on the surface of the second copper pillar that is away from the second surface.

[0014] The step of obtaining a substrate to be processed, which includes a packaging substrate and at least one first copper pillar and a first chip disposed on a first surface of the packaging substrate, specifically includes: obtaining a packaging substrate; the packaging substrate includes a first surface and a second surface disposed opposite to each other; obtaining at least one first copper pillar and a first chip; and attaching the first copper pillar and the first chip to the first surface of the packaging substrate to obtain the substrate to be processed.

[0015] To solve the above-mentioned technical problems, the second technical solution adopted in this application is to provide a package, including: a package substrate, the package substrate including a first surface and a second surface disposed opposite to each other; at least one first copper pillar and a first chip, the first copper pillar and the first chip being disposed on the first surface of the package substrate; a first insulating dielectric layer, the first insulating dielectric layer being located around the first copper pillar and covering the first chip and the first surface of the package substrate; an inductor element, the inductor element being disposed on the surface of the first copper pillar away from the first surface; at least one second copper pillar and a second chip, the second copper pillar and the second chip being disposed on the second surface of the package substrate; a second insulating dielectric layer, the second insulating dielectric layer being located around the second copper pillar and covering the second chip and the second surface of the package substrate; and a ball, the ball being disposed on the surface of the second copper pillar away from the second surface.

[0016] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides a packaging method and a package body. By attaching at least one first copper pillar and one second copper pillar respectively when mounting the first chip and the second chip, it ensures that the first insulating dielectric layer and the second insulating dielectric layer can respectively cover the first chip and the second chip, while exposing the surfaces of the first copper pillar and the second copper pillar away from the packaging substrate. This allows the first chip and the second chip to dissipate heat outward through the first copper pillar and the second copper pillar, thereby enhancing the heat dissipation performance of the stacked packaging structure and improving the reliability of the wafer. Furthermore, by packaging the chip on both sides, the vertical space of the package body can be utilized for layout, thereby achieving the requirements of miniaturized package size, high density, and multifunctionality. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating one embodiment of the packaging method of this application;

[0019] Figure 2This is a flowchart illustrating one embodiment of the method for obtaining the material to be processed in S11;

[0020] Figure 3 This is a schematic diagram of the structure of one embodiment of the plate material to be processed obtained in S11;

[0021] Figure 4 This is a schematic diagram of the structure of the substrate to be processed obtained after injection molding the first surface of the packaging substrate in S12;

[0022] Figure 5 This is a schematic diagram of the structure of one embodiment of the plate material to be processed obtained in S13;

[0023] Figure 6 This is a schematic diagram of the structure of the substrate to be processed obtained after injection molding the second surface of the packaging substrate in S14, according to one embodiment.

[0024] Figure 7 This is a schematic diagram of the structure of one embodiment of the plate to be treated after grinding;

[0025] Figure 8 This is a schematic diagram of one embodiment of a substrate to be processed on which inductive components are mounted.

[0026] Figure 9 This is a schematic diagram of one embodiment of the package of this application. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated above. “Multiple” generally includes at least two, but does not exclude the inclusion of at least one.

[0029] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0030] It should be understood that the terms "comprising," "including," or any other variations used herein are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0031] In existing technologies, most functional integrated circuit (IC) modules employ stacked packaging, whether it's PiP (package-in-package) or POP (package-on-package), utilizing the vertical space of the IC package to achieve high density, multifunctionality, and miniaturization. However, current industry practices typically rely on epoxy resin for heat dissipation, resulting in poor heat dissipation performance. Stacked packaging structures are prone to inadequate heat dissipation due to increased internal temperatures, leading to lower reliability.

[0032] Based on the above, this application provides a packaging method and a package body that can solve the problem of poor heat dissipation performance in existing stacked packaging structures.

[0033] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0034] Please see Figure 1 , Figure 1 This is a flowchart illustrating one embodiment of the encapsulation method of this application.

[0035] like Figure 1 As shown, in this embodiment, the method includes:

[0036] S11: Obtain the substrate to be processed, which includes a packaging substrate and at least one first copper pillar and a first chip disposed on the first surface of the packaging substrate.

[0037] In this embodiment, the first chip includes a semiconductor bonding chip.

[0038] The height of the first copper pillar along the packaging direction is greater than the height of the first chip along the packaging direction, so that one side surface of the first copper pillar can be ground out after packaging, thereby conducting heat vertically through the first copper pillar and enhancing the heat dissipation performance of the overall device.

[0039] In this embodiment, other electronic components, such as resistors and capacitors, are also mounted on the first surface of the packaging substrate. Here, resistors and capacitors refer to components consisting of resistors and capacitors.

[0040] Specifically, please refer to Figure 2 , Figure 2 This is a flowchart illustrating one embodiment of the method for obtaining the material to be processed in S11. For example... Figure 2 As shown, in this embodiment, the method includes:

[0041] S111: Obtain the packaging substrate; the packaging substrate includes a first surface and a second surface disposed opposite to each other.

[0042] In this embodiment, the packaging substrate includes an insulating layer (dielectric layer) and a copper layer. The insulating layer can cover the copper layer on one side or on both sides. In this embodiment, we will take the case where the insulating layer of the copper-clad laminate is covered with copper layers on both sides as an example.

[0043] S112: Obtain at least one first copper pillar and a first chip, and mount the first copper pillar and the first chip on the first surface of the packaging substrate to obtain the substrate to be processed.

[0044] In this embodiment, at least one first copper pillar, a first chip, and a resistive capacitor are obtained, and the first copper pillar, the first chip, and the resistive capacitor are mounted on the first surface of the packaging substrate.

[0045] Specifically, please refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of the material to be processed obtained in S11 according to one embodiment. For example... Figure 3 As shown, the substrate 100 to be processed includes a packaging substrate 10, which includes a first surface 101 and a second surface 102 disposed opposite to each other; a plurality of first copper pillars 21 and first chips 22, which are disposed on the first surface 101 of the packaging substrate 10.

[0046] The first surface 101 of the packaging substrate 10 is also provided with a first resistor 23 and a first capacitor 24.

[0047] S12: Obtain the first insulating material, and press the first insulating material with the first surface of the packaging substrate, the first copper pillar and the first chip to form a first insulating dielectric layer; wherein the first insulating dielectric layer is located around the first copper pillar and covers the first chip and the first surface of the packaging substrate.

[0048] In this embodiment, a first insulating material is obtained, and the first insulating material is pressed together with the first surface of the packaging substrate, the first copper pillar, and the first chip, so that the first insulating material covers the side surface of the first copper pillar away from the first surface, the side surface of the first chip away from the first surface, and the first surface.

[0049] The first insulating material includes one or more of epoxy resin, phenolic resin, polyimide, BT, ABF, and ceramic matrix.

[0050] Understandably, encapsulating the first surface of the packaging substrate, the first copper pillar, the first chip, and the resistive capacitor components using injection molding equipment can protect the first copper pillar, the first chip, and the resistive capacitor components.

[0051] Specifically, please refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of the substrate to be processed obtained after injection molding the first surface of the packaging substrate in S12, according to one embodiment. Figure 4 As shown, the substrate 200 to be processed includes a packaging substrate 10, which includes a first surface 101 and a second surface 102 disposed opposite to each other. A plurality of first copper pillars 21 and first chips 22 are disposed on the first surface 101 of the packaging substrate 10. A first resistor 23 and a first capacitor 24 are disposed on the first surface 101 of the packaging substrate 10. A first insulating material 30 covers the side surfaces of the first copper pillars 21, the first chip 22, the first resistor 23, and the first capacitor 24 that are away from the first surface 101, as well as the first surface 101 itself.

[0052] In this embodiment, a second copper pillar and a second chip are mounted on the second surface of the packaging substrate. After injection molding the second surface, the first insulating material on the first surface is ground until the side of the first copper pillar away from the first surface is exposed, thereby forming a first insulating dielectric layer. The first insulating dielectric layer is located around the first copper pillar and covers the first chip and the first surface of the packaging substrate.

[0053] Understandably, the height of the first copper pillar along the packaging direction is greater than the height of the first chip along the packaging direction. Therefore, the first insulating dielectric layer formed after grinding can still cover the first chip and the resistive and capacitive components to protect multiple components.

[0054] S13: At least one second copper pillar and a second chip are mounted on the second surface of the packaging substrate; wherein the second surface is disposed opposite to the first surface.

[0055] In this embodiment, the second chip includes an IC chip.

[0056] The height of the second copper pillar along the packaging direction is greater than that of the second chip along the packaging direction, so that one side surface of the second copper pillar can be ground out after packaging, thereby conducting heat vertically through the second copper pillar and enhancing the heat dissipation performance of the overall device.

[0057] In this embodiment, other electronic components, such as capacitors, are also mounted on the second surface of the packaging substrate.

[0058] Understandably, by mounting chips and copper pillars on both sides of the packaging substrate, the vertical space of the package can be utilized for layout, thereby achieving the requirements of miniaturized package size, high density, and multifunctionality.

[0059] Specifically, please refer to Figure 5 , Figure 5 This is a structural schematic diagram of an embodiment of the plate material to be processed obtained in S13. For example... Figure 5 As shown, the substrate 300 to be processed includes a packaging substrate 10, which includes a first surface 101 and a second surface 102 disposed opposite to each other. A plurality of first copper pillars 21 and first chips 22 are disposed on the first surface 101 of the packaging substrate 10. A first resistor 23 and a first capacitor 24 are disposed on the first surface 101 of the packaging substrate 10. A first insulating material 30 covers the surfaces of the first copper pillars 21, the first chips 22, the first resistor 23, and the first capacitor 24 that are away from the first surface 101, as well as the first surface 101 itself. A plurality of second copper pillars 41 and second chips 42 are disposed on the second surface 102 of the packaging substrate 10. A second resistor 43 and a second capacitor 44 are disposed on the second surface 102 of the packaging substrate 10.

[0060] S14: Obtain the second insulating material, and press the second insulating material with the second surface of the packaging substrate, the second copper pillar and the second chip to form a second insulating dielectric layer; wherein the second insulating dielectric layer is located around the second copper pillar and covers the second chip and the second surface of the packaging substrate.

[0061] In this embodiment, a second insulating material is obtained, and the second insulating material is pressed together with the second surface of the packaging substrate, the second copper pillar, and the second chip, so that the second insulating material covers the side surface of the second copper pillar away from the second surface, the side surface of the second chip away from the second surface, and the second surface.

[0062] The second insulating material includes one or more of epoxy resin, phenolic resin, polyimide, BT, ABF, and ceramic matrix.

[0063] Understandably, encapsulating the second surface of the packaging substrate, the second copper pillar, the second chip, and the resistive and capacitive components using injection molding equipment can protect the second copper pillar, the second chip, and the resistive and capacitive components.

[0064] Specifically, please refer to Figure 6 , Figure 6 This is a schematic diagram of the structure of the substrate to be processed obtained after injection molding the second surface of the packaging substrate in S14, according to one embodiment. Figure 6 As shown, the substrate 400 to be processed includes a packaging substrate 10, which includes a first surface 101 and a second surface 102 disposed opposite to each other. A plurality of first copper pillars 21 and first chips 22 are disposed on the first surface 101 of the packaging substrate 10. A first resistor 23 and a first capacitor 24 are disposed on the first surface 101 of the packaging substrate 10. A first insulating material 30 covers the surfaces of the first copper pillars 21, the first chips 22, the first resistor 23, and the first capacitor 24 that are away from the first surface 101, as well as the first surface 101 itself. A plurality of second copper pillars 41 and second chips 42 are disposed on the second surface 102 of the packaging substrate 10. A second resistor 43 and a second capacitor 44 are disposed on the second surface 102 of the packaging substrate 10. The second insulating material 50 covers the side surface of the second copper pillar 41 away from the second surface 102, the side surface of the second chip 42 away from the second surface 102, the side surface of the second resistor 43 away from the second surface 102, the side surface of the second capacitor 44 away from the second surface 102, and the second surface 102.

[0065] Further, the first insulating material is ground until the surface of the first copper pillar furthest from the first surface is exposed, to form a first insulating dielectric layer; wherein the first insulating dielectric layer is located around the first copper pillar and covers the first surface of the first chip and the packaging substrate. Simultaneously, the second insulating material is ground until the surface of the second copper pillar furthest from the second surface is exposed, to form a second insulating dielectric layer. wherein the second insulating dielectric layer is located around the second copper pillar and covers the second surface of the second chip and the packaging substrate.

[0066] Specifically, please refer to Figure 7 , Figure 7 This is a schematic diagram of one embodiment of the material to be treated after grinding. For example... Figure 7As shown, the substrate 500 to be processed includes a packaging substrate 10, which includes a first surface 101 and a second surface 102 disposed opposite to each other. A plurality of first copper pillars 21 and a first chip 22 are disposed on the first surface 101 of the packaging substrate 10. A first resistor 23 and a first capacitor 24 are disposed on the first surface 101 of the packaging substrate 10. A first insulating dielectric layer 31 is located around the first copper pillars 21 and covers the side of the first chip 22 away from the first surface 101, the side of the first resistor 23 away from the first surface 101, the side of the first capacitor 24 away from the first surface 101, and the first surface 101 itself. A plurality of second copper pillars 41 and second chips 42 are disposed on the second surface 102 of the packaging substrate 10. A second resistor 43 and a second capacitor 44 are disposed on the second surface 102 of the packaging substrate 10. The second insulating dielectric layer 51 is located around the second copper pillar 41 and covers the side surface of the second chip 42 away from the second surface 102, the side surface of the second resistor 43 away from the second surface 102, the side surface of the second capacitor 44 away from the second surface 102, and the second surface 102.

[0067] In this embodiment, after grinding to expose the surfaces of the first copper pillar and the second copper pillar away from the packaging substrate, tin or gold is plated on the surfaces of the first copper pillar away from the first surface and the second copper pillar away from the second surface to form a tin oxide layer.

[0068] Understandably, the purpose of setting the tin plating layer is to prevent the first or second copper pillar from being oxidized.

[0069] Furthermore, an inductor element is soldered onto the surface of the first copper pillar away from the first surface using SMT (Surface Mounted Technology), and conductive adhesive is filled onto the surface of the inductor element that contacts the first copper pillar.

[0070] Conductive adhesive is an adhesive that has a certain conductivity after curing or drying. It is usually composed of a base resin and conductive fillers, i.e., conductive particles. The conductive particles are bonded together by the adhesive effect of the base resin to form a conductive path and achieve conductive connection of the bonded materials.

[0071] Understandably, external inductors allow the heat from the inductor to be dissipated directly into the air, while the conductive adhesive further enhances the heat dissipation of the inductor, thereby improving the overall heat dissipation performance of the device.

[0072] Specifically, please refer to Figure 8 , Figure 8This is a schematic diagram of one embodiment of a substrate to be processed, on which inductive components are mounted. (See diagram below.) Figure 8 As shown, the substrate 600 to be processed includes a packaging substrate 10, which includes a first surface 101 and a second surface 102 disposed opposite to each other. A plurality of first copper pillars 21 and first chips 22 are disposed on the first surface 101 of the packaging substrate 10. A first resistor 23 and a first capacitor 24 are disposed on the first surface 101 of the packaging substrate 10. A first insulating dielectric layer 31 is located around the first copper pillars 21 and covers the surface of the first chip 22 away from the first surface 101, the surface of the first resistor 23 away from the first surface 101, the surface of the first capacitor 24 away from the first surface 101, and the first surface 101 itself. An inductor 60 is disposed on the surface of the first copper pillars 21 away from the first surface 101 and is bonded to the first copper pillars 21 by conductive adhesive 61. Multiple second copper pillars 41 and second chips 42 are disposed on the second surface 102 of the packaging substrate 10. A second resistor 43 and a second capacitor 44 are also disposed on the second surface 102 of the packaging substrate 10. A second insulating dielectric layer 51 is located around the second copper pillars 41 and covers the side of the second chip 42 away from the second surface 102, the side of the second resistor 43 away from the second surface 102, the side of the second capacitor 44 away from the second surface 102, and the second surface 102 itself.

[0073] Furthermore, a ball is implanted on the surface of the second copper pillar away from the second surface to obtain an encapsulation.

[0074] Understandably, the ball can conduct the heat emitted by the second copper pillar into the air, thereby further optimizing the heat dissipation effect and greatly improving the thermal performance and reliability of the product.

[0075] In this embodiment, multiple packages can be generated simultaneously on a large packaging substrate using the above process. Therefore, it is also necessary to use a cutting device to separate the boards to obtain multiple independent packages.

[0076] Unlike existing technologies, this embodiment mounts at least one first copper pillar and one second copper pillar during the mounting of the first and second chips. This ensures that the first and second insulating dielectric layers respectively cover the first and second chips, while exposing the surfaces of the first and second copper pillars away from the packaging substrate. This allows the first and second chips to dissipate heat through the first and second copper pillars, thereby enhancing the heat dissipation performance of the stacked packaging structure and improving the reliability of the wafer. Furthermore, by using double-sided chip packaging, the vertical space of the package can be utilized for layout, thus achieving the requirements of miniaturized package size, high density, and multifunctionality.

[0077] Correspondingly, this application provides a package.

[0078] Specifically, please refer to Figure 9 , Figure 9 This is a schematic diagram of one embodiment of the package of this application. Figure 9 As shown, the package 700 includes a package substrate 10, which includes a first surface 101 and a second surface 102 disposed opposite to each other. A plurality of first copper pillars 21 and first chips 22 are disposed on the first surface 101 of the package substrate 10. A first resistor 23 and a first capacitor 24 are disposed on the first surface 101 of the package substrate 10. A first insulating dielectric layer 31 is located around the first copper pillars 21 and covers the surface of the first chip 22 away from the first surface 101, the surface of the first resistor 23 away from the first surface 101, the surface of the first capacitor 24 away from the first surface 101, and the first surface 101 itself. An inductor 60 is disposed on the surface of the first copper pillars 21 away from the first surface 101 and is bonded to the first copper pillars 21 by conductive adhesive 61. Multiple second copper pillars 41 and second chips 42 are disposed on the second surface 102 of the packaging substrate 10. Second resistors 43 and second capacitors 44 are disposed on the second surface 102 of the packaging substrate 10. A second insulating dielectric layer 51 is located around the second copper pillars 41 and covers the surface of the second chip 42, the surface of the second resistor 43, the surface of the second capacitor 44, and the second surface 102 itself. Ball bearings 70 are disposed on the surface of the second copper pillars 41 away from the second surface 102.

[0079] Unlike existing technologies, the package provided in this embodiment, by attaching at least one first copper pillar and one second copper pillar respectively when mounting the first chip and the second chip, ensures that the first and second insulating dielectric layers can respectively cover the first and second chips, while exposing the surfaces of the first and second copper pillars away from the package substrate. This allows the first and second chips to dissipate heat outward through the first and second copper pillars, thereby enhancing the heat dissipation performance of the stacked package structure and improving the reliability of the wafer. Furthermore, by packaging the chips on both sides, the vertical space of the package can be utilized for layout, thus achieving the requirements of miniaturized package size, high density, and multifunctionality.

[0080] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A packaging method, characterized by, The method comprises the following steps: obtaining a to-be-processed board, the to-be-processed board comprising a packaging substrate, at least one first copper column arranged on a first surface of the packaging substrate, and a first chip; the height of the first copper column along the packaging direction is greater than the height of the first chip along the packaging direction; obtaining a first insulating material, and pressing the first insulating material and the first surface of the packaging substrate, the first copper column, and the first chip to form a first insulating medium layer; wherein the first insulating medium layer is located around the first copper column and covers the first chip and the first surface of the packaging substrate; attaching at least one second copper column and a second chip on a second surface of the packaging substrate; wherein the second surface is arranged opposite to the first surface; the height of the second copper column along the packaging direction is greater than the height of the second chip along the packaging direction; obtaining a second insulating material, and pressing the second insulating material and the second surface of the packaging substrate, the second copper column, and the second chip to form a second insulating medium layer; wherein the second insulating medium layer is located around the second copper column and covers the second chip and the second surface of the packaging substrate.

2. The packaging method according to claim 1, characterized in that, The step of obtaining the first insulating material and pressing the first insulating material and the first surface of the packaging substrate, the first copper column, and the first chip to form a first insulating medium layer specifically comprises the following steps: obtaining the first insulating material, and pressing the first insulating material and the first surface of the packaging substrate, the first copper column, and the first chip, so that the first insulating material covers a side surface of the first copper column away from the first surface, a side surface of the first chip away from the first surface, and the first surface; grinding the first insulating material until the side surface of the first copper column away from the first surface is exposed, to form the first insulating medium layer; wherein the first insulating medium layer is located around the first copper column and covers the first chip and the first surface of the packaging substrate.

3. The packaging method of claim 1, wherein, The step of obtaining the second insulating material and pressing the second insulating material and the second surface of the packaging substrate, the second copper column, and the second chip to form a second insulating medium layer specifically comprises the following steps: obtaining the second insulating material, and pressing the second insulating material and the second surface of the packaging substrate, the second copper column, and the second chip, so that the second insulating material covers a side surface of the second copper column away from the second surface, a side surface of the second chip away from the second surface, and the second surface; grinding the second insulating material until the side surface of the second copper column away from the second surface is exposed, to form the second insulating medium layer; wherein the second insulating medium layer is located around the second copper column and covers the second chip and the second surface of the packaging substrate.

4. The packaging method according to any one of claims 1 to 3, characterized in that, The first and second insulating materials include one or more of epoxy, phenol resin, polyimide, BT, ABF, and ceramic-based materials.

5. The packaging method of claim 1, wherein, After the step of obtaining the second insulating material and pressing the second insulating material with the second surface of the packaging substrate, the second copper pillar, and the second chip to form a second insulating medium layer, the method further includes: Tinning or gold plating is performed on the side surface of the first copper pillar away from the first surface and the side surface of the second copper pillar away from the second surface to form a tin layer.

6. The packaging method according to claim 5, wherein, After the step of tinning or gold plating on the side surface of the first copper pillar away from the first surface and the side surface of the second copper pillar away from the second surface to form a tin layer, the method further includes: An inductive element is soldered on the side surface of the first copper pillar away from the first surface.

7. The packaging method according to claim 6, characterized in that, After the step of soldering the inductive element on the side surface of the first copper pillar away from the first surface, the method further includes: Conductive glue is filled on the side surface of the inductive element in contact with the first copper pillar.

8. The packaging method according to claim 7, characterized in that, After the step of filling conductive glue on the side surface of the inductive element in contact with the first copper pillar, the method further includes: A ball is implanted on the side surface of the second copper pillar away from the second surface.

9. The packaging method of claim 1, wherein, The step of obtaining the to-be-processed board material, which includes a packaging substrate and at least one first copper pillar and a first chip arranged on a first surface of the packaging substrate, specifically includes: The packaging substrate is obtained, and the packaging substrate includes the first surface and the second surface arranged oppositely. The at least one first copper pillar and the first chip are obtained, and the first copper pillar and the first chip are attached on the first surface of the packaging substrate to obtain the to-be-processed board material.

10. A package, characterized by The method includes: The packaging substrate includes the first surface and the second surface arranged oppositely. The at least one first copper pillar and the first chip are arranged on the first surface of the packaging substrate, and the height of the first copper pillar along the packaging direction is greater than the height of the first chip along the packaging direction. The first insulating medium layer is located around the first copper pillar and covers the first chip and the first surface of the packaging substrate. The inductive element is arranged on the side surface of the first copper pillar away from the first surface. The at least one second copper pillar and the second chip are arranged on the second surface of the packaging substrate, and the height of the second copper pillar along the packaging direction is greater than the height of the second chip along the packaging direction. The second insulating medium layer is located around the second copper pillar and covers the second chip and the second surface of the packaging substrate. The ball is arranged on the side surface of the second copper pillar away from the second surface.

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