Semiconductor structure and measurement method

Abstract

The embodiments of the present disclosure provide a semiconductor structure and a measurement method. The semiconductor structure comprises a first wafer, a second wafer and a test structure. The test structure comprises N first test pads in the first wafer, and a first bonding surface exposes surfaces of the first test pads. The test structure comprises N second test pads in the second wafer, and a second bonding surface exposes surfaces of the second test pads. Each second test pad is opposite to a corresponding first test pad. An nth second test pad is offset relative to an nth first test pad in a same offset direction parallel to a first direction. A direction in which the nth second test pad points to a first second test pad is the offset direction. In the first direction, a width of the opposite of the nth first test pad and the nth second test pad is n*M. n is a positive integer greater than or equal to 1 and less than or equal to N. M is a preset value. The embodiments of the present disclosure are at least beneficial to improve the alignment accuracy of wafer bonding.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a measurement method. Background Technology

[0002] Wafer bonding technology refers to the process of tightly joining two polished homogeneous or heterogeneous wafers through chemical and physical interactions. After wafer bonding, the atoms at the bonding interface react under the action of external forces to form covalent bonds and become one, so that the bonding interface reaches a specific bonding strength.

[0003] Wafer bonding requires controlling the accuracy of wafer alignment. Alignment marks are usually designed at the bonding interface of the two wafers. However, the process of aligning the two wafers using the current alignment marks cannot accurately determine the amount of displacement between the two wafers. This results in poor alignment accuracy between the two wafers, which in turn affects the performance of the bonded semiconductor structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a measurement method, which at least helps to improve the alignment accuracy of wafer bonding.

[0005] This disclosure provides a semiconductor structure, including: a first wafer having a first bonding surface; a second wafer having a second bonding surface bonded to the first bonding surface; and at least one set of test structures, each test structure including: N first test pads, the N first test pads being spaced apart along a first direction within the first wafer, with the first bonding surface exposing the surface of the first test pads; and N second test pads, the N second test pads being spaced apart along the first direction within the second wafer, with the second bonding surface exposing the surface of the second test pads, each second test pad being directly opposite a corresponding first test pad; wherein the nth second test pad is offset relative to the nth first test pad in the same offset direction parallel to the first direction, the direction from the nth second test pad to the first second test pad is the offset direction, and along the first direction, the width of the direct opposition between the nth first test pad and the nth second test pad is n×M, where n is a positive integer greater than or equal to 1 and less than or equal to N, and M is a preset value.

[0006] In some embodiments, along the first direction, each first test pad exposed on the first bonding surface has the same width, and the spacing between adjacent first test pads exposed on the first bonding surface is the same.

[0007] In some embodiments, along the first direction, each of the second test pads exposed on the second bonding surface has the same width.

[0008] In some embodiments, along the first direction, the width of the first test pad exposed on the first bonding surface is the same as the width of the second test pad exposed on the second bonding surface.

[0009] In some embodiments, the shape of the first test pad exposed on the first bonding surface is the same as the shape of the second test pad exposed on the second bonding surface.

[0010] In some embodiments, the system further includes: a first signal pad, wherein a first bonding surface exposes the first signal pad; and a second signal pad, wherein a second bonding surface exposes the second signal pad, and the first signal pad and the second signal pad are directly opposite each other.

[0011] In some embodiments, along the first direction, the width of the first signal pad exposed on the first bonding surface is the same as the width of the second signal pad exposed on the second bonding surface.

[0012] In some embodiments, the first wafer has a first central region and a first edge region, and the second wafer has a second central region and a second edge region. The first central region and the second central region are directly opposite each other, and the first edge region and the second edge region are directly opposite each other. The first central region and the directly opposite second central region have corresponding test structures, and the first edge region and the directly opposite second edge region also have corresponding test structures.

[0013] In some embodiments, a first wafer includes a plurality of first chips, and a second wafer includes a plurality of second chips, each first chip being directly opposite a corresponding second chip; a portion of the first chips and the corresponding second chips have corresponding test structures.

[0014] In some embodiments, both the first chip and the second chip have a central chip region and a chip edge region, and the central chip region of the first chip and the central chip region of the second chip are directly opposite each other, and the chip edge region of the first chip and the chip edge region of the second chip are directly opposite each other, with the test structure located in the directly opposite central chip region and the directly opposite chip edge region.

[0015] In some embodiments, both the first chip and the second chip have a central chip region, the central chip region of the first chip and the central chip region of the opposite second chip are directly opposite each other, the first wafer also includes a first dicing channel located at the edge of the first chip, the second wafer also includes a second dicing channel located at the edge of the second chip and directly opposite the corresponding first dicing channel, the test structure is located in the central chip region directly opposite each other, and is located within the first dicing channel and the opposite second dicing channel.

[0016] In some embodiments, the first direction includes the X direction; the semiconductor structure has at least two sets of test structures, wherein the offset direction in at least one set of test structures is the +X direction, and the offset direction in at least another set of test structures is the -X direction.

[0017] In some embodiments, the first direction includes the Y direction; the semiconductor structure has at least two sets of test structures, wherein the offset direction in at least one set of test structures is the +Y direction, and the offset direction in at least another test structure is the -Y direction.

[0018] In some embodiments, the material of the first test pad is the same as the material of the second test pad.

[0019] Another aspect of this disclosure provides a measurement method, comprising: providing a first wafer and a second wafer in any of the above-described semiconductor structures; bonding a first bonding surface and a second bonding surface together for pre-bonding; and after pre-bonding, acquiring the connection state between each first test pad and the corresponding second test pad, wherein if the nth first test pad and the nth second test pad are in a disconnected state, and the (n+1)th first test pad and the (n+1)th second test pad are in an interconnected state, then it is determined that the second wafer has undergone a displacement of n×M relative to the first wafer in the offset direction.

[0020] In some embodiments, the method of measuring the connection state between each first test pad and the corresponding second test pad includes: measuring the contact resistance between the first test pad and the corresponding second test pad; if the contact resistance is greater than or equal to a preset value, then it is determined that the first test pad and the corresponding second test pad are in a disconnected state; if the contact resistance is less than the preset value, then it is determined that the first test pad and the corresponding second test pad are in an interconnected state.

[0021] The technical solution provided in this disclosure has at least the following advantages: The semiconductor structure includes a first wafer and a second wafer bonded together, wherein the first bonding surface of the first wafer and the second bonding surface of the second wafer are bonded together. The bonded first wafer and the second wafer have a test structure for measuring the alignment deviation between the first wafer and the second wafer. The test structure includes N first test pads exposed on the first bonding surface and N second test pads exposed on the second bonding surface. The nth first test pad corresponds to the nth second test pad, and the N first test pads and the N second test pads are all spaced apart along a first direction. The arrangement is such that the second test pad corresponding to the nth first test pad is offset relative to the nth first test pad in a first offset direction parallel to the first direction. If the first direction is the X direction, then the first offset direction can be either the +X direction or the -X direction. The first offset direction is also the direction from the nth second test pad to the first second test pad. Furthermore, in the first direction, the facing widths of the first test pad and the corresponding second test pad are different. If the nth first test pad and the corresponding second test pad are defined as the nth group of pads, the direction from the first second test pad to the nth second test pad... In terms of orientation, the facing widths of the first group of pads to the Nth group of pads are respectively: M, 2M...n×M...N×M, where M is the smallest dimension that the measuring device can measure. Thus, if the facing width between the first test pad and the corresponding second test pad in the nth group of pads is zero (i.e., the first test pad and the corresponding second test pad in the nth group of pads are disconnected), and the facing width between the first test pad and the corresponding second test pad in the (n+1)th group of pads is not zero (i.e., the first test pad and the corresponding second test pad in the (n+1)th group of pads are connected), then the second crystal... The second wafer is displaced relative to the first wafer in the first offset direction. The displacement is n×M based on the disconnected nth group of pads and the connected (n+1)th group of pads. Thus, the test structure can be used to determine whether the second wafer and the first wafer are aligned and bonded. If the second wafer and the first wafer are not aligned and bonded, the displacement of the second wafer relative to the first wafer can be obtained through the test structure. Based on the displacement, the bonding between the first wafer and the second wafer in the next semiconductor structure can be calibrated, which can improve the alignment accuracy of the bonding between the first wafer and the second wafer in the semiconductor structure, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0024] Figure 2 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0025] Figure 3 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0026] Figure 4 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0027] Figure 5 This is a schematic diagram of the structure of a first wafer provided in an embodiment of the present disclosure;

[0028] Figure 6 This is a schematic diagram illustrating the positional relationship between a test structure on a first wafer and a first chip, provided in an embodiment of this disclosure.

[0029] Figure 7 This is a schematic diagram illustrating the positional relationship between a test structure on a first wafer and a first chip, as provided in an embodiment of this disclosure. Detailed Implementation

[0030] As is known from the background art, the process of aligning two bonded wafers using current alignment marks cannot accurately determine the amount of displacement between the two bonded wafers, which in turn affects the performance of the semiconductor structure.

[0031] This disclosure provides a semiconductor structure and a measurement method. The semiconductor structure includes a first wafer and a second wafer bonded together. The first wafer has a first bonding surface, and the second wafer has a second bonding surface for bonding with the first bonding surface. The semiconductor structure also includes a test structure for measuring the alignment deviation between the first wafer and the second wafer. The test structure includes N first test pads exposed on the first bonding surface and N second test pads exposed on the second bonding surface. The nth first test pad corresponds to the nth second test pad. The second test pad corresponding to the nth first test pad is offset relative to the nth first test pad in a first offset direction parallel to a first direction. If the first direction is the X direction, then the first offset direction can be +X or -X. The first offset direction is also the direction from the nth second test pad to the first second test pad. Furthermore, the facing widths of the first test pads and the corresponding second test pads are different. The nth first test pad and the corresponding second test pad are defined as the nth group of pads. Along the direction from the first second test pad to the nth second test pad, the facing widths of the first group of pads to the facing widths of the Nth group of pads are respectively: M, 2M...n×M...N×M, where M is the smallest dimension that the measuring device can measure. Thus, if the first test pad in the nth group of pads is disconnected from the corresponding second test pad, and the first test pad in the (n+1)th group of pads is connected to the corresponding second test pad, it is determined that the second wafer has been displaced relative to the first wafer in the first offset direction. The displacement amount is n×M based on the disconnected nth group of pads and the connected (n+1)th group of pads. In this way, the test structure can be used to determine whether the second wafer and the first wafer are aligned and bonded, and to obtain the displacement amount of the second wafer relative to the first wafer. Based on the displacement amount, the bonding between the first wafer and the second wafer in the next semiconductor structure is calibrated, which helps to improve the alignment accuracy of the bonding between the first wafer and the second wafer in the semiconductor structure.

[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0033] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure; Figure 3 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure; Figure 4 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure; Figure 5 This is a schematic diagram of the structure of a first wafer provided in an embodiment of the present disclosure; Figure 6 This is a schematic diagram illustrating the positional relationship between a test structure on a first wafer and a first chip, provided in an embodiment of this disclosure. Figure 7 This is a schematic diagram illustrating the positional relationship between a test structure on a first wafer and a first chip, as provided in an embodiment of this disclosure.

[0034] refer to Figure 1 The semiconductor structure includes: a first wafer 100 having a first bonding surface; a second wafer 110 having a second bonding surface bonded to the first bonding surface; and at least one set of test structures 120, each test structure 120 including: N first test pads 101 spaced apart along a first direction within the first wafer 100, with the first bonding surface exposing the surface of the first test pads 101; and N second test pads 111 spaced apart along the first direction within the second wafer 110. The second bonding surface exposes the surface of the second test pad 111, and each second test pad 111 is directly opposite to the corresponding first test pad 101; wherein, the nth second test pad is offset relative to the nth first test pad 101 in the same offset direction parallel to the first direction, the direction of the nth second test pad 111 pointing to the first second test pad 111 is the offset direction, and along the first direction, the width of the direct opposition between the nth first test pad 101 and the nth second test pad 111 is n×M, where n is a positive integer greater than or equal to 1 and less than or equal to N, and M is a preset value.

[0035] If the nth first test pad 101 and the corresponding second test pad 111 are defined as the nth group of pads, the facing widths of the first group of pads to the nth group of pads along the direction from the first second test pad 111 to the nth second test pad 111 are respectively: M, 2M...n×M...N×M, where M is the measurement resolution, i.e., the minimum displacement dimension that the measuring equipment can measure. When measuring the alignment accuracy of the first wafer 100 and the second wafer 110, if the facing width of the first test pad 101 and the corresponding second test pad 111 in the nth group of pads is zero, and the facing width of the first test pad 101 and the corresponding second test pad 111 in the (n+1)th group of pads is... If the width of the first wafer 110 is not zero, it is determined that the second wafer 110 has been displaced relative to the first wafer 100 in the first offset direction. The displacement amount is n×M based on the disconnected nth group of pads and the connected (n+1)th group of pads. The test structure 120 can be used to determine whether the second wafer 110 and the first wafer 100 are aligned and bonded. If the second wafer 110 and the first wafer 100 are not aligned and bonded, the bonding of the first wafer 100 and the second wafer 110 in the next semiconductor structure is calibrated based on the displacement amount of the second wafer 110 relative to the first wafer 100 obtained through the test structure 120, thereby improving the alignment accuracy of the bonding of the first wafer 100 and the second wafer 110 in the semiconductor structure.

[0036] The first wafer 100 and the second wafer 110 are two wafers for bonding to each other. A wafer refers to a chip used to fabricate semiconductor devices or circuits. In some embodiments, the wafer can be a chip with semiconductor devices or circuits fabricated on a silicon substrate. In other embodiments, the substrate of the wafer can also be other semiconductor materials or other materials that can be used as substrates.

[0037] Bonding the first wafer 100 to the second wafer 110 can be used to electrically connect semiconductor devices or circuits in the first wafer 100 to semiconductor devices or circuits in the second wafer 110. Specifically, the first bonding surface of the first wafer 100 and the second bonding surface of the second wafer 110 are arranged opposite to each other and bonded together. The first bonding surface can expose the pads for leading out semiconductor devices or circuits in the first wafer 100, and the second bonding surface can expose the pads for leading out semiconductor devices or circuits in the second wafer 110. After the first wafer 100 and the second wafer 110 are bonded together, the first bonding surface and the second bonding surface are in contact, and the pads on the first bonding surface can be connected to the corresponding pads on the second bonding surface, thereby realizing the connection between the semiconductor devices or circuits in the first wafer 100 and the semiconductor devices or circuits in the second wafer 110.

[0038] The interface state between the first and second bonding surfaces affects the electrical performance and structural stability of the bonded semiconductor structure. Specifically, the structural stability of the bond between the first wafer 100 and the second wafer 110 can be improved by optimizing the stress matching between the first and second bonding surfaces, and by avoiding impurities or bubbles at the bonding interface formed by the first and second bonding surfaces, thereby enhancing the structural stability of the bond between the first wafer 100 and the second wafer 110. Furthermore, the electrical performance of the semiconductor structure can be improved by increasing the alignment accuracy of the bonding to ensure accurate alignment between the pads on the first wafer 100 and the pads on the second wafer 110.

[0039] The test structure 120 in the semiconductor structure provided in this embodiment is a structure used to improve the alignment accuracy between the first wafer 100 and the second wafer 110. Specifically, the test structure 120 includes N first test pads 101 and N second test pads 111. The first bonding surface of the first wafer 100 exposes the first test pads 101, and the second bonding surface of the second wafer 110 exposes the second test pads 111. The first test pads 101 and the second test pads 111 are arranged at intervals along a first direction. The first direction can be any direction parallel to the surface of the first wafer 100 or the second wafer 110. If the first direction is the X direction, the first test pads 101 and the second test pads 111 arranged in the first direction can be used to measure whether the second wafer 110 has been displaced relative to the first wafer 100 in the X direction.

[0040] Furthermore, N is an integer greater than or equal to 1, such as 3, 4, 5, 6, 7, or 8. The value of N is related to the displacement that the test structure 120 can measure. The larger N is, the greater the displacement that the test structure 120 can measure. Therefore, the number of first test pads 101 and the number of second test pads 111 in the test structure 120 can be reasonably set according to the areas of the first bonding surface and the second bonding surface, as well as the maximum possible displacement. In this embodiment, N is 5 as an example to illustrate the test structure 120.

[0041] Furthermore, the displacement of the second wafer 110 relative to the first wafer 100 in the X direction includes two cases: one is that the second wafer 110 is displaced in the +X direction relative to the first wafer 100, and the other is that the second wafer 110 is displaced in the -X direction relative to the first wafer 100. The arrangement of the first test pad 101 and the second test pad 111 in the test structure 120 for determining displacement in the +X direction is different from that in the test structure 120 for determining displacement in the -X direction. The following will take the test structure 120 for measuring the displacement of the second wafer 110 relative to the first wafer 100 in the +X direction as an example to explain the arrangement of the first test pad 101 and the second test pad 111 in the test structure 120.

[0042] refer to Figure 1 and Figure 2 In some embodiments, the test structure 120 can be used to measure whether the second wafer 110 is displaced relative to the first wafer 100 in the +X direction, and to measure the amount of displacement of the second wafer 110 relative to the first wafer 100 in the +X direction. The test structure 120 may include five first test pads 101 and five second test pads 111. The first first test pad 101 corresponds to the first second test pad 111, the second first test pad 101 corresponds to the second second test pad 111, and so on. Each second test pad 111 is offset relative to its corresponding first test pad 101 in the +X direction. That is, the offset direction of the second test pad 111 relative to its corresponding first test pad 101 is the +X direction. The direction in which the fifth second test pad 111 points to the first second test pad 111 is the +X direction. In the first direction, the width of each first test pad 101 facing the corresponding second test pad 111 is different. The width of the nth first test pad 101 facing the nth second test pad 111 is n×M, that is, the width of the first first test pad 101 facing the first second test pad 111 is M, the width of the second first test pad 101 facing the second second test pad 111 is 2M, and so on. Along the +X direction, the widths of the first test pad 101 facing the corresponding second test pad 111 are 5M, 4M, 3M, 2M, and M, respectively.

[0043] refer to Figure 2 If the second wafer 110 is displaced by an amount of M in the +X direction relative to the first wafer 100, the first test pad 101 will be disconnected from the first second test pad 111, while the second test pad 101 will remain connected to the second second test pad 111.

[0044] Similarly, if the second wafer 110 is displaced by 2M relative to the first wafer 100 in the +X direction, the second first test pad 101 will disconnect from the second second test pad 111, while the third first test pad 101 will remain connected to the third second test pad 111. Therefore, by determining the connection status between the first test pad 101 and the corresponding second test pad 111 in the test structure 120, the displacement status of the second wafer 110 relative to the first wafer 100 in the +X direction can be obtained. Furthermore, by determining the position of the disconnected first test pad 101 and the corresponding second test pad 111, the displacement amount of the second wafer 110 relative to the first wafer 100 in the +X direction can be obtained. Based on the displacement amount, the bonding between the first wafer 100 and the second wafer 110 in the next semiconductor structure is calibrated, thereby improving the alignment accuracy of the bonding between the first wafer 100 and the second wafer 110 in the semiconductor structure, which in turn helps to improve the performance of the semiconductor structure.

[0045] In some embodiments, reference Figure 3 and Figure 4 The semiconductor structure has at least two sets of test structures, wherein at least one set of test structures 120 has an offset direction in the +X direction, and at least another set of test structures 120 has an offset direction in the -X direction. Thus, by using the test structure 120 with an offset direction in the +X direction to measure whether the second wafer 110 has shifted relative to the first wafer 100 in the +X direction, and by using the test structure 120 with an offset direction in the -X direction to measure whether the second wafer 110 has shifted relative to the first wafer 100 in the -X direction, it is possible to measure multiple directions of offset of the second wafer 110 relative to the first wafer 100. This is beneficial for improving the alignment accuracy of the first wafer 100 and the second wafer 110 in multiple directions within the semiconductor structure using the test structure 120.

[0046] For details, please refer to Figure 4 If the second wafer 110 is displaced by 2M relative to the first wafer 100 in the -X direction, the first test pad 101 and the corresponding second test pad 111 in the test structure 120 with the offset direction in the +X direction are both connected. In the test structure 120 with the offset direction in the -X direction, the first first test pad 101 will be disconnected from the first second test pad 111, the second first test pad 101 will be disconnected from the second second test pad 111, and the third first test pad 101 will still be connected to the third second test pad 111.

[0047] In some embodiments, the first direction further includes the Y direction; the semiconductor structure has at least two sets of test structures 120, wherein the offset direction in at least one set of test structures 120 is the +Y direction, and the offset direction in at least another set of test structures 120 is the -Y direction. It should be noted that the Y direction and the X direction are different directions. By setting at least two additional sets of test structures 120 within the semiconductor structure, with one set of test structures 120 having an offset direction of +Y and the other set having an offset direction of -Y, the test structure 120 with an offset direction of +Y is used to measure whether the second wafer 110 has shifted relative to the first wafer 100 in the +Y direction, and the test structure 120 with an offset direction of -Y is used to measure whether the second wafer 110 has shifted relative to the first wafer 100 in the -Y direction. This allows for the measurement of the offset directions of the second wafer 110 relative to the first wafer 100, excluding the X direction. This, in turn, helps to improve the alignment accuracy of the first wafer 100 and the second wafer 110 in more directions within the semiconductor structure using the test structure 120.

[0048] In some embodiments, the Y direction is perpendicular to the X direction. Four sets of test structures 120 can be set in the semiconductor structure. By combining the displacement measured by the four sets of test structures 120, the displacement of the first wafer 100 and the second wafer 110 in all directions parallel to the surface of the first wafer 100 can be measured. This is beneficial to improve the alignment accuracy of the first wafer 100 and the second wafer 110 in the semiconductor structure by using the test structures 120.

[0049] In some embodiments, reference Figure 1Taking the X-direction as an example, along the X-direction, the width of each exposed first test pad 101 on the first bonding surface is the same, and the spacing between adjacent exposed first test pads 101 is the same. Forming the first test pads 101 typically requires photolithography and etching processes. Photolithography is mainly used to define the shape and dimensions of the first test pads 101. However, during photoresist exposure, the incident light used in the photolithography process can produce unwanted reflected or refracted light. This unwanted reflected or refracted light may cause unwanted photoresist to be exposed. After development, the resulting photoresist pattern will have errors compared to the preset photoresist pattern. Furthermore, the intensity and direction of the reflected or refracted light are also related to the preset photoresist pattern. If the preset photoresist pattern is different, the error in the photolithography process will increase. Therefore, by setting each of the first test pads 101 exposed on the first bonding surface to have the same width and setting the spacing between adjacent first test pads 101 to the same size, the size error between the first test pads 101 with different widths in the first direction due to the difference in photolithography error can be avoided when forming the first test pads 101 using photolithography. This helps to reduce the size error between different first test pads 101, and thus helps to use the first test pads 101 with smaller size error to measure the alignment accuracy of wafer bonding more accurately.

[0050] In some embodiments, reference Figure 1 Taking the X-direction as an example, along the X-direction, the width of each exposed second test pad 111 on the second bonding surface is the same. Similarly, forming the second test pad 111 usually requires photolithography and etching processes. Since the width and spacing of the first test pads 101 are the same in the X-direction, setting each exposed second test pad 111 on the second bonding surface to have the same width results in the same spacing between adjacent second test pads 111. Thus, when forming the second test pads 111 using photolithography, the dimensional errors caused by different photolithography errors between second test pads 111 with different widths in the X-direction are avoided. This helps reduce the dimensional errors between different second test pads 111, and further facilitates more accurate measurement of wafer bonding alignment using second test pads 111 with smaller dimensional errors.

[0051] In some embodiments, reference Figure 1Taking the X-direction as an example, along the X-direction, the width of the first test pad 101 exposed on the first bonding surface is the same as the width of the second test pad 111 exposed on the second bonding surface. In the X-direction, the photolithographic error forming the width of the first test pad 101 is made the same as the photolithographic error forming the width of the second test pad 111. This helps to reduce the difference between the widths of the first test pad 101 and the second test pad 111, thereby facilitating the formation of a test structure 120 with higher measurement accuracy in the X-direction.

[0052] In some embodiments, the shape of the first test pad exposed on the first bonding surface is the same as the shape of the second test pad 111 exposed on the second bonding surface. As can be seen from the above embodiments, the shape of the pad is related to lithography errors. Therefore, even if the widths of the first test pad 101 and the second test pad 111 are the same in the first direction, differences in dimensions in other directions will affect the width in the first direction. Therefore, to minimize the width error between the first test pad 101 and the second test pad 111 in the first direction, the first test pad 101 and the second test pad 111 can be formed with identical shapes. This ensures a higher degree of matching between the first test pad 101 and the second test pad 111 in terms of morphology and spacing, thereby facilitating the formation of a test structure 120 with higher measurement accuracy. In one example, the shape of the first test pad 101 exposed on the first bonding surface or the shape of the second test pad 111 exposed on the second bonding surface is square. In other examples, the shape of the first test pad 101 exposed on the first bonding surface or the shape of the second test pad 111 exposed on the second bonding surface may also be circular or other shapes.

[0053] In some embodiments, reference Figure 1 Taking the X-direction as an example, the width of the first test pad 101 along the first direction can be from 100nm to 10000nm, for example, 150nm, 350nm, 400nm, 4000nm, 8000nm, etc. The width of the second test pad 111 can be from 100nm to 10000nm, for example, 500nm, 1000nm, 2000nm, 2500nm, 7500nm, etc. The widths of the first test pad 101 and the second test pad 111 in the first direction can be reasonably set according to the dimensions of the first wafer 100 and the second wafer 110 in the first direction.

[0054] In some embodiments, reference Figure 1Taking the X-direction as an example, the length of the first test pad 101 perpendicular to the first direction is 100nm to 1000nm, for example, it can be 150nm, 350nm, 450nm, 500nm, 800nm, etc. The length of the second test pad 111 is 100nm to 1000nm, for example, it can be 250nm, 300nm, 400nm, 530nm, 760nm, etc. Similarly, the widths of the first test pad 101 and the second test pad 111 in the first direction can be reasonably set according to the dimensions of the first wafer 100 and the second wafer 110 perpendicular to the first direction.

[0055] In some embodiments, reference Figure 1 Both the first wafer 100 and the second wafer 110 include an insulating layer 130, which can be made of silicon oxide or silicon nitride. A first bonding surface exposes the insulating layer 130 of the first wafer 100, and a first test pad 101 is located within the insulating layer 130. The first test pad 101 is made of a conductive material, such as copper, tungsten, or aluminum. A second bonding surface exposes the insulating layer 130 of the second wafer 110, and a second test pad 111 is located within the insulating layer 130. The second test pad 111 is also made of a conductive material, such as copper, tungsten, or aluminum.

[0056] In some embodiments, the material of the first test pad 101 is the same as the material of the second test pad 111. This is advantageous because it allows for the use of the same fabrication process and the same source material to fabricate the first test pad 101 and the second test pad 111, thereby reducing the fabrication difficulty of the first test pad 101 and the second test pad 111.

[0057] In some embodiments, the semiconductor structure further includes: a first signal pad 102, with a first bonding surface exposing the first signal pad 102; and a second signal pad 112, with a second bonding surface exposing the second signal pad 112, and the first signal pad 102 and the second signal pad 112 facing each other. The first signal pad 102 may be a pad for providing signals to semiconductor devices or circuits within the first wafer 100, and the second signal pad 112 may be a pad for providing signals to semiconductor devices or circuits within the second wafer 110. The facing first signal pad 102 and the second signal pad 112 are interconnected and can be used for signal transmission between semiconductor devices or circuits within the first wafer 100 and semiconductor devices or circuits within the second wafer 110.

[0058] In some embodiments, reference Figure 1Taking the X-direction as an example, along the first direction, the width of the first signal pad 102 exposed on the first bonding surface is the same as the width of the second signal pad 112 exposed on the second bonding surface. The first signal pad 102 and the second signal pad 112, which are of the same width and directly opposite each other in the first direction, can serve as positioning marks during the setting process of the first test pad 101 and the second test pad 111. This facilitates the accurate setting of the first test pad 101 in the first wafer 100 and the second test pad 111 in the second wafer 110 using the first signal pad 102 and the second signal pad 112, avoiding the need to set additional positioning marks, and thus reducing the manufacturing difficulty of the first test pad 101 and the second test pad 111.

[0059] In some embodiments, a first signal pad 102 is disposed within an insulating layer 130 of a first wafer 100, and a second signal pad 112 is disposed within an insulating layer 130 of a second wafer 110. The first signal pad 102 and the second signal pad 112 are made of the same material, which may include copper, tungsten, or aluminum. Furthermore, the first signal pad 102 is exposed on the surface of the first wafer 100 opposite to the first bonding surface, and the second signal pad 112 is exposed on the surface of the second wafer 110 opposite to the second bonding surface. This facilitates the use of the first signal pad 102 to provide signals to semiconductor devices or circuits within the first wafer 100, and facilitates the use of the second signal pad 112 to provide signals to semiconductor devices or circuits within the second wafer 110.

[0060] In some embodiments, reference Figure 5The first wafer 100 has a first central region 103 and a first edge region 104, and the second wafer 110 has a second central region and a second edge region. The first central region 103 and the second central region are directly opposite each other, and the first edge region 104 and the second edge region are directly opposite each other. The first central region 103 and the directly opposite second central region have corresponding test structures 120, and the first edge region 104 and the directly opposite second edge region also have corresponding test structures 120. It should be noted that multiple test structures 120 can be provided in the first edge region 104 and the opposite first edge region 104. Thus, by utilizing multiple test structures 120 in the middle and edges of the first wafer 100 and the second wafer 110, alignment measurements can be performed on the edges of the first wafer 100 and the second wafer 110, as well as on the center of the first wafer 100 and the center of the second wafer 110. Aligning the center and edges allows for overall alignment measurements of the first wafer 100 and the second wafer 110. This facilitates accurate measurement of the bonding between the first wafer 100 and the second wafer 110 using a limited number of test structures 120, and also reduces the complexity of the measurement process by measuring the alignment accuracy of the bonding with fewer test structures 120. It should also be noted that the second middle region and the second edge region of the second wafer are similar to those of the first wafer 100, and are not shown in the figure.

[0061] In some embodiments, reference Figure 6 and Figure 7 The first wafer 100 includes a plurality of first chips 105, and the second wafer 110 includes a plurality of second chips, with each first chip 105 facing a corresponding second chip. Some of the first chips 105 and the facing second chips have corresponding test structures 120. Thus, not only can the displacement of the second wafer 110 relative to the first wafer 100 as a whole be measured using the test structures 120, but also the displacement of the second chips within the second wafer 110 relative to the corresponding first chips 105 within the first wafer 100 can be measured. This facilitates the accurate acquisition of the displacement between the second chips and the first chips 105 using the test structures 120, thereby achieving accurate alignment and bonding between the second chips and the first chips 105. Higher alignment accuracy of the first chips 105 and second chips improves the performance of the semiconductor structure. It should be noted that the arrangement of the second chips on the second wafer is similar to that of the first chips 105 in the first wafer 100; therefore, the second chips on the second wafer are not shown.

[0062] In some embodiments, reference Figure 6Both the first chip 105 and the second chip have a central region and an edge region. The central region of the first chip 105 is aligned with the central region of the opposite second chip, and the edge regions of the first chip 105 and the opposite second chip are aligned. The test structure 120 is located in the central region and the edge region of the opposite chip. To improve the measurement of the alignment accuracy between the first chip 105 and the opposite second chip, two sets of corresponding test structures 120 can be set within the first chip 105 and the opposite second chip. The two sets of test structures 120 can be located in the central region and the edge region of the chip, respectively. In this way, the alignment state of the central part of the first chip 105 and the second chip can be measured using the test structure 120 in the central region, and the alignment state of the edge of the first chip 105 and the second chip can be measured using the test structure 120 in the edge region. This facilitates accurate measurement of the bonding alignment of the first chip 105 and the opposite second chip.

[0063] In some embodiments, reference Figure 7 Both the first chip 105 and the second chip have a central region. The central regions of the first chip 105 and the corresponding central regions of the second chip are aligned. The first wafer 100 also includes a first dicing channel 106 located at the edge of the first chip 105, and the second wafer 110 also includes a second dicing channel located at the edge of the second chip and aligned with the corresponding first dicing channel 106. The test structure 120 is located in the corresponding central region of the chip and within the first dicing channel 106 and the corresponding second dicing channel. Thus, the alignment status of the central regions of the first chip 105 and the second chip can be measured using the test structure 120 in the central region of the chip, and the alignment status of the edges of the first chip 105 and the second chip can be measured using the test structure 120 within the first dicing channel 106 and the second dicing channel. This facilitates accurate measurement of the bonding alignment between the first chip 105 and the corresponding second chip.

[0064] It is understood that, in the above embodiments, references Figure 6 and Figure 7Taking the alignment measurement of the bonding between the middle of the first chip 105 and the opposing second chip as an example, four sets of test structures 120 can be set at the middle of the first chip 105 and the opposing second chip. The offset directions of the four sets of test structures 120 are different, and the offset directions of the four sets of test structures 120 can be -X direction, -Y direction, +X direction, and +Y direction, respectively. In this way, the displacement of the middle of the first chip 105 and the opposing second chip in various directions can be measured. Similarly, the test structures 120 for measuring the displacement of the edges of the first chip 105 and the opposing second chip in various directions are also similar. Four sets of test structures 120 with different offset directions can be set at the edges of the first chip 105 and the opposing second chip. The offset directions of the four sets of test structures 120 can be -X direction, -Y direction, +X direction, and +Y direction, respectively.

[0065] In some embodiments, the spacing between the test structures 120 measuring in different directions can be small. In one example, a first chip 105 and an opposite second chip have multiple adjacent sets of test structures 120 measuring in different directions. In other embodiments, the spacing between the test structures 120 measuring in different directions can be larger.

[0066] In the semiconductor structure provided in the above embodiments, a first wafer 100 and a second wafer 110 are bonded together. The first wafer 100 has a first bonding surface, and the second wafer 110 has a second bonding surface for bonding with the first bonding surface. The semiconductor structure also includes a test structure 120 for measuring the alignment deviation between the first wafer 100 and the second wafer 110. The test structure 120 includes N first test pads 101 exposed on the first bonding surface and N second test pads 111 exposed on the second bonding surface. The facing widths of the first test pads 101 and the corresponding second test pads 111 are different. If the nth first test pad 101 and the corresponding second test pad 111 are defined as the nth group of pads, the facing widths of the first group of pads to the nth group of pads along the direction from the first second test pad 111 to the nth second test pad 111 are respectively: M, 2M...n×M...N×M, where... M is the smallest dimension that the measuring device can measure. Thus, if the first test pad 101 in the nth group of pads is disconnected from the corresponding second test pad 111, and the first test pad 101 in the (n+1)th group of pads is connected to the corresponding second test pad 111, it is determined that the second wafer 110 has been displaced relative to the first wafer 100 in the first offset direction. The displacement is n×M based on the disconnected nth group of pads and the connected (n+1)th group of pads. Thus, the test structure 120 can determine whether the second wafer 110 and the first wafer 100 are aligned and bonded, and obtain the displacement of the second wafer 110 relative to the first wafer 100. Based on the displacement, the bonding between the first wafer 100 and the second wafer 110 in the next semiconductor structure is calibrated, which can improve the alignment accuracy of the bonding between the first wafer 100 and the second wafer 110 in the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0067] Accordingly, this disclosure also provides a measurement method for measuring the semiconductor structure provided in the above embodiments. It should be noted that the parts that are the same as or corresponding to those in the foregoing embodiments can be found in the detailed descriptions of the foregoing embodiments, and will not be repeated hereafter.

[0068] Measurement methods include: reference Figure 1The present invention provides a first wafer 100 and a second wafer 110 in the semiconductor structure described in the above embodiments; a first bonding surface and a second bonding surface are bonded together for pre-bonding; after pre-bonding, the connection state between each first test pad 101 and the corresponding second test pad 111 is obtained, wherein if the nth first test pad 101 and the nth second test pad 111 are in a disconnected state, and the (n+1)th first test pad 101 and the (n+1)th second test pad 111 are in an interconnected state, it is determined that the second wafer 110 has a displacement of n×M relative to the first wafer 100 in the offset direction. This facilitates accurate measurement of the displacement of the second wafer 110 relative to the first wafer 100 using the test structure 120, and further uses the measured displacement to calibrate the bonding between the next first wafer 100 and the bonded second wafer 110, so that the first wafer 100 and the second wafer 110 have a small offset, which is beneficial to improving the performance of the semiconductor structure.

[0069] In some embodiments, reference Figure 1 The method for measuring the connection status between each first test pad and the corresponding second test pad 111 includes: measuring the contact resistance between the first test pad 101 and the corresponding second test pad 111; if the contact resistance is greater than or equal to a preset value, it is determined that the first test pad 101 and the corresponding second test pad 111 are in a disconnected state; if the contact resistance is less than the preset value, it is determined that the first test pad 101 and the corresponding second test pad 111 are in an interconnected state. Specifically, leads can be set to bring out the first test pad 101 and the second test pad 111, and test current can be provided to the first test pad 101 and the second test pad 111 through the leads. If the measured contact resistance between the first test pad 101 and the corresponding second test pad 111 is infinite, it can be determined that the first test pad 101 and the second test pad 111 are open circuit, that is, the first test pad 101 and the second test pad 111 are in an open state. If the measured contact resistance between the first test pad 101 and the corresponding second test pad 111 is a measurable specific resistance value, it can be determined that the first test pad 101 and the second test pad 111 are in a connected state.

[0070] In some embodiments, the connection status between the first test pad 101 and the second test pad 111 can also be measured by infrared measurement.

[0071] In the measurement method provided in the above embodiments, the displacement state of the second wafer 110 relative to the first wafer 100 is determined by testing the connection state between the first test pad 101 and the second test pad 111. Based on the connection state between the first test pad 101 and the second test pad 111, the displacement amount of the second wafer 110 relative to the first wafer 100 is obtained. Then, the bonding between the first wafer 100 and the bonded second wafer 110 is calibrated using the measured displacement amount, so that the first wafer 100 and the second wafer 110 have a small offset, which is beneficial to improving the performance of the semiconductor structure.

[0072] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own variations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A first wafer, the first wafer having a first bonding surface; The second wafer has a second bonding surface that is bonded to the first bonding surface; At least one set of test structures, the test structures including: N first test pads are arranged at intervals along a first direction within the first wafer, and the first bonding surface exposes the surface of the first test pads. N second test pads are arranged at intervals along the first direction within the second wafer, and the second bonding surface exposes the surface of the second test pads. Each second test pad is directly opposite the corresponding first test pad. Wherein, the nth second test pad is offset relative to the nth first test pad in the same offset direction parallel to the first direction, the direction in which the nth second test pad points to the first second test pad is the offset direction, and along the first direction, the width of the nth first test pad and the nth second test pad facing each other is n×M, where n is a positive integer greater than or equal to 1 and less than or equal to N, and M is a preset value.

2. The semiconductor structure as described in claim 1, characterized in that, Along the first direction, each of the first test pads exposed on the first bonding surface has the same width, and the spacing between adjacent first test pads exposed on the first bonding surface is the same.

3. The semiconductor structure as described in claim 2, characterized in that, Along the first direction, each of the second test pads exposed on the second bonding surface has the same width.

4. The semiconductor structure as described in claim 3, characterized in that, Along the first direction, the width of the first test pad exposed on the first bonding surface is the same as the width of the second test pad exposed on the second bonding surface.

5. The semiconductor structure as described in claim 1, characterized in that, The shape of the first test pad exposed on the first bonding surface is the same as the shape of the second test pad exposed on the second bonding surface.

6. The semiconductor structure as described in claim 1, characterized in that, Also includes: A first signal pad, the first bonding surface of which exposes the first signal pad; a second signal pad, the second bonding surface of which exposes the second signal pad, and the first signal pad and the second signal pad are directly opposite each other.

7. The semiconductor structure as described in claim 6, characterized in that, Along the first direction, the width of the first signal pad exposed on the first bonding surface is the same as the width of the second signal pad exposed on the second bonding surface.

8. The semiconductor structure as described in claim 1, characterized in that, The first wafer has a first central region and a first edge region, and the second wafer has a second central region and a second edge region. The first central region and the second central region are directly opposite each other, and the first edge region and the second edge region are directly opposite each other. The first central region and the directly opposite second central region have corresponding test structures, and the first edge region and the directly opposite second edge region also have corresponding test structures.

9. The semiconductor structure as described in claim 1, characterized in that, The first wafer includes a plurality of first chips, and the second wafer includes a plurality of second chips, each of the first chips being opposite to a corresponding second chip; a portion of the first chips and the opposite second chips have the corresponding test structure.

10. The semiconductor structure as described in claim 9, characterized in that, Both the first chip and the second chip have a central chip region and a chip edge region. The central chip region of the first chip and the central chip region of the second chip are directly opposite each other, and the chip edge regions of the first chip and the second chip are directly opposite each other. The test structure is located in the central chip region and the chip edge region of the opposite chip.

11. The semiconductor structure as described in claim 9, characterized in that, Both the first chip and the second chip have a central chip region, and the central chip region of the first chip and the central chip region of the opposite second chip are directly opposite each other. The first wafer also includes a first dicing channel located at the edge of the first chip, and the second wafer also includes a second dicing channel located at the edge of the second chip and directly opposite the corresponding first dicing channel. The test structure is located in the central chip region directly opposite each other, and is located within the first dicing channel and the opposite second dicing channel.

12. The semiconductor structure as described in claim 1, characterized in that, The first direction includes the X direction; the semiconductor structure has at least two sets of the test structures, wherein the offset direction in at least one set of the test structures is the +X direction, and the offset direction in at least another set of the test structures is the -X direction.

13. The semiconductor structure as described in claim 1, characterized in that, The first direction includes the Y direction; the semiconductor structure has at least two sets of the test structures, wherein the offset direction in at least one set of the test structures is the +Y direction, and the offset direction in at least another set of the test structures is the -Y direction.

14. The semiconductor structure as described in claim 1, characterized in that, The material of the first test pad is the same as that of the second test pad.

15. A measurement method, characterized in that, include: Provides the first wafer and the second wafer in any of the semiconductor structures described in claims 1-14; The first bonding surface and the second bonding surface are attached together for pre-bonding; After the pre-bonding is performed, the connection status between each first test pad and the corresponding second test pad is obtained. If the nth first test pad and the nth second test pad are in a disconnected state, and the (n+1)th first test pad and the (n+1)th second test pad are in an interconnected state, then it is determined that the second wafer has been displaced by an amount of n×M relative to the first wafer in the offset direction.

16. The measurement method as described in claim 15, characterized in that, The methods for measuring the connection status between each first test pad and the corresponding second test pad include: Measure the contact resistance between the first test pad and the corresponding second test pad; If the contact resistance is greater than or equal to the preset value, it is determined that the first test pad and the corresponding second test pad are in a disconnected state. If the contact resistance is less than the preset value, it is determined that the first test pad and the corresponding second test pad are in an interconnected state.

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