Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a base, a fin, and an isolation layer, the isolation layer being located between adjacent fins, and the isolation layer surface being lower than the top surface of the fin; forming a plurality of mutually discrete gate structures on the isolation layer, the gate structures spanning the top surface and the side wall surface of the fin; forming source and drain openings in the fins on both sides of the gate structure; using a first selective epitaxial growth process to form a buffer layer on the inner wall surface of the source and drain opening; after forming the buffer layer, performing a first back-etching on the surface of the gate structure; using a second selective epitaxial growth process to form a body layer on the surface of the buffer layer in the source and drain opening; after forming the body layer, performing a second back-etching on the surface of the gate structure; after the second back-etching, forming a cap layer on the surface of the body layer. Thus, the production efficiency of the semiconductor structure is improved while the reliability of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] As integrated circuits develop towards very large scale integrated circuits, the circuit density inside integrated circuits is increasing, the number of components contained is increasing, and the size of components is also decreasing. As the size of semiconductor structures decreases, the channel of devices in semiconductor structures is shortened. Due to the shortening of the channel, the gradual channel approximation is no longer valid, and various adverse physical effects (especially the short channel effect) are highlighted, which causes the performance and reliability of devices to degrade, limiting the further reduction of device size.

[0003] In order to overcome the short channel effect of the device and suppress leakage current, the prior art proposes a fin field effect transistor (Fin FET). The fin field effect transistor is a common multi-gate device. The structure of the fin field effect transistor includes: a fin and an isolation layer located on the surface of a semiconductor substrate, the isolation layer covers a portion of the side wall of the fin, and the surface of the isolation layer is lower than the top of the fin; a gate structure located on the surface of the isolation layer, and the top and side wall surfaces of the fin; and a source region and a drain region in the fin located on both sides of the gate structure.

[0004] However, in the prior art, the production efficiency and reliability of semiconductor structures still need to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, so as to improve the production efficiency of the semiconductor structure and at the same time improve the reliability of the semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a base, a plurality of mutually discrete fins located on the base, and an isolation layer located on the surface of the base, the isolation layer is also located between adjacent fins, and the surface of the isolation layer is lower than the top surface of the fin; forming a plurality of mutually discrete gate structures on the isolation layer, the gate structure spanning the top surface and side wall surface of the fin; forming source and drain openings in the fins on both sides of the gate structure; adopting a first selective epitaxial growth process to form a buffer layer on the inner wall surface of the source and drain opening; after forming the buffer layer, performing a first back-etching on the surface of the gate structure; adopting a second selective epitaxial growth process to form a body layer on the surface of the buffer layer in the source and drain opening; after forming the body layer, performing a second back-etching on the surface of the gate structure; after the second back-etching, forming a cap layer on the surface of the body layer.

[0007] Optionally, the material of the buffer layer includes SiP, and the material of the body layer includes SiP.

[0008] Optionally, the first back etching process includes a dry etching process.

[0009] Optionally, in the first back-etching process, the duration ranges from 20 seconds to 40 seconds, and in the second back-etching process, the duration ranges from 70 seconds to 90 seconds.

[0010] Optionally, the second back-etching process includes a dry etching process, and a flow rate of a reaction gas in the second back-etching is greater than a flow rate of a reaction gas in the first back-etching.

[0011] Optionally, in the first back-etching process, the reaction gas includes hydrogen and hydrogen chloride gas; in the second back-etching process, the reaction gas includes hydrogen and hydrogen chloride gas.

[0012] Optionally, in the first etching process, the flow range of the reaction gas is 5 L / min to 15 L / min for hydrogen gas, and the flow range of the hydrogen chloride gas is 110 ml / min to 130 ml / min.

[0013] Optionally, the gate structure includes a gate and a sidewall spacer located on a sidewall of the gate.

[0014] Optionally, the method for forming the gate structure includes: forming a gate material layer on the isolation layer; forming a plurality of discrete gate mask structures on the surface of the gate material layer; etching the gate material layer with the gate mask structure until the surface of the isolation layer is exposed to form the gate; and forming the sidewalls on the side walls of the gate and the gate mask structure.

[0015] Optionally, it also includes: after forming the cap layer, forming a dielectric layer on the substrate and the body layer, the dielectric layer is also located on the side walls of the sidewalls; after forming the dielectric layer, removing the gate mask structure and the gate, forming a gate opening in the dielectric layer; and forming a metal gate in the gate opening.

[0016] Optionally, the material of the gate includes polysilicon or amorphous silicon.

[0017] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0018] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the first back-etching is used to remove the buffer layer defect seeds on the surface of the gate structure, and the second back-etching is used to remove the body layer defect seeds on the surface of the gate structure. Since the first back-etching is performed on the surface of the gate structure after the buffer layer is formed and before the body layer is formed, the buffer layer defect seeds remaining on the surface of the gate structure are reduced, and the surface area of ​​the buffer layer defect seeds remaining on the surface of the gate structure is also reduced. Therefore, the body layer material grown on the surface of the buffer layer defect seeds can be reduced, so that the second back-etching removes the body layer defect seeds quickly and effectively, and the body layer defect seeds remaining after the second back-etching are less. In addition, compared with the etching process in the first selective epitaxial growth process, the first back-etching is an independent etching process mainly for the surface of the gate structure. Therefore, the control independence of the flow rate of the reaction gas and the etching angle is high, and the upper limit of the etching intensity is also high. Therefore, the first back-etching can achieve the effect of removing the buffer layer material on the surface of the gate structure in a relatively short time. In summary, the method for forming a semiconductor structure can improve the production efficiency of the semiconductor structure while reducing the short circuit risk caused by the buffer layer material and the body layer material remaining on the surface of the gate structure, thereby improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figures 1 to 3 It is a schematic diagram of the cross-sectional structure of each step in the formation process of a semiconductor structure;

[0020] Figures 4 to 9 It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] As described in the background art, while the production efficiency of semiconductor structures is improved, the reliability of existing semiconductor structures still needs to be improved.

[0022] Figures 1 to 3 It is a schematic diagram of the cross-sectional structure of each step in the formation process of a semiconductor structure.

[0023] Please refer to Figure 1 , providing a substrate 100 ; forming a plurality of mutually independent gate structures 110 on the substrate 100 ; forming source and drain openings 101 in the substrate 100 on both sides of the gate structures 110 .

[0024] Please refer to Figure 2 A source-drain structure is formed in the source-drain opening 101 by a selective epitaxial growth process. The source-drain structure includes a buffer layer 121 located on the inner wall of the source-drain opening 101 and a body layer 122 located on the surface of the buffer layer 121 .

[0025] Please refer to Figure 3 After forming the body layer 122, the surface of the gate structure 110 is etched to remove the source and drain structure materials (such as Figure 2 as shown in area A in the figure).

[0026] In the selective epitaxial growth process, usually, by controlling the composition, flow rate, duration and other parameters of the reaction gas introduced in the selective epitaxial growth process, the material growth of the buffer layer 121 and the body layer 122 and the material etching of the buffer layer 121 and the body layer 122 are carried out simultaneously to achieve the selectivity of the epitaxial growth process.

[0027] Specifically, while growing the materials of the buffer layer 121 and the body layer 122, since the materials on the surface of the gate structure 110 are different from the materials on the inner wall of the source-drain opening 101, the internal microstructures such as the crystal state of the materials of the buffer layer 121 and the body layer 122 grown on the surface of the gate structure 110 and the materials of the buffer layer 121 and the body layer 122 grown on the inner wall of the source-drain opening 101 are different. Therefore, in the process of etching the materials of the buffer layer 121 and the body layer 122, the etching rate of the materials of the buffer layer 121 and the body layer 122 grown on the surface of the gate structure 110 can be made greater than the etching rate of the materials of the buffer layer 121 and the body layer 122 grown on the inner wall of the source-drain opening 101. Therefore, in the process of simultaneously growing the materials of the buffer layer 121 and the body layer 122 and etching the materials of the buffer layer 121 and the body layer 122, the selectivity of the epitaxial growth process is improved.

[0028] However, in the above-mentioned embodiment, in order to make the epitaxial growth process more selective, it is necessary to better balance the material growth of the buffer layer 121 and the body layer 122 and the material etching rates of the buffer layer 121 and the body layer 122 that are carried out simultaneously. On the one hand, in order to prevent the materials of the buffer layer 121 and the body layer 122 grown on the inner wall of the source and drain opening 101 from being quickly etched, the selective epitaxial growth process takes a long time. On the other hand, since the etching direction is difficult to be controlled alone, the time required for the selective epitaxial growth process is also increased. As a result, the production efficiency of the semiconductor structure is very low.

[0029] In order to solve the problem of low production efficiency of semiconductor structures, another method for forming a semiconductor structure is proposed, wherein the etching of the materials of the buffer layer 121 and the body layer 122 in the selective epitaxial growth process is reduced, so that the growth rate of the materials of the buffer layer 121 and the body layer 122 is faster, thereby greatly reducing the time spent in the selective epitaxial growth process, thereby achieving an improvement in the production efficiency of the semiconductor structure and an increase in the wafer output per hour (WPH).

[0030] However, since the etching of the materials of the buffer layer 121 and the body layer 122 in the selective epitaxial growth process is reduced, the growth selectivity of the buffer layer 121 material will be deteriorated, thereby causing the increase of the buffer layer 121 material on the surface of the gate structure 110, so that the surface area of ​​the buffer layer 121 material on the surface of the gate structure 110 is increased, and then the material of the body layer 122 formed on the surface of the gate structure 110 is also increased, that is, the material of the buffer layer 121 and the body layer 122 on the surface of the gate structure 110 are increased. Due to the increase of the materials of the buffer layer 121 and the body layer 122 on the surface of the gate structure 110 (such as Figure 3 As shown in the middle area A), after etching the surface of the gate structure 110, a large amount of source-drain structure material remains on the surface of the gate structure 110, resulting in a high risk of short circuit in the formed semiconductor device, resulting in poor reliability of the semiconductor device.

[0031] In order to solve the problem of a large amount of source-drain structure material remaining on the surface of the gate structure 110, another method for forming a semiconductor structure is proposed. Specifically, by increasing the etching time or increasing the flow rate of the reaction gas in the etching process, the etching intensity on the surface of the gate structure 110 is increased to better remove the materials of the buffer layer 121 and the body layer 122 on the surface of the gate structure 110. However, since the etching of the surface of the gate structure 110 is performed after the body layer 112 is formed, and the etching intensity is increased, while removing the materials of the buffer layer 121 and the body layer 122 on the surface of the gate structure 110, it is easy to cause damage to the surface of the source-drain structure, resulting in poor performance and reliability of the semiconductor device.

[0032] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, by performing a first back-etching on the surface of the gate structure after forming the buffer layer and before forming the body layer, and performing a second back-etching on the surface of the gate structure after forming the body layer, thereby improving the production efficiency of the semiconductor structure while improving the reliability of the semiconductor structure.

[0033] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] Figures 4 to 9 It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0035] Please refer to Figure 4 , providing a substrate 200.

[0036] The substrate 200 is made of a semiconductor material.

[0037] In this embodiment, the material of the substrate 200 is silicon.

[0038] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, multinary semiconductor materials composed of III-V group elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, multinary semiconductor materials composed of III-V group elements include InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0039] In this embodiment, the substrate 200 includes: a base (not shown), a plurality of mutually discrete fins (not shown) located on the base, and an isolation layer located on the surface of the base, wherein the isolation layer is also located between adjacent fins, and the surface of the isolation layer is lower than the top surface of the fin.

[0040] The isolation layer functions to electrically insulate adjacent fins and between the semiconductor device and the substrate.

[0041] Please continue to refer to Figure 4 , a plurality of mutually independent gate structures 210 are formed on the isolation layer.

[0042] In this embodiment, the gate structure 210 spans across the top surface and sidewall surfaces of the fin.

[0043] In this embodiment, the gate structure 210 includes: a gate oxide layer (not shown), a gate 211 located on the surface of the gate oxide layer, and a sidewall spacer 212 located on the gate oxide layer and the sidewall of the gate.

[0044] In this embodiment, the gate mask structure 213 is used to pattern the gate oxide material film and the gate material layer to form the gate oxide layer and the gate 211. On the other hand, the gate mask structure 213 and the sidewall 212 are used to protect the surface of the gate 211 and the gate oxide layer, and reduce the damage to the gate 211 and the gate oxide layer in the subsequent etching process for forming the source and drain structure. In addition, in the subsequent selective epitaxial growth process for forming the source and drain structure, since the gate mask structure 213 and the sidewall 212 are made of different materials from the substrate 200, the selectivity of the epitaxial growth process is also achieved.

[0045] In this embodiment, the spacer 212 is also used to define the positions of source and drain openings later.

[0046] In this embodiment, the material of the gate includes polysilicon or amorphous silicon.

[0047] In this embodiment, the material of the gate oxide layer includes silicon oxide.

[0048] In this embodiment, the material of the spacer 212 includes a low-k dielectric material (k is less than 3.9) or a combination of multiple low-k dielectric materials, such as SiOC, SiOCN, and SiOCH.

[0049] In this embodiment, the material of the gate mask structure 213 includes silicon nitride.

[0050] In other embodiments, the material of the gate mask structure further includes silicon oxide between the silicon nitride and the gate.

[0051] In this embodiment, the method for forming the gate structure 210 includes: forming a gate oxide material film (not shown) on the isolation layer; forming a gate material layer (not shown) on the surface of the gate oxide material film; forming a plurality of separate gate mask structures 213 on the surface of the gate material layer; etching the gate material layer and the gate oxide material film with the gate mask structure 213 until the surface of the isolation layer is exposed to form the gate 211 and the gate oxide layer; and forming the sidewalls 212 on the sidewalls of the gate oxide layer, the gate 211 and the gate mask structure 213.

[0052] In this embodiment, the process for forming the gate material layer includes: an epitaxial growth process or a deposition process, etc. The deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process, etc.

[0053] Please refer to Figure 5 , source and drain openings 201 are formed in the fins on both sides of the gate structure 210 .

[0054] The source-drain openings 201 provide space for subsequently forming source-drain structures.

[0055] In this embodiment, the method for forming the source-drain opening 201 includes: forming a source-drain mask layer (not shown) on the surface of the substrate 200 and the surface of the gate structure 210, the source-drain mask layer exposing the surface of the substrate 200 between adjacent gate structures 210; using the source-drain mask layer and the side wall 212 as a mask, etching the substrate 200 to form source-drain openings 201 in the substrate 200 on both sides of the gate structure 210.

[0056] In this embodiment, the etching process for forming the source / drain openings 210 includes at least one of a dry etching process and a wet etching process.

[0057] In this embodiment, after the source / drain openings 201 are formed, the source / drain mask layer is removed.

[0058] Please refer to Figure 6 , a buffer layer 220 is formed on the inner wall surface of the source / drain opening 201 by using a first selective epitaxial growth process.

[0059] In the first selective epitaxial growth process, by controlling process parameters, such as the composition, flow rate, duration and other parameters of the introduced reaction gas, the material growth of the buffer layer 220 and the material etching of the buffer layer 220 are performed simultaneously to achieve the selectivity of the epitaxial growth process.

[0060] In the first selective epitaxial growth process of the present embodiment, while growing the material of the buffer layer 220, since the material on the surface of the gate structure 210 is different from the material on the inner wall of the source-drain opening 201, the internal microstructures such as the crystal state of the material of the buffer layer 220 grown on the surface of the gate structure 210 and the material of the buffer layer 220 grown on the inner wall of the source-drain opening 201 are different. Therefore, in the process of etching the material of the buffer layer 220, the etching rate of the material of the buffer layer 220 grown on the surface of the gate structure 210 can be made greater than the etching rate of the material of the buffer layer 220 grown on the inner wall of the source-drain opening 201. Thus, the selectivity of the epitaxial growth process is achieved.

[0061] On this basis, in the first selective epitaxial growth process of the present embodiment, by reducing and increasing parameters such as the gas flow rate for forming the buffer layer 220 material and reducing parameters such as the gas flow rate for etching the buffer layer 220 material, the growth rate of the buffer layer 220 material is greatly accelerated, and the time spent in the first selective epitaxial growth process is reduced, thereby achieving an improvement in the production efficiency of the semiconductor structure and an increase in the wafer output per hour (WPH).

[0062] Specifically, in this embodiment, the duration of the first selective epitaxial growth process is 170 seconds to 190 seconds. Preferably, the duration of the first selective epitaxial growth process is 180 seconds.

[0063] However, in the first selective epitaxial growth process, while the growth rate of the buffer layer 220 material is greatly accelerated, the growth selectivity of the buffer layer 220 material is deteriorated, so that more buffer layer defect seeds 221 remain on the surface of the gate structure 210 .

[0064] In this embodiment, the material of the buffer layer 220 includes SiP.

[0065] In this embodiment, the buffer layer 220 is located in the fins on both sides of the gate structure 210 .

[0066] Please refer to Figure 7 After forming the buffer layer 220 , a first back etching is performed on the surface of the gate structure 210 .

[0067] The first etching back is used to remove the buffer layer defect seeds 221 on the surface of the gate structure 210 .

[0068] Since the first etching is performed on the surface of the gate structure after the buffer layer is formed and before the body layer is formed, the buffer layer defect seeds 221 remaining on the surface of the gate structure are reduced and the surface area of ​​the buffer layer defect seeds 221 remaining on the surface of the gate structure is also reduced. Therefore, the body layer material subsequently grown on the surface of the buffer layer defect seeds 221 can be reduced and reduced (the body layer defect seeds become fewer and smaller), so that the subsequent second etching to remove the body layer defect seeds is fast and effective, and the body layer defect seeds remaining after the second etching are fewer and smaller.

[0069] At the same time, since the first back-etching and the second back-etching have a good effect in removing the buffer layer defect seeds 221 and the body layer defect seeds, when the buffer layer 220 and the body layer are grown rapidly, that is, when the duration of the first selective epitaxial growth process and the subsequent second selective epitaxial growth process is greatly reduced and the selectivity becomes worse, the buffer layer defect seeds 221 and the body layer defect seeds remaining on the surface of the gate structure 210 can still be reduced, which is beneficial to taking into account the formation efficiency and reliability of the semiconductor structure.

[0070] Moreover, compared with the etching process in the first selective epitaxial growth process, the first back-etching is an independent etching process mainly for the surface of the gate structure 210. Therefore, the control independence of the flow rate of the reaction gas and the etching angle is high, and the upper limit of the etching intensity is also high, so that the first back-etching can achieve the effect of removing the buffer layer material on the surface of the gate structure 210 in a relatively short time. Furthermore, the duration of the first back-etching can be much shorter than the duration reduced by reducing etching in the first selective epitaxial growth process, so that the duration of the first back-etching has less impact on the improvement of production efficiency and the increase of wafer output per hour (WPH, Wafer Per Hour).

[0071] In summary, the method for forming a semiconductor structure can improve the production efficiency of the semiconductor structure while reducing the short circuit risk caused by the buffer layer material and the body layer material remaining on the surface of the gate structure, thereby improving the reliability of the semiconductor structure.

[0072] In this embodiment, the first back etching process includes a dry etching process.

[0073] In this embodiment, the duration of the first back-etching process is in the range of 20 seconds to 40 seconds. Preferably, the duration of the first back-etching process is 30 seconds.

[0074] In this embodiment, in the first back-etching process, the reaction gas includes: hydrogen gas and hydrogen chloride gas.

[0075] In this embodiment, in the first etching process, the flow rate of hydrogen is in the range of 5 liters / minute to 15 liters / minute, and the flow rate of hydrogen chloride is in the range of 110 milliliters / minute to 130 milliliters / minute. Preferably, the flow rate of hydrogen is 10 liters / minute, and the flow rate of hydrogen chloride is 120 milliliters / minute.

[0076] By controlling the duration and the flow rate of the reaction gas in the first back-etching, on the one hand, the residual buffer layer defect seeds 221 on the surface of the gate structure 210 are effectively reduced, and on the other hand, the adverse effect on improving the production efficiency of the semiconductor structure is reduced. In addition, the risk of damage to the buffer layer 220 caused by the first back-etching is also reduced.

[0077] Please refer to Figure 8 , a second selective epitaxial growth process is used to form a body layer 230 on the surface of the buffer layer 220 in the source / drain opening 201 .

[0078] In the second selective epitaxial growth process, by controlling process parameters, such as the composition, flow rate, duration and other parameters of the introduced reaction gas, material growth of the body layer 230 and material etching of the body layer 230 are performed simultaneously to achieve the selectivity of the epitaxial growth process.

[0079] Similarly, in the second selective epitaxial growth process of the present embodiment, while the material of the body layer 230 is grown, since the material on the surface of the gate structure 210 is different from the material on the surface of the buffer layer 220, the internal microstructures such as the crystal state of the material of the body layer 230 grown on the surface of the gate structure 210 and the material of the body layer 230 grown on the surface of the buffer layer 220 are different. Therefore, in the process of etching the material of the body layer 230, the etching rate of the material of the body layer 230 grown on the surface of the gate structure 210 can be made greater than the etching rate of the material of the body layer 230 grown on the surface of the buffer layer 220. Thus, the selectivity of the epitaxial growth process is achieved.

[0080] On this basis, in the second selective epitaxial growth process of this embodiment, by reducing and increasing parameters such as the gas flow rate for forming the body layer 230 material and reducing parameters such as the gas flow rate for etching the body layer 230 material, the growth rate of the body layer 230 material is greatly accelerated, and the time spent in the second selective epitaxial growth process is reduced, thereby further improving the production efficiency of the semiconductor structure and increasing the wafer output per hour (WPH, Wafer Per Hour).

[0081] At the same time, since the first back etching reduces the buffer layer defect seeds 221 remaining on the surface of the gate structure 210 and reduces the surface area of ​​the buffer layer defect seeds 221 remaining on the surface of the gate structure 210, in the process of forming the body layer 230, the body layer defect seeds 231 grown by the buffer layer defect seeds 221 are reduced and become smaller.

[0082] Specifically, in this embodiment, the duration of the second selective epitaxial growth process ranges from 310 to 320 seconds. Preferably, the duration of the second selective epitaxial growth process is 315 seconds.

[0083] In this embodiment, the material of the body layer 230 includes SiP.

[0084] In this embodiment, the body layer 230 is also located in the fins on both sides of the gate structure 210 .

[0085] Please refer to Fig. 9 After the body layer 230 is formed, a second back etching is performed on the surface of the gate structure 210 .

[0086] The second etching back is used to remove the bulk layer defect seeds 231 .

[0087] It should be understood that, since the body layer defect seeds 231 mainly grow on the surface of the buffer layer defect seeds 221 , the body layer defect seeds 231 include the buffer layer defect seeds 221 .

[0088] In this embodiment, the second back-etching process includes a dry etching process, and the flow rate of the reaction gas in the second back-etching is greater than the flow rate of the reaction gas in the first back-etching.

[0089] The flow rate of the reaction gas in the second back-etching is greater than the flow rate of the reaction gas in the first back-etching, which can speed up the removal speed of the body layer defect seeds 231 by the second back-etching. At the same time, since the thickness and volume of the body layer 230 are much greater than the buffer layer 220, even if the flow rate of the reaction gas in the second back-etching is greater than the flow rate of the reaction gas in the first back-etching, the risk of damage to the body layer 230 is relatively small. Therefore, the second back-etching can effectively remove the body layer defect seeds 231, and at the same time, the risk of causing damage to the body layer 230 is relatively small.

[0090] In this embodiment, in the second etching process, the reaction gas includes hydrogen gas and hydrogen chloride gas.

[0091] In this embodiment, in the second etching process, the flow rate of hydrogen is in the range of 5-15 liters / minute, and the flow rate of hydrogen chloride is in the range of 450-550 milliliters / minute. Preferably, the flow rate of hydrogen is 10 liters / minute, and the flow rate of hydrogen chloride is 500 milliliters / minute.

[0092] In this embodiment, the duration of the second back-etching is longer than that of the first back-etching. Similarly, the removal speed of the body layer defect seeds 231 by the second back-etching can be accelerated. At the same time, since the thickness and volume of the body layer 230 are much larger than the buffer layer 220, even if the duration of the second back-etching is longer than that of the first back-etching, the risk of damage to the body layer 230 is relatively small. Therefore, the second back-etching can effectively remove the body layer defect seeds 231, and at the same time, the risk of causing damage to the body layer 230 is relatively small.

[0093] In this embodiment, the duration of the second back-etching process is in the range of 70 seconds to 90 seconds. Preferably, the duration of the second back-etching process is 80 seconds.

[0094] In this embodiment, after the second etch-back, a capping layer (not shown) is formed on the surface of the body layer 230 .

[0095] The buffer layer 220 , the body layer 230 and the cap layer form a source-drain structure.

[0096] In this embodiment, the method for forming the semiconductor structure also includes: after forming the cap layer, forming a dielectric layer (not shown) on the substrate 200 and the body layer, and the dielectric layer is also located on the side walls of the sidewall 212; after forming the dielectric layer, removing the gate mask structure 213 and the gate 211, and forming a gate opening (not shown) in the dielectric layer; after forming the gate opening, forming a metal gate (not shown) in the gate opening.

[0097] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a base, a plurality of mutually discrete fins located on the base, and an isolation layer located on a surface of the base, the isolation layer is also located between adjacent fins, and a surface of the isolation layer is lower than a top surface of the fin; forming a plurality of mutually discrete gate structures on the isolation layer, wherein the gate structures span the top surface and the sidewall surface of the fin; forming source and drain openings in the fins on both sides of the gate structure; Using a first selective epitaxial growth process to form a buffer layer on the inner wall surface of the source and drain openings; After forming the buffer layer and before forming the body layer, performing a first back etching on the surface of the gate structure to remove the buffer layer defect seeds on the surface of the gate structure; Using a second selective epitaxial growth process to form a body layer on the surface of the buffer layer in the source and drain openings; After forming the body layer, performing a second back etching on the surface of the gate structure to remove body layer defect seeds on the surface of the gate structure; After the second back etching, forming a cap layer on the surface of the body layer; In the first selective epitaxial growth process, the growth of the buffer layer material and the etching of the buffer layer material are performed simultaneously; in the second selective epitaxial growth process, the growth of the bulk layer material and the etching of the bulk layer material are performed simultaneously.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the buffer layer includes SiP, and the material of the body layer includes SiP.

3. The method for forming a semiconductor structure according to claim 1, wherein: The first etching process includes a dry etching process.

4. The method for forming a semiconductor structure according to claim 3, wherein: In the first etching process, the duration ranges from 20 seconds to 40 seconds, and in the second etching process, the duration ranges from 70 seconds to 90 seconds.

5. The method for forming a semiconductor structure according to claim 3, wherein: The second back-etching process includes a dry etching process, and a flow rate of a reaction gas in the second back-etching is greater than a flow rate of a reaction gas in the first back-etching.

6. The method for forming a semiconductor structure according to claim 5, wherein: In the first etching process, the reaction gas includes hydrogen and hydrogen chloride gas; in the second etching process, the reaction gas includes hydrogen and hydrogen chloride gas.

7. The method for forming a semiconductor structure according to claim 6, wherein: In the first etching process, the flow rate of hydrogen gas is in the range of 5 liters / minute to 15 liters / minute, and the flow rate of hydrogen chloride gas is in the range of 110 milliliters / minute to 130 milliliters / minute.

8. The method for forming a semiconductor structure according to claim 1, wherein: The gate structure includes a gate and a sidewall located on a sidewall of the gate.

9. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the gate structure includes: forming a gate material layer on the isolation layer; forming a plurality of mutually discrete gate mask structures on the surface of the gate material layer; etching the gate material layer with the gate mask structure until the surface of the isolation layer is exposed to form the gate; and forming the sidewalls on the sidewalls of the gate and the gate mask structure.

10. The method for forming a semiconductor structure according to claim 9, wherein: Also includes: After forming the cap layer, forming a dielectric layer on the substrate and the body layer, wherein the dielectric layer is also located on the sidewalls of the spacer; After forming the dielectric layer, the gate mask structure and the gate are removed, and a gate opening is formed in the dielectric layer; and a metal gate is formed in the gate opening.

11. The method for forming a semiconductor structure according to claim 8, wherein: The gate is made of polysilicon or amorphous silicon.

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