Manufacturing method of semiconductor device

Abstract

The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of a semiconductor device. Comprising the following steps: providing a semiconductor substrate; forming a deep trench isolation structure in the isolation region, wherein the upper surface of the deep trench isolation structure is higher than the upper surface of the active region by a specific height; sequentially performing first etching and second etching on the active region of the high-voltage device region and the edge part, close to the active region, of the deep trench isolation structure of the high-voltage device region; etching the edge part, close to the active region, of the deep trench isolation structure of the high-voltage device region after the first etching and the second etching, and reducing the height difference between the upper surface of the active region of the high-voltage device region and the upper surface of the edge part, close to the active region, of the deep trench isolation structure of the high-voltage device region; and depositing to form a high-voltage oxide layer, wherein the high-voltage oxide layer covers the upper surface of the active region of the high-voltage device region and the upper surface of the edge part, close to the active region, of the deep trench isolation structure of the high-voltage device region.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] As the size of transistors continues to shrink, metal gates have replaced polysilicon gates and become an indispensable part of the process below 28nm.

[0003] The gate oxide process in the existing high-voltage MOS tube is to directly grow a gate oxide layer on the surface of a silicon substrate. However, since the thickness of the gate oxide layer of the high-voltage MOS tube and the medium-voltage MOS tube is thicker than the thickness of the gate oxide layer of the low-voltage MOS tube on the same wafer, in the high-voltage MOS tube and the medium-voltage MOS tube, the high-voltage gate oxide layer and the medium-voltage gate oxide layer grown according to the existing process have a large step difference on their respective active areas and isolation areas.

[0004] During the metal gate manufacturing process, since all devices on the same wafer are ground at the same time, the gate oxide layers of the high-voltage MOS tube region and the medium-voltage MOS tube region at the junction of their respective active regions and isolation regions are ground unevenly due to the large step difference, resulting in the metal gates formed in the high-voltage MOS tube region and the medium-voltage MOS tube region having regions that are too thin, which can easily cause the contact holes manufactured subsequently to easily penetrate the metal gates of the high-voltage MOS tube region and the medium-voltage MOS tube region, thereby causing the performance failure of the device. Summary of the invention

[0005] The present application provides a method for manufacturing a semiconductor device, which can solve the problem in the related art that the gate oxide layer at the junction of the active area and the isolation area of ​​the high-voltage MOS tube area and the medium-voltage MOS tube area has a large step difference.

[0006] In order to solve the technical problem in the background technology, the present application provides a method for manufacturing a semiconductor device, and the method for manufacturing a semiconductor device comprises the following steps:

[0007] Providing a semiconductor substrate, the semiconductor substrate comprising a high voltage device region, a medium voltage device region and a low voltage device region, wherein the high voltage device region, the medium voltage device region and the low voltage device region each comprise an active region and an isolation region;

[0008] A deep trench isolation structure is formed in the isolation region, wherein the upper surface of the deep trench isolation structure is higher than the upper surface of the active region by a specific height;

[0009] Sequentially performing a first etching and a second etching on the active area of ​​the high-voltage device area and the edge portion of the deep trench isolation structure of the high-voltage device area close to the active area; wherein the etching amount in the first etching accounts for 70% to 85% of the total etching amount, and the total etching amount is the total etching amount of the first etching and the second etching;

[0010] Etching the edge portion of the deep trench isolation structure of the high voltage device region close to the active region after the first etching and the second etching to reduce the height difference between the upper surface of the active region of the high voltage device region and the upper surface of the edge portion of the deep trench isolation structure of the high voltage device region close to the active region;

[0011] A high-voltage oxide layer is formed by deposition, and the high-voltage oxide layer covers the upper surface of the active area of ​​the high-voltage device area and the upper surface of the edge portion of the deep trench isolation structure of the high-voltage device area close to the active area.

[0012] Optionally, the step of sequentially performing a first etching and a second etching on the active area of ​​the high-voltage device area and the edge portion of the deep trench isolation structure of the high-voltage device area close to the active area; wherein the etching amount in the first etching accounts for 70% to 85% of the total etching amount, and the total etching amount is the total etching amount of the first etching and the second etching, comprises:

[0013] A high-voltage oxide layer mask pattern structure is formed on the semiconductor substrate, wherein the active area of ​​the high-voltage device region and the edge portion of the deep trench isolation structure of the high-voltage device region close to the active area are exposed from the high-voltage oxide layer mask pattern structure;

[0014] Based on the high-voltage oxide layer mask pattern structure, performing a first etching according to a first etching amount on the structure exposed from the high-voltage oxide layer mask pattern structure;

[0015] Based on the first etching, and again based on the high-voltage oxide layer mask pattern structure, performing a second etching according to a second etching amount on the structure exposed from the high-voltage oxide layer mask pattern structure;

[0016] The first etching amount accounts for 70% to 85% of the total etching amount, and the total etching amount is the sum of the first etching amount and the second etching amount.

[0017] Optionally, the step of forming a high-voltage oxide layer mask pattern structure on the semiconductor substrate, wherein the active area of ​​the high-voltage device area and the edge portion of the deep trench isolation structure of the high-voltage device area close to the active area are exposed from the high-voltage oxide layer mask pattern structure, comprises:

[0018] Depositing a hard mask layer on the semiconductor substrate;

[0019] The hard mask layer is etched by a photolithography and etching process to form a high-voltage oxide layer mask pattern structure, wherein the high-voltage oxide layer mask pattern structure includes a high-voltage oxide layer forming window; an active area of ​​the high-voltage device area, and an edge portion of a deep trench isolation structure of the high-voltage device area close to the active area are exposed from the high-voltage oxide layer forming window.

[0020] Optionally, the step of performing a first etching according to a first etching amount on the structure exposed from the high-voltage oxide layer mask pattern structure based on the high-voltage oxide layer mask pattern structure comprises:

[0021] In an atmosphere containing any one or more of nitrogen tetrafluoride, nitrogen trifluoride, and chlorine, a dry etching plasma is generated, so that the dry etching plasma bombards a device with the high-voltage oxide layer mask pattern structure, and a first etching is performed on a structure exposed from the high-voltage oxide layer mask pattern structure according to a first etching amount.

[0022] Optionally, the step of performing a second etching according to a second etching amount on the structure exposed from the high-voltage oxide layer mask pattern structure based on the first etching again based on the high-voltage oxide layer mask pattern structure comprises:

[0023] On the basis of the first etching, a dry etching plasma is generated in a gas atmosphere containing any one or more combinations of nitrogen tetrafluoride, nitrogen trifluoride, and chlorine, so that the dry etching plasma bombards the device with the high-voltage oxide layer mask pattern structure, and performs a second etching on the structure exposed from the high-voltage oxide layer mask pattern structure according to a second etching amount.

[0024] Optionally, the method further comprises the following steps:

[0025] The edge portion of the deep trench isolation structure of the medium voltage device area close to the active area is etched to reduce the height difference between the upper surface of the active area of ​​the medium voltage device area and the upper surface of the edge portion of the deep trench isolation structure of the medium voltage device area close to the active area.

[0026] A medium voltage oxide layer is formed by deposition, and the medium voltage oxide layer covers the upper surface of the active area of ​​the medium voltage device area and the upper surface of the edge portion of the deep trench isolation structure of the medium voltage device area close to the active area.

[0027] The technical solution of the present application includes at least the following advantages: the present application improves the height uniformity of the high-voltage oxide layer or the medium-voltage oxide layer and the upper surface of the isolation structure so that the thickness uniformity of the metal gate is greater in the subsequent process of manufacturing the metal gate, thereby avoiding the appearance of too thin thickness areas in the manufactured metal gate, thereby paving the way for improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 A flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application is shown;

[0030] Figure 2 A schematic diagram of the longitudinal cross-sectional structure of the semiconductor substrate provided in step S1 is shown;

[0031] Figure 3 A schematic diagram of the longitudinal cross-sectional structure of the device after step S2 is completed is shown;

[0032] Figure 4 shows a schematic diagram of the longitudinal cross-sectional structure of the high-voltage device area after step S31 is completed;

[0033] Figure 5 A schematic diagram of the longitudinal cross-sectional structure of the device after step S32 is completed is shown;

[0034] Figure 6 A schematic diagram of the longitudinal cross-sectional structure of the device after step S33 is completed is shown;

[0035] Figure 7 A schematic diagram of the cross-sectional structure of the device after step S4 is completed is shown;

[0036] Figure 8 A schematic diagram of the cross-sectional structure of the device after step S5 is completed is shown;

[0037] Fig. 9 FIG. 4 shows a schematic diagram of a cross-sectional structure of the device after step S7 is completed. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0040] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0041] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0042] Figure 1 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application is shown. Figure 1 It can be seen that the method for manufacturing the semiconductor device comprises the following steps:

[0043] Step S1: providing a semiconductor substrate, wherein the semiconductor substrate comprises a high voltage device region, a medium voltage device region and a low voltage device region, wherein the high voltage device region, the medium voltage device region and the low voltage device region each comprise an active region and an isolation region.

[0044] The substrate includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer located below a thin semiconductor layer as an active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor generally include crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or their alloys (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0045] Figure 2 The longitudinal cross-sectional structure diagram of the semiconductor substrate provided in step S1 is shown. Figure 2 As can be seen in the figure, the semiconductor substrate includes a high voltage device area 300, a medium voltage device area 200 and a low voltage device area 100 in the lateral direction. The high voltage device area 300 includes a high voltage device active area 310 and a high voltage device isolation area 320 located on both sides of the high voltage device active area 310. The high voltage device active area 310 is used to form a high voltage device in a subsequent process, and the high voltage device isolation area 320 is used to isolate the high voltage device active area 310 from other areas. The medium voltage device area 200 includes a medium voltage device active area 210 and a medium voltage device isolation area 220 located on both sides of the medium voltage device active area 210. The medium voltage device active area 210 is used to form a medium voltage device in a subsequent process, and the medium voltage device isolation area 220 is used to isolate the medium voltage device active area 210 from other areas. The low voltage device area 100 includes a low voltage device active area 110 and a low voltage device isolation area 120 located on both sides of the low voltage device active area 110. The low voltage device active region 110 is used to form a low voltage device in a subsequent process, and the low voltage device isolation region 120 is used to isolate the low voltage device active region 110 from other regions.

[0046] Step S2: forming a deep trench isolation structure in the isolation region, wherein the upper surface of the deep trench isolation structure is higher than the upper surface of the active region by a specific height.

[0047] Reference Figure 3 , which shows a schematic diagram of the longitudinal cross-sectional structure of the device after step S2 is completed, from Figure 3 It can be seen that the deep trench isolation structures of various device regions are arranged at the isolation region positions in the corresponding device regions, including the high voltage device isolation structure 321 located at the high voltage device isolation region 320 , the medium voltage device isolation structure 221 located at the medium voltage device isolation region 220 , and the low voltage device isolation structure 121 located at the low voltage device isolation region 120 .

[0048] The upper surface of the high-voltage device isolation structure 321 is higher than the upper surface of the high-voltage device active area 310 by a first height, the upper surface of the medium-voltage device isolation structure 221 is higher than the upper surface of the medium-voltage device active area 210 by a second height, and the upper surface of the low-voltage device isolation structure 121 is higher than the upper surface of the low-voltage device active area 110 by a third height.

[0049] Step S3: sequentially performing a first etching and a second etching on the active area of ​​the high-voltage device area and the edge portion of the deep trench isolation structure of the high-voltage device area close to the active area; wherein the etching amount in the first etching accounts for 70% to 85% of the total etching amount, and the total etching amount is the total etching amount of the first etching and the second etching.

[0050] Exemplarily, step S3 may be implemented by the following steps S31 to S33:

[0051] Step S31: forming a high voltage oxide layer mask pattern structure on the semiconductor substrate, wherein the active area of ​​the high voltage device area and the edge portion of the deep trench isolation structure of the high voltage device area close to the active area are exposed from the high voltage oxide layer mask pattern structure.

[0052] Reference Figure 4 , which shows a schematic diagram of the longitudinal cross-sectional structure of the high voltage device area after step S31 is completed. Figure 1 It can be seen that a high-voltage oxide layer mask pattern structure 400 is formed on the semiconductor substrate, the high-voltage device active area 310, and the edge portion of the high-voltage device isolation structure 321 close to the high-voltage device active area 310 (part A in the figure) are exposed from the high-voltage oxide layer mask pattern structure 400.

[0053] Exemplarily, step S31 may be implemented by the following steps S311 to S312 performed in sequence:

[0054] Step S311: depositing a hard mask layer on the semiconductor substrate.

[0055] Step S312: Etching the hard mask layer through a photolithography and etching process to form a high-voltage oxide layer mask pattern structure, wherein the high-voltage oxide layer mask pattern structure includes a high-voltage oxide layer forming window; the active area of ​​the high-voltage device area, and the edge portion of the deep trench isolation structure of the high-voltage device area close to the active area are exposed from the high-voltage oxide layer forming window.

[0056] Step S32: Based on the high-voltage oxide layer mask pattern structure, performing a first etching according to a first etching amount on the structure exposed from the high-voltage oxide layer mask pattern structure.

[0057] Reference Figure 5 , which shows a schematic diagram of the longitudinal cross-sectional structure of the device after step S32 is completed. Figure 5 It can be seen that after the first etching is completed, the substrate of the high voltage device active area 310 and the edge portion of the high voltage device isolation structure 321 close to the high voltage device active area 310 (portion A in the figure) are etched away from their respective upper surfaces downward according to the first etching amount OE1.

[0058] Exemplarily, the first etching may be performed by dry etching, for example, in an atmosphere of one or more of nitrogen tetrafluoride, nitrogen trifluoride, and chlorine, a dry etching plasma is generated to perform the first etching according to the first etching amount on the structure exposed from the high-voltage oxide layer mask pattern structure.

[0059] Step S33: Based on the first etching, and again based on the high-voltage oxide layer mask pattern structure, performing a second etching according to a second etching amount on the structure exposed from the high-voltage oxide layer mask pattern structure;

[0060] The first etching amount accounts for 70% to 85% of the total etching amount, wherein the total etching amount is the sum of the first etching amount and the second etching amount.

[0061] Reference Figure 6 , which shows a schematic diagram of the longitudinal cross-sectional structure of the device after step S33 is completed. Figure 6 It can be seen that after the second etching is completed, based on the first etching, the substrate of the high-voltage device active area 310 and the edge portion of the high-voltage device isolation structure 321 close to the high-voltage device active area 310 (part A in the figure) continue to be etched and removed from their respective upper surfaces downward according to the second etching amount OE2.

[0062] Exemplarily, the second etching may be performed by dry etching, for example, in an atmosphere of one or more of nitrogen tetrafluoride, nitrogen trifluoride, and chlorine, a dry etching plasma is generated to perform a second etching on the structure exposed from the high-voltage oxide layer mask pattern structure according to a second etching amount.

[0063] In this embodiment, the structure exposed from the high-voltage oxide layer mask pattern structure is etched twice, and the total etching amount is the sum of the first etching amount and the second etching amount, and the first etching is the main etching step, and the proportion of the etching amount in the first etching in the total etching amount is increased, and the proportion of the etching amount in the second etching in the total etching amount is reduced, so as to reduce the height difference between the upper surface of the active area of ​​the high-voltage device area and the upper surface of the edge part of the deep trench isolation structure of the high-voltage device area close to the active area, thereby reducing the height difference between the metal gate in the active area of ​​the high-voltage device area and the deep trench isolation structure.

[0064] Step S4: etching the edge portion of the deep trench isolation structure of the high voltage device area close to the active area after the first etching and the second etching to reduce the height difference between the upper surface of the active area of ​​the high voltage device area and the upper surface of the edge portion of the deep trench isolation structure of the high voltage device area close to the active area.

[0065] Reference Figure 7 , which shows a schematic diagram of the cross-sectional structure of the device after step S4 is completed. Figure 7It can be seen that after step S4 is completed, the edge portion of the high-voltage device isolation structure 321 exposed from the high-voltage oxide layer mask pattern structure 400 close to the high-voltage device active area 310 (part A in the figure) continues to be etched downward, while the substrate of the high-voltage device active area 310 is not etched, thereby reducing the step between the upper surface of the edge portion of the high-voltage device isolation structure 321 close to the high-voltage device active area 310 (part A in the figure) and the upper surface of the high-voltage device active area 310, so that after the subsequent process of manufacturing the high-voltage oxide layer on the active area of ​​the high-voltage device area is completed, the surface morphology of the high-voltage device area can be flatter.

[0066] Exemplarily, a wet etching solution can be used to have different etching selectivities for different materials. By adopting a wet etching process with a higher etching selectivity for the deep trench isolation structure than for etching the active area substrate of the high-voltage device area, the edge portion of the deep trench isolation structure in the high-voltage device area close to the active area is etched to reduce the height difference between the upper surface of the active area of ​​the high-voltage device area and the upper surface of the edge portion of the deep trench isolation structure in the high-voltage device area close to the active area.

[0067] Step S4 can be performed using a wet etching solution with a hydrogen-fluorine concentration ratio of (100:1 to 200:1) to etch the edge portion of the deep trench isolation structure in the high-voltage device area close to the active area after the first etching and the second etching, thereby reducing the height difference between the upper surface of the active area of ​​the high-voltage device area and the upper surface of the edge portion of the deep trench isolation structure in the high-voltage device area close to the active area.

[0068] Step S5: depositing and forming a high-voltage oxide layer, wherein the high-voltage oxide layer covers the upper surface of the active area of ​​the high-voltage device region and the upper surface of the edge portion of the deep trench isolation structure of the high-voltage device region close to the active area.

[0069] Reference Figure 8 , which shows a schematic diagram of the cross-sectional structure of the device after step S5 is completed. Figure 8 It can be seen that the formed high-voltage oxide layer 500 covers between the upper surface of the edge portion (part A in the figure) of the high-voltage device isolation structure 321 close to the high-voltage device active area 310 and the upper surface of the high-voltage device active area 310. In addition, the high-voltage oxide layer 500 covers the step between the high-voltage device active area 310 and the high-voltage device isolation structure 321, and is connected to the high-voltage device isolation structure 321. Since the above steps reduce the step height of the step, the height uniformity of the upper surface of the high-voltage oxide layer 500 and the upper surface of the high-voltage device isolation structure 321 is relatively strong.

[0070] In other embodiments, after completing step S5, the following steps may be performed:

[0071] Step S6: etching the edge portion of the deep trench isolation structure of the medium voltage device region close to the active region to reduce the height difference between the upper surface of the active region of the medium voltage device region and the upper surface of the edge portion of the deep trench isolation structure of the medium voltage device region close to the active region.

[0072] Exemplarily, a wet etching solution can be used to have different etching selectivities for different materials. By adopting a wet etching process with a higher etching selectivity for the deep trench isolation structure than for etching the active area substrate of the medium voltage device area, the edge portion of the deep trench isolation structure of the medium voltage device area close to the active area is etched to reduce the height difference between the upper surface of the active area of ​​the medium voltage device area and the upper surface of the edge portion of the deep trench isolation structure of the medium voltage device area close to the active area.

[0073] A wet etching solution with a hydrogen-fluorine concentration ratio of (100:1 to 200:1) can be used to perform step S6 to etch the edge portion of the deep trench isolation structure of the medium voltage device area close to the active area, thereby reducing the height difference between the upper surface of the active area of ​​the medium voltage device area and the upper surface of the edge portion of the deep trench isolation structure of the medium voltage device area close to the active area.

[0074] Step S7: depositing and forming a medium voltage oxide layer, wherein the medium voltage oxide layer covers the upper surface of the active area of ​​the medium voltage device area and the upper surface of the edge portion of the deep trench isolation structure of the medium voltage device area close to the active area.

[0075] Reference Fig. 9 , which shows a schematic diagram of the cross-sectional structure of the device after step S7 is completed. Fig. 9 It can be seen that the formed medium voltage oxide layer covers between the upper surface of the edge portion (B portion in the figure) of the medium voltage device isolation structure 221 close to the medium voltage device active area 210 and the upper surface of the medium voltage device active area 210. In addition, the medium voltage oxide layer 600 covers the step between the medium voltage device active area 210 and the medium voltage device isolation structure 221, and is connected to the medium voltage device isolation structure 221. Since the above steps reduce the step height, the upper surface of the medium voltage oxide layer 600 and the upper surface of the medium voltage device isolation structure 221 have a strong height uniformity.

[0076] This embodiment improves the height uniformity of the high-voltage oxide layer or the medium-voltage oxide layer and the upper surface of the isolation structure so that the thickness uniformity of the metal gate is greater in the subsequent process of manufacturing the metal gate, avoiding the appearance of too thin thickness areas in the manufactured metal gate, thereby paving the way for improving the reliability of the device.

[0077] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method for manufacturing the semiconductor device comprises the following steps: Providing a semiconductor substrate, the semiconductor substrate comprising a high voltage device region, a medium voltage device region and a low voltage device region, wherein the high voltage device region, the medium voltage device region and the low voltage device region each comprise an active region and an isolation region; A deep trench isolation structure is formed in the isolation region, wherein the upper surface of the deep trench isolation structure is higher than the upper surface of the active region by a specific height; Sequentially performing a first etching and a second etching on the active area of ​​the high-voltage device area and the edge portion of the deep trench isolation structure of the high-voltage device area close to the active area; wherein the etching amount in the first etching accounts for 70% to 85% of the total etching amount, and the total etching amount is the total etching amount of the first etching and the second etching; Etching the edge portion of the deep trench isolation structure of the high voltage device region close to the active region after the first etching and the second etching to reduce the height difference between the upper surface of the active region of the high voltage device region and the upper surface of the edge portion of the deep trench isolation structure of the high voltage device region close to the active region; A high-voltage oxide layer is formed by deposition, and the high-voltage oxide layer covers the upper surface of the active area of ​​the high-voltage device area and the upper surface of the edge portion of the deep trench isolation structure of the high-voltage device area close to the active area.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of sequentially performing a first etching and a second etching on the active area of ​​the high voltage device area and the edge portion of the deep trench isolation structure of the high voltage device area close to the active area; wherein the etching amount in the first etching accounts for 70% to 85% of the total etching amount, and the total etching amount is the total etching amount of the first etching and the second etching, comprises: A high-voltage oxide layer mask pattern structure is formed on the semiconductor substrate, wherein the active area of ​​the high-voltage device region and the edge portion of the deep trench isolation structure of the high-voltage device region close to the active area are exposed from the high-voltage oxide layer mask pattern structure; Based on the high-voltage oxide layer mask pattern structure, performing a first etching according to a first etching amount on the structure exposed from the high-voltage oxide layer mask pattern structure; Based on the first etching, and again based on the high-voltage oxide layer mask pattern structure, performing a second etching according to a second etching amount on the structure exposed from the high-voltage oxide layer mask pattern structure; The first etching amount accounts for 70% to 85% of the total etching amount, and the total etching amount is the sum of the first etching amount and the second etching amount.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The step of forming a high-voltage oxide layer mask pattern structure on the semiconductor substrate, wherein the active area of ​​the high-voltage device area and the edge portion of the deep trench isolation structure of the high-voltage device area close to the active area are exposed from the high-voltage oxide layer mask pattern structure comprises: Depositing a hard mask layer on the semiconductor substrate; The hard mask layer is etched by a photolithography and etching process to form a high-voltage oxide layer mask pattern structure, wherein the high-voltage oxide layer mask pattern structure includes a high-voltage oxide layer forming window; an active area of ​​the high-voltage device area, and an edge portion of a deep trench isolation structure of the high-voltage device area close to the active area are exposed from the high-voltage oxide layer forming window.

4. The method for manufacturing a semiconductor device according to claim 2, wherein: The step of performing a first etching according to a first etching amount on the structure exposed from the high-voltage oxide layer mask pattern structure based on the high-voltage oxide layer mask pattern structure comprises: In an atmosphere containing any one or more of nitrogen tetrafluoride, nitrogen trifluoride, and chlorine, a dry etching plasma is generated, so that the dry etching plasma bombards a device with the high-voltage oxide layer mask pattern structure, and a first etching is performed on a structure exposed from the high-voltage oxide layer mask pattern structure according to a first etching amount.

5. The method for manufacturing a semiconductor device according to claim 2, wherein: The step of performing a second etching according to a second etching amount on the structure exposed from the high-voltage oxide layer mask pattern structure based on the first etching again based on the high-voltage oxide layer mask pattern structure comprises: On the basis of the first etching, a dry etching plasma is generated in a gas atmosphere containing any one or more combinations of nitrogen tetrafluoride, nitrogen trifluoride, and chlorine, so that the dry etching plasma bombards the device with the high-voltage oxide layer mask pattern structure, and performs a second etching on the structure exposed from the high-voltage oxide layer mask pattern structure according to a second etching amount.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The following steps are also included: The edge portion of the deep trench isolation structure of the medium voltage device area close to the active area is etched to reduce the height difference between the upper surface of the active area of ​​the medium voltage device area and the upper surface of the edge portion of the deep trench isolation structure of the medium voltage device area close to the active area. A medium voltage oxide layer is formed by deposition, and the medium voltage oxide layer covers the upper surface of the active area of ​​the medium voltage device area and the upper surface of the edge portion of the deep trench isolation structure of the medium voltage device area close to the active area.

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