An encapsulation structure and a corresponding manufacturing method

Abstract

The present invention relates to the field of packaging technology, and discloses a packaging structure and a corresponding manufacturing method. The packaging structure comprises: a substrate, a chip structure, a plastic sealing layer, and a connection structure arranged on the surface of the substrate, the chip structure is arranged on the surface of the connection structure and is electrically connected to the substrate through the connection structure, the substrate surface around the chip structure is also provided with chip retaining walls, the plastic sealing layer is located on the surface of the substrate and plastic seals the chip structure and the chip retaining walls, and the connection structure between the chip structure and the substrate after plastic sealing is a cavity. The present invention isolates the cavity and the plastic sealing layer by arranging the chip retaining wall, prevents the resin film in the plastic sealing layer from overflowing into the cavity and contaminating the connection structure, improves product performance, and has good application prospects.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and specifically provides a packaging structure and a corresponding manufacturing method. Background Art

[0002] In the existing chip packaging structure, as Figure 1 shown, the chip structure 40 is electrically connected to the substrate 10 through the connection structure 20. The encapsulation layer 50 is disposed on the surface of the substrate 10 and encapsulates the chip structure 40. An air cavity 60 is formed in the encapsulated structure after encapsulation. However, in such a packaging structure, during the process of forming the encapsulation layer 50 by molding extrusion, the resin film will be squeezed under the chip structure and contact the connection structure under the chip structure, resulting in contamination of the connection structure and reducing the effective volume of the air cavity at the same time. In addition, during the operation of the formed packaging structure, there is a risk that the resin films on both sides of the encapsulation layer 50 will be washed away due to the air pressure difference inside and outside the air cavity. Summary of the Invention

[0003] The purpose of the present invention is to overcome the problem that the existing packaging structure may cause contamination of the connection structure, and provides a packaging structure and a corresponding manufacturing method.

[0004] To achieve the above purpose, the present invention provides a packaging structure, including: a substrate, a chip structure, a connection structure, an encapsulation layer, and a chip retaining wall. The connection structure is located on the surface of the substrate. The chip structure is disposed on the surface of the connection structure and is electrically connected to the substrate through the connection structure. A chip retaining wall is further disposed on the surface of the substrate around the chip structure. The encapsulation layer is located on the surface of the substrate and encapsulates the chip structure and the chip retaining wall. An air cavity is formed around the connection structure between the chip structure and the substrate. The chip retaining wall is used to isolate the air cavity and the encapsulation layer.

[0005] As an implementable manner, a groove is provided on the surface of the chip retaining wall.

[0006] As an implementable manner, the groove is "V"-shaped.

[0007] As an implementable manner, the chip retaining wall includes an inner retaining wall close to the chip structure and an outer retaining wall away from the chip structure. The width of the lower surface of the inner retaining wall is greater than the width of the upper surface of the inner retaining wall, and the width of the lower surface of the outer retaining wall is greater than the width of the upper surface of the outer retaining wall.

[0008] As an implementable manner, a surface area of the substrate is exposed between the lower surfaces of the inner retaining wall and the outer retaining wall, and the exposed surface area of the substrate is in a concave shape.

[0009] As an implementable manner, the chip retaining wall is an annular metal retaining wall.

[0010] As an implementable manner, the chip structure does not contact the chip barriers around the chip structure, and the spacing between the chip barriers and the chip structure is such that the encapsulation film in the encapsulation layer does not overflow into the cavity.

[0011] As an implementable manner, the height of the chip barrier is less than or equal to the height at half of the thickness of the chip structure after encapsulation, and the height of the chip barrier is greater than the height of the bottom surface of the chip structure facing the connection structure after encapsulation.

[0012] Correspondingly, the present invention also provides a method for manufacturing an encapsulation structure, including the following steps:

[0013] Provide a substrate, and form chip barriers at predetermined positions on the surface of the substrate, wherein the chip barriers at the predetermined positions are located around the encapsulation positions of the chip structures.

[0014] Form a connection structure on the surface of the substrate, and the connection structure is located at the encapsulation position of the chip structure on the surface of the substrate; provide a chip structure to be encapsulated, and place the chip structure to be encapsulated on the surface of the connection structure and electrically connect it to the substrate through the connection structure.

[0015] Determine the encapsulation position of the chip structure on the surface of the substrate, and form chip barriers on the surface of the substrate at a predetermined distance outside the encapsulation position of the chip structure, so that the chip barriers are respectively located around the chip structure after subsequent encapsulation.

[0016] As an implementable manner, the step of forming chip barriers at predetermined positions on the surface of the substrate, wherein the chip barriers at the predetermined positions are located around the encapsulation positions of the chip structures, includes:

[0017] Determine the encapsulation position of the chip structure on the surface of the substrate, and form chip barriers on the surface of the substrate at a predetermined distance outside the encapsulation position of the chip structure, so that the chip barriers are respectively located around the chip structure after subsequent encapsulation.

[0018] As an implementable manner, the predetermined distance is 30 um.

[0019] As an implementable manner, the surface of the chip is provided with a groove; the step of forming a chip barrier provided with a groove at a predetermined position on the surface of the substrate includes: forming an annular barrier at a predetermined position on the surface of the substrate, and performing laser cutting on the surface of the annular barrier to form a groove, so as to obtain a chip barrier including the groove.

[0020] As an implementable manner, during the process of cutting the surface of the annular retaining wall based on the laser cutting process to form a groove, it further includes: extending the depth of the laser cutting into the substrate to form an inner retaining wall close to the chip structure and an outer retaining wall away from the chip structure. The width of the lower surface of the inner retaining wall is greater than the width of the upper surface of the inner retaining wall, the width of the lower surface of the outer retaining wall is greater than the width of the upper surface of the inner retaining wall, and there is also a substrate surface area between the lower surface of the inner retaining wall and the lower surface of the outer retaining wall, and the substrate surface area is in a concave shape.

[0021] Advantages of the present invention: The present invention discloses a packaging structure and a corresponding manufacturing method. The packaging structure includes: a substrate, a chip structure, a plastic encapsulation layer, and a connection structure provided on the surface of the substrate. The chip structure is disposed on the surface of the connection structure and is electrically connected to the substrate through the connection structure. Chip retaining walls are respectively provided on the substrate surface around the chip structure. The plastic encapsulation layer is located on the substrate surface and encapsulates the chip structure and the chip retaining walls. A cavity is formed around the connection structure between the encapsulated chip structure and the substrate; by setting the chip retaining walls, the present invention isolates the cavity and the plastic encapsulation layer, prevents the resin film in the plastic encapsulation layer from overflowing into the cavity and polluting the connection structure, and prevents the resin film outside the prepared single packaging structure from being washed away due to the internal and external air pressure difference formed by the high temperature during the operation of the product, improves the product performance, and has good application prospects. Description of the Drawings

[0022] Figure 1 Schematic diagram of an existing packaging structure;

[0023] Figure 2 Schematic diagram of the packaging structure of an embodiment of the present invention;

[0024] Figures 3 - 9 Schematic diagram of the manufacturing process of the packaging structure of an embodiment of the present invention;

[0025] Figure 10 Schematic diagram of the steps of the manufacturing method of the packaging structure of an embodiment of the present invention. Detailed Embodiments

[0026] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0027] This embodiment provides a technical solution: a packaging structure, including: a substrate, a chip structure, a connection structure, a plastic encapsulation layer, and a chip barrier. The connection structure is located on the surface of the substrate. The chip structure is disposed on the surface of the connection structure and is electrically connected to the substrate through the connection structure. Chip barriers are further provided on the surface of the substrate around the chip structure. The plastic encapsulation layer is located on the surface of the substrate and encapsulates the chip structure and the chip barriers. There is a cavity around the connection structure between the chip structure and the substrate. The chip barriers are used to isolate the cavity and the plastic encapsulation layer.

[0028] Specifically, referring to Figure 2 , a single packaging structure includes a substrate 10, a chip structure 40, a plastic encapsulation layer 50, and a connection structure 20 disposed on the surface of the substrate 10 and electrically connected to the substrate 10. The chip structure 40 is disposed on the surface of the connection structure 20 and is electrically connected to the substrate 10 through the connection structure 20. Chip barriers 30 are further provided on the surface of the substrate 10 around the chip structure 40. The plastic encapsulation layer 50 is located on the surface of the substrate 10 and encapsulates the chip structure 40 and the chip barriers 30. The cavity 60 is formed around the connection structure 20 between the encapsulated chip structure 40 and the substrate 10. The chip barriers 30 are used to isolate the cavity 60 and the plastic encapsulation layer 50, preventing the resin film in the plastic encapsulation layer 50 from overflowing into the cavity 60 and contaminating the connection structure 20.

[0029] Specifically, the substrate 10 is used to package the chip structure 40. One packaging structure includes one substrate 10 and one chip structure 40, and correspondingly has one chip barrier 30. In other embodiments, one substrate can also package multiple chip structures at the same time, and chip barriers are provided around each chip structure.

[0030] The chip structure 40 can be a single chip, or a stacked structure of multiple chips, or a pre-packaged chip packaging structure.

[0031] The connection structure 20 is a metal solder ball or a metal welding post, and due to the certain height of the connection structure 20, a cavity 60 is formed around the connection structure 20 between the encapsulated chip structure 40 and the substrate 10.

[0032] In this embodiment, the chip barrier 30 is annular, that is, an enclosing structure surrounding the chip. The chip barrier is an annular metal barrier. Specifically, the chip barrier can be a copper barrier. In other embodiments, the chip barrier can also be made of other materials, such as graphite, etc.

[0033] Such as Figure 5As shown, in one embodiment, the surface of the chip retaining wall 30 is provided with a groove 31, and the groove can be in a shape such as a "V" shape, so as to form an included angle force.

[0034] Further, in another embodiment, as Figure 6 shown, the chip retaining wall 30 includes an inner retaining wall 32 close to the chip structure and an outer retaining wall 33 far from the chip structure. The width of the lower surface of the inner retaining wall 32 is greater than the width of the upper surface of the inner retaining wall 32, and the width of the lower surface of the outer retaining wall 33 is greater than the width of the upper surface of the outer retaining wall 33. A groove 31 is formed between the inner retaining wall 32 and the outer retaining wall 33.

[0035] Further, in another embodiment, as Figure 7 shown, the substrate surface area is exposed between the lower surface of the inner retaining wall 32 and the lower surface of the outer retaining wall 33, and the exposed substrate surface area is in a concave shape.

[0036] In this embodiment, as Figure 9 shown, the chip retaining wall 30 is used to make the resin film accumulate towards the inside of the groove 31 in the direction of the arrows f3 and f4 through the included angle force formed by the inclined surfaces on both sides of the groove 31, so as to prevent the resin film from overflowing into the cavity 60 and polluting the connection structure. At the same time, the resin film is tightly combined with the inclined surface in the direction of the arrows f1 and f2 through the included angle force formed by the inclined surfaces on both sides of the groove 31, so as to prevent the resin film on the outside of the single encapsulation structure after preparation as Figure 2 shown from being washed away due to the internal and external air pressure difference formed by the high temperature during the operation of the product.

[0037] Further, in order to prevent the chip retaining walls on both sides of the chip structure from scratching the chip structure, the chip structure and the chip retaining walls on both sides of the chip structure do not contact; and the distance between the chip retaining wall and the chip structure is such that the encapsulation film in the encapsulation layer will not overflow into the cavity;

[0038] Specifically, when setting the specific positions of the chip structure and the chip retaining walls around the chip structure, since the chip structure needs to be mounted on the surface of the connection structure by a chip structure mounting machine, when the accuracy of the chip structure mounting machine is about 20 μm (i.e., the error may be about 20 μm), the chip structure packaging position on the substrate surface for mounting the chip structure can be set first, and then a predetermined position 30 μm outside the chip structure packaging position is used as the setting position of the chip retaining wall to form the chip retaining wall; then a connection structure is formed at the corresponding position within the chip structure packaging position on the substrate surface for mounting the chip structure, and then the chip structure mounting machine is used to mount the chip structure on the surface of the connection structure within the chip structure packaging position; during the mounting process, even if the chip structure mounting machine really has an error of about 20 μm, the chip structure can be mounted on the surface of the connection structure in a way that does not hit the chip retaining wall, thereby preventing the chip retaining wall from scratching the chip structure; after the encapsulation is completed, the actual distance between the chip retaining wall and the chip structure is determined according to the actual encapsulation situation.

[0039] Moreover, since the chip structure will be loaded and mounted on the surface of the connection structure through a jig, that is, a chip structure mounting machine, if the chip retaining wall is too high, it will hit the jig, resulting in poor contact between the chip structure and the connection structure. Therefore, the height of the chip retaining wall can be limited to be less than or equal to the height at the half-thickness position of the chip structure after encapsulation, so as to prevent interference with the mounting of the chip structure. Here, the height at the half-thickness position of the chip structure after encapsulation refers to the height from the substrate surface at the half-thickness position of the chip structure 40 when the chip structure 40 is encapsulated in the Figure 2 encapsulation structure as shown.

[0040] Furthermore, in this embodiment, the height of the chip retaining wall is also set to be greater than the height of the bottom surface of the chip structure facing the connection structure after encapsulation, so as to more effectively prevent the resin film in the plastic encapsulation layer from overflowing into the cavity; where the height of the bottom surface of the chip structure facing the connection structure after encapsulation refers to the height from the substrate surface of the bottom surface of the chip structure 40 facing the connection structure when the chip structure 40 is encapsulated in the Figure 2 encapsulation structure as shown.

[0041] Based on the same inventive concept, referring to Figure 10 , the embodiment of the present invention also provides a manufacturing method for an encapsulation structure, including the following steps:

[0042] Step S100, provide a substrate, and form a chip retaining wall at a predetermined position on the surface of the substrate, where the chip retaining wall at the predetermined position is located around the chip structure packaging position;

[0043] Step S200, form a connection structure on the surface of the substrate, where the connection structure is located at the chip structure packaging position on the substrate surface; provide a chip structure to be packaged, and place the chip structure to be packaged on the surface of the connection structure and electrically connect it to the substrate through the connection structure;

[0044] Step S300, form a plastic encapsulation layer on the surface of the substrate and encapsulate the chip structure and the chip dam, wherein there is a cavity around the connection structure between the encapsulated chip structure and the substrate; the chip dam is used to isolate the cavity and the plastic encapsulation layer.

[0045] Execute step S100, as Figure 3 and Figure 5 shown, provide a substrate 10, and form chip dams 30 at different predetermined positions on the surface of the substrate 10.

[0046] Among them, the step of forming the chip dam 30 includes:

[0047] Determine the chip structure packaging position on the surface of the substrate 10, and form a chip dam 30 on the surface of the substrate at a predetermined distance outside the chip structure packaging position, so that the chip dam is located around the chip structure after subsequent packaging. Among them, the predetermined distance can be determined according to the accuracy of the mounting machine. When the accuracy of the mounting machine is 20 microns, the predetermined distance can be 30 microns, so that the chip structure is mounted on the surface of the connection structure in a way that does not hit the chip dam, thereby preventing the chip dam from scratching the chip structure.

[0048] The surface of the chip is provided with a groove; as Figures 3 - 5 shown, the step of forming a chip dam at a predetermined position on the surface of the substrate includes: forming an annular dam at a predetermined position on the surface of the substrate, and performing laser cutting on the surface of the annular dam to form a groove, so as to obtain a chip dam including the groove.

[0049] In this embodiment, the groove of the chip dam can be formed by laser cutting technology, that is, after determining the set position of the chip dam on the substrate, as Figure 4 shown, first form an annular dam 11 at the set position based on electroplating technology, and then perform laser cutting on the surface of the annular dam 11, so as to form a groove 31 of the type as Figures 5 - 7 shown on the surface of the annular dam, and obtain a chip dam.

[0050] However, in other embodiments, it can also be other groove types that can achieve the purpose; among them, the annular dam can specifically be an annular metal column.

[0051] In one embodiment, as Figure 5As shown, a groove 31 is provided on the surface of the chip retaining wall 30. The groove can be in the shape of a "V" or other shapes, so as to form an included angle force.

[0052] Further, in another embodiment, as Figure 6 shown, the chip retaining wall 30 includes an inner retaining wall 32 close to the chip structure and an outer retaining wall 33 far from the chip structure. The width of the lower surface of the inner retaining wall 32 is greater than the width of the upper surface of the inner retaining wall 32, and the width of the lower surface of the outer retaining wall 33 is greater than the width of the upper surface of the outer retaining wall 33. A groove 31 is formed between the inner retaining wall 32 and the outer retaining wall 33.

[0053] Further, in another embodiment, as Figure 7 shown, the substrate surface area is exposed between the lower surface of the inner retaining wall 32 and the lower surface of the outer retaining wall 33, and the exposed substrate surface area is in a concave shape.

[0054] When forming a groove 31 as Figure 7 shown, the depth of the laser cutting can be directly extended into the substrate to form a groove 31 as Figure 7 shown, where the bottom of the groove is the substrate surface area and the substrate surface area is in a concave shape, so that the groove 31 can have a greater depth, thereby making the combination of the resin film and the groove 31 more firm and improving the product reliability.

[0055] Specifically, when forming a groove shape as Figure 7 shown; in the process of cutting the surface of the annular retaining wall to form a groove based on the laser cutting process, it further includes: extending the depth of the laser cutting into the substrate to form an inner retaining wall close to the chip structure and an outer retaining wall far from the chip structure. The width of the lower surface of the inner retaining wall is greater than the width of the upper surface of the inner retaining wall, and the width of the lower surface of the outer retaining wall is greater than the width of the upper surface of the inner retaining wall. A substrate surface area is also included between the lower surface of the inner retaining wall and the lower surface of the outer retaining wall, and the substrate surface area is in a concave shape.

[0056] Execute step S200. As Figure 8 shown, a connection structure 20 is formed on the surface of the substrate 10. The connection structure 20 is electrically connected to the substrate 10; a chip structure 40 is disposed on the surface of the connection structure 20 and is electrically connected to the substrate 10 through the connection structure 20.

[0057] Execute step S300. As Figure 9Shown is a plastic encapsulation layer 50 formed on the surface of the substrate 10. The plastic encapsulation layer 50 encapsulates the chip structure 40 and the chip retaining wall 30. After encapsulation, a cavity 60 is formed around the connection structure between the chip structure 40 and the substrate 10. The chip retaining wall 30 is used to isolate the cavity 60 from the plastic encapsulation layer 50, preventing the resin film in the plastic encapsulation layer 50 from overflowing into the cavity 60 and contaminating the connection structure.

[0058] When the chip retaining wall 30 has a groove 31 as Figures 5 - 7 shown, the resin film can penetrate into the groove 31, making the combination of the resin film and the groove 31 firmer and improving the product reliability.

[0059] And as Figure 9 shown, since the chip retaining wall 30 includes an inner retaining wall 32 close to the chip structure and an outer retaining wall 33 far from the chip structure, the width of the lower part of the inner retaining wall 32 is greater than the width of the upper part of the inner retaining wall 32, and the width of the lower surface of the outer retaining wall 33 is greater than the width of the upper surface of the outer retaining wall 33, forming a V-shaped groove 31. When the chip retaining wall 30 makes the resin film accumulate towards the inside of the groove 31 in the directions of the arrows f3 and f4 through the included angle force formed by the two inclined surfaces on both sides of the groove 31, it can prevent the resin film from overflowing into the cavity 60 and contaminating the connection structure. At the same time, through the included angle force formed by the two inclined surfaces on both sides of the groove 31, the resin film is tightly combined with the inclined surfaces in the directions of the arrows f1 and f2, preventing the resin film on both sides of the encapsulation structure as Figure 2 shown from being washed away.

[0060] Meanwhile, when the cross-sectional shape of the inner retaining wall 32 is triangular and the width of the upper part of the inner retaining wall 32 at the top is small, there is a tendency to retract towards the chip structure under the extrusion of the resin film, so that the resin film in the external plastic encapsulation layer 50 will not overflow into the cavity 60 and will not contaminate the connection structure.

[0061] After obtaining the structure as Figure 9 shown, cut between the two chip retaining walls 30 as Figure 9 shown to obtain a single encapsulation structure as Figure 2 shown.

[0062] Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention all fall within the protection scope of the technical solution of the present invention.

Claims

1. An encapsulation structure, characterized in that, it includes: a substrate, a chip structure, a connection structure, a plastic encapsulation layer, and a chip barrier wall. The connection structure is located on the surface of the substrate. The chip structure is disposed on the surface of the connection structure and is electrically connected to the substrate through the connection structure. A chip barrier wall is further provided on the surface of the substrate around the chip structure. A groove is provided on the surface of the chip barrier wall, and the groove is in a "V" shape. The plastic encapsulation layer is located on the surface of the substrate and encapsulates the chip structure and the chip barrier wall. There is a cavity around the connection structure between the chip structure and the substrate, and the chip barrier wall is used to isolate the cavity and the plastic encapsulation layer.

2. The encapsulation structure according to claim 1, characterized in that, the chip barrier wall includes an inner barrier wall close to the chip structure and an outer barrier wall away from the chip structure. The width of the lower surface of the inner barrier wall is greater than the width of the upper surface of the inner barrier wall, and the width of the lower surface of the outer barrier wall is greater than the width of the upper surface of the outer barrier wall.

3. The encapsulation structure according to claim 2, characterized in that, a surface area of the substrate is also exposed between the lower surface of the inner barrier wall and the lower surface of the outer barrier wall, and the exposed surface area of the substrate is in a concave shape.

4. The encapsulation structure according to claim 1, characterized in that, the chip barrier wall is an annular metal barrier wall.

5. The encapsulation structure according to claim 1, characterized in that, the chip structure does not contact the chip barrier wall around the chip structure, and the distance between the chip barrier wall and the chip structure is such that the plastic encapsulation film in the plastic encapsulation layer will not overflow into the cavity.

6. The encapsulation structure according to claim 1, characterized in that, the height of the chip barrier wall is less than or equal to the height at half of the thickness of the chip structure after encapsulation, and the height of the chip barrier wall is greater than the height of the bottom surface of the chip structure facing the connection structure after encapsulation.

7. A manufacturing method of an encapsulation structure, characterized in that, it includes the following steps: providing a substrate, forming a chip barrier wall at a predetermined position on the surface of the substrate, wherein the chip barrier wall at the predetermined position is located around the encapsulation position of the chip structure, and a groove is provided on the surface of the chip barrier wall, and the groove is in a "V" shape; forming a connection structure on the surface of the substrate, the connection structure being located at the encapsulation position of the chip structure on the surface of the substrate; providing a chip structure to be encapsulated, and disposing the chip structure to be encapsulated on the surface of the connection structure and electrically connecting it to the substrate through the connection structure; forming a plastic encapsulation layer on the surface of the substrate and encapsulating the chip structure and the chip barrier wall, wherein there is a cavity around the connection structure between the encapsulated chip structure and the substrate; the chip barrier wall is used to isolate the cavity and the plastic encapsulation layer.

8. The manufacturing method of the encapsulation structure according to claim 7, characterized in that, the step of forming a chip barrier wall at a predetermined position on the surface of the substrate, wherein the chip barrier wall at the predetermined position is located around the encapsulation position of the chip structure, includes: Determine the packaging position of the chip structure on the surface of the substrate, and form chip retaining walls on the surface of the substrate at a predetermined distance outside the packaging position of the chip structure, so that the chip retaining walls are respectively located around the chip structure after subsequent packaging.

9. The manufacturing method of the packaging structure according to claim 8, characterized in that the predetermined distance is 30 um.

10. The manufacturing method of the packaging structure according to claim 7, characterized in that the step of forming a chip retaining wall at a predetermined position on the surface of the substrate includes: forming an annular retaining wall at a predetermined position on the surface of the substrate, and cutting the surface of the annular retaining wall based on a laser cutting process to form a groove, so as to obtain a chip retaining wall including the groove.

11. The manufacturing method of the packaging structure according to claim 10, characterized in that during the process of cutting the surface of the annular retaining wall based on the laser cutting process to form a groove, it further includes: extending the depth of the laser cutting into the substrate to form an inner retaining wall close to the chip structure and an outer retaining wall far from the chip structure, the width of the lower surface of the inner retaining wall is greater than the width of the upper surface of the inner retaining wall, the width of the lower surface of the outer retaining wall is greater than the width of the upper surface of the inner retaining wall, and a substrate surface area is further included between the lower surface of the inner retaining wall and the lower surface of the outer retaining wall, and the substrate surface area is in a concave shape.

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