A chip package, a manufacturing method thereof, and an electronic device

Abstract

The present application discloses a chip package, a manufacturing method thereof, and an electronic device. The chip package includes: at least two pads arranged at intervals; at least one chip component, the chip component including a conductive connection body and a chip; the conductive connection body is arranged on the pad, and a groove is arranged on the side facing away from the pad, and the chip is arranged in the groove; wherein, the thickness of the chip is greater than the depth of the groove; a conductive layer is arranged on the chip to connect at least two chips through the conductive layer, or to connect at least one chip to other pads without chip components. By the above method, the chip package in the present application can effectively enhance the strength of the pads, enhance the bonding force between the chips and the pads, improve the alignment ability of the chips, reduce the alignment between the chips and the blind holes, and effectively improve the overall yield of the product.

Description

Technical Field

[0001] The present application relates to the technical field of chip packaging, and particularly relates to a chip package, a manufacturing method thereof, and an electronic device. Background Art

[0002] As one of the advanced packaging technologies, the fan-out panel-level packaging technology has been widely applied in discrete devices at present. However, for the products obtained by the current packaging solutions, there are certain defects in terms of structural reliability and the solutions. To address these problems, a new structure is needed to improve the product reliability.

[0003] Among them, as Figure 1 shown, Figure 1 is a schematic structural diagram of a chip package in the prior art. It can be seen from this that the chip in this chip package is directly soldered on the bottom copper bumps, and blind holes are drilled on the pads above and to the right of the chip by laser drilling, and then copper is plated to form an interconnection. Therefore, there will inevitably be some structural defects. For example, the strength of the bottom pads is too low, and there is a risk of the pads and the chip falling off during product soldering; the blind holes on the chip have high requirements for equipment accuracy, and there is a problem of misalignment when applied to small-sized chips; there is also a risk of misalignment in the alignment of the chip on the pads, and the relative offset between the laser drilling and the chip has a certain impact on the product yield. Summary of the Invention

[0004] The present application provides a chip package, a manufacturing method thereof, and an electronic device to solve the problems in the prior art that the pads of the chip package have low strength, there is a risk of the chip and the pads falling off, there is a problem of drilling misalignment for small-sized chips, and there is also a risk of misalignment in the alignment of the chip on the pads, thus affecting the product yield.

[0005] To solve the above technical problems, a technical solution adopted by the present application is: to provide a chip package, wherein the chip package includes: at least two pads arranged at intervals; at least one chip component, the chip component including a conductive connection body and a chip; the conductive connection body is arranged on the pad, and a groove is arranged on the side facing away from the pad, and the chip is arranged in the groove; wherein, the thickness of the chip is greater than the depth of the groove; a conductive layer is arranged on the chip to connect at least two chips through the conductive layer, or to connect at least one chip to other pads without chip components.

[0006] Among them, the chip package further includes an insulating layer, and the insulating layer covers the chip component and the conductive layer.

[0007] Among them, the conductive connection body includes a conductive column and a connection body that are arranged in contact with each other or integrally formed. The conductive column is arranged on the pad, and a groove is arranged on the side of the connection body facing away from the conductive column for accommodating the chip; wherein, the projected area of the connection body on the pad is greater than the projected area of the conductive column on the pad.

[0008] Wherein, the connecting body is an arc-shaped structure, and the radian of the arc surface close to the conductive post is greater than that of the arc surface far from the conductive post.

[0009] Wherein, the center lines of the conductive connecting body, the chip, and the pad on which the chip component is arranged in the same chip component coincide.

[0010] Wherein, when there are at least two chips, one side of the at least two chips far from the pad is on the same plane, so that the conductive layer arranged on the chips is a plane.

[0011] Wherein, the conductive connecting body is a cylinder or a cube.

[0012] To solve the above technical problems, another technical solution adopted by this application is: to provide a manufacturing method of a chip package body, wherein, the manufacturing method includes: providing a carrier copper clad laminate, and arranging at least one conductive connecting body on the carrier copper clad laminate; forming a first insulating layer on the carrier copper clad laminate and the conductive connecting body, and exposing a part of the conductive connecting body; opening a groove at the exposed part corresponding to each conductive connecting body; arranging a chip in each groove; wherein, the thickness of the chip is greater than the depth of the groove; forming a conductive layer on at least two chips, so that the at least two chips are connected by the conductive layer; or, forming a conductive layer in at least one chip and the first insulating layer, so that at least one chip is connected to a set position on the carrier copper clad laminate where no conductive connecting body is arranged; patterning the carrier copper clad laminate to form at least two pads at intervals corresponding to the conductive connecting body, or the set positions of the conductive connecting body and the carrier copper clad laminate.

[0013] Wherein, arranging at least one conductive connecting body on the carrier copper clad laminate includes: arranging at least one conductive post on the carrier copper clad laminate; arranging a connecting body on each conductive post to form a conductive connecting body composed of the conductive post and the connecting body; wherein, the projected area of the connecting body onto the pad is greater than the projected area of the conductive post onto the pad.

[0014] To solve the above technical problems, another technical solution adopted by this application is: to provide an electronic device, wherein, the electronic device includes the chip package body described in any one of the foregoing items.

[0015] The beneficial effects of the present application are as follows: Different from the prior art, in the chip package provided by the present application, the conductive connector is disposed on at least two pads arranged at intervals, and a groove is provided on the side of the conductive connector facing away from the pads, and the chip is specifically disposed in the groove, so as to effectively enhance the strength of the pads through the conductive connector and enhance the bonding force between the chip and the pads, and by disposing the chip in the groove, the risk of misalignment in the alignment of the chip on the pads is also effectively avoided; and the conductive layer is disposed on the chip, so that at least two chips are connected by means of the conductive layer, or at least one chip is connected to other pads without chip components, and it is also possible to reduce the opening of blind holes on the chips, so as to form a conductive layer between the chips through the opening of blind holes, thereby avoiding the occurrence of the problem of misalignment of drilling of small-sized chips and its impact on the overall yield of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings, where:

[0017] Figure 1 is a schematic structural diagram of a chip package in the prior art;

[0018] Figure 2 is a schematic structural diagram of the first embodiment of the chip package of the present application;

[0019] Figure 3 is Figure 2 a detailed schematic structural diagram of an embodiment of the connector in the chip package in;

[0020] Figure 4 is Figure 2 a detailed schematic structural diagram of another embodiment of the connector in the chip package in;

[0021] Figure 5 is a schematic structural diagram of the second embodiment of the chip package of the present application;

[0022] Figure 6a is a schematic flow chart of the first embodiment of the manufacturing method of the chip package of the present application;

[0023] Figures 6b - 6j is Figure 6a a schematic structural diagram of an implementation manner corresponding to S31-S36 in;

[0024] Figure 7 is Figure 6a a schematic flow chart of an embodiment of S31 in;

[0025] Figure 8 is a schematic structural diagram of an embodiment of the electronic device of the present application. Detailed implementation manners

[0026] To make the technical problems solved by the present application, the technical solutions adopted, and the achieved technical effects clearer, the technical solutions of the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0027] Referring to "embodiments" herein means that the specific features, structures, or characteristics described in connection with the embodiments may be included in at least one embodiment of the present application. The phrase appears in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

[0028] Please refer to Figure 2 and Figure 3 , wherein, Figure 2 is a schematic structural diagram of the first embodiment of the chip package of the present application, Figure 3 is Figure 2 a detailed schematic structural diagram of an embodiment of the connecting body in the chip package in. In this embodiment, the chip package 10 includes at least two pads 11 arranged at intervals, at least one chip component 12, and a conductive layer 13.

[0029] Among them, the pad 11 specifically refers to the welding pin of the chip package 10 for realizing electrical connection with external devices or external circuits, etc., and is used for electrical connection to each functional circuit layer inside the chip package 10 to be able to correspondingly realize the corresponding communication interaction and signal functions. And for the convenience of the external connection of the chip package 10, at least two pads 11 are specifically arranged at intervals on one side surface of the chip package 10.

[0030] Specifically, the chip component 12 further includes a conductive connecting body 121 and a chip 122. Among them, each conductive connecting body 121 is correspondingly arranged on a pad 11, and a groove 12121 is further arranged on the side of the conductive connecting body 121 facing away from the pad 11, and the chip 122 is further arranged in the groove 12121 to be able to achieve a closer combination with the conductive connecting body 121, and further be able to achieve a stronger combination with the corresponding pad 11 through the conductive connecting body 121, effectively avoiding the detachment of the pad 11 and the chip 122.

[0031] Among them, the thickness of the chip 122 is greater than the depth of the groove 12121, that is, the chip 122 protrudes from the groove 12121, so as to facilitate the subsequent formation of the conductive layer 13 on the side of the chip 122 facing away from the conductive connecting body 121.

[0032] Further, a conductive layer 13 is disposed on the chip 122 so that at least two chips 122 can be connected by means of the conductive layer 13.

[0033] It can be understood that when there are at least two chips 122 and the sides of at least two chips 122 intended to be connected, which are away from the pad 11, are in the same plane, the conductive layer 13 disposed on the chip 122 is specifically a plane and can be obtained by patterning a copper clad laminate, without making blind holes in the corresponding chips 122 and forming the corresponding conductive layer 13 through any reasonable process such as electroless copper plating and electroplating to realize the connection between at least two chips 122.

[0034] Thus, it can be known that the obtained chip package 10 can effectively reduce the making of blind holes on one side of the chip 122, and thus can also reduce the problem of drilling deviation existing in the small-sized chip 122. Moreover, by reducing the corresponding process flow, the manufacturing cost of the corresponding chip package 10 can also be effectively reduced.

[0035] When at least one of the chips 122 does not need to be connected to other chips 122, in order to ensure that the side of the chip 122 facing away from the conductive connection body 121 can also be electrically connected to an external device or an external circuit, etc., the chip 122 can specifically be connected to the pad 11 of other non-chip components 12 through the conductive layer 13.

[0036] In an embodiment, the chip package 10 further includes an insulating layer 14, and the insulating layer 14 specifically covers the chip component 12 and the conductive layer 13 to be used for encapsulating the chip component 12 and the conductive layer 13.

[0037] In an embodiment, the conductive connection body 121 specifically includes a conductive column 1211 and a connection body 1212 that are mutually attached or integrally formed. The conductive column 1211 is disposed on the pad 11, and a groove 12121 is disposed on the side of the connection body 1212 facing away from the conductive column 1211 for accommodating the chip 122. Among them, the projected area of the connection body 1212 on the pad 11 is larger than the projected area of the conductive column 1211 on the pad 11, that is, the projection of the connection body 1212 on the pad 11 completely covers the side of the conductive column 1211 facing the connection body 1212, so that through the irregular structure pattern of the connection body 1212, the combination of the conductive connection body 121 and the insulating layer 14 can be more firm, thereby being able to enhance the bonding force between the pad 11 and the insulating layer 14 and improve the reliability and yield of the product.

[0038] Optionally, the connector 1212 is an arc-shaped structure, that is, a partial sphere, and the curvature of the arc surface close to the conductive column 1211 is greater than the curvature of the arc surface away from the conductive column 1211, and together with the conductive column 1211, it forms a mushroom-shaped conductive connector 121.

[0039] Optionally, the conductive column 1211 is any reasonable column structure such as a cylinder or a cube, and the present application does not limit this.

[0040] In another embodiment, if Figure 4 As shown, Figure 4 yes Figure 2 A detailed structural diagram of another embodiment of the connector in the chip package. The connector 1212 can also be a triangle, and a groove 12121 is formed at one end of the triangle, and a corner is removed, and the projection area of the connector 1212 to the pad 11 is larger than the projection area of the conductive column 1211 to the pad 11. In other embodiments, the connector 1212 can also be a trapezoid or any other reasonable irregular structural style whose projection area to the pad 11 is larger than the projection area of the conductive column 1211 to the pad 11, and a groove 12121 is formed on the side away from the conductive column 1211, and the present application does not limit this.

[0041] In one embodiment, the conductive connector 121 is any reasonable columnar structure such as a cylinder or a cube, and the present application does not limit this.

[0042] In one embodiment, the chip package 10 further includes a conductive adhesive layer 15 disposed between the chip 122 and the bottom of the groove 12121 of the conductive connector 121 , so that the chip 122 can be bonded to the bottom of the groove 12121 through the conductive adhesive layer 15 .

[0043] Optionally, the conductive adhesive layer 15 may be made of a material such as solder paste or silver paste that can achieve conductive connection, and the present application does not limit this.

[0044] In one embodiment, the center lines of the conductive connector 121, the chip 122, and the pad 11 on which the chip component 12 is disposed in the same chip component 12 coincide with each other, that is, the corresponding position relationship of the three constitutes an "I" shape. In other embodiments, the center lines of the conductive connector 121, the chip 122, and the pad 11 on which the chip component 12 is disposed in the same chip component 12 may not coincide with each other, and the corresponding position relationship constitutes a "Z" shape, which is not limited in this application.

[0045] Differing from the prior art, in the chip package provided by the present application, the conductive connector is disposed on at least two pads arranged at intervals, and a groove is provided on a side of the conductive connector facing away from the pads, and the chip is specifically disposed in the groove, so as to effectively enhance the strength of the pads through the conductive connector and enhance the bonding force between the chip and the pads, and by disposing the chip in the groove, the risk of misalignment in the alignment of the chip on the pads is also effectively avoided; and the conductive layer is disposed on the chip, so that at least two chips are connected by means of the conductive layer, or at least one chip is connected to the pads of other pad sets without chip components, and it is also possible to reduce the formation of blind holes on the chip, so as to form a conductive layer through the blind holes between the chips, thereby avoiding the occurrence of the problem of misalignment of drilling for small-sized chips and its impact on the overall yield of the product.

[0046] Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of the second embodiment of the chip package of the present application. The difference between this embodiment and Figure 2 the first embodiment of the chip package provided by the present application in

[0047] is that when at least one chip 222 in the chip package 20 does not need to be connected to other chips 222, to ensure that the side of the chip 222 facing away from the conductive connector 221 can also be electrically connected to an external device or an external circuit, etc., the chip 222 can specifically also be connected to the pads 21 of other pad sets 22 without chip components through the conductive layer 23.

[0048] It can be understood that to connect at least one chip 222 to the pads 21 of other pad sets 22 without chip components, specifically, a blind hole (not shown in the figure) is formed corresponding to the pad 21, so as to be able to form a conductive layer 23 on the side surface of the chip 222 facing away from the conductive connector 221, as well as on the hole wall and bottom of the blind hole, and connect at least one chip 222 to the pads 21 of other pad sets 22 without chip components. In other embodiments, two blind holes can also be formed in the insulating layer 24 respectively corresponding to the side surface of the chip 222 facing away from the conductive connector 221 and the pads 21 to be connected thereto, so as to be able to form a conductive layer 23 on the hole walls and bottoms of the two blind holes, and connect at least one chip 222 to the pads 21 of other pad sets 22 without chip components. The present application does not make any limitations in this regard.

[0048] Among them, the conductive posts 2211, the connectors 2212, and the conductive adhesive layers 25 are the same as the conductive posts 1211, the connectors 1212, and the conductive adhesive layers 15 respectively. For details, please refer to Figure 2 and Figure 3 and the relevant text content, which will not be elaborated here.

[0049] On the other hand, the present application also provides a manufacturing method for a chip package. Please refer to Figures 6a - 6j , wherein,Figure 6a It is a schematic flow chart of the first embodiment of the manufacturing method of the chip package of the present application. Figures 6b - 6j It is Figure 6a a schematic structural diagram of an implementation manner corresponding to S31 - S36 in

[0050] S31: Provide a carrier copper clad laminate, and set at least one conductive connection body on the carrier copper clad laminate.

[0051] Specifically, as Figure 6b shown, after providing a carrier copper clad laminate 41, at least one conductive connection body 42 is further set on the carrier copper clad laminate 41. For example, in one embodiment, copper pillars are electroplated on an ultra-thin peelable carrier, and then a mushroom-shaped conductive connection body 42 is made based on the copper pillars.

[0052] For the convenience of description, in this embodiment, the number of conductive connection bodies 42 is stated as 2. It can be understood that in other embodiments, the number of the conductive connection bodies 42 can also be any reasonable number such as 1, 3, or 5, etc., and the present application does not limit this.

[0053] Optionally, the conductive connection body 42 can specifically also be any reasonable columnar structure such as a cylinder or a cube, etc., and the present application does not limit this.

[0054] S32: Form a first insulating layer on the carrier copper clad laminate and the conductive connection body, and expose part of the conductive connection body.

[0055] Further, as Figure 6c and Figure 6d shown, a first insulating layer 43 is formed on the carrier copper clad laminate 41 and the conductive connection body 42 to completely cover the conductive connection body 42, and then the side of the first insulating layer 43 facing away from the carrier copper clad laminate 41 is polished until part of the conductive connection body 42 is exposed. In other embodiments, a first insulating layer 43 that exposes part of the conductive connection body 42 can also be directly formed on the carrier copper clad laminate 41 and the conductive connection body 42, and the present application does not limit this.

[0056] S33: Open a groove at the exposed part corresponding to each conductive connection body.

[0057] Specifically, as Figure 6e shown, a groove 4221 is opened at the exposed part corresponding to each of the conductive connection bodies 42. For example, a groove 4221 is made on the conductive connection body 42 by an etching process.

[0058] S34: Set a chip in each groove.

[0059] Further, asFigure 6f As shown, a chip 44 is correspondingly disposed in each groove 4221. For example, the chip 44 is attached to the groove 4221 by a conductive adhesive, solder paste, silver paste or other substances that can achieve conductive connection.

[0060] Wherein, the thickness of the chip 44 is greater than the depth of the groove 4221.

[0061] In one embodiment, the chip 44 is specifically bonded to the bottom of the groove 4221 through a conductive adhesive layer 45, and the conductive adhesive layer 45 can specifically be made of one of solder paste, silver paste or other substances that can achieve conductive connection. The present application does not limit this.

[0062] S35: Form a conductive layer on at least two chips so that the at least two chips are connected by means of the conductive layer.

[0063] It can be understood that, as Figure 6g and Figure 6h shown, when there are at least two chips 44 and the side surfaces of the at least two chips 44 aimed at connection away from the pads 411 are on the same plane, a conductive layer 47 corresponding to a plane can also be directly formed on the at least two chips 44 so that the at least two chips 44 are connected by means of the conductive layer 47.

[0064] Specifically, in one embodiment, after each chip 44 is disposed in the corresponding groove 4221, a second insulating layer 46 is further formed on the first insulating layer 43 to cover each chip 44 through the second insulating layer 46 and the first insulating layer 43, and then the surface resin of each chip 44 is removed. For example, the insulating resin above each chip 44 is removed by means of laser ablation, chemical solution corrosion, etc. to expose the side of each chip 44 facing away from the conductive connector 42.

[0065] Furthermore, a copper clad laminate (not shown in the figure) is disposed on the chip 44 and the second insulating layer 46, and the copper clad laminate is patterned according to actual needs to obtain the corresponding conductive layer 47.

[0066] Still further, as Figure 6i shown, a third insulating layer 48 is formed on the second insulating layer 46 and the conductive layer 47 to cover the conductive layer 47 through the second insulating layer 46 and the third insulating layer 48 to protect the conductive layer 47.

[0067] It can be seen therefrom that the corresponding chip package effectively reduces the process flow of making blind holes on one side of the chip 44 and forming the corresponding conductive layer 47 through the processes of electroless copper plating and electroplating, effectively avoids the problem of drilling deviation existing in small-size chips 44, and also reduces the manufacturing cost of the corresponding chip package by reducing the corresponding process flow.

[0068] In another embodiment, after each chip 44 is disposed in the corresponding groove 4221, a conductive layer 47 may be directly formed on at least two chips 44 that are intended to be connected, and then a third insulating layer 48 may be formed to cooperate with the second insulating layer 46 to cover each chip 44 and the conductive layer 47 therewith.

[0069] Optionally, the materials of the first insulating layer 43, the second insulating layer 46, and the third insulating layer 48 may be the same. For example, they may all be a resin material or any other reasonable insulating encapsulation material, or they may be different. This application does not make any limitation thereto.

[0070] S36: Pattern the carrier copper clad laminate to form at least two pads corresponding to the conductive connectors at intervals.

[0071] Specifically, after the conductive layer 47 is formed so that at least two chips 44 are connected by means of the conductive layer 47, the carrier copper clad laminate 41 is patterned. For example, any reasonable process flow such as a preset solder mask and etching process is performed on the carrier copper clad laminate 41 to form at least two pads 411 corresponding to the conductive connectors 42 at intervals.

[0072] Further, in one embodiment, when at least one of the chips 44 does not need to be connected to other chips 44, in the above S35, it further includes: at positions corresponding to the chip 44 and the positions on the carrier copper clad laminate 41 where the pads 411 are to be formed, two blind holes are formed in the first insulating layer 43 and the second insulating layer 46, and then a conductive layer 47 is formed on the hole walls and bottoms of the blind holes to achieve the connection between at least one chip 44 and the positions on the carrier copper clad laminate 41 where the pads 411 are to be formed and where no conductive connectors 42 are provided.

[0073] Please refer to Figure 7 , Figure 7 is Figure 6a a schematic flow chart of an embodiment of S11 in

[0074] S311: Provide at least one conductive post on the carrier copper clad laminate.

[0075] Specifically, as Figure 6b shown, at least one conductive post 421 is provided at a preset position of the carrier copper clad laminate 41. For example, a copper post is electroplated on an ultra-thin peelable carrier.

[0076] Optionally, the conductive post 421 has any reasonable columnar structure such as a cylinder or a cube. This application does not make any limitation thereto.

[0077] S312: Disposing a connector on each conductive column, so that a conductive connector is formed by the conductive column and the connector.

[0078] Furthermore, if Figure 6b As shown, a connector 422 is disposed on each conductive column 421, so that the conductive column 421 and the connector 422 are formed into a conductive connector 42. The projection area of the connector 422 to the pad 411 is larger than the projection area of the conductive column 421 to the pad 411.

[0079] Optionally, the connector 422 is an arc-shaped structure, that is, a partial sphere, and the arc surface close to the conductive column 421 has a greater curvature than the arc surface away from the conductive column 421 , and together with the conductive column 421 , forms a mushroom-shaped conductive connector 42 .

[0080] Optionally, the connector 422 may also be a triangle, and a groove 4221 is correspondingly formed at one end of the triangle, and a corner is correspondingly removed, and the projection area of the connector 422 to the pad 411 is larger than the area of the pad 411. In other embodiments, the connector 422 may also be a trapezoid or any other reasonable irregular structural style in which the projection area to the pad 411 is larger than the projection area of the conductive column 421 to the pad 411, and a groove 4221 is correspondingly formed on the side away from the conductive column 421, which is not limited in the present application.

[0081] In another aspect, the present application also provides an electronic device, see Figure 8 , Figure 8 1 is a schematic diagram of the structure of an embodiment of the electronic device of the present application. The electronic device 51 includes a chip package 511. It should be noted that the chip package 511 described in this embodiment is the chip package 10 or the chip package 20 described in any one of the above embodiments, which will not be described in detail here.

[0082] Different from the prior art, the conductive connector in the chip package provided by the present application is arranged on at least two pads arranged at intervals, and a groove is arranged on the side of the conductive connector away from the pad, and the chip is specifically arranged in the groove, so that the strength of the pad can be effectively enhanced by the conductive connector, and the bonding force between the chip and the pad can be enhanced. By setting the chip in the groove, the risk of deviation of the chip on the pad is also effectively avoided; and the conductive layer is set on the chip so that at least two chips are connected through the conductive layer, or at least one chip is connected to other pads without chip components, which can also reduce the opening of blind holes on the chip, so as to realize the formation of a conductive layer between the chips by opening blind holes, thereby avoiding the occurrence of deviation problems in drilling holes of small-size chips and its impact on the overall yield of the product.

[0083] The above are only embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be similarly included in the patent protection scope of the present application.

Claims

1. A chip package, characterized in that, The chip package includes: At least two pads arranged at intervals; At least one chip component, the chip component including a conductive connection body and a chip; the conductive connection body is arranged on the pad, and a groove is arranged on a side facing away from the pad, and the chip is arranged in the groove; wherein, the thickness of the chip is greater than the depth of the groove; A conductive adhesive layer arranged between the chip and the bottom of the groove to bond the chip to the bottom of the groove; A conductive layer arranged on the chip to connect at least two chips through the conductive layer, or to connect at least one chip to other pads without the chip component arranged thereon; The conductive connection body includes a conductive column and a connection body that are attached to each other or integrally formed. The conductive column is arranged on the pad, and the connection body is provided with the groove on a side facing away from the conductive column for accommodating the chip; Wherein, the projected area of the connection body on the pad is greater than the projected area of the conductive column on the pad.

2. The chip package according to claim 1, wherein The chip package further includes an insulating layer that coats the chip component and the conductive layer.

3. The chip package according to claim 1, wherein The connection body is in an arc structure, and the radian of the arc surface close to the conductive column is greater than the radian of the arc surface far from the conductive column.

4. The chip package according to any one of claims 1-2, characterized in that, The center lines of the conductive connection body, the chip, and the pad on which the chip component is arranged in the same chip component coincide.

5. The chip package according to any one of claims 1-2, characterized in that, When there are at least two chips, one side surfaces of at least two chips facing away from the pad are on the same plane, so that the conductive layer arranged on the chips is a plane.

6. The chip package according to any one of claims 1-2, wherein The conductive connection body is a cylinder or a cube.

7. A manufacturing method of a chip package, characterized in that, The manufacturing process method includes: Providing a carrier copper clad laminate, and arranging at least one conductive connection body on the carrier copper clad laminate, including: arranging at least one conductive column on the carrier copper clad laminate; arranging a connection body on each conductive column to form the conductive connection body from the conductive column and the connection body; Forming a first insulating layer on the carrier copper clad laminate and the conductive connection body, and exposing a part of the conductive connection body; Opening a groove at the exposed part of each conductive connection body; Arranging a chip in each groove; wherein, the thickness of the chip is greater than the depth of the groove, and the chip is bonded to the bottom of the groove through a conductive adhesive layer; Forming a conductive layer on at least two chips to connect at least two chips through the conductive layer; or, forming the conductive layer in at least one chip and the first insulating layer to connect at least one chip to a set position on the carrier copper clad laminate where the conductive connection body is not arranged; Patterning the carrier copper clad laminate to form at least two pads at intervals corresponding to the conductive connection body, or a set position of the conductive connection body and the carrier copper clad laminate; wherein, the projected area of the connection body on the pad is greater than the projected area of the conductive column on the pad.

8. An electronic device, the electronic device comprising a chip package as described in any one of claims 1-6.

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