Display substrate, manufacturing method thereof, and display device

Abstract

Provided are a display substrate, a manufacturing method thereof, and a display device, belonging to the field of display technology. The display substrate includes a substrate, and a pixel electrode, an interlayer film layer, a source-drain metal layer, a passivation layer, and a common electrode located on one side of the substrate and stacked in sequence in a direction away from the substrate. The interlayer film layer has a via exposing the pixel electrode, and the source-drain metal layer can be directly overlapped with the pixel electrode through the via. Correspondingly, it can be seen that the orthographic projection of the via on the substrate can be located within the orthographic projection of the pixel electrode on the substrate, and can be covered by the source-drain metal layer. In this way, on the basis of ensuring that the source-drain metal layer is reliably overlapped with the pixel electrode, it can be ensured that the aperture ratio of the display substrate is large, and thus the transmittance of the display substrate can be ensured to be good.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] The display substrate is an essential part of the display device and is used to display images.

[0003] Currently, display substrates generally include a substrate and a pixel structure located on one side of the substrate. The pixel structure generally includes a pixel electrode, a gate insulation layer, a source / drain metal layer, a passivation layer, and a common electrode, stacked in sequence along the side facing away from the substrate. The common electrode is connected to the source / drain metal layer and the pixel electrode through vias penetrating the passivation layer and the gate insulation layer, respectively, to couple the source / drain metal layer and the pixel electrode to each other.

[0004] However, due to the influence of the overlapping method, the current display substrate has a small aperture ratio and low transmittance. Summary of the Invention

[0005] Provided are a display substrate, a manufacturing method thereof, and a display device, which can solve the problems of small aperture ratio and low transmittance of display substrates in related technologies. The technical solution is as follows:

[0006] In one aspect, a display substrate is provided, comprising:

[0007] substrate;

[0008] a pixel electrode located on one side of the substrate;

[0009] an interlayer film layer located on a side of the pixel electrode away from the substrate, the interlayer film layer having a via hole exposing the pixel electrode, and an orthographic projection of the via hole on the substrate being within an orthographic projection of the pixel electrode on the substrate;

[0010] a source / drain metal layer located on a side of the interlayer film layer away from the substrate, wherein the orthographic projection of the source / drain metal layer on the substrate is located within the orthographic projection of the pixel electrode on the substrate and covers the orthographic projection of the via hole on the substrate, and the source / drain metal layer is overlapped with the pixel electrode through the via hole;

[0011] Also, a passivation layer and a common electrode are located on a side of the source / drain metal layer away from the substrate and are sequentially stacked in a direction away from the substrate.

[0012] Optionally, the interlayer film layer includes: a gate insulating layer located on a side of the pixel electrode away from the substrate;

[0013] The orthographic projection of the gate insulation layer on the substrate covers the orthographic projection of the pixel electrode on the substrate.

[0014] Optionally, the display substrate further comprises: an active layer located between the gate insulating layer and the source / drain metal layer;

[0015] The orthographic projection of the active layer on the substrate does not overlap with the orthographic projection of the pixel electrode on the substrate.

[0016] Optionally, the interlayer film layer includes: a gate insulating layer and an active layer located on a side of the pixel electrode away from the substrate and stacked in sequence in a direction away from the substrate;

[0017] In which, the orthographic projection of the gate insulation layer on the substrate covers the orthographic projection of the pixel electrode on the substrate; in the active layer, the orthographic projection of the first part having the via hole on the substrate is located within the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the second part other than the first part on the substrate does not overlap with the orthographic projection of the pixel electrode on the substrate.

[0018] Optionally, the display substrate further comprises: a gate metal layer located between the pixel electrode and the interlayer film layer;

[0019] The orthographic projection of the gate metal layer on the substrate does not overlap with the orthographic projection of the pixel electrode on the substrate.

[0020] In another aspect, a method for manufacturing a display substrate is provided, for manufacturing the display substrate according to the above aspect, the method comprising:

[0021] providing a substrate;

[0022] forming a pixel electrode on one side of the substrate;

[0023] forming an interlayer film layer on a side of the pixel electrode away from the substrate, wherein the interlayer film layer has a via hole exposing the pixel electrode, and an orthographic projection of the via hole on the substrate is located within an orthographic projection of the pixel electrode on the substrate;

[0024] forming a source-drain metal layer on a side of the interlayer film away from the substrate, wherein the orthographic projection of the source-drain metal layer on the substrate is located within the orthographic projection of the pixel electrode on the substrate and covers the orthographic projection of the via hole on the substrate, and the source-drain metal layer is overlapped with the pixel electrode through the via hole;

[0025] A passivation layer and a common electrode are formed on a side of the source / drain metal layer away from the substrate and are sequentially stacked in a direction away from the substrate.

[0026] Optionally, the interlayer film layer includes: a gate insulating layer located on a side of the pixel electrode away from the substrate; and forming the interlayer film layer on a side of the pixel electrode away from the substrate includes:

[0027] forming a gate insulating film on a side of the pixel electrode away from the substrate;

[0028] Performing a patterning process on the gate insulating film using a mask to form a gate insulating layer and a via hole penetrating the gate insulating layer;

[0029] After forming the gate insulating layer and the via hole penetrating the gate insulating layer, the method further includes:

[0030] An active layer is formed on a side of the gate insulating layer away from the substrate, and an orthographic projection of the active layer on the substrate does not overlap with an orthographic projection of the pixel electrode on the substrate.

[0031] Optionally, forming a source / drain metal layer on a side of the interlayer film layer away from the substrate includes:

[0032] forming a source-drain metal film on a side of the interlayer film away from the substrate;

[0033] Performing a patterning process on the source / drain metal film using a first mask to form a source / drain metal layer;

[0034] The interlayer film layer includes: a gate insulating layer and an active layer that are located on a side of the pixel electrode away from the substrate and are sequentially stacked in a direction away from the substrate; the interlayer film layer formed on the side of the pixel electrode away from the substrate includes:

[0035] forming a gate insulating film and an active film stacked in sequence in a direction away from the substrate on a side of the pixel electrode away from the substrate;

[0036] Using a second mask plate, the active film and the gate insulating film are patterned in sequence to form an active layer pattern, a gate insulating layer, and a via hole penetrating the active layer pattern and the gate insulating layer;

[0037] The active layer pattern is patterned using the first mask plate to form an active layer. In the formed active layer, the orthographic projection of the first portion having the via hole on the substrate is located within the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the second portion other than the first portion on the substrate does not overlap with the orthographic projection of the pixel electrode on the substrate.

[0038] Optionally, before forming an interlayer film layer on a side of the pixel electrode away from the substrate, the method further includes:

[0039] forming a gate metal layer on a side of the pixel electrode away from the substrate, wherein an orthographic projection of the gate metal layer on the substrate does not overlap with an orthographic projection of the pixel electrode on the substrate;

[0040] The step of forming an interlayer film layer on a side of the pixel electrode away from the substrate comprises:

[0041] An interlayer film layer is formed on a side of the gate metal layer away from the substrate.

[0042] In another aspect, a display device is provided, comprising: a power supply component, and the display substrate according to the above aspect;

[0043] The power supply component is coupled to the display substrate and is used to supply power to the display substrate.

[0044] In summary, the beneficial effects brought about by the technical solutions provided by the embodiments of the present disclosure may include at least:

[0045] Provided are a display substrate, a method for manufacturing the same, and a display device. The display substrate includes a substrate, and a pixel electrode, an interlayer film layer, a source / drain metal layer, a passivation layer, and a common electrode located on one side of the substrate and stacked in sequence in a direction away from the substrate. The interlayer film layer has a via that exposes the pixel electrode, and the source / drain metal layer can be directly overlapped with the pixel electrode through the via. Accordingly, it can be seen that the orthographic projection of the via on the substrate can be located within the orthographic projection of the pixel electrode on the substrate, and can be covered by the source / drain metal layer. In this way, on the basis of ensuring that the source / drain metal layer is reliably overlapped with the pixel electrode, the aperture ratio of the display substrate can be ensured to be large, and thus the transmittance of the display substrate can be ensured to be good. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0048] Figure 2 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0049] Figure 3 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0050] Figure 4is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0051] Figure 5 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0052] Figure 6 is a flow chart of a method for manufacturing a display substrate provided by an embodiment of the present disclosure;

[0053] Figure 7 is a flow chart of another method for manufacturing a display substrate provided by an embodiment of the present disclosure;

[0054] Figure 8 is a flow chart of a manufacturing process of a display substrate provided by an embodiment of the present disclosure;

[0055] Figure 9 is a flow chart of another process for manufacturing a display substrate provided by an embodiment of the present disclosure;

[0056] Figure 10 It is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0058] Figure 1 Schematic diagram of the structure of a display substrate provided by an embodiment of the present disclosure. Figure 1 As shown, the display substrate includes:

[0059] Substrate 01.

[0060] The pixel electrode 02 is located on one side of the substrate 01.

[0061] The interlayer film layer 03 is located on the side of the pixel electrode 02 away from the substrate 01. The interlayer film layer 03 has a via K1 exposing the pixel electrode 02, and the orthographic projection of the via K1 on the substrate 01 is located within the orthographic projection of the pixel electrode 02 on the substrate 01.

[0062] The source and drain (SD) metal layer 04, also called the SD layer, is located on the side of the interlayer film layer 03 away from the substrate 01. The orthographic projection of the source and drain metal layer 04 on the substrate 01 is located within the orthographic projection of the pixel electrode 02 on the substrate 01 and covers the orthographic projection of the via K1 on the substrate 01. Furthermore, the source and drain metal layer 04 is overlapped with the pixel electrode 02 through the via K1 (overlapping can mean electrically connected).

[0063] Also, a passivation (PVX) layer 05 and a common electrode 06 are located on the side of the source / drain metal layer 04 away from the substrate 01 and are sequentially stacked in a direction away from the substrate 01 . The passivation layer 05 is also called a PVX layer.

[0064] That is, in the embodiment of the present disclosure, the pixel electrode 02, the interlayer film layer 03, the source-drain metal layer 04, the passivation layer 05 and the common electrode 06 can be stacked in sequence in the direction away from the substrate 01, and the pixel electrode 02 is closest to the substrate 01 relative to the other film layers. In addition, the source-drain metal layer 04 can be directly overlapped with the pixel electrode 02 through the via K1 that passes through the interlayer film layer 03 located therebelow, that is, there is no need to indirectly overlap with the pixel electrode 02 through other film layers. In this way, on the one hand, the overlap reliability can be ensured. On the other hand, as described in the above embodiment, the via K1 for overlapping the pixel electrode 02 with the source-drain metal layer 04 can be covered by the source-drain metal layer 04, that is, the via K1 is not separately opened at a position not covered by the source-drain metal layer 04. In this way, it can be ensured that the aperture ratio of the display substrate can be maximized and that the transmittance of the display substrate can be better.

[0065] In summary, an embodiment of the present disclosure provides a display substrate. The display substrate includes a substrate, and a pixel electrode, an interlayer film layer, a source / drain metal layer, a passivation layer, and a common electrode located on one side of the substrate and stacked in sequence in a direction away from the substrate. The interlayer film layer has a via exposing the pixel electrode, and the source / drain metal layer can be directly overlapped with the pixel electrode through the via. Correspondingly, it can be seen that the orthographic projection of the via on the substrate can be located within the orthographic projection of the pixel electrode on the substrate, and can be covered by the source / drain metal layer. In this way, on the basis of ensuring that the source / drain metal layer is reliably overlapped with the pixel electrode, it can be ensured that the aperture ratio of the display substrate is large, and thus the transmittance of the display substrate can be ensured to be good.

[0066] As an optional implementation: refer to Figure 2 As shown in the structural diagram of another display substrate, the interlayer film layer 03 may include: a gate insulator (GI) layer located on the side of the pixel electrode 02 away from the substrate 01 .

[0067] The orthographic projection of the gate insulating layer GI on the substrate 01 can cover the orthographic projection of the pixel electrode 02 on the substrate 01. Accordingly, a via K1 can be opened in the gate insulating layer GI to expose the pixel electrode 02, allowing the source and drain metal layer 04 to overlap the pixel electrode 02 through the via K1 that penetrates the gate insulating layer GI. In other words, the display substrate may include: a gate insulating layer GI, and a via K1 that penetrates the gate insulating layer GI and exposes the pixel electrode 02.

[0068] exist Figure 2 Based on the structure shown, Figure 3A structural schematic diagram of another display substrate provided by an embodiment of the present disclosure is shown. Figure 2 The structure shown can be considered as Figure 3 The structure is shown in a cross-sectional view along the AA' direction.

[0069] refer to Figure 3 It can be seen that the display substrate provided by the embodiment of the present disclosure may further include: an active layer Ac1 located between the gate insulating layer GI and the source / drain metal layer 04 .

[0070] The orthographic projection of the active layer Ac1 on the substrate 01 may not overlap with the orthographic projection of the pixel electrode 02 on the substrate 01. Overlapping may refer to overlapping or partially overlapping. Figure 3 It can also be seen that the active layer Ac1 can be electrically connected to the source-drain metal layer 04 .

[0071] As another optional implementation: refer to Figure 4 As shown in the structural diagram of another display substrate, the interlayer film layer 03 may include: a gate insulating layer GI and an active layer Ac1 located on the side of the pixel electrode 02 away from the substrate 01 and stacked in sequence in a direction away from the substrate 01 .

[0072] The orthographic projection of the gate insulating layer GI on the substrate 01 may cover the orthographic projection of the pixel electrode 02 on the substrate 01 .

[0073] In the active layer Ac1, the orthographic projection of the first part Ac1-1 having the via K1 on the substrate 01 can be located within the orthographic projection of the pixel electrode 02 on the substrate 01, and the orthographic projection of the second part Ac1-2 other than the first part Ac1-1 on the substrate 01 may not overlap with the orthographic projection of the pixel electrode 02 on the substrate 01.

[0074] exist Figure 4 Based on the structure shown, Figure 5 A structural schematic diagram of another display substrate provided by an embodiment of the present disclosure is shown. Figure 4 The structure shown can be considered as Figure 5 Cross-sectional view of the structure shown in the BB' direction.

[0075] Combine Figure 5 It can be seen that in another implementation, the active layer Ac1 included in the display substrate may have a first portion Ac1-1 and a second portion Ac1-2 located in the same layer and arranged at intervals.

[0076] The orthographic projection of the first portion Ac1-1 on the substrate 01 can be located within the orthographic projection of the pixel electrode 02 on the substrate 01. That is, the interlayer film layer 03 located between the pixel electrode 02 and the source / drain metal layer 04 includes the first portion Ac1-1 of the active layer Ac1 and the gate insulating layer GI stacked in sequence. Accordingly, a via K1 needs to be opened in the first portion Ac1-1 of the active layer Ac1 and the gate insulating layer GI to expose the pixel electrode 02, allowing the source / drain metal layer 04 to overlap the pixel electrode 02 through the via K1 that penetrates the first portion Ac1-1 of the active layer Ac1 and the gate insulating layer GI. In other words, the display substrate may include: the gate insulating layer GI, the active layer Ac1, and the via K1 that penetrates the first portion Ac1-1 of the active layer Ac1 and the gate insulating layer GI and exposes the pixel electrode 02.

[0077] The orthographic projection of the second portion Ac1-2 on the substrate 01 does not overlap with the orthographic projection of the pixel electrode 02 on the substrate 01, and the orthographic projection of the second portion Ac1-2 on the substrate 01 does not overlap with the orthographic projection of the pixel electrode 02 on the substrate 01. Figure 5 , the second portion Ac1-2 can be electrically connected to the source-drain metal layer 04. Figure 3 It can be seen that the second part Ac1-2 of the active layer Ac1 in this other implementation is actually equivalent to Figure 3 Active layer Ac1 is shown. Figure 5 Relative to Figure 3 In terms of structure, it can be considered that the active layer Ac1 also includes a first portion Ac1 - 1 located between the pixel electrode 02 and the source / drain metal layer 04 , and a via hole passing through the first portion Ac1 - 1 .

[0078] It should be noted that the active layer Ac1 may have a semiconductor region (also called a channel region) and conductive regions located on both sides of the channel region (referred to as a source region and a drain region, respectively). The semiconductor region may not be doped, or the doping type may be different from that of the source region and the drain region, and thus have semiconductor properties. The conductive region may be doped and thus have conductivity. The doped impurities may vary depending on the type of transistor (i.e., N-type or P-type). The source and drain metal layer 04 may overlap with the conductive region therein.

[0079] It should also be noted that being located in the same layer may refer to a layer structure formed by patterning the film layer for forming a specific pattern using the same film-forming process, and then patterning the film layer using the same mask through a single composition process. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and / or parts located in the "same layer" are made of the same material and are formed through the same composition process. In this way, the manufacturing process and manufacturing costs can be saved, and the manufacturing efficiency can be accelerated. That is, the first part Ac1-1 and the second part Ac1-2 of the active layer Ac1 recorded in the embodiment of the present disclosure can be made of the same material and formed through a single composition process.

[0080] Combine Figure 3 and Figure 5 It can also be seen that the display substrate provided by the embodiment of the present disclosure may further include: a gate metal layer 07 located between the pixel electrode 02 and the interlayer film layer 03. The gate metal layer 07 may also be referred to as a gate layer.

[0081] The orthographic projection of the gate metal layer 07 on the substrate 01 may not overlap with the orthographic projection of the pixel electrode 02 on the substrate 01 , and may overlap with the orthographic projection of the active layer Ac1 on the substrate 01 .

[0082] That is, in the embodiment of the present disclosure, in a direction away from the substrate 01, the pixel electrode 02, gate metal layer 07, gate insulation layer GI, active layer Ac1, source / drain metal layer 04, passivation layer 05, and common electrode 06 may be stacked in sequence. The structure composed of the film layers other than the substrate 01 can be referred to as a pixel structure.

[0083] Optionally, the pixel structure may include: a driving transistor and a light emitting unit. The substrate 01 may have a transistor area and a display area. Figure 2 and Figure 4 Only the display area is shown. The driving transistor may include a gate metal layer 07, a gate insulating layer GI, an active layer Ac1, a source / drain metal layer 04, and a passivation layer 05. The light emitting unit may include a pixel electrode 02 and a common electrode 06.

[0084] Accordingly, combined Figures 2 to 5 It can be seen that in the embodiment of the present disclosure, the pixel electrode 02 can be located in the display area. The gate metal layer 07 can be located in the transistor area. The gate insulating layer GI can be located partially in the display area and partially in the transistor area, and can cover the substrate 01 in its entirety. Figure 2 and Figure 3 In an optional embodiment shown in FIG, the active layer Ac1 may be located only in the transistor region. Figure 4 and Figure 5 In another optional embodiment shown, the active layer Ac1 can be partially (specifically, the second portion Ac1-2) located in the transistor area, and partially (specifically, the first portion Ac1-1) located in the display area. The source-drain metal layer 04 can be partially located in the display area and partially located in the transistor area, and the portion located in the display area overlaps with the pixel electrode 02, and the portion located in the transistor area overlaps with the active layer Ac1 located in the transistor area. The passivation layer 05 can be partially located in the display area and partially located in the transistor area, and the entire layer covers the substrate 01. The common electrode 06 can be partially located in the display area and partially located in the transistor area, and can cover the entire layer of the substrate 01.

[0085] Optionally, the display substrate described in the embodiments of the present disclosure may be a high-aperture ratio and high-advanced dimension switch (HADS) display substrate. Accordingly, the pixel structure described in the embodiments of the present disclosure may also be referred to as a HADS pixel structure. The HADS pixel structure offers advantages such as high transmittance and a wide viewing angle, and can be applied to display products such as mobile phones and computers.

[0086] Optionally, in the embodiment of the present disclosure, the substrate 01 may be a glass substrate. Of course, in some other embodiments, the substrate 01 may also be a flexible substrate, that is, a substrate made of a flexible material. The flexible material may be, for example, a polyimide material.

[0087] Optionally, in the disclosed embodiment, the material of the pixel electrode 02 and the material of the common electrode 06 can both be transparent conductive materials. For example, the transparent material can include: indium tin oxide (ITO) material. In this way, the transmittance of the display substrate can be ensured to be good, and the display effect can be better. Accordingly, combined with the position of the pixel electrode 02 and the common electrode 06, in the disclosed embodiment, the pixel electrode 02 can also be referred to as the 1TO layer, and the common electrode 06 can also be referred to as the 2TO layer.

[0088] Optionally, in the embodiment of the present disclosure, the material of the gate metal layer 07 and the material of the source / drain metal layer 04 may both include: metal materials with strong conductivity, such as metal aluminum, metal silver, metal molybdenum or alloys.

[0089] Optionally, in the embodiment of the present disclosure, the material of the gate insulating layer GI may include an inorganic material or an organic material, such as silicon nitride SiNx.

[0090] Optionally, in the embodiment of the present disclosure, the material of the active layer Ac1 may include semiconductor materials such as polysilicon, amorphous silicon (a-Si) or oxide semiconductor.

[0091] Optionally, in the embodiment of the present disclosure, the material of the passivation layer 05 may include: inorganic material.

[0092] Currently, as described in the background art, when the pixel electrode 02 is located on the side of the gate insulating layer GI close to the substrate 01, it is necessary to open a via hole in the portion of the source / drain metal layer 04 that does not overlap with the substrate 01, and to set a common electrode at the top to indirectly connect the source / drain metal layer 04 to the pixel electrode 02 through the via hole. This implementation method not only results in a smaller aperture ratio of the display substrate, but also poor connection reliability. On the other hand, combined with Figure 2 , currently, in the direction away from the substrate 01, the gate insulating layer GI, the pixel electrode 02 and the source-drain metal layer 04 can be stacked in sequence, and the source-drain metal layer 04 is in contact with the pixel electrode 02. However, in this implementation, the pixel electrode 02 cannot be set on the side of the gate insulating layer GI close to the substrate 01. On the other hand, combined with Figure 4 Currently, the gate insulating layer GI, active layer Ac1, source / drain metal layer 04, and pixel electrode 02 are stacked sequentially in a direction away from substrate 01, with pixel electrode 02 overlapping the source / drain metal layer 04 by climbing along the sidewalls of the source / drain metal layer 04. However, with this implementation, pixel electrode 02 cannot be positioned on the side of gate insulating layer GI close to substrate 01. Furthermore, pixel electrode 02 is prone to fracture as it climbs over source / drain metal layer 04, a common problem in mass production.

[0093] Based on the above embodiments, it can be seen that the display substrate provided by the embodiments of the present disclosure not only enables the pixel electrode 02 to be located on the side of the gate insulating layer GI closer to the substrate 01, that is, below the gate insulating layer GI, but also ensures that the aperture ratio of the display substrate is maximized. In addition, it can also prevent the pixel electrode 02 from breaking. The display substrate provided by the embodiments of the present disclosure has a good product yield.

[0094] In summary, an embodiment of the present disclosure provides a display substrate. The display substrate includes a substrate, and a pixel electrode, an interlayer film layer, a source / drain metal layer, a passivation layer, and a common electrode located on one side of the substrate and stacked in sequence in a direction away from the substrate. The interlayer film layer has a via exposing the pixel electrode, and the source / drain metal layer can be directly overlapped with the pixel electrode through the via. Correspondingly, it can be seen that the orthographic projection of the via on the substrate can be located within the orthographic projection of the pixel electrode on the substrate, and can be covered by the source / drain metal layer. In this way, on the basis of ensuring that the source / drain metal layer is reliably overlapped with the pixel electrode, it can be ensured that the aperture ratio of the display substrate is large, and thus the transmittance of the display substrate can be ensured to be good.

[0095] Figure 6 This is a flow chart of a method for manufacturing a display substrate provided by an embodiment of the present disclosure. The method can be used to manufacture Figures 1 to 5 Any of the display substrates shown. Figure 6 As shown, the method includes:

[0096] Step 601: Provide a substrate.

[0097] Optional, combined Figure 1 As described in the above embodiment, the provided substrate 01 can be a glass substrate or a flexible substrate.

[0098] Step 602: forming a pixel electrode on one side of the substrate.

[0099] Optional, combined Figure 1 A pixel electrode film may be first deposited on a substrate, and then patterned using a mask to form the pixel electrode 02. The patterning process may include sequentially performing steps of coating, exposure, development, and etching.

[0100] Step 603: forming an interlayer film layer on a side of the pixel electrode away from the substrate.

[0101] Among them, combined Figure 1 The formed interlayer film layer 03 may have a via K1 exposing the pixel electrode 02, and the orthographic projection of the via K1 on the substrate 01 may be located within the orthographic projection of the pixel electrode 02 on the substrate 01. Optionally, as in step 602 above, a mask may be used to form the interlayer film layer through a patterning process.

[0102] Step 604 : forming a source / drain metal layer on a side of the interlayer film layer away from the substrate.

[0103] Among them, combined Figure 1 The orthographic projection of the formed source / drain metal layer 04 on the substrate 01 can be located within the orthographic projection of the pixel electrode 02 on the substrate 01 and cover the orthographic projection of the via K1 on the substrate 01. The source / drain metal layer 04 can overlap the pixel electrode 02 through the via K1. Optionally, as in step 602 above, a mask can be used to form an interlayer film through a patterning process.

[0104] Step 605 : forming a passivation layer and a common electrode stacked in sequence in a direction away from the substrate on a side of the source / drain metal layer away from the substrate.

[0105] Optional, combined Figure 1 As in step 602 above, a mask plate may also be used to form a sequentially stacked passivation layer 05 and a common electrode 06 through a patterning process.

[0106] In summary, the embodiments of the present disclosure provide a method for manufacturing a display substrate. In this method, a pixel electrode, an interlayer film layer, a source / drain metal layer, a passivation layer, and a common electrode stacked in sequence in a direction away from the substrate can be formed on one side of the provided substrate. In addition, the formed interlayer film layer has a via exposing the pixel electrode, and the source / drain metal layer can be directly overlapped with the pixel electrode through the via. Correspondingly, it can be seen that the orthographic projection of the via on the substrate can be located within the orthographic projection of the pixel electrode on the substrate, and can be covered by the source / drain metal layer. In this way, on the basis of ensuring that the source / drain metal layer is reliably overlapped with the pixel electrode, it can be ensured that the aperture ratio of the display substrate is large, and thus the transmittance of the display substrate can be ensured to be good.

[0107] Optional, reference Figure 7 As shown in another method flow chart, before forming the interlayer film layer on the side of the pixel electrode away from the substrate, the method may further include:

[0108] Step 606: forming a gate metal layer on the side of the pixel electrode away from the substrate.

[0109] Among them, combined Figure 3 and Figure 5 It can be seen that the orthographic projection of the formed gate metal layer 07 on the substrate 01 may not overlap with the orthographic projection of the pixel electrode 02 on the substrate 01. Optionally, as in step 602 above, a mask may be used to form the gate metal layer through a patterning process.

[0110] On this basis, reference Figure 7 The above-mentioned step 603, i.e. forming an interlayer film layer on a side of the pixel electrode away from the substrate, may include: forming an interlayer film layer on a side of the gate metal layer away from the substrate.

[0111] Optional, combined with the above Figure 2 and Figure 3 It can be seen that, as an optional implementation manner, the interlayer film layer 03 may include: a gate insulating layer GI located on the side of the pixel electrode 02 away from the substrate 01 .

[0112] On this basis, forming an interlayer film layer on the side of the pixel electrode away from the substrate (i.e., the above step 603) may include:

[0113] A gate insulating film is formed on a side of the pixel electrode away from the substrate.

[0114] A mask plate is used to perform patterning on the gate insulating film to form a gate insulating layer and a via hole penetrating the gate insulating layer.

[0115] Among them, combined Figure 2 and Figure 3It can be seen that the formed gate insulating layer GI has a via hole K1 that can expose the pixel electrode 02 , so that the source / drain metal layer 04 can be directly connected to the pixel electrode 02 through the via hole K1 .

[0116] In this implementation, after forming the gate insulating layer and the via hole penetrating the gate insulating layer, the display substrate manufacturing method of the embodiment of the present disclosure may further include: forming an active layer on a side of the gate insulating layer away from the substrate.

[0117] Among them, combined Figure 3 The orthographic projection of the formed active layer Ac1 on the substrate 01 may not overlap with the orthographic projection of the pixel electrode 02 on the substrate 01. Optionally, as in step 602 above, a mask may be used to form the active layer Ac1 through a patterning process.

[0118] For example, taking the above-mentioned manufacturing method of one implementation as an example, Figure 8 A production process flow chart is shown. Figure 8 It can be seen that the entire process can be summarized as follows:

[0119] (1) First, a pixel electrode film can be formed on one side of the substrate, and then a mask plate is used to pattern the pixel electrode film to form a pixel electrode on one side of the substrate. Figure 8 The display substrate marked with “1#” is formed with the pixel electrode 02 .

[0120] (2) Then, a stacked gate metal film, a gate insulating film, and an active film can be formed in sequence on the side of the pixel electrode away from the substrate. Furthermore, three masks are used to perform patterning processes on the gate metal film, the gate insulating film, and the active film, respectively, to form a stacked gate metal layer, a gate insulating layer, and an active layer on the side of the pixel electrode away from the substrate. Figure 8 The display substrate marked with "2#" is formed with a gate insulating layer GI. Figure 8 Only part of the film layer in the display area is shown. Figure 8 The gate metal layer 07 and the active layer Ac1 are not shown. Furthermore, during the formation of the gate insulating layer GI, the portion below the source / drain metal layer 04 is etched to ensure that the gate insulating film between the source / drain metal layer 04 and the pixel electrode 02 is reliably removed, leaving a lap joint for the source / drain metal layer 04 and the pixel electrode 02 to reliably lap.

[0121] (3) Then, a source-drain metal film is formed on the side of the active layer away from the substrate, and a mask plate (referred to as the "first mask plate" in the embodiment of the present disclosure) is further used to perform a patterning process on the source-drain metal film to form a source-drain metal layer. Figure 8The display substrate marked with "3#" is formed with the source-drain metal layer 04, and the reference Figure 8 It can be seen that the formed source-drain metal layer 04 can be reliably connected to the pixel electrode 02 through the via hole K1 penetrating the gate insulating layer GI.

[0122] (4) Finally, a passivation film and a common electrode film can be formed on the side of the source / drain metal layer away from the substrate. Furthermore, two masks are used to perform patterning processes on the passivation film and the common electrode film in sequence, so as to form a passivation layer and a common electrode stacked in sequence on the side of the source / drain metal layer away from the substrate. Figure 8 The display substrate marked with “4#” is formed with a passivation layer 05 . Figure 8 The display substrate marked with “5#” is formed with the common electrode 06 .

[0123] In combination with the above embodiments, it can be seen that based on this implementation, seven masks can be used to complete the production of the display substrate, that is, the display substrate can be produced using a 7-mask process to complete the overlap of the source / drain metal layer 04 and the pixel electrode 02 .

[0124] Optional, combined with the above Figure 4 and Figure 5 It can be seen that, as another optional implementation, the interlayer film layer 03 may include: a gate insulating layer GI and an active layer Ac1 located on the side of the pixel electrode 02 away from the substrate 01 and stacked in sequence in a direction away from the substrate 01 .

[0125] On this basis, forming an interlayer film layer on the side of the pixel electrode away from the substrate (i.e., the above step 603) may include:

[0126] A gate insulating film and an active film are formed on a side of the pixel electrode away from the substrate and are sequentially stacked in a direction away from the substrate.

[0127] The active film and the gate insulating film are patterned in sequence using a second mask plate to form an active layer pattern, a gate insulating layer and a via hole penetrating the active layer pattern and the gate insulating layer.

[0128] The active layer pattern is patterned using a first mask to form an active layer.

[0129] As described in the above embodiment, the first mask is the mask used when forming the source and drain metal layers. Figure 4 and Figure 5It can be seen that in the formed active layer Ac1, the orthographic projection of the first part Ac1-1 having the via K1 on the substrate 01 can be located within the orthographic projection of the pixel electrode 02 on the substrate 01, and the orthographic projection of the second part Ac1-2 other than the first part Ac1-1 on the substrate 01 may not overlap with the orthographic projection of the pixel electrode 02 on the substrate 01.

[0130] For example, taking the above-mentioned manufacturing method of another implementation as an example, Figure 9 Another production process flow chart is shown. Figure 9 It can be seen that the entire process can be summarized as follows:

[0131] (1) First, a pixel electrode film can be formed on one side of the substrate, and then a mask plate is used to pattern the pixel electrode film to form a pixel electrode on one side of the substrate. Figure 9 The display substrate marked with “1#” is formed with the pixel electrode 02 .

[0132] (2) Then, a stacked gate metal film can be formed in sequence on the side of the pixel electrode away from the substrate, and a mask plate is further used to pattern the gate metal film to form a gate metal layer ( Figure 9 not shown).

[0133] (3) Then, a stacked gate insulating film and an active film can be formed in sequence on the side of the gate metal layer away from the substrate. Furthermore, a second mask is used to sequentially pattern the active film and the gate insulating film to form an active layer pattern, a gate insulating layer, and a via hole penetrating the active layer pattern and the gate insulating layer. Figure 9 The display substrate marked with "2#" in Figure 9 is formed with a gate insulating film GI-m and an active layer pattern Ac1-m, and "2#" also shows a portion of the via K1 penetrating the active layer pattern Ac1-m. The display substrate marked with "3#" in Figure 9 is formed with a gate insulating layer GI and a via K1. That is, a mask plate (referred to as the second mask plate in the embodiment of the present disclosure) can be used to form the active layer pattern, the gate insulating layer and the via hole penetrating the active layer pattern and the gate insulating layer. That is, in the process of forming the gate insulating layer GI and the active layer Ac1, the portion located below the source and drain metal layer 04 will be etched to ensure that the gate insulating film and the active film between the source and drain metal layer 04 and the pixel electrode 02 are reliably removed, and an overlapping position is reserved for reliable overlapping of the source and drain metal layer 04 and the pixel electrode 02.

[0134] Optionally, the etching method during the patterning process can be dry etching using an etching gas. Because the gate insulating film and the active film are made of different materials, the etching gas used in the patterning process for the active film can be different from the etching gas used in the patterning process for the gate insulating film. That is, after the gate insulating film is patterned using a first mask, the etching gas can be changed and the first mask can be used again to pattern the active film, resulting in two etching steps.

[0135] (4) Then, a source-drain metal film is formed on the side of the active layer away from the substrate, and a mask plate (referred to as the "first mask plate" in the embodiment of the present disclosure) is further used to perform a patterning process on the source-drain metal film and the active layer pattern Ac1-m to form the active layer and the source-drain metal layer. Figure 9 The display substrate marked with "4#" is formed with the source-drain metal layer 04 and the active layer Ac1 (herein, the first part Ac1-1), and the reference Figure 9 It can be seen that the formed source-drain metal layer 04 can reliably overlap the pixel electrode 02 through the via K1 penetrating the gate insulating layer GI. That is, in the embodiment of the present disclosure, the active layer and the source-drain metal layer can also be formed by exposure using the same mask.

[0136] (5) Finally, a passivation film and a common electrode film can be formed on the side of the source / drain metal layer away from the substrate. Furthermore, two masks are used to perform patterning processes on the passivation film and the common electrode film in sequence, so as to form a passivation layer and a common electrode stacked in sequence on the side of the source / drain metal layer away from the substrate. Figure 9 The display substrate marked with “5#” is formed with a passivation layer 05 . Figure 9 The display substrate marked with “6#” is formed with a common electrode 06 .

[0137] In combination with the above embodiments, it can be seen that based on this other implementation, six masks can be used to complete the production of the display substrate, that is, the display substrate can be produced using a 6-mask process to complete the overlap of the source / drain metal layer 04 and the pixel electrode 02 .

[0138] Based on the above embodiment, it can be seen that the difference between the above one implementation method and the other implementation method described in the embodiment of the present disclosure is that when the interlayer film layer 03 only includes the gate insulating layer GI, as shown in FIG. Figure 8 As shown, the display substrate can be manufactured using a 7-mask process. When the interlayer film layer 03 includes a gate insulating layer GI and an active layer Ac1, as shown in FIG. Figure 9 As shown in FIG, the display substrate can be manufactured using the 6-mask process. Figure 8However, both the 6-mask and 7-mask processes require additional process steps compared to related technologies, and the resulting display substrate can achieve the pixel electrode 01 being located below the gate insulating layer GI while maximizing the aperture ratio and reducing the risk of the pixel electrode 02 being broken due to slope climbing.

[0139] Optionally, in the embodiments of the present disclosure, in the methods described in the above embodiments, the mask used may be a half-tone mask or a gray-tone mask.

[0140] In summary, the embodiments of the present disclosure provide a method for manufacturing a display substrate. In this method, a pixel electrode, an interlayer film layer, a source / drain metal layer, a passivation layer, and a common electrode stacked in sequence in a direction away from the substrate can be formed on one side of the provided substrate. In addition, the formed interlayer film layer has a via exposing the pixel electrode, and the source / drain metal layer can be directly overlapped with the pixel electrode through the via. Correspondingly, it can be seen that the orthographic projection of the via on the substrate can be located within the orthographic projection of the pixel electrode on the substrate, and can be covered by the source / drain metal layer. In this way, on the basis of ensuring that the source / drain metal layer is reliably overlapped with the pixel electrode, it can be ensured that the aperture ratio of the display substrate is large, and thus the transmittance of the display substrate can be ensured to be good.

[0141] Figure 10 Schematic diagram of a display device provided by an embodiment of the present disclosure. Figure 10 As shown, the display device may include: a power supply component J1, and Figures 1 to 5 Any of the display substrates 00 shown.

[0142] The power supply component J1 may be coupled to (ie, electrically connected to) the display substrate 00 and used to supply power to the display substrate 00 .

[0143] Optionally, the display device may be: a liquid crystal display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator or a transparent display product, or any other product or component with a display function.

[0144] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0145] Furthermore, the terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of the present disclosure should have the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0146] For example, in the embodiments of the present disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0147] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0148] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0149] “Up,” “down,” “left,” or “right” are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0150] "And / or" indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0151] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A display substrate, characterized in that: The display substrate comprises: a substrate comprising a transistor region and a display region; a pixel electrode located on one side of the substrate, wherein the pixel electrode is located in the display area; an interlayer film layer located on a side of the pixel electrode away from the substrate, the interlayer film layer having a via hole exposing the pixel electrode, and an orthographic projection of the via hole on the substrate being within an orthographic projection of the pixel electrode on the substrate; a source / drain metal layer located on a side of the interlayer film layer away from the substrate, wherein the orthographic projection of the source / drain metal layer on the substrate is located within the orthographic projection of the pixel electrode on the substrate and covers the orthographic projection of the via hole on the substrate, and the source / drain metal layer is overlapped with the pixel electrode through the via hole; and, a passivation layer and a common electrode located on a side of the source / drain metal layer away from the substrate and stacked sequentially in a direction away from the substrate; The interlayer film layer includes: a gate insulating layer and an active layer located on a side of the pixel electrode away from the substrate and stacked in sequence in a direction away from the substrate, the active layer having a first portion and a second portion located in the same layer and spaced apart; the first portion and the gate insulating layer have a via hole exposing the pixel electrode; In which, the orthographic projection of the gate insulation layer on the substrate covers the orthographic projection of the pixel electrode on the substrate; in the active layer, the orthographic projection of the first part having the via hole on the substrate is located within the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the second part other than the first part on the substrate does not overlap with the orthographic projection of the pixel electrode on the substrate, the first part is located in the display area, the second part is located in the transistor area, part of the source and drain metal layer is located in the display area, and part is located in the transistor area, and the part of the source and drain metal layer located in the display area overlaps with the pixel electrode, and the part located in the transistor area overlaps with the second part.

2. The display substrate according to claim 1, wherein: The display substrate further includes: a gate metal layer located between the pixel electrode and the interlayer film layer; The orthographic projection of the gate metal layer on the substrate does not overlap with the orthographic projection of the pixel electrode on the substrate.

3. A method for manufacturing a display substrate, characterized in that: For manufacturing the display substrate according to claim 1 or 2, the method comprises: Providing a substrate, wherein the substrate includes a transistor area and a display area; forming a pixel electrode on one side of the substrate, wherein the pixel electrode is located in the display area; forming an interlayer film layer on a side of the pixel electrode away from the substrate, wherein the interlayer film layer has a via hole exposing the pixel electrode, and an orthographic projection of the via hole on the substrate is located within an orthographic projection of the pixel electrode on the substrate; forming a source-drain metal layer on a side of the interlayer film away from the substrate, wherein the orthographic projection of the source-drain metal layer on the substrate is located within the orthographic projection of the pixel electrode on the substrate and covers the orthographic projection of the via hole on the substrate, and the source-drain metal layer is overlapped with the pixel electrode through the via hole; forming a passivation layer and a common electrode stacked in sequence in a direction away from the substrate on a side of the source / drain metal layer away from the substrate; The interlayer film layer includes: a gate insulating thin layer and an active layer located on the side of the pixel electrode away from the substrate; the active layer has a first portion and a second portion located in the same layer and arranged at intervals; the first portion and the gate insulating layer have a via hole exposing the pixel electrode; The orthographic projection of the gate insulating layer on the substrate covers the orthographic projection of the pixel electrode on the substrate; in the active layer, the orthographic projection of the first part having the via hole on the substrate is located within the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the second part other than the first part on the substrate does not overlap with the orthographic projection of the pixel electrode on the substrate, the first part is located in the display area, the second part is located in the transistor area, part of the source and drain metal layer is located in the display area, and part is located in the transistor area, and the part of the source and drain metal layer located in the display area overlaps with the pixel electrode, and the part located in the transistor area overlaps with the second part.

4. The method according to claim 3, characterized in that Forming the interlayer film layer includes: forming a stacked gate insulating film and an active film; The active film and the gate insulating film are patterned in sequence using a second mask to form an active layer pattern, a gate insulating layer and a via hole penetrating the active layer pattern and the gate insulating layer.

5. The method according to claim 3 or 4, characterized in that Before forming an interlayer film layer on a side of the pixel electrode away from the substrate, the method further includes: forming a gate metal layer on a side of the pixel electrode away from the substrate, wherein an orthographic projection of the gate metal layer on the substrate does not overlap with an orthographic projection of the pixel electrode on the substrate; The step of forming an interlayer film layer on a side of the pixel electrode away from the substrate comprises: An interlayer film layer is formed on a side of the gate metal layer away from the substrate.

6. A display device, characterized in that: The display device comprises: a power supply component, and a display substrate according to claim 1 or 2; The power supply component is coupled to the display substrate and is used to supply power to the display substrate.

Images