A passivated contact structure based on silicon nanocrystal heterojunction and a preparation method thereof
By introducing a silicon nanocrystalline thin film carrier collection layer into the tunneling oxide passivated contact structure, and using the interface oxide layer and dielectric layer to restrict the crystallization of amorphous silicon, the problem of increasing the upper limit of open circuit voltage was solved, and higher open circuit voltage and sintering stability were achieved.
Patent Information
- Application Number
- CN202210773208.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-07-01
- Publication Date
- 2026-01-20
- Estimated Expiration
- 2042-07-01
AI Technical Summary
In existing tunneling oxide passivated contact structures, it is difficult to further increase the upper limit of the open-circuit voltage, mainly because the band gap of heavily doped polycrystalline silicon is the same as that of the silicon substrate, resulting in limited carrier collection effect.
By employing a carrier collection layer based on silicon nanocrystalline thin films, the crystallization of amorphous silicon is restricted by an interface oxide layer and a dielectric layer to form a wide-bandgap silicon nanocrystalline thin film, thereby increasing the quasi-Fermi level difference between the carrier collection layer and the silicon substrate and raising the upper limit of the open-circuit voltage.
By widening the band gap of silicon nanocrystalline thin films through the quantum confinement effect, the carrier collection effect is improved, resulting in higher open-circuit voltage and sintering stability, making them suitable for industrial production.
Smart Images
Figure CN115274890B_ABST