A method for preparing a hybrid integrated single-photon LED device

Abstract

The present invention relates to a method for preparing a hybrid integrated single-photon LED device, comprising the steps of: S1 sequentially growing a buffer layer, a sacrificial layer and a P-I-N structure on a first substrate to obtain a first film; S2 depositing a first metal pattern, and corroding or etching to obtain a second film; S3 wet-etching or dry-etching the sacrificial layer to obtain a third film; S4 picking up the third film and turning it 180°; S5 depositing a second metal pattern on a second substrate; S6 aligning and contacting the first metal pattern with the second metal pattern, performing gold-gold bonding to obtain a fourth film; S7 depositing the third metal pattern to obtain a hybrid integrated single-photon LED device. The method for preparing a hybrid integrated single-photon LED device of the present invention solves the problem of insufficient adhesion between the transferred film and the substrate by using a gold-gold bonding method, and the subsequent electrode process does not require the growth of an insulating layer, which effectively simplifies the process flow.

Description

Technical Field

[0001] The invention relates to the technical field of LED device preparation, and more specifically to a method for preparing a hybrid integrated single-photon LED device. Background Art

[0002] The single-photon source is an important quantum light source, which has important application value for the development of quantum information technology. At present, semiconductor materials that can produce single photons mainly include semiconductor quantum dots, diamond color centers, etc. Due to the differences in optical properties, device process difficulty, etc. between different semiconductor material platforms, hybrid integration of different semiconductor materials can effectively and fully integrate the advantages of different materials. Therefore, integrating materials that can generate single photons with other materials can comprehensively play the advantages of different material platforms, thereby improving the scalable application capabilities of single-photon sources. The realization of an electroluminescent single-photon source is conducive to the realization of a fully electrically controlled quantum light source, which is of great value for improving the integration of optical quantum devices. Therefore, the realization of hybrid integrated single-photon LED devices has important application value.

[0003] At present, there are three main hybrid integration schemes. The following is an example of manufacturing a single-photon LED device that is hybrid-integrated with silicon-based and III-V materials. The first hybrid integration scheme is a wafer bonding method. First, a PIN structure is grown on a III-V substrate using molecular beam epitaxy. Then, plasma is used to activate the surface of the Si substrate and the III-V material to enhance its hydrophilicity. After reacting with water molecules, a bond is formed on its surface, which allows the two materials to bond and form hydrogen bonds. After high-temperature annealing, a stable covalent bond is formed. After the two materials are bonded, the III-V substrate can be removed by ion implantation, grinding, thinning and polishing, or chemical etching, leaving a flat III-V material film on Si. Finally, the manufacture of a single-photon LED device integrated with silicon-based III-V materials is completed by semiconductor processes such as chemical etching, photolithography, and evaporation coating. In this scheme, the steps are relatively cumbersome, and the bonding interface is the entire interface, and small-scale alignment bonding cannot be achieved. This solution is also unable to locate and transfer single-photon thin film materials to substrates with photonic or electronic structures, and is even less conducive to the integration of more than two materials. The second hybrid integration solution is to use transfer printing technology to pick up the III-V group material film using a viscous flexible material such as PDMS (polydimethylsiloxane) on a high-precision displacement stage, and then transfer it to the Si substrate. This method can achieve accurate positioning and transfer of thin film materials, but there are currently no reports on hybrid integrated single-photon LED devices based on this transfer method. The third hybrid integration solution is the pick-and-place method, that is, using a nanomanipulator (such as a probe, etc.) under an optical microscope (or electron microscope, etc.) to pick up the III-V group material film from the substrate and then transfer it to the Si substrate. This method can also achieve accurate positioning and transfer, but there are currently no reports on hybrid integrated single-photon LED devices based on this transfer method. The difficulty of the latter two hybrid integration methods lies in the electrode process manufacturing plan after the thin film material is transferred to other substrates. One reason is that the adhesion between the transferred thin film material and the substrate is not sufficient to keep the thin film material from falling off in the subsequent electrode process; another reason is that before the electrode process, a thicker insulating layer needs to be grown to pre-treat the insulation of the positive and negative electrodes, which greatly increases the process difficulty. Summary of the invention

[0004] The purpose of the present invention is to provide a method for preparing a hybrid integrated single-photon LED device, which solves the problem of insufficient adhesion between the transferred film and the substrate by using a gold-gold bonding method, and the subsequent electrode process does not require the growth of an insulating layer, effectively simplifying the process flow and improving the device yield.

[0005] The present invention provides a method for preparing a hybrid integrated single-photon LED device, comprising the following steps:

[0006] S1: growing a buffer layer, a sacrificial layer and a PIN structure on a first substrate in sequence to obtain a first thin film;

[0007] S2: depositing a preset first metal pattern on the first film, and corroding or etching the first film to obtain a second film having a step-type PIN structure;

[0008] S3: performing thorough lateral selective wet etching or dry etching on the sacrificial layer to obtain a third film, wherein the third film includes a step-type PIN structure and the first metal pattern covering the upper surface thereof;

[0009] S4: Pick up the third film by using a sticky flexible material and turn it over 180°;

[0010] S5: depositing a preset second metal pattern on the second substrate;

[0011] S6: aligning and contacting the first metal pattern and the second metal pattern of the third film, heating and applying pressure to perform gold-gold bonding to obtain a fourth film;

[0012] S7: depositing a preset third metal pattern on the fourth film to obtain a hybrid integrated single-photon LED device.

[0013] Furthermore, the material of the first substrate is a III-V group material, a II-VI group material, a IV group material, glass or a flexible material.

[0014] Furthermore, a single-photon material is arranged in the I-type region of the PIN structure.

[0015] Furthermore, the single-photon material is a semiconductor quantum dot or a color center.

[0016] Furthermore, step S2 further comprises:

[0017] S21: cleaning the first film, spin-coating photoresist, photolithography, developing, metallizing, and photoresist stripping, and depositing a preset first metal pattern on the surface of the first film;

[0018] S22: using the first metal pattern as a mask, performing a first etching or corroding on the first film, etching or corroding the I-type region and the P-type doped region of the PIN structure, and leaving the N-type doped region;

[0019] S23: performing cleaning, spin coating of photoresist, photolithography, and development again to obtain a photoresist pattern covering the first metal pattern and having a larger area;

[0020] S24: using the photoresist pattern as a mask, corroding or etching the first film for a second time, corroding or etching away the N-type doped region, stopping at the sacrificial layer, and then washing away the photoresist pattern to obtain a second film with a step-type PIN structure.

[0021] Furthermore, the flexible material with adhesiveness is PDMS.

[0022] Further, step S4 includes:

[0023] A first piece of PDMS is brought into contact with the first metal pattern of the third film, the third film is picked up and flipped 180°, and then a second piece of PDMS is brought into contact with the step-type PIN structure of the flipped third film, and the third film is picked up again, so that the first metal pattern of the third film is separated from the first piece of PDMS.

[0024] Furthermore, the material of the second substrate is a Group III-V material, a Group II-VI material, a Group IV material, glass or a flexible material.

[0025] Further, the metal in the first metal pattern, the second metal pattern and the third metal pattern is one or more of chromium, aluminum, copper, titanium or gold.

[0026] Furthermore, the material of the PIN structure is GaAs, and the material of the sacrificial layer is AlAs.

[0027] The preparation method of the hybrid integrated single-photon LED device of the present invention etches a step-type PIN structure that can effectively prevent a short circuit between a P-type doped region and an N-type doped region, so that in the subsequent electrode manufacturing process, there is no need to grow an insulating layer to insulate the P-type and N-type motors of the PIN structure, thereby effectively simplifying the process flow; the transfer printing technology is combined with the low-temperature, low-pressure gold-gold bonding technology, which effectively increases the adhesion between the transferred fourth film and the second substrate, so that in the subsequent electrode manufacturing process, the film temperature is maintained without falling off the second substrate, effectively improving the success rate of the process flow of the hybrid integrated single-photon LED device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a flow chart of a method for preparing a hybrid integrated single-photon LED device according to an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of a process for preparing a silicon-based InAs quantum dot hybrid integrated single-photon LED device according to an embodiment of the present invention;

[0030] Figure 3A current-voltage curve diagram of a silicon-based InAs quantum dot hybrid integrated single-photon LED device according to an embodiment of the present invention;

[0031] Figure 4 A quantum dot luminescence spectrum diagram of a silicon-based InAs quantum dot hybrid integrated single-photon LED device according to an embodiment of the present invention;

[0032] Figure 5 This is a measurement curve diagram of the second-order correlation function of a silicon-based InAs quantum dot hybrid integrated single-photon LED device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The preferred embodiments of the present invention are given below in conjunction with the accompanying drawings and described in detail.

[0034] like Figure 1 As shown, the present invention provides a method for preparing a hybrid integrated single-photon LED device, comprising the following steps:

[0035] S1: growing a buffer layer, a sacrificial layer and a PIN structure on a first substrate in sequence to obtain a first thin film;

[0036] In this step, a buffer layer, a sacrificial layer and a PIN structure may be grown on the first substrate by using a molecular beam epitaxy technique or an organic metal chemical vapor deposition method.

[0037] The first substrate can be any material that can be used to process electrodes, including but not limited to various III-V materials, II-VI materials, IV materials, glass, flexible materials, etc. The buffer layer material is the same as the first substrate. The sacrificial layer material is selected according to the material of the PIN structure, and it needs to be selectively etched with the material of the PIN structure.

[0038] The PIN structure includes an N-type doped region, an I-type region, and a P-type doped region stacked in sequence from bottom to top. The single-photon material is set in the I-type region, and the P-type doped region and the N-type doped region are electrode contact regions. The P-type doped region and the N-type doped region are used to apply electrical injection, so that the single-photon material in the I-type region can achieve electroluminescence. The PIN structure is a conventional structure in the art, and its principle and formation method are not repeated here.

[0039] S2: depositing a preset first metal pattern on the first film, and corroding or etching the first film to obtain a second film having a step-type PIN structure;

[0040] Step S2 specifically includes:

[0041] S21: cleaning the first film, spin-coating photoresist, photolithography (or electron beam exposure), developing, metal plating, photoresist stripping and other process steps are performed on the first film to deposit a preset first metal pattern on the surface of the first film;

[0042] S22: using the first metal pattern as a mask for wet etching (or dry etching), using a corrosive chemical to perform a first etching (or etching) on ​​the first film, etching away the I-type region and the P-type doped region, and leaving the N-type doped region;

[0043] S23: performing cleaning, spin coating of photoresist, photolithography (or electron beam exposure), development and other process steps again to obtain a photoresist pattern covering the first metal pattern and having a larger area;

[0044] S24: Using the photoresist pattern as a mask, use corrosive chemicals to perform a second etching on the first film, corrode the N-type doped area, stop etching at the sacrificial layer, and then wash away the photoresist pattern to obtain a second film with a step-type PIN structure.

[0045] The step-type PIN structure refers to a PIN structure in which the I-type region and the P-type doping region have the same size, and the N-type doping region has a size larger than the I-type region and the P-type doping region.

[0046] S3: using corrosive chemicals to perform thorough lateral selective wet etching or dry etching on the sacrificial layer to obtain a third film that can be used for transfer printing, including a step-type PIN structure and a first metal pattern covering the upper surface thereof;

[0047] After the sacrificial layer is etched away, there is no adhesion between the third film and the first substrate and the buffer layer, and the third film can be bonded together by a sticky flexible material such as PDMS, so as to be used for transfer printing.

[0048] S4: Pick up the third film by using the sticky flexible material and flip it 180 degrees, so that the step-type PIN structure serves as a contact surface with the flexible material;

[0049] Specifically, the sticky flexible material can be PDMS. On a high-precision transfer platform, the stickiness of the first piece of PDMS is used to pick up the third film from above and flip it 180°. At this time, the first metal pattern is in contact with the PDMS. Then a second piece of PDMS with greater stickiness is used to contact the step-type PIN structure of the flipped third film from above and pick up the third film. Since the second piece of PDMS has greater stickiness, the first metal pattern will be separated from the first piece of PDMS. In this way, the first metal pattern can serve as a gold-gold bonding interface.

[0050] S5: depositing a preset second metal pattern on the second substrate;

[0051] The second substrate can be any material that can be processed into electrodes, including but not limited to various III-V materials, II-VI materials, IV materials, glass, flexible materials, etc. It is subjected to cleaning, spin coating of photoresist, photolithography (or electron beam exposure), development, metal plating, photoresist stripping and other process flows, leaving a preset second metal pattern on its surface, which serves as the contact electrode and gold-gold bonding electrode of the P-type electrode of the step-type PIN structure of the third film.

[0052] S6: aligning and contacting the first metal pattern of the third film with the second metal pattern, heating and applying pressure to perform gold-gold bonding to obtain a fourth film;

[0053] Specifically, on a high-precision transfer platform, by moving the second PDMS, the first metal pattern of the third film on it is aligned with and in contact with the second metal pattern, and then heating and applying pressure to allow the two to undergo low-temperature, low-pressure gold-gold bonding (which can be bonding between the same type of metal or different types of metals); the temperature, pressure and bonding time need to be set according to different materials, and the setting method is a conventional technology in the field and will not be repeated here. After the bonding is completed, stop heating, slowly lift the second PDMS, and the third film can be separated from it and transferred to the second substrate to obtain the fourth film.

[0054] S7: depositing a preset third metal pattern on the fourth film to obtain a hybrid integrated single-photon LED device.

[0055] Specifically, the fourth film is subjected to a process of cleaning, spin coating of photoresist, photolithography (or electron beam exposure), development, metal plating, photoresist stripping, etc., leaving a preset third metal pattern on the surface of the fourth film, which serves as the N-type electrode of the PIN structure to obtain a hybrid integrated single-photon LED device.

[0056] The plated metal used in the present invention can be a metal material with good electrical conductivity such as chromium, aluminum, copper, titanium, gold, etc. The single-photon material used can be any material that can generate single photons by electrical injection, including but not limited to semiconductor quantum dots, color centers, etc. The PIN structure can also be replaced by any structure that can achieve single photon generation by electrical injection. The exposure method of the photoresist used includes but is not limited to methods such as photolithography or electron beam exposure. The photoresist used includes but is not limited to AZ5214, AZ4620, ZEP, etc. The etching method of the thin film used can be a method such as wet etching or dry etching, and the corrosive chemicals used for etching are not limited to the chemical solution described in this embodiment, and can be other chemical solutions or etching gases that can corrode the thin film material.

[0057] The following takes the preparation of a silicon-based InAs quantum dot hybrid integrated single-photon LED device as an example to specifically illustrate the detailed steps of the preparation method of the present invention.

[0058] like Figure 2 As shown, the method for preparing an InAs quantum dot hybrid integrated single-photon LED device comprises the following steps:

[0059] S100a: Using molecular beam epitaxy technology, a GaAs buffer layer 20, an AlAs sacrificial layer 30 and a PIN structure 40 of GaAs semiconductor material are grown on a GaAs substrate 10 (i.e., the first substrate) in sequence to obtain a first film 1; wherein the PIN structure 40 includes an N-type doped GaAs region 41, an I-type region 42 and a P-type doped GaAs region 43 stacked in sequence from bottom to top, the InAs quantum dot material is in the I-type region 42, and the P-type doped GaAs region 43 and the N-type doped GaAs region 41 are electrode contact regions, thereby providing material support for generating single photons using a DC power supply or electric pulse triggering. S100a is step S1 above.

[0060] S100b: After the first film 1 is properly cleaned, AZ5214 photoresist is spin-coated on the surface of the first film 1, and after drying the photoresist, photolithography and development are performed to obtain a preset AZ5214 photoresist pattern on the surface, and then 10nm Ti and 200nm Au metal coating is performed on it by electron beam evaporation method. After the metal coating is completed, acetone (or degumming liquid) is used to strip the photoresist, and the preset first metal pattern 50 can be left on the surface of the first film 1. S100b is the above step S21.

[0061] S100c: Using the first metal pattern 50 as a wet etching mask, the first film 1 is etched for the first time using a corrosive chemical (H2SO4:H2O2:H2O=1:8:200), the I-type region 42 and the P-type doped GaAs region 43 are etched away, leaving the N-type doped GaAs region 41, and obtaining a second film 2 with a stepped PIN structure. S100c is the above step S22.

[0062] S100d: The second film 2 is sequentially subjected to spin coating of AZ5214 photoresist, drying of the photoresist, photolithography and development treatments, so that an AZ5214 photoresist pattern 60 having a larger area and covering the first metal pattern 50 is obtained on its surface; the AZ5214 photoresist pattern 60 is used as a mask for wet etching, and is corroded using a corrosive chemical (H2SO4:H2O2:H2O=1:8:200) to etch away the N-type doped GaAs region 43, and the etching stops at the sacrificial layer 30.

[0063] S100e: Use acetone (or a degumming solution) to wash away the photoresist to obtain a stepped PIN structure for preventing the P-type doped GaAs region from short-circuiting with the N-type doped GaAs region. S100d and S100e are steps S23 and S24 above.

[0064] S100f: The AlGaAs sacrificial layer 30 is thoroughly etched laterally with a corrosive chemical (HF:H20=1:10), thereby obtaining a PIN-type thin film material containing InAs quantum dot single-photon material for transfer printing, i.e., the third thin film 3. At this time, the upper surface of the third thin film 3 is the first metal pattern 50, which can be used as one of the contact electrodes (P-type doped GaAs electrode). S100f is the above step S3.

[0065] S100g: On the high-precision transfer platform, the third film 3 is picked up from above using the first PDMS 71 and flipped 180°, so that the third film 3 remains on the PDMS. At this time, the contact surface between the third film 3 and the first PDMS 71 is the first metal pattern 50 .

[0066] S100h: Use the second PDMS 72 with stronger adhesion to pick up the third film 3 from the first PDMS 71 from above. At this time, the third film 3 will be separated from the first PDMS 71, and the first metal pattern 50 will no longer contact it, while the N-type doped GaAs region 41 of the flipped third film is the contact surface with the second PDMS 72. S100g and S100h are the above step S4.

[0067] S100i: After the silicon substrate 200 (i.e., the second substrate) is properly cleaned, AZ5214 photoresist is spin-coated on its surface. After the photoresist is dried, photolithography and development are performed to obtain a corresponding AZ5214 photoresist pattern on its surface. Then, 10nm Ti and 200nm Au metal coating is performed on the silicon substrate 200 by electron beam evaporation. After the metal coating is completed, acetone (or a degumming solution) is used to strip the photoresist to leave a preset second metal pattern 300 on the silicon substrate 200, which serves as a contact electrode with the P-type doped GaAs electrode (i.e., the first metal pattern 50) of the third film 3. Specifically, on a high-precision transfer platform, the first metal pattern 50 of the third film 3 on the second PDMS 72 is aligned and contacted with the second metal pattern 300 on the silicon substrate 200, heated to 130°C and pressure applied to 100KPa to perform low-temperature, low-pressure gold-gold bonding for 1 hour, then the heating is stopped, and the second PDMS 72 is slowly lifted to separate the third film 3 from the second PDMS 72 and transfer to the silicon substrate 200, thereby obtaining the fourth film 4. S100i is the above steps S5 and S6.

[0068] S100j: After the fourth film 4 is properly cleaned, AZ5214 photoresist is spin-coated on the surface, and after drying the photoresist, photolithography and development are performed to obtain a preset AZ5214 photoresist pattern on the surface; then, the sample is metal-plated with 10nm Ti and 200nm Au by electron beam evaporation method, and after the metal plating is completed, acetone (or degumming liquid) is used to strip the photoresist, leaving a preset third metal pattern 400 on the surface of the fourth film 4, which is used as an N-type doped GaAs electrode of a PIN structure, thereby obtaining a silicon-based InAs quantum dot hybrid integrated single-photon LED device 5. S100j is step S7 above.

[0069] In order to verify whether the silicon-based InAs quantum dot hybrid integrated single-photon LED device of this embodiment can realize electrical injection into the PIN structure, an electrical test of the current-voltage characteristics of the silicon-based InAs quantum dot hybrid integrated single-photon LED device under DC voltage was carried out, wherein a positive voltage was applied to the P-type doped GaAs electrode and a negative voltage was applied to the N-type doped GaAs electrode, referring to Figure 3 , we can see the typical current-voltage curve of the PIN structure, indicating that the InAs quantum dot hybrid integrated single-photon LED device can achieve electrical injection into the PIN structure.

[0070] In order to verify whether the electric injection applied to the PIN structure of the silicon-based InAs quantum dot hybrid integrated single-photon LED device of this embodiment can cause the InAs quantum dot material to electroluminesce, an optical test was performed on the silicon-based InAs quantum dot hybrid integrated single-photon LED device at a temperature of 4K, wherein the applied voltage was 2.5V. Figure 4 , we can see the electroluminescence peaks of excitons (X) and biexcitons (XX) in InAs quantum dots at 4K, indicating that electroluminescence can be achieved.

[0071] In order to verify the single-photon nature of the electroluminescent exciton (X) in the InAs quantum dots of the silicon-based InAs quantum dot hybrid integrated single-photon LED device of this embodiment, the second-order correlation function of the luminescence of the exciton (X) was measured. Figure 5 The second-order correlation function of the measured fitting curve shows that the g of the exciton (X) 2 The (0) value is 0.06±0.005, indicating that the silicon-based InAs quantum dot hybrid integrated single-photon LED device can generate high-quality single photons.

[0072] In summary, the hybrid integrated single-photon LED device prepared by the method of the present invention can generate high-quality single photons.

[0073] The preparation method of the hybrid integrated single-photon LED device provided in the embodiment of the present invention, by etching out a step-type PIN structure that can effectively prevent a short circuit between a P-type doped region and an N-type doped region, does not need to grow an insulating layer to insulate the P-type and N-type motors of the PIN structure in the subsequent electrode manufacturing process, thereby effectively simplifying the process flow; combines transfer printing technology with low-temperature, low-pressure gold-gold bonding technology, effectively increases the adhesion between the transferred fourth film and the second substrate, ensures that the film material does not fall off the second substrate in the subsequent electrode manufacturing process, and effectively improves the success rate of the process flow of the hybrid integrated single-photon LED device.

[0074] The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The above embodiment of the present invention can also be modified in various ways. That is, all simple, equivalent changes and modifications made according to the claims and the description of the present invention fall within the scope of protection of the claims of the present invention. The contents not described in detail in the present invention are all conventional technical contents.

Claims

1. A method for preparing a hybrid integrated single-photon LED device, characterized in that: The following steps are involved: S1: growing a buffer layer, a sacrificial layer and a PIN structure on a first substrate in sequence to obtain a first thin film; S2: depositing a preset first metal pattern on the first film, and corroding or etching the first film to obtain a second film having a step-type PIN structure; S3: performing thorough lateral selective wet etching or dry etching on the sacrificial layer to obtain a third film, wherein the third film includes a step-type PIN structure and the first metal pattern covering the upper surface thereof; S4: Pick up the third film by using a sticky flexible material and turn it over 180°; S5: depositing a preset second metal pattern on the second substrate; S6: aligning and contacting the first metal pattern and the second metal pattern of the third film, heating and applying pressure to perform gold-gold bonding to obtain a fourth film; S7: depositing a preset third metal pattern on the fourth film to obtain a hybrid integrated single-photon LED device; Step S2 further comprises: S21: cleaning the first film, spin-coating photoresist, photolithography, developing, metallizing, and photoresist stripping, and depositing a preset first metal pattern on the surface of the first film; S22: using the first metal pattern as a mask, performing a first etching or corroding on the first film, etching or corroding the I-type region and the P-type doped region of the PIN structure, and leaving the N-type doped region; S23: performing cleaning, spin coating of photoresist, photolithography, and development again to obtain a photoresist pattern covering the first metal pattern and having a larger area; S24: using the photoresist pattern as a mask, corroding or etching the first film for a second time, corroding or etching away the N-type doped region, stopping at the sacrificial layer, and then washing away the photoresist pattern to obtain a second film with a step-type PIN structure.

2. The method for preparing a hybrid integrated single-photon LED device according to claim 1, characterized in that: The material of the first substrate is a III-V group material, a II-VI group material, a IV group material, glass or a flexible material.

3. The method for preparing a hybrid integrated single-photon LED device according to claim 1, characterized in that: A single-photon material is arranged in the I-type region of the PIN structure.

4. The method for preparing a hybrid integrated single-photon LED device according to claim 3, characterized in that: The single-photon material is a semiconductor quantum dot or a color center.

5. The method for preparing a hybrid integrated single-photon LED device according to claim 1, characterized in that: The flexible material with adhesiveness is PDMS.

6. The method for preparing a hybrid integrated single-photon LED device according to claim 5, characterized in that: Step S4 includes: A first piece of PDMS is brought into contact with the first metal pattern of the third film, the third film is picked up and flipped 180°, and then a second piece of PDMS is brought into contact with the step-type PIN structure of the flipped third film, and the third film is picked up again, so that the first metal pattern of the third film is separated from the first piece of PDMS.

7. The method for preparing a hybrid integrated single-photon LED device according to claim 1, characterized in that: The material of the second substrate is a III-V group material, a II-VI group material, a IV group material, glass or a flexible material.

8. The method for preparing a hybrid integrated single-photon LED device according to claim 1, characterized in that: The metal in the first metal pattern, the second metal pattern and the third metal pattern is one or more of chromium, aluminum, copper, titanium or gold.

9. The method for preparing a hybrid integrated single-photon LED device according to claim 1, characterized in that: The material of the PIN structure is GaAs, and the material of the sacrificial layer is AlAs.

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