Light-emitting diode chip with improved heat dissipation and preparation method thereof

Abstract

The present disclosure provides a light-emitting diode chip with improved heat dissipation and a method for manufacturing the same, belonging to the field of optoelectronic manufacturing technology. The light-emitting diode chip comprises: a substrate, a light-emitting structure, a first electrode, and a second electrode; the light-emitting structure comprises a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer sequentially stacked on the substrate; the surface of the second semiconductor layer has a groove exposing the first semiconductor layer; the first electrode is located within the groove; and the second electrode comprises a plurality of sub-electrodes arranged at intervals, wherein the plurality of sub-electrodes are located on the side of the second semiconductor layer away from the substrate. The embodiments of the present disclosure can enhance the heat dissipation capability of the chip and alleviate the problem of electrical overstress in the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode chip with improved heat dissipation and a preparation method thereof. Background Art

[0002] Micro LEDs (Micro Light Emitting Diodes) refer to ultra-small light-emitting diodes with side lengths ranging from 10μm to 100μm. Due to their small size, micro LEDs can be arranged more densely, significantly improving resolution. They also have self-luminous properties, and have the characteristics of high brightness, high contrast, high responsiveness, and energy saving.

[0003] In related technologies, a light-emitting diode chip generally includes a substrate, a light-emitting structure, and two electrodes. The light-emitting structure includes an n-type layer, a multi-quantum well layer, and a p-type layer stacked in sequence on the substrate. One electrode is located on the p-type layer and electrically connected to the p-type layer. A groove is also provided on the p-type layer to expose the n-type layer. The other electrode is located in the groove and electrically connected to the n-type layer.

[0004] Because the current density at the location of the two electrodes in the chip is high and the heat generated is high, and the electrodes are set in the central area of ​​the light-emitting structure, and the heat dissipation in the central area is poor, this will cause the chip's electrical overstress (EOS) to decrease, making the chip more susceptible to damage under high current. Summary of the Invention

[0005] The present disclosure provides a light-emitting diode chip with improved heat dissipation and a method for manufacturing the same, which can enhance the chip's heat dissipation capability and alleviate the chip's electrical overstress degradation problem. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode chip with improved heat dissipation, wherein the light-emitting diode chip includes: a substrate, a light-emitting structure, a first electrode, and a second electrode; the light-emitting structure includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence on the substrate, the surface of the second semiconductor layer has a groove exposing the first semiconductor layer, the first electrode is located in the groove, and the second electrode includes a plurality of sub-electrodes arranged at intervals, and the plurality of sub-electrodes are located on the side of the second semiconductor layer away from the substrate.

[0007] Optionally, the light-emitting diode chip also includes a passivation layer, which is located at least on the second semiconductor layer, the first electrode, the groove and the second electrode. The passivation layer has a through hole and a plurality of concave holes, the through hole exposes the first electrode, and the plurality of concave holes correspond one-to-one to the plurality of sub-electrodes; the distance from the bottom surface of the concave hole to the sub-electrode is negatively correlated with the distance from the concave hole to the first electrode.

[0008] Optionally, the second electrode includes a first electrode group, a second electrode group and a third electrode group arranged in sequence along a direction away from the first electrode; the shortest distance between each sub-electrode in the first electrode group and the first electrode is the same, the shortest distance between each sub-electrode in the second electrode group and the first electrode is the same, and the shortest distance between each sub-electrode in the third electrode group and the first electrode is the same.

[0009] Optionally, in the first electrode group, the distance from the bottom surface of the concave hole corresponding to the sub-electrode to the sub-electrode is 20 angstroms to 30 angstroms, in the second electrode group, the distance from the bottom surface of the concave hole corresponding to the sub-electrode to the sub-electrode is 10 angstroms to 15 angstroms, and in the third electrode group, the distance from the bottom surface of the concave hole corresponding to the sub-electrode to the sub-electrode is 3 angstroms to 6 angstroms.

[0010] Optionally, the distance from the bottom surface of the concave hole to the sub-electrode gradually decreases in a direction away from the first electrode.

[0011] Optionally, the sub-electrode is in a fan-shaped ring or a strip shape.

[0012] On the other hand, an embodiment of the present disclosure also provides a method for preparing a light-emitting diode chip with improved luminous efficiency, the preparation method comprising: providing an epitaxial wafer, the epitaxial wafer comprising a substrate and a light-emitting structure located on the substrate, the light-emitting structure comprising a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence on the substrate, the surface of the second semiconductor layer having a groove exposing the first semiconductor layer; making a first electrode and a second electrode on the epitaxial wafer, the first electrode being located in the groove, the second electrode comprising a plurality of sub-electrodes arranged at intervals, the plurality of sub-electrodes being located on a side of the second semiconductor layer away from the substrate.

[0013] Optionally, after the first electrode and the second electrode are produced on the epitaxial wafer, the preparation method further includes: forming a passivation layer on the epitaxial wafer, the passivation layer being located at least on the second semiconductor layer, the first electrode, the groove and the second electrode; etching on the passivation layer to form a through hole exposing the first electrode, and a plurality of recessed holes corresponding one-to-one to a plurality of sub-electrodes.

[0014] Optionally, the second electrode includes a first electrode group, a second electrode group and a third electrode group arranged in sequence along a direction away from the first electrode; the shortest distance between each sub-electrode in the first electrode group and the first electrode is the same, the shortest distance between each sub-electrode in the second electrode group and the first electrode is the same, and the shortest distance between each sub-electrode in the third electrode group and the first electrode is the same.

[0015] Optionally, fabricating the second electrode on the epitaxial wafer includes: performing laser annealing on a region of the second semiconductor layer where the sub-electrode is to be formed; and forming the sub-electrode in the region where the sub-electrode is to be formed.

[0016] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0017] The light-emitting diode chip provided by the embodiment of the present disclosure includes a light-emitting structure stacked on a substrate, and a first electrode and a second electrode are also provided on the light-emitting structure. The first electrode is located in the groove and connected to the first semiconductor layer, and the second electrode is connected to the second semiconductor layer. In this way, when the first electrode and the second electrode are energized, the light-emitting diode chip can be controlled to be energized and emit light.

[0018] The second electrode on the second semiconductor layer includes multiple sub-electrodes arranged at intervals, each located on the side of the second semiconductor layer away from the substrate. By distributing multiple sub-electrodes across the second electrode layer, compared to a single, blocky electrode, the high current density is dispersed to various areas of the light-emitting structure. This, in turn, disperses heat to different regions of the light-emitting structure, avoiding excessive heat generation in the center of the structure. This reduces electrical overstress on the chip and improves its competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 is a structural schematic diagram of a light-emitting diode chip provided by an embodiment of the present disclosure;

[0021] Figure 2 is a top view of a light-emitting diode chip provided by an embodiment of the present disclosure;

[0022] Figure 3 Schematic diagram of the distribution of a passivation film in a concave hole provided by an embodiment of the present disclosure;

[0023] Figure 4is a top view of another light-emitting diode chip provided by an embodiment of the present disclosure;

[0024] Figure 5 This is a flow chart of a method for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0025] Figure 6 This is a schematic diagram of a process for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0026] Figure 7 This is a schematic diagram of a process for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0027] Figure 8 This is a schematic diagram of a process for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0028] Figure 9 This is a schematic diagram of a process for preparing a light-emitting diode chip provided in an embodiment of the present disclosure.

[0029] The descriptions of the marks in the figure are as follows:

[0030] 10. Substrate; 11. GaAs chip;

[0031] 20. Light-emitting structure; 21. First semiconductor layer; 22. Multi-quantum well layer; 23. Second semiconductor layer; 24. Groove;

[0032] 31. First electrode; 32. Second electrode; 321. Sub-electrode;

[0033] 40. passivation layer; 41. through hole; 42. recessed hole;

[0034] 51. First soldering point block; 52. Second soldering point block;

[0035] 60. Protective layer; 61. Bonding layer;

[0036] 71. Photoresist layer; 72. Opening; 73. Adhesive film;

[0037] 81. First electrode group; 82. Second electrode group; 83. Third electrode group. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0039] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar words used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprise" mean that the elements or objects preceding "include" or "comprises" encompass the elements or objects listed after "include" or "comprises," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0040] Figure 1 FIG. 1 is a schematic diagram of the structure of a light-emitting diode chip provided by an embodiment of the present disclosure. Figure 1 As shown, the light emitting diode chip includes: a substrate 10 , a light emitting structure 20 , a first electrode 31 and a second electrode 32 .

[0041] like Figure 1 As shown, the light emitting structure 20 includes a first semiconductor layer 21 , a multi-quantum well layer 22 and a second semiconductor layer 23 sequentially stacked on a substrate 10 . The surface of the second semiconductor layer 23 has a groove 24 exposing the first semiconductor layer 21 , and the first electrode 31 is located in the groove 24 .

[0042] Figure 2 FIG. 1 is a top view of a light emitting diode chip provided by an embodiment of the present disclosure. Figure 2 As shown, the second electrode 32 includes a plurality of sub-electrodes 321 arranged at intervals, and the plurality of sub-electrodes 321 are located on a side of the second semiconductor layer 23 away from the substrate 10 .

[0043] The light-emitting diode chip provided by the embodiment of the present disclosure includes a light-emitting structure 20 stacked on a substrate 10. A first electrode 31 and a second electrode 32 are also provided on the light-emitting structure 20. The first electrode 31 is located in the groove 24 and is connected to the first semiconductor layer 21. The second electrode 32 is connected to the second semiconductor layer 23. In this way, when the first electrode 31 and the second electrode 32 are energized, the light-emitting diode chip can be controlled to be energized and emit light.

[0044] The second electrode 32 on the second semiconductor layer includes a plurality of sub-electrodes 321 arranged at intervals. The sub-electrodes 321 are located on the side of the second semiconductor layer 23 away from the substrate 10. By distributing the second electrode 32 across multiple sub-electrodes 321, compared to a single, block-shaped electrode, the current density at locations with high density is dispersed to various regions of the light-emitting structure 20. This, in turn, disperses the heat to different areas of the light-emitting structure 20, thereby avoiding excessive heat generation in the central region of the light-emitting structure 20. This reduces electrical overstress on the chip and improves its competitiveness.

[0045] Optionally, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate 10. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.

[0046] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0047] As an example, the first semiconductor layer 21 is a p-type layer, the first electrode 31 is a p-type electrode, the second semiconductor layer 23 is an n-type layer, and the second electrode 32 is an n-type electrode.

[0048] Optionally, the first semiconductor layer 21 is an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.

[0049] Optionally, the multi-quantum well layer 22 includes alternately grown AlGaInP quantum well layers and AlGaInP quantum barrier layers, wherein the Al content in the AlGaInP quantum well layers and the AlGaInP quantum barrier layers is different. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0050] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0051] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0052] Optionally, the second semiconductor layer 23 is an indium-doped p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.

[0053] Alternatively, as Figure 1As shown, the light-emitting diode chip also includes a passivation layer 40, which is located at least on the second semiconductor layer 23, the first electrode 31, the groove 24 and the second electrode 32. The passivation layer 40 has a through hole 41 and multiple recessed holes 42. The through hole 41 exposes the first electrode 31, and the multiple recessed holes 42 correspond one-to-one to the multiple sub-electrodes 321.

[0054] For example, the passivation layer 40 may be a distributed Bragg reflector (DBR layer), which includes a plurality of periodically alternating SiO2 layers and TiO2 layers. The number of periods in the DBR layer may be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0055] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0056] In addition to the passivation function, the DBR layer is also used to reflect the light emitted from the multi-quantum well layer 22 to the DBR layer to the substrate 10, thereby improving the light extraction effect.

[0057] In the embodiment of the present disclosure, Figure 3 Schematic diagram of the distribution of the passivation film in a concave hole provided by an embodiment of the present disclosure. Figure 3 As shown, the distance H from the bottom surface of the recessed hole 42 to the sub-electrode 321 is negatively correlated with the distance from the recessed hole 42 to the first electrode 31 .

[0058] The distance H between the bottom surface of the concave hole 42 and the sub-electrode 321 may be the maximum distance between the bottom surface of the concave hole 42 and the sub-electrode 321 .

[0059] The concave hole may be a hole structure formed when etching the passivation layer but not completely from the top surface of the passivation layer to the sub-electrode, so that part of the passivation layer remains between the bottom surface of the concave hole and the sub-electrode.

[0060] In the embodiment of the present disclosure, the distance between the bottom surface of the recessed hole 42 and the sub-electrode 321 is 3 angstroms to 30 angstroms. Since the distance between the bottom surface of the recessed hole 42 and the sub-electrode 321 is small, the current is not completely blocked.

[0061] Since the closer the recessed hole 42 is to the first electrode 31, the greater the distance between the bottom surface of the recessed hole 42 and the sub-electrode 321, the greater the recessed hole 42's ability to block current. The farther the recessed hole 42 is from the first electrode 31, the smaller the distance between the bottom surface of the recessed hole 42 and the sub-electrode 321, and the smaller the recessed hole 42's ability to block current. The greater the distance between the bottom surface of the recessed hole 42 and the sub-electrode 321, the less likely current is to spread from the recessed hole 42 to the sub-electrode 321, and the lower the current density at the sub-electrode 321, thereby reducing heat generation at the sub-electrode 321. The smaller the distance between the bottom surface of the recessed hole 42 and the sub-electrode 321, the easier it is for current to spread from the recessed hole 42 to the sub-electrode 321, the higher the current density at the sub-electrode 321, and the relatively higher heat generation at the sub-electrode 321. Since the sub-electrode 321 close to the first electrode 31 is closer to the center area of ​​the chip, and the sub-electrode 321 farther away from the first electrode 31 is closer to the edge area of ​​the chip, the heat generated in the middle area of ​​the chip can be reduced and the heat can be transferred to the edge area of ​​the chip, thereby improving the heat dissipation capacity of the chip; moreover, the dispersed sub-electrodes 321 can also balance the current of the chip and allow the current to extend to the entire plane of the second semiconductor layer 23, thereby improving the problem of electrical overstress drop of the chip.

[0062] Alternatively, as Figure 2 As shown, the second electrode 32 includes a first electrode group 81, a second electrode group 82 and a third electrode group 83 arranged in sequence along a direction away from the first electrode 31, the shortest distance between each sub-electrode 321 in the first electrode group 81 and the first electrode is the same, the shortest distance between each sub-electrode 321 in the second electrode group 82 and the first electrode is the same, and the shortest distance between each sub-electrode 321 in the third electrode group 83 and the first electrode is the same.

[0063] In the above implementation, the sub-electrodes 321 are divided into three groups, and the shortest distance from each sub-electrode 321 to the first electrode 31 in each electrode group is the same. This allows the passivation rate of the recessed hole 42 to decrease evenly as it moves away from the first electrode 31. Specifically, the passivation rate decreases as the sub-electrodes 321 are further away from the first electrode 31. This causes the chip's heat generation to gradually increase with increasing distance from the first electrode 31. This reduces heat generation in the central region of the chip and transfers heat to the edge of the chip, thereby improving the chip's heat dissipation capability.

[0064] Illustratively, in the first electrode group 81, the distance between the bottom surface of the recessed hole 42 corresponding to the sub-electrode 321 and the sub-electrode 321 is 20 angstroms to 30 angstroms. For example, in the first electrode group 81, the distance between the bottom surface of the recessed hole 42 corresponding to the sub-electrode 321 and the sub-electrode 321 is 25 angstroms.

[0065] When the distance from the bottom surface of the recessed hole 42 to the sub-electrode 321 is within this range, the recessed hole can block 50% to 60% of the current from extending from the recessed hole 42 to the sub-electrode 321 compared to a fully conductive through hole.

[0066] By setting the distance from the bottom surface of the recessed hole 42 closest to the first electrode 31 to the sub-electrode 321 within the above range, an effective blocking effect can be formed on the current, preventing a large amount of current from extending from the recessed hole 42 to the sub-electrode 321, thereby reducing the current density of the sub-electrode 321 closest to the first electrode 31 and reducing the heat generated in the area of ​​the chip closest to the first electrode 31.

[0067] Illustratively, in the second electrode group 82, the distance between the bottom surface of the recessed hole 42 corresponding to the sub-electrode 321 and the sub-electrode 321 is 10 angstroms to 15 angstroms. For example, in the second electrode group 82, the distance between the bottom surface of the recessed hole 42 corresponding to the sub-electrode 321 and the sub-electrode 321 is 12 angstroms.

[0068] When the distance from the bottom surface of the recessed hole 42 to the sub-electrode 321 is within this range, the recessed hole can block 20% to 30% of the current from extending from the recessed hole 42 to the sub-electrode 321 compared to a fully conductive through hole.

[0069] By setting the distance from the bottom surface of the recessed hole 42 closer to the first electrode 31 to the sub-electrode 321 within the above range, it can not only form a certain blocking effect on the current, but also ensure that an appropriate amount of current can be extended to the sub-electrode 321. It can block part of the current from extending from the recessed hole 42 to the sub-electrode 321, while satisfying the chip's luminous effect, it can also reduce the heat generated in the area of ​​the chip closer to the first electrode 31.

[0070] Illustratively, in the third electrode group 83, the distance between the bottom surface of the recessed hole 42 corresponding to the sub-electrode 321 and the sub-electrode 321 is 3 angstroms to 6 angstroms. For example, in the third electrode group 83, the distance between the bottom surface of the recessed hole 42 corresponding to the sub-electrode 321 and the sub-electrode 321 is 5 angstroms.

[0071] When the distance from the bottom surface of the recessed hole 42 to the sub-electrode 321 is within this range, the recessed hole can block 0 to 10% of the current from extending from the recessed hole 42 to the sub-electrode 321 compared to a fully conductive through hole.

[0072] By setting the distance from the bottom surface of the recessed hole 42 farthest from the first electrode 31 to the sub-electrode 321 within the above range, most of the current can be extended through the recessed hole 42 to the sub-electrode 321, thereby ensuring the luminous effect of the chip. At the same time, the heat generated by the chip is concentrated in the edge area of ​​the chip where heat is easily dissipated, thereby improving the heat dissipation effect of the chip.

[0073] Alternatively, as Figure 3As shown, the distance from the bottom surface of the concave hole 42 to the sub-electrode 321 gradually decreases in the direction away from the first electrode 31 .

[0074] In the above implementation, within a single recessed hole 42, the closer the bottom surface of the recessed hole 42 is to the first electrode 31, the greater the distance from the bottom surface of the recessed hole 42 to the sub-electrode 321. This reduces the current density in the area of ​​the recessed hole 42 near the first electrode 31, thereby reducing heat generation. Meanwhile, the current density in the area of ​​the recessed hole 42 farther from the first electrode 31 increases, thereby increasing heat generation. In other words, the area near the first electrode 31 generates less heat, facilitating heat dissipation.

[0075] For example, in the recess 42 , the maximum difference in the distance from the bottom of the recess 42 to the sub-electrode 321 does not exceed 10% of the maximum distance from the bottom of the recess 42 to the sub-electrode 321 , so as to avoid excessive differences in heat generation between different regions of the sub-electrode 321 .

[0076] Alternatively, as Figure 2 As shown, the sub-electrode 321 is in the shape of a fan ring or a strip.

[0077] In the embodiment of the present disclosure, the shape of the sub-electrode 321 may be related to the shape of the groove 24. For example, when the groove 24 is an arc-shaped groove, the sub-electrode 321 may be in the shape of a sector ring to ensure that the spacing between each sub-electrode 321 and the first electrode 31 is the same. For example, when the groove 24 is a rectangular groove, the sub-electrode 321 may be in the shape of a strip to ensure that the spacing between each sub-electrode 321 and the first electrode 31 is the same.

[0078] Alternatively, as Figure 1 As shown, the light-emitting diode chip also includes: a first solder point block 51 and a second solder point block 52. The first solder point block 51 and the second solder point block 52 are located on the passivation layer 40. The first solder point block 51 is connected to the first electrode 31 through the through hole 41, and the second solder point block 52 is connected to the second electrode 32 through the recessed hole 42.

[0079] Figure 4 FIG. 1 is a top view of another light emitting diode chip provided by an embodiment of the present disclosure. Figure 4 As shown, the first soldering point block 51 and the second soldering point block 52 are both rectangular blocks, which increase the area and facilitate electrical conduction. In addition, the first soldering point block 51 and the second soldering point block 52 are spaced apart on the surface of the passivation layer 40.

[0080] Alternatively, as Figure 1 As shown, a protective layer 60 is further provided on the surface of the passivation layer 40 , and the protective layer 60 extends from the surface of the passivation layer 40 to the substrate 10 , and the protective layer 60 has vias exposing the first solder block 51 and the second solder block 52 for electrical connection.

[0081] For example, in the embodiment of the present disclosure, the protective layer 60 may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.

[0082] Figure 5 This is a flow chart of a method for preparing a light-emitting diode chip provided by an embodiment of the present disclosure. Figure 1 The light emitting diode chip shown. Figure 5 As shown, the preparation method comprises:

[0083] S11 : providing an epitaxial wafer, wherein the epitaxial wafer includes a substrate 10 and a light emitting structure 20 located on the substrate 10 .

[0084] The light emitting structure 20 includes a first semiconductor layer 21 , a multi-quantum well layer 22 and a second semiconductor layer 23 sequentially stacked on the substrate 10 . The surface of the second semiconductor layer 23 has a groove 24 exposing the first semiconductor layer 21 .

[0085] S12: forming a first electrode 31 and a second electrode 32 on the epitaxial wafer.

[0086] The first electrode 31 is located in the groove 24 , and the second electrode 32 includes a plurality of sub-electrodes 321 arranged at intervals. The plurality of sub-electrodes 321 are located on a side of the second semiconductor layer 23 away from the substrate 10 .

[0087] The light-emitting diode chip prepared by this preparation method includes a light-emitting structure 20 stacked on a substrate 10. A first electrode 31 and a second electrode 32 are also provided on the light-emitting structure 20. The first electrode 31 is located in the groove 24 and is connected to the first semiconductor layer 21, and the second electrode 32 is connected to the second semiconductor layer 23. In this way, when the first electrode 31 and the second electrode 32 are energized, the light-emitting diode chip can be controlled to emit light. Among them, the second electrode 32 located on the second semiconductor includes a plurality of sub-electrodes 321 arranged at intervals. The plurality of sub-electrodes 321 are located on the side of the second semiconductor layer 23 away from the substrate 10. In this way, by distributing the second electrode 32 into a plurality of sub-electrodes 321, compared to a single block electrode, the location with high current density is dispersed to various areas of the light-emitting structure 20. In other words, the heat is dispersed to different areas of the light-emitting structure 20 to avoid the problem of excessive heat generation in the middle area of ​​the light-emitting structure 20, thereby reducing the electrical overstress of the chip and improving the chip's competitiveness.

[0088] Figure 6 FIG. 1 is a schematic diagram of a process for preparing a light-emitting diode chip according to an embodiment of the present disclosure. Figure 6 As shown, the epitaxial wafer fabrication in step S11 may include the following steps:

[0089] In the first step, a GaAs wafer 11 is provided.

[0090] In the second step, a light emitting structure 20 is grown on the GaAs wafer 11 . The light emitting structure 20 includes a second semiconductor layer 23 , a multi-quantum well layer 22 and a first semiconductor layer 21 stacked in sequence.

[0091] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0092] For example, the second semiconductor layer 23 may be an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.

[0093] For example, the first semiconductor layer 21 is an indium-doped p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.

[0094] Optionally, the multi-quantum well layer 22 includes alternately grown AlGaInP quantum well layers and AlGaInP quantum barrier layers, wherein the Al content in the AlGaInP quantum well layers and the AlGaInP quantum barrier layers is different. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0095] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0096] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0097] In the second step, an etching stop layer may be grown before growing the second semiconductor layer 23 , and an AlInP carrier confinement layer may be grown before growing the multi-quantum well layer 22 .

[0098] For example, in the embodiment of the present disclosure, the first semiconductor layer 21 may be a p-type layer.

[0099] After growing the first semiconductor layer 21 , a GaP window layer may be further grown, wherein the thickness of the GaP window layer is 10,000 angstroms to 20,000 angstroms.

[0100] Illustratively, the thickness of the GaP window layer is 11,000 angstroms.

[0101] The third step, such as Figure 7 As shown, a bonding layer 61 is formed between the first semiconductor layer 21 and the sapphire substrate 10 , the light emitting structure 20 is bonded to the sapphire substrate 10 , and the GaAs wafer 11 is removed.

[0102] Since the sapphire substrate 10 has a relatively high light transmittance, and the sapphire material is relatively hard and has relatively stable chemical properties, the use of the sapphire substrate 10 can enable the light-emitting diode to have good light-emitting effect and stability.

[0103] Specifically, the process may include coating silicon oxide liquid on the surface of the second semiconductor layer 23, placing the sapphire substrate 10 on the surface of the second semiconductor layer 23, and heating the epitaxial wafer to heat and solidify the silicon oxide liquid to form a bonding layer 61 between the second semiconductor layer 23 and the sapphire substrate 10.

[0104] Optionally, the heating temperature of the epitaxial wafer is 250° C. to 350° C. Exemplarily, the heating temperature may be 300° C.

[0105] like Figure 8 As shown, before step S12 , the preparation method further includes: etching the second semiconductor layer 23 to form a groove 24 exposing the second semiconductor layer 23 .

[0106] Specifically, the method may include: etching the second semiconductor layer 23 by dry etching to expose the first semiconductor layer 21 .

[0107] In step S12 , preparing the first electrode 31 and the second electrode 32 may include: forming the first electrode 31 in the groove 24 , and forming a plurality of sub-electrodes 321 on the second semiconductor layer 23 .

[0108] The forming of the first electrode 31 and each sub-electrode 321 may include: processing the first electrode 31 and the second electrode 32 separately by using a negative resist stripping method.

[0109] Among them, the first electrode 31 uses gold-beryllium as the main component, and each sub-electrode 321 uses gold-germanium as the base material for vapor deposition. When evaporating the gold-germanium alloy, the evaporation power must be guaranteed to avoid the evaporation time exceeding seconds to prevent the deviation of the alloy composition, and annealing is performed.

[0110] Optionally, manufacturing the second electrode 32 on the epitaxial wafer includes: performing laser irradiation on regions of the second semiconductor layer 23 corresponding to the sub-electrodes 321 ; and forming the sub-electrodes 321 in the laser irradiated regions.

[0111] Laser irradiation is performed on the areas corresponding to the sub-electrodes 321 on the second semiconductor layer 23, that is, laser irradiation annealing is performed on these areas, so that the doping activation in these areas is more thorough and the carrier concentration is higher, thereby obtaining a better contact effect and further improving the problem of electrical overstress drop of the chip.

[0112] After step S12, the preparation method may further include the following steps:

[0113] In the first step, a passivation layer 40 is formed on the epitaxial wafer. The passivation layer 40 is at least located on the second semiconductor layer 23 , the first electrode 31 , the groove 24 and the second electrode 32 .

[0114] The passivation layer 40 may be a distributed Bragg reflector layer, which may be a DBR layer. The DBR layer includes a plurality of periodically alternating SiO2 layers and TiO2 layers. The number of periods in the DBR layer may be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0115] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0116] In the second step, a through hole 41 and a plurality of recessed holes corresponding to the plurality of sub-electrodes are formed on the passivation layer 40 .

[0117] After the passivation layer 40 is formed, a through hole 41 is formed by etching on a surface of the passivation layer 40 away from the substrate 10 , and the through hole 41 exposes the first electrode 31 .

[0118] like Figure 9 As shown, forming a concave hole may include the following steps:

[0119] In the first step, a photoresist layer 71 is formed on the surface of the passivation layer 40 . The photoresist layer 71 has a plurality of openings 72 . An adhesive film 73 remains in the openings 72 . The thickness of the adhesive film 73 is negatively correlated with the distance from the opening 72 to the first electrode 31 .

[0120] The smaller the thickness of the adhesive film 73 in the opening 72 , the easier it is for the etching medium to pass through the opening 72 to etch the opening 72 , and the smaller the distance between the bottom surface of the recessed hole 42 and the sub-electrode 321 .

[0121] The thicker the film 73 in the opening 72 is, the harder it is for the etching medium to pass through the opening 72 , resulting in a poorer etching effect on the opening 72 . This increases the distance between the bottom surface of the recessed hole 42 and the sub-electrode 321 .

[0122] In the embodiment of the present disclosure, the photoresist layer 71 can be formed in the following manner:

[0123] First, a photoresist film is formed on the second semiconductor layer 23 , and the photoresist film is photolithographically processed using a mask structure.

[0124] The mask structure corresponding to opening 72 is made of chromium metal. This metal weakens light intensity, resulting in varying degrees of etching of the photoresist film at openings 72 corresponding to the chromium metal. By varying the thickness of the chromium metal, openings 72 with varying thicknesses of the photoresist film 73 can be created on the photoresist film to form photoresist layer 71.

[0125] In the second step, recessed holes 42 corresponding to the openings 72 are formed on the passivation layer 40 through the openings 72 .

[0126] Among them, the second electrode 32 includes a first electrode group 81, a second electrode group 82 and a third electrode group 83 arranged in sequence along a direction away from the first electrode 31, the shortest distance between each sub-electrode 321 in the first electrode group 81 and the first electrode is the same, the shortest distance between each sub-electrode 321 in the second electrode group 82 and the first electrode is the same, and the shortest distance between each sub-electrode 321 in the third electrode group 83 and the first electrode is the same.

[0127] Illustratively, in the first electrode group 81, the distance between the bottom surface of the recessed hole 42 corresponding to the sub-electrode 321 and the sub-electrode 321 is 20 angstroms to 30 angstroms. For example, in the first electrode group 81, the distance between the bottom surface of the recessed hole 42 corresponding to the sub-electrode 321 and the sub-electrode 321 is 25 angstroms.

[0128] When the distance from the bottom surface of the concave hole 42 to the sub-electrode 321 is within this range, 50% to 60% of the current can be blocked from extending from the concave hole 42 to the sub-electrode 321 .

[0129] Illustratively, in the second electrode group 82, the distance between the bottom surface of the recessed hole 42 corresponding to the sub-electrode 321 and the sub-electrode 321 is 10 angstroms to 15 angstroms. For example, in the second electrode group 82, the distance between the bottom surface of the recessed hole 42 corresponding to the sub-electrode 321 and the sub-electrode 321 is 12 angstroms.

[0130] When the distance from the bottom surface of the concave hole 42 to the sub-electrode 321 is within this range, 20% to 30% of the current can be blocked from extending from the concave hole 42 to the sub-electrode 321 .

[0131] Illustratively, in the third electrode group 83, the distance between the bottom surface of the recessed hole 42 corresponding to the sub-electrode 321 and the sub-electrode 321 is 3 angstroms to 6 angstroms. For example, in the third electrode group 83, the distance between the bottom surface of the recessed hole 42 corresponding to the sub-electrode 321 and the sub-electrode 321 is 5 angstroms.

[0132] When the distance from the bottom surface of the concave hole 42 to the sub-electrode 321 is within this range, 0 to 10% of the current can be blocked from extending from the concave hole 42 to the sub-electrode 321 .

[0133] Optionally, the distance from the bottom surface of the concave hole 42 to the sub-electrode 321 gradually decreases in a direction away from the first electrode 31 .

[0134] For example, in the recess 42 , the maximum difference in the distance from the bottom of the recess 42 to the sub-electrode 321 does not exceed 10% of the maximum distance from the bottom of the recess 42 to the sub-electrode 321 , so as to avoid excessive differences in heat generation between different regions of the sub-electrode 321 .

[0135] Alternatively, as Figure 2 As shown, the sub-electrode 321 is in the shape of a fan ring or a strip.

[0136] like Figure 1 As shown, after forming the through hole 41 and the recessed hole 42, the preparation method may further include: making a first solder joint block 51 and a second solder joint block 52 on the surface of the passivation layer 40, the first solder joint block 51 being connected to the first electrode 31 through the through hole 41, and the second solder joint block 52 being located in the recessed hole 42.

[0137] A first solder joint block 51 is formed on the surface of the passivation layer 40 by photolithography, so that the first solder joint block 51 is connected to the first electrode 31 through the through hole 41; then, a second solder joint block 52 is formed on the surface of the passivation layer 40 by photolithography, so that the second solder joint block 52 is located in the recessed hole 42.

[0138] In the embodiment of the present disclosure, the first soldering block 51 and the second soldering block 52 may include a Ti layer, a first Ni layer, an Au layer, a second Ni layer, and a Sn alloy layer stacked in sequence.

[0139] Illustratively, the thickness of the Ti layer may be 500 angstroms to 1500 angstroms, for example, the thickness of the Ti layer may be 1000 angstroms.

[0140] Illustratively, the thickness of the first Ni layer may be 500 angstroms to 1500 angstroms. For example, the thickness of the first Ni layer may be 1000 angstroms.

[0141] Illustratively, the thickness of the Au layer may be 8,000 angstroms to 12,000 angstroms. For example, the thickness of the Au layer may be 10,000 angstroms.

[0142] Illustratively, the thickness of the second Ni layer may be 2000 angstroms to 4000 angstroms. For example, the thickness of the second Ni layer may be 3000 angstroms.

[0143] Illustratively, the thickness of the Sn alloy layer may be 80,000 angstroms to 100,000 angstroms. For example, the thickness of the Sn alloy layer may be 90,000 angstroms.

[0144] In the embodiment of the present disclosure, after the first solder joint block 51 and the second solder joint block 52 are manufactured, the preparation method may further include: manufacturing a protective layer 60 on the surface of the passivation layer 40 , and the protective layer 60 extends from the surface of the passivation layer 40 to the substrate 10 .

[0145] For example, in the embodiment of the present disclosure, the protective layer 60 may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.

[0146] It should be noted that after the protective layer 60 is grown on the surface of the passivation layer 40 , a photolithography technique may be used to etch via holes on the surface of the protective layer 60 to expose the solder joints for electrical connection.

[0147] Finally, the sapphire can be subjected to invisible cutting and cleaving, which can effectively reduce the loss of brightness. Then, the light-emitting diode chip is obtained by testing.

[0148] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A light-emitting diode chip with improved heat dissipation, characterized in that: The light-emitting diode chip comprises: a substrate (10), a light-emitting structure (20), a first electrode (31) and a second electrode (32); The light emitting structure (20) comprises a first semiconductor layer (21), a multi-quantum well layer (22), and a second semiconductor layer (23) stacked in sequence on the substrate (10); the surface of the second semiconductor layer (23) comprises a groove (24) exposing the first semiconductor layer (21); the first electrode (31) is located in the groove (24); the second electrode (32) comprises a plurality of sub-electrodes (321) arranged at intervals; the plurality of sub-electrodes (321) are located on a side of the second semiconductor layer (23) away from the substrate (10); The light-emitting diode chip further comprises a passivation layer (40), the passivation layer (40) being located at least on the second semiconductor layer (23), the first electrode (31), the groove (24), and the second electrode (32), the passivation layer (40) having a through hole (41) and a plurality of recessed holes (42), the through hole (41) exposing the first electrode (31), and the plurality of recessed holes (42) corresponding one-to-one to the plurality of sub-electrodes (321); The distance from the bottom surface of the concave hole (42) to the sub-electrode (321) is negatively correlated with the distance from the concave hole (42) to the first electrode (31), and the passivation layer (40) is located in the concave hole (42).

2. The light-emitting diode chip according to claim 1, characterized in that The second electrode (32) comprises a first electrode group (81), a second electrode group (82), and a third electrode group (83) arranged in sequence in a direction away from the first electrode (31); The shortest distance between each of the sub-electrodes (321) in the first electrode group (81) and the first electrode (31) is the same, the shortest distance between each of the sub-electrodes (321) in the second electrode group (82) and the first electrode (31) is the same, and the shortest distance between each of the sub-electrodes (321) in the third electrode group (83) and the first electrode (31) is the same.

3. The light-emitting diode chip according to claim 2, characterized in that: In the first electrode group (81), the distance from the bottom surface of the concave hole (42) corresponding to the sub-electrode (321) to the sub-electrode (321) is 20 angstroms to 30 angstroms, in the second electrode group (82), the distance from the bottom surface of the concave hole (42) corresponding to the sub-electrode (321) to the sub-electrode (321) is 10 angstroms to 15 angstroms, and in the third electrode group (83), the distance from the bottom surface of the concave hole (42) corresponding to the sub-electrode (321) to the sub-electrode (321) is 3 angstroms to 6 angstroms.

4. The light-emitting diode chip according to claim 1, characterized in that The distance from the bottom surface of the concave hole (42) to the sub-electrode (321) gradually decreases in a direction away from the first electrode (31).

5. The light-emitting diode chip according to any one of claims 1 to 4, characterized in that: The sub-electrode (321) is in the shape of a fan ring or a strip.

6. A method for preparing a light-emitting diode chip with improved light efficiency, characterized in that: The preparation method comprises: An epitaxial wafer is provided, comprising a substrate and a light-emitting structure located on the substrate, wherein the light-emitting structure comprises a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer sequentially stacked on the substrate, wherein a surface of the second semiconductor layer has a groove exposing the first semiconductor layer; Fabricating a first electrode and a second electrode on the epitaxial wafer, wherein the first electrode is located in the groove, and the second electrode includes a plurality of sub-electrodes arranged at intervals, and the plurality of sub-electrodes are located on a side of the second semiconductor layer away from the substrate; forming a passivation layer on the epitaxial wafer, wherein the passivation layer is at least located on the second semiconductor layer, the first electrode, the groove, and the second electrode; A through hole exposing the first electrode and a plurality of concave holes corresponding to the plurality of sub-electrodes are etched on the passivation layer, wherein the distance from the bottom surface of the concave hole to the sub-electrode is negatively correlated with the distance from the concave hole to the first electrode, and the passivation layer (40) is located in the concave hole (42).

7. The preparation method according to claim 6, characterized in that The second electrode includes a first electrode group, a second electrode group and a third electrode group arranged in sequence along a direction away from the first electrode; the shortest distance between each sub-electrode in the first electrode group and the first electrode is the same, the shortest distance between each sub-electrode in the second electrode group and the first electrode is the same, and the shortest distance between each sub-electrode in the third electrode group and the first electrode is the same.

8. The preparation method according to claim 6 or 7, characterized in that Producing a second electrode on the epitaxial wafer includes: performing laser annealing on a region of the second semiconductor layer where a sub-electrode is to be formed; The sub-electrode is formed in the region where the sub-electrode is to be formed.

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