Wide range high adaptability power conversion circuit

Abstract

The present application relates to a kind of wide-range high adaptability power conversion circuit.It includes current field comparator, when input common-mode voltage VCM is greater than power supply voltage VDD, output the voltage comparison selection signal of first level state;When input common-mode voltage VCM is not greater than power supply voltage VDD, output the voltage comparison selection signal of second level state;Voltage selection drive circuit receives the voltage comparison selection signal output by current field comparator, wherein, when the voltage comparison selection signal is first level state, the voltage selection drive circuit selects input common-mode voltage VCM as conversion output voltage V power ;When the voltage comparison selection signal is second level state, the voltage selection drive circuit selects power supply voltage VDD as conversion output voltage V power .The present application can effectively realize the processing of input common-mode voltage and power supply voltage, to adapt to the power supply demand of current detection amplifier etc. at different input common-mode voltage, and the adaptation range is wide.

Description

Technical Field

[0001] This invention relates to a conversion circuit, and more particularly to a wide-range, highly adaptable power conversion circuit. Background Technology

[0002] In general, in CMOS integrated circuit design, operational amplifiers using PMOS as input transistors have a common-mode operating voltage range of (VSS-0.2V) to (VDD-1.5V); operational amplifiers using NMOS as input transistors have a common-mode operating voltage range of (VSS+1.5V) to (VDD+0.2V). In practical applications, operational amplifiers with better performance typically require a rail-to-rail common-mode operating voltage range, i.e., (VSS-0.2V) to (VDD+0.2V); where VSS is the negative power supply when using dual power supplies, and VDD is the positive power supply when using dual power supplies.

[0003] Current sense amplifiers used in high-voltage short-circuit protection, DC / DC converters, and other applications differ from general-purpose operational amplifiers, which can only handle signals with input common-mode voltages within the supply voltage range. They require a wide common-mode input range extending beyond the supply voltage. Furthermore, for current sense amplifiers, when the input common-mode voltage is lower than the supply voltage, a standard operational amplifier with rail-to-rail input characteristics is sufficient to handle the input signal. However, when the input common-mode voltage is higher than the supply voltage, if the input stage circuit of the operational amplifier is still powered by the supply voltage, it cannot handle the input signal properly. In this case, a power supply with a voltage no lower than the input common-mode voltage is needed to power the input stage operational amplifier. However, in the defined application scenarios, switching to a higher power supply is impractical.

[0004] Therefore, in practical applications such as current sense amplifiers, how to effectively process the input common-mode voltage to adapt to different input common-mode voltages and power supply voltages, and achieve stable operation under different application scenarios, is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a wide-range, highly adaptable power conversion circuit that can effectively process the input common-mode voltage and the power supply voltage to adapt to the power supply requirements of current sensing amplifiers and other devices with different input common-mode voltages. It has a wide range of applications and is safe and reliable.

[0006] According to the technical solution provided by the present invention, the wide-range, highly adaptable power conversion circuit includes:

[0007] The current domain comparator receives and extracts the input common-mode voltage VCM through the VIN+ and VIN- terminals, and compares the extracted input common-mode voltage VCM with the power supply voltage VDD in the current domain. When the input common-mode voltage VCM is greater than the power supply voltage VDD, it outputs a voltage comparison selection signal at a first level; when the input common-mode voltage VCM is not greater than the power supply voltage VDD, it outputs a voltage comparison selection signal at a second level.

[0008] A voltage selection drive circuit is adapted and connected to a current domain comparator, and receives the voltage comparison selection signal output by the current domain comparator. When the voltage comparison selection signal is in the first level state, the voltage selection drive circuit selects the input common-mode voltage VCM as the converted output voltage V. power When the voltage comparison selection signal is in the second level state, the voltage selection drive circuit selects the power supply voltage VDD as the conversion output voltage V. power .

[0009] The current domain comparator includes a common-mode voltage extraction unit for extracting the input common-mode voltage VCM, a common-mode voltage conversion unit for converting the input common-mode voltage VCM into a desired current, a power supply voltage conversion unit for converting the power supply voltage VDD into the desired current, and a voltage comparison selection output unit for outputting a voltage comparison selection signal.

[0010] The common-mode voltage converter, the power supply voltage converter, and the voltage comparison and selection output unit are adapted and connected. When the current converted by the common-mode voltage converter is greater than the current converted by the power supply voltage converter, the voltage comparison and selection output unit outputs a voltage comparison and selection signal with a first level high.

[0011] When the current converted by the common-mode voltage converter is less than or equal to the current converted by the power supply voltage converter, the voltage comparison and selection output unit outputs a voltage comparison and selection signal with a second low level.

[0012] The common-mode voltage extraction section includes resistors R10 and R20. One end of resistor R10 is connected to the VIN+ connection terminal, and one end of resistor R20 is connected to the VIN- connection terminal. The other ends of resistor R10 and the other ends of resistor R20 are connected to each other to form a common-mode voltage extraction node VCM.

[0013] The common-mode voltage conversion unit includes an inverting transistor N40. One end of the inverting transistor N40 is connected to the common-mode voltage extraction node VCM, and the other end of the inverting transistor N40 is connected to the voltage comparison and selection output unit through a common-mode amplifying current mirror. The common-mode amplifying current mirror includes transistors Q1 and Q2.

[0014] The collector, base, and base of transistor Q1 and transistor Q2 are all connected to the other end of the inverting transistor N40. The emitter of transistor Q1 and the emitter of transistor Q2 are both grounded. The collector of transistor Q2 is connected to the voltage comparator output section.

[0015] The power supply voltage conversion section includes an inverting transistor N30 and a power supply amplifying current mirror. The power supply amplifying current mirror includes transistors Q3 and Q4. One end of the inverting transistor N30 is connected to the power supply voltage VDD, and the other end of the inverting transistor N30 is connected to the base of transistor Q3, the collector of transistor Q4, and the base of transistor Q4. The emitter of transistor Q3 and the emitter of transistor Q4 are both grounded. The collector of transistor Q3 is connected to the voltage comparison and selection output section.

[0016] Resistors R10 and R20 are resistors with the same resistance value, and the resistance value formed by the inverting transistor N30 is the same as the resistance value formed by the inverting transistor N40.

[0017] The magnification of the common-mode current mirror is the same as that of the power supply current mirror.

[0018] The voltage comparison and selection output section includes a current comparator U1 and a Schmitt trigger SCT1. The collector of transistor Q2 is connected to the non-inverting input of the current comparator U1, the collector of transistor Q3 is connected to the inverting input of the current comparator U1, the output of the current comparator U1 is connected to the input of the Schmitt trigger SCT1, and the output of the Schmitt trigger SCT1 is connected to the voltage selection drive circuit.

[0019] The power supply terminal of the current comparator U1 is connected to the positive terminal of the internal low-voltage source VCC_inner, and the negative terminal of the internal voltage source VCC_inner is grounded.

[0020] The voltage selection drive circuit includes a high-voltage NMOS transistor HVN1 for receiving a voltage comparison selection signal, a high-voltage PMOS transistor HVP1 for adapting to the connection of the power supply voltage VDD, and a high-voltage PMOS transistor HVP2 for adapting to the connection of the input common-mode voltage VCM.

[0021] The source terminal of the high-voltage NMOS transistor HVN1 is connected to the source terminal of the high-voltage NMOS transistor HVN2. The drain terminal of the high-voltage NMOS transistor HVN1 is connected to the gate terminal of the PMOS transistor P2 and one end of the resistor R30. The source terminal of the high-voltage NMOS transistor HVN1 is grounded through the current source I3.

[0022] The drain terminal of the high-voltage PMOS transistor HVP1 is connected to the power supply voltage VDD. The source terminal of the high-voltage PMOS transistor HVP1 is connected to the other end of resistor R30, the source terminal of PMOS transistor P2, the emitter terminal of transistor T1, the source terminal of the high-voltage PMOS transistor HVP2, and the emitter terminal of transistor T4 to form the output voltage V for output conversion. power The converted voltage output terminal;

[0023] The gate of high-voltage PMOS transistor HVP1 is connected to the drain of high-voltage NMOS transistor HVN2, the drain of PMOS transistor P2, the input of inverter INV1, the base of transistor T3, and the collector of transistor T3.

[0024] The output of inverter INV1 is connected to the gate of high-voltage PMOS transistor HVP2. The emitter of transistor T3 is connected to the base and collector of transistor T2. The emitter of transistor T2 is connected to the base and collector of transistor T1.

[0025] The base and collector terminals of transistor T4 are connected to the emitter terminal of transistor T5. The base and collector terminals of transistor T5 are connected to the emitter terminal of transistor T6. The base and collector terminals of transistor T6 are connected to the first power supply terminal of inverter INV1 and the drain terminal of high-voltage NMOS transistor HVN3. The second power supply terminal of inverter INV1 is connected to the conversion voltage output terminal.

[0026] The gate terminals of high-voltage NMOS transistors HVN3 and HVN2 are both connected to the bias voltage NBIAS1, and the source terminal of high-voltage NMOS transistor HVN3 is grounded through current source I4.

[0027] It also includes a current-sensing amplifier, which includes an operational amplifier A1, wherein the voltage-selective drive circuit outputs a converted output voltage V. power This serves as the power supply voltage for operational amplifier A1;

[0028] The non-inverting input of operational amplifier A1 is connected to one end of resistor R3 and one end of resistor R4. The inverting input of operational amplifier A1 is connected to one end of resistor R1 and one end of resistor R2. The other end of resistor R3 is connected to the VIN+ terminal. The other end of resistor R1 is connected to the VIN- terminal. The other end of resistor R2 is connected to the output terminal of operational amplifier A1 to form the current detection amplification output terminal OUT of the current detection amplifier. The other end of resistor R4 is connected to the reference terminal REF.

[0029] Configure resistor R4 as a reference resistor R0, an adjusting resistor series, and a pre-adjustment resistor R6, wherein...

[0030] The regulating resistor string includes m+1 regulating resistors connected in series. The corresponding end of the first regulating resistor forms the first end of the regulating resistor string, and the corresponding end of the last regulating resistor forms the second end of the regulating resistor string. Along the series connection direction from the first resistor to the last resistor, the resistance values ​​of the m+1 regulating resistors increase proportionally, and each regulating resistor is connected in parallel with a trimming fuse.

[0031] One end of the reference resistor R0 is connected to one end of the pre-adjustment resistor R6 and the first end of the adjusting resistor string. The other end of the reference resistor R0 is connected to the resistor R3 and the non-inverting input of the operational amplifier A1. The other end of the pre-adjustment resistor R6 is adjusted to the test reference connection terminal REF_test, and the second end of the adjusting resistor string is connected to the reference connection terminal REF.

[0032] When configuring the common-mode rejection ratio of the current-sensing amplifier, connect the pre-adjustment resistor R6 and measure the pre-adjustment offset voltage with the pre-adjustment resistor R6 connected.

[0033] Based on the pre-adjustment offset voltage and the target offset voltage, determine the target adjustment resistance value connected in the adjustment resistor string, and blow the corresponding adjustment fuse in the adjustment resistor string to obtain the actual adjustment resistance value that matches the target adjustment resistance value.

[0034] The common ratio of the resistance values ​​of adjacent adjusting resistors in the adjusting resistor string is two. The reference resistor R0 is less than the resistor R2, and the resistance value of the pre-adjustment resistor R6 is configured to be the resistance value corresponding to the middle adjusting resistor in the adjusting resistor string.

[0035] Advantages of this invention: The input common-mode voltage VCM is compared with the power supply voltage VDD in the current domain using a current-domain comparator, and a corresponding voltage comparison selection signal is output based on the magnitudes of the input common-mode voltage VCM and the power supply voltage VDD. When the voltage comparison selection signal is in the first level state, the voltage selection drive circuit selects the input common-mode voltage VCM as the converted output voltage V. power When the voltage comparison selection signal is in the second level state, the voltage selection drive circuit selects the power supply voltage VDD as the conversion output voltage V. power The voltage selection drive circuit outputs the conversion output voltage V. power As the power supply voltage in practical applications, it can effectively process the input common-mode voltage VCM and the power supply voltage VDD, so as to adapt to the power supply requirements of current sensing amplifiers and other devices with different input common-mode voltages VCM, improve the adaptability, and ensure safety and reliability. Attached Figure Description

[0036] Figure 1 This is a circuit block diagram of the present invention.

[0037] Figure 2 This is a circuit diagram of the current domain comparator of the present invention.

[0038] Figure 3 This is a circuit diagram of the voltage selection drive circuit of the present invention.

[0039] Figure 4 This is a schematic diagram of the present invention in conjunction with a current sensing amplifier.

[0040] Figure 5 This is a schematic diagram illustrating the common-mode rejection ratio configuration of the current-sensing amplifier according to the present invention.

[0041] Explanation of reference numerals in the attached figures: 1-Current domain comparator, 2-Voltage selection drive circuit, 3-Common mode voltage extraction unit, 4-Common mode voltage conversion unit, 5-Power supply voltage conversion unit, and 6-Voltage comparison and selection output unit. Detailed Implementation

[0042] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0043] To effectively process the input common-mode voltage VCM and the power supply voltage VDD, and to adapt to the power supply requirements of current-sensing amplifiers and other devices with different input common-mode voltages VCM, this invention provides a wide-range, highly adaptable power conversion circuit, specifically comprising:

[0044] The current domain comparator 1 receives and extracts the input common-mode voltage VCM through the VIN+ and VIN- terminals, and compares the extracted input common-mode voltage VCM with the power supply voltage VDD in the current domain. When the input common-mode voltage VCM is greater than the power supply voltage VDD, it outputs a voltage comparison selection signal at a first level; when the input common-mode voltage VCM is not greater than the power supply voltage VDD, it outputs a voltage comparison selection signal at a second level.

[0045] The voltage selection drive circuit 2 is adapted and connected to the current domain comparator 1, and receives the voltage comparison selection signal output by the current domain comparator 1. When the voltage comparison selection signal is in the first level state, the voltage selection drive circuit 2 selects the input common-mode voltage VCM as the converted output voltage V. power When the voltage comparison selection signal is in the second level state, the voltage selection drive circuit 2 selects the power supply voltage VDD as the conversion output voltage V. power .

[0046] As can be seen from the above description, for the input common-mode voltage VCM in a specific application scenario, there is a situation where the processing capability of the application scenario can be extended to a wide common-mode input range beyond the power supply voltage VDD. That is, without changing the power supply voltage VDD, the processing capability of the input common-mode voltage for the specific application scenario can be met.

[0047] To meet the requirements of the aforementioned application scenarios, the wide-range, highly adaptable power conversion circuit of this invention utilizes a current-domain comparator 1 to compare the input common-mode voltage VCM with the power supply voltage VDD in the current domain. Specifically, this involves converting the input common-mode voltage VCM and the power supply voltage VDD into corresponding currents before comparison. However, directly comparing the input common-mode voltage VCM and the power supply voltage VDD using a voltage comparator or similar method presents the problem of determining the comparator's power supply. This is because the function of the voltage comparator is to compare the input common-mode voltage VCM and the power supply voltage VDD; however, only by using the higher voltage as the comparator's power supply can the correctness of the comparison result be guaranteed, which can lead to a logic deadlock problem related to high-voltage judgment.

[0048] In this embodiment of the invention, since the current domain comparator 1 can be powered by an internal low-voltage power supply, the accuracy of voltage judgment can be ensured. Specifically, the input common-mode voltage VCM is received through the VIN+ and VIN- terminals. When comparing the received input common-mode voltage VCM with the power supply voltage VDD, if the input common-mode voltage VCM is greater than the power supply voltage VDD, a voltage comparison selection signal of the first level is output; if the input common-mode voltage VCM is not greater than the power supply voltage VDD, a voltage comparison selection signal of the second level is output. That is, when the input common-mode voltage VCM is less than or equal to the power supply voltage VDD, the current domain comparator 1 outputs a voltage comparison selection signal of the second level. The first and second level states are two opposite levels; for example, if the first level state is high, the second level state is low; similarly, if the first level state is low, the second level state is high. The specific first and second level states can be selected as needed to meet the actual application requirements.

[0049] The voltage selection drive circuit 2 is adapted and connected to the current domain comparator 1, meaning that the voltage selection drive circuit 2 receives the voltage comparison selection signal output by the current domain comparator 1. Specifically, when the voltage comparison selection signal is in the first level state, the voltage selection drive circuit 2 selects the input common-mode voltage VCM as the converted output voltage V. power When the voltage comparison selection signal is in the second level state, the voltage selection drive circuit 2 selects the power supply voltage VDD as the conversion output voltage V. power The output voltage V output by the voltage selection drive circuit 2 is converted. power As the power supply voltage in practical applications, it can be seen from the above description that it can effectively process the input common-mode voltage VCM and the power supply voltage VDD, so as to adapt to the power supply requirements of current sensing amplifiers and other devices with different input common-mode voltages VCM, and improve the adaptability range.

[0050] Further, the current domain comparator 1 includes a common-mode voltage extraction unit 3 for extracting the input common-mode voltage VCM, a common-mode voltage conversion unit 4 for converting the input common-mode voltage VCM into the required current, a power supply voltage conversion unit 5 for converting the power supply voltage VDD into the required current, and a voltage comparison selection output unit 6 for outputting a voltage comparison selection signal, wherein,

[0051] The common-mode voltage converter 4, the power supply voltage converter 5, and the voltage comparison and selection output unit 6 are adapted and connected. When the current converted by the common-mode voltage converter 4 is greater than the current converted by the power supply voltage converter 5, the voltage comparison and selection output unit 6 outputs a voltage comparison and selection signal with a first level high.

[0052] When the current converted by the common-mode voltage converter 4 is less than or equal to the current converted by the power supply voltage converter 5, the voltage comparison and selection output unit 6 outputs a voltage comparison and selection signal with a second low level.

[0053] In this embodiment of the invention, the common-mode voltage extraction unit 3 is adapted to connect to the VIN+ and VIN- terminals and extracts the input common-mode voltage VCM. The common-mode voltage conversion unit 4 can convert the input common-mode voltage VCM into a corresponding current, and the power supply voltage conversion unit 5 can convert the power supply voltage VDD into a corresponding current, so that direct current comparison can be performed.

[0054] The voltage comparison selection output unit 6 outputs a voltage comparison selection signal. Specifically, when the current converted by the common-mode voltage conversion unit 4 is greater than the current converted by the power supply voltage conversion unit 5, the voltage comparison selection output unit 6 outputs a voltage comparison selection signal with a first high level. When the current converted by the common-mode voltage conversion unit 4 is less than or equal to the current converted by the power supply voltage conversion unit 5, the voltage comparison selection output unit 6 outputs a voltage comparison selection signal with a second low level.

[0055] Figure 2 The image shows a specific implementation of the current domain comparator 1. Specifically, the common-mode voltage extraction unit 3 includes a resistor R10 and a resistor R20. One end of the resistor R10 is connected to the VIN+ connection terminal, and one end of the resistor R20 is connected to the VIN- connection terminal. The other ends of the resistor R10 and the other ends of the resistor R20 are connected to each other to form a common-mode voltage extraction node VCM.

[0056] The common-mode voltage conversion unit 4 includes an inverting transistor N40. One end of the inverting transistor N40 is connected to the common-mode voltage extraction node VCM, and the other end of the inverting transistor N40 is connected to the voltage comparison and selection output unit 6 through a common-mode amplifying current mirror. The common-mode amplifying current mirror includes transistors Q1 and Q2.

[0057] The collector terminal of transistor Q1, the base terminal of transistor Q1, and the base terminal of transistor Q2 are all connected to the other end of the inverting transistor N40. The emitter terminals of transistor Q1 and Q2 are both grounded. The collector terminal of transistor Q2 is connected to the voltage comparison selection output section 6.

[0058] The power supply voltage conversion unit 5 includes an inverting transistor N30 and a power supply amplifying current mirror. The power supply amplifying current mirror includes transistors Q3 and Q4. One end of the inverting transistor N30 is connected to the power supply voltage VDD, and the other end of the inverting transistor N30 is connected to the base of transistor Q3, the collector of transistor Q4, and the base of transistor Q4. The emitter of transistor Q3 and the emitter of transistor Q4 are both grounded. The collector of transistor Q3 is adapted and connected to the voltage comparison and selection output unit 6.

[0059] In practical implementation, resistors R10 and R20 use resistors with the same resistance value, i.e., R10 = R20. When the wide-range, highly adaptable power conversion circuit of this invention is applied to a current-sensing amplifier, since the current-sensing amplifier requires an external, relatively small sensing resistor for differential voltage acquisition, the sensing resistor is connected in parallel with the equivalent resistance of the series connection of resistors R10 and R20. To reduce the impact on the effective value of the sensing resistor and the accuracy of current detection, resistors R10 and R20 should be sufficiently large.

[0060] In addition, if the input common-mode voltage VCM is higher than the supply voltage VDD, then the input stage of the current-sense amplifier will be powered by the input common-mode voltage VCM. Therefore, current will inevitably flow through resistors R10 and R20, resulting in an additional voltage drop. To ensure that excessive voltage drops are not generated across terminals R10 and R20, and to guarantee that the supply voltage of the current-sense amplifier's input stage can handle the higher common-mode input voltage VCM, the resistance values ​​of resistors R10 and R20 should not be too large. In practice, the corresponding resistance values ​​of resistors R10 and R20 are determined based on the current consumed by the input stage of the current-sense amplifier, to meet the actual application requirements.

[0061] In practical implementation, the inverting transistor N40 comprises several NMOS transistors. The gates of all NMOS transistors within N40 are interconnected and connected to the common-mode voltage extraction node VCM. For adjacent NMOS transistors, the source terminal of one NMOS transistor is connected to the drain terminal of another, thus creating a large resistance through the inverting transistor N40. Transistors Q1 through Q4 can all be NPN transistors.

[0062] In practical implementation, the reciprocating tube N30 adopts the exact same form as the reciprocating tube N40. For details regarding the reciprocating tube N30, please refer to the above description. Figure 2 This will not be further explained here. In this embodiment of the invention, the resistance value formed by the inverting ratio tube N30 is the same as the resistance value formed by the inverting ratio tube N40.

[0063] The magnification factor of the common-mode current mirror is the same as that of the power supply current mirror. In practice, the corresponding current amplification factors of the common-mode current mirror and the power supply current mirror are both 1:8, that is, the current after converting the input common-mode voltage VCM and the current after converting the power supply voltage VDD are amplified by 8 times before comparison.

[0064] In actual operation, the input common-mode voltage VCM is converted into current by the inverting transistor N40, and then amplified by the common-mode current mirror formed by transistors Q1 and Q2 before flowing into the voltage comparison and selection output section 6.

[0065] The power supply voltage VDD is converted into current by the inverting transistor N30, and the power supply current mirror formed by transistors Q3 and Q4 is amplified to transistor Q3, which is finally loaded onto the voltage comparison and selection output unit 6. The voltage comparison and selection output unit 6 compares the two converted currents to obtain the voltage comparison and selection signal.

[0066] In actual operation, if the input common-mode voltage VCM is higher than the power supply voltage VDD, the current converted by the common-mode voltage conversion unit 4 is greater than the current converted by the power supply voltage conversion unit 5, and a high-level voltage comparison selection signal is obtained through the voltage comparison selection output unit 6; if the input common-mode voltage VCM is not greater than the power supply voltage VDD, the current converted by the common-mode voltage conversion unit 4 is less than or equal to the current converted by the power supply voltage conversion unit 5, and a low-level voltage comparison selection signal is obtained through the voltage comparison selection output unit 6.

[0067] Figure 2In the above, the voltage comparison and selection output unit 6 includes a current comparator U1 and a Schmitt trigger SCT1. The collector of transistor Q2 is connected to the non-inverting input of the current comparator U1, the collector of transistor Q3 is connected to the inverting input of the current comparator U1, the output of the current comparator U1 is connected to the input of the Schmitt trigger SCT1, and the output of the Schmitt trigger SCT1 is connected to the voltage selection drive circuit 2.

[0068] The power supply terminal of the current comparator U1 is connected to the positive terminal of the internal low-voltage source VCC_inner, and the negative terminal of the internal voltage source VCC_inner is grounded.

[0069] Figure 2 In this circuit, the common-mode voltage converter 4 converts the current I1, and the power supply voltage converter 5 converts the current I2. The current comparator U1 compares current I1 and current I2 and outputs a voltage comparison selection signal through the Schmitt trigger SCT1. The current comparator U1 can adopt a commonly used form, which can be selected according to needs to meet the comparison of current I1 and current I2. Of course, in specific implementations, the voltage comparison selection output unit 6 can also adopt other forms, which can be selected according to needs to meet actual requirements, and will not be listed here.

[0070] The internal low-voltage source VCC_inner can output its own low voltage, VCC_inner, which is used to power the current domain comparator 1. The specific configuration of the internal low-voltage VCC_inner can be selected according to the actual application scenario, referring to the above description. In specific implementation, the voltage comparison selection signal output by the current domain comparator 1, within the internal low-voltage Vcc_inner, is passed through the Schmitt trigger SCT1 and used as the gate control signal for the high-voltage NMOS turn-off transistor HVN4 in the voltage selection drive circuit 2 described below; that is, the voltage range of the voltage comparison selection signal is 0-Vcc_inner. In specific implementation, the supply voltage of the Schmitt trigger SCT1 is also the internal low-voltage Vcc_inner.

[0071] Figure 3 The diagram illustrates one embodiment of a voltage selection drive circuit 2, which includes a high-voltage NMOS transistor HVN1 for receiving a voltage comparison and selection signal, a high-voltage PMOS transistor HVP1 adapted to the connection of the power supply voltage VDD, and a high-voltage PMOS transistor HVP2 adapted to the connection of the input common-mode voltage VCM.

[0072] The source terminal of the high-voltage NMOS transistor HVN1 is connected to the source terminal of the high-voltage NMOS transistor HVN2. The drain terminal of the high-voltage NMOS transistor HVN1 is connected to the gate terminal of the PMOS transistor P2 and one end of the resistor R30. The source terminal of the high-voltage NMOS transistor HVN1 is grounded through the current source I3.

[0073] The drain terminal of the high-voltage PMOS transistor HVP1 is connected to the power supply voltage VDD. The source terminal of the high-voltage PMOS transistor HVP1 is connected to the other end of resistor R30, the source terminal of PMOS transistor P2, the emitter terminal of transistor T1, the source terminal of the high-voltage PMOS transistor HVP2, and the emitter terminal of transistor T4 to form the output voltage V for output conversion. power The converted voltage output terminal;

[0074] The gate of high-voltage PMOS transistor HVP1 is connected to the drain of high-voltage NMOS transistor HVN2, the drain of PMOS transistor P2, the input of inverter INV1, the base of transistor T3, and the collector of transistor T3.

[0075] The output of inverter INV1 is connected to the gate of high-voltage PMOS transistor HVP2. The emitter of transistor T3 is connected to the base and collector of transistor T2. The emitter of transistor T2 is connected to the base and collector of transistor T1.

[0076] The base and collector terminals of transistor T4 are connected to the emitter terminal of transistor T5. The base and collector terminals of transistor T5 are connected to the emitter terminal of transistor T6. The base and collector terminals of transistor T6 are connected to the first power supply terminal of inverter INV1 and the drain terminal of high-voltage NMOS transistor HVN3. The second power supply terminal of inverter INV1 is connected to the conversion voltage output terminal.

[0077] The gate terminals of high-voltage NMOS transistors HVN3 and HVN2 are both connected to the bias voltage NBIAS1, and the source terminal of high-voltage NMOS transistor HVN3 is grounded through current source I4.

[0078] Specifically, the gate of the high-voltage NMOS transistor HVN4 is connected to the output of the Schmitt trigger SCT1. Current sources I3 and I4 are used to provide quiescent current; the specific configuration of the quiescent circuit provided by current sources I3 and I4 can be selected based on actual application requirements. In practice, node A is formed by connecting the input of inverter INV1 to the drain of PMOS transistor P2, the gate of high-voltage PMOS transistor HVP1, the drain of high-voltage NMOS transistor HVN2, the base of transistor T3, and the collector of transistor T3. Node B is formed by connecting the output of inverter INV1 to the gate of high-voltage PMOS transistor HVP2.

[0079] In practical implementation, transistors T1 through T6 are all PNP transistors; of course, other types can also be used, depending on the specific requirements, which will not be elaborated here. The specific value of the bias voltage NBIAS1 can be selected as needed, based on meeting the actual application requirements.

[0080] When the voltage comparison selection signal applied to the gate of the high-voltage NMOS transistor HVN1 is high, HVN1 is turned on. After HVN1 is turned on, current flows through resistor R30, providing a bias voltage for PMOS transistor P2 to turn it on. At this time, node A is pulled up to a high potential, and node B is pulled down to a low potential. The low potential of node B is three times lower than the PMOS threshold voltage compared to the high potential of node A. Based on the voltages of nodes A and B, high-voltage PMOS transistor HVP1 is turned off, and high-voltage PMOS transistor HVP2 is turned on. The converted output voltage V is output through the conversion voltage output terminal. power The input common-mode voltage is VCM.

[0081] Corresponding to the above states, when the voltage comparison selection signal applied to the gate terminal of the high-voltage NMOS transistor HVN1 is low, the high-voltage NMOS transistor HVN1 is turned off, and the current flows through transistors T1, T2, and T3 to clamp the potential of node A to the ratio conversion output voltage V. power Three times lower V be The low potential. Where, V beThis refers to the base-emitter junction voltage of the transistor. To ensure circuit reliability, the voltage drop clamping voltage formed by the series connection of transistors T1, T2, and T3 should be slightly lower than the voltage drop clamping voltage formed by the series connection of transistors T4, T5, and T6. "Slightly lower" generally means a small difference; the specific value can be chosen based on the actual application scenario to meet the requirements. At this time, node A is at a low potential and node B is at a high potential, causing high-voltage PMOS transistor HVP1 to conduct and high-voltage PMOS transistor HVP2 to turn off. The converted output voltage V is then output through the conversion voltage output terminal. power This is the power supply voltage VDD.

[0082] In specific implementation, for either the high-voltage PMOS transistor HVP1 or HVP2, when the gate voltage of the high-voltage PMOS transistor is high, the high level of the gate is equal to the source potential of the high-voltage PMOS transistor; when the gate voltage of the PMOS transistor is low, the low level potential is equal to the source potential of either the high-voltage PMOS transistor HVP1 or HVP2 minus three times the voltage V. be Specifically, the source potentials of the high-voltage PMOS transistors HVP1 and HVP4 are the conversion output voltage V. power Therefore, the gate-source voltages of high-voltage PMOS transistors HVP1 and HVP2 are always within the 5V range, ensuring that the source and drain of the high-voltage PMOS transistors can withstand high voltage and preventing damage.

[0083] In summary, for a wide-range, highly adaptable power conversion circuit, we have:

[0084]

[0085] Specifically, when the input common-mode voltage VCM is higher than the power supply voltage VDD, the voltage comparison selection signal output by current domain comparator 1 is high, the high-voltage NMOS transistor HVN1 is turned on, and the converted output voltage V is output through the converted voltage output terminal. power The input common-mode voltage is VCM. When the input common-mode voltage VCM is less than or equal to the power supply voltage VDD, the voltage comparison selection signal output by the current domain comparator is low, the high-voltage NMOS transistor HVN1 is turned off, and the converted output voltage V is output through the conversion voltage output terminal. power The power supply voltage is VDD, which means that the power supply voltage adaptive conversion function is realized.

[0086] like Figure 4 and Figure 5As shown, it also includes a current-sensing amplifier, which includes an operational amplifier A1, wherein the voltage selection drive circuit outputs a converted output voltage V. power This serves as the power supply voltage for operational amplifier A1;

[0087] The non-inverting input of operational amplifier A1 is connected to one end of resistor R3 and one end of resistor R4. The inverting input of operational amplifier A1 is connected to one end of resistor R1 and one end of resistor R2. The other end of resistor R3 is connected to the VIN+ terminal. The other end of resistor R1 is connected to the VIN- terminal. The other end of resistor R2 is connected to the output terminal of operational amplifier A1 to form the current detection amplification output terminal OUT of the current detection amplifier. The other end of resistor R4 is connected to the reference terminal REF.

[0088] Specifically, Figure 4 and Figure 5 The adaptive power conversion circuit in it is Figure 1 The circuit form in the middle, using Figure 1 When the wide-range, highly adaptable power conversion circuit in the current sense amplifier provides the power supply voltage for the operational amplifier A1, as explained above, the current sense amplifier can be extended to a wide common-mode input range beyond the power supply voltage VDD. Figure 4 and Figure 5 Operational amplifier A1 in the amplifier is typically a multi-stage operational amplifier. A wide-range, highly adaptable power conversion circuit powers the input stage of operational amplifier A1. That is, when the input common-mode voltage VCM is lower than the power supply voltage VDD, the input stage of operational amplifier A1 is powered by the power supply voltage VDD; when the input common-mode voltage VCM is higher than the power supply voltage VDD, the input stage of operational amplifier A1 is powered by the input common-mode voltage VCM.

[0089] As those skilled in the art will know, a current sense amplifier is an amplifier that detects current by measuring the voltage drop across the resistor in the current path. The output of a current sense amplifier is a voltage or current proportional to the measured current, and it is widely used in automobiles, power management, battery chargers and other fields.

[0090] right Figure 4 In the current sensing amplifier, ideally, when the gain is configured through resistors R1 and R4, the condition of equation (1) should be met, and the ideal output voltage expressed by equation (2) can be obtained.

[0091]

[0092] V OUT =V REF +V sense ×Gain (2)

[0093] Where Gain is the gain of the current sense amplifier, V REF V is the reference voltage. OUT This is the output voltage of the current-sensing amplifier. Reference voltage V. REF It is typically loaded to the reference connection end REF.

[0094] The common-mode rejection ratio (CMRR) of an operational amplifier is a very important indicator, reflecting the ability of a differential amplifier circuit to amplify differential signals and suppress common-mode signals. The formula for calculating the CMRR is:

[0095]

[0096] Where CMRR1 is the common-mode rejection ratio of the operational amplifier, A d A is the voltage amplification factor for the differential signal. c This is the voltage amplification factor for the common-mode signal.

[0097] If operational amplifier A1 has a sufficiently high common-mode rejection ratio (CMRR), then the overall CMRR of the current-sensing amplifier is determined by the matching accuracy between the resistors. According to the definition of CMRR, the CMRR² of the current-sensing amplifier can be obtained as:

[0098]

[0099] Assuming the target gain is 1, ideally all resistors should be equal. If one resistor has a 0.1% mismatch, and assuming R1 = R2 = R3 = R and R4 = 1.001R, then:

[0100]

[0101] Therefore, the common-mode rejection ratio (CMRR) of a current-sense amplifier is always affected by resistor mismatch. Even a 0.1% mismatch in one resistor can result in a CMRR of only 66 dB. It is clear from the above equation that to achieve a high CMRR, the ratio of resistors R2 to R1 must be infinitely close to the ratio of resistors R4 to R3. If these ratios are equal, an infinitely high CMRR will be obtained.

[0102] If a common-mode rejection ratio (CMRR) of over 80dB is desired for a current-sense amplifier, then the resistor matching accuracy needs to reach 0.01%. However, due to limitations in domestic semiconductor manufacturing processes, achieving a resistor matching accuracy of around 0.3% is already quite difficult. Therefore, in current technologies, it is impossible to fabricate a current-sense amplifier with high CMRR solely based on matching accuracy guaranteed by the manufacturing process.

[0103] To achieve the desired common-mode rejection ratio (CMRR) configuration for the current-sensing amplifier, and to ensure a high CMRR, in this embodiment of the invention, resistor R4 is configured as a reference resistor R0, an adjusting resistor string, and a pre-adjustment resistor R6.

[0104] The regulating resistor string includes m+1 regulating resistors connected in series. The corresponding end of the first regulating resistor forms the first end of the regulating resistor string, and the corresponding end of the last regulating resistor forms the second end of the regulating resistor string. Along the series connection direction from the first resistor to the last resistor, the resistance values ​​of the m+1 regulating resistors increase proportionally, and each regulating resistor is connected in parallel with a trimming fuse.

[0105] One end of the reference resistor R0 is connected to one end of the pre-adjustment resistor R6 and the first end of the adjusting resistor string. The other end of the reference resistor R0 is connected to the resistor R3 and the non-inverting input of the operational amplifier A1. The other end of the pre-adjustment resistor R6 is adjusted to the test reference connection terminal REF_test, and the second end of the adjusting resistor string is connected to the reference connection terminal REF.

[0106] When configuring the common-mode rejection ratio of the current-sensing amplifier, connect the pre-adjustment resistor R6 and measure the pre-adjustment offset voltage with the pre-adjustment resistor R6 connected.

[0107] Based on the pre-adjustment offset voltage and the target offset voltage, determine the target adjustment resistance value connected in the adjustment resistor string, and blow the corresponding adjustment fuse in the adjustment resistor string to obtain the actual adjustment resistance value that matches the target adjustment resistance value.

[0108] To achieve a high common-mode rejection ratio in the current-sensing amplifier, as explained above, the ratio of resistors R2 and R1 should be made infinitely close to the ratio of resistors R4 and R3. In this embodiment of the invention, the ratio of resistors R4 and R3 is changed by adjusting the value of resistor R4, making the resistance value approach the ratio of resistors R2 and R1. During circuit design, resistor R0 is designed to be smaller than resistor R2. After chip manufacturing, a portion of the adjustable resistors in the adjustable resistor string (Res Block) is connected to the circuit to change the ratio of resistors R4 and R3, making it approach the ratio of resistors R2 and R1.

[0109] Figure 5 In the series of resistors, the m+1 adjustable resistors are: resistor R30, resistor R51, resistor R52, ..., resistor R5(m-1), resistor R5m. The resistance values ​​of the m+1 adjustable resistors can be in the following relationship: 1:2:4:2 m-1 :2 mThis means that, based on the resistance value of resistor R30, the corresponding resistance values ​​of adjacent adjusting resistors are proportionally related, and the common ratio of the resistance values ​​of adjacent adjusting resistors in the adjusting resistor string is 2. The resistance value of resistor R30 determines the configurable precision; the smaller the resistance value of R30, the higher the configurable common-mode rejection ratio. In practice, each adjusting resistor in the adjusting resistor string is connected in parallel with a trimming fuse. That is, in the initial state, by default, resistors R30 to R5m are all short-circuited by their respective trimming fuses. Figure 5 In the diagram, the adjustment fuses are Fuese0, Fuse1, ..., Fusem, which correspond one-to-one with the adjustable resistors R30, R51, ..., R5m.

[0110] Use resistor R6 as the pre-adjustment resistor. The resistance value of the pre-adjustment resistor R6 should preferably be the middle value between the adjustment resistor R30 and the adjustment resistor R5m. That is, the resistance value of the pre-adjustment resistor R6 should be configured to be the resistance value corresponding to the middle adjustment resistor in the adjustment resistor string.

[0111] When the pre-adjustment resistor R6 is connected to the circuit, the pre-adjustment offset voltage output by the current sense amplifier can be measured using techniques commonly used in this field. For a given current sense amplifier, the target offset voltage can be determined based on the application scenario. Therefore, the actual resistance value of the configuration resistor R4 can be determined based on the relationship between the target offset voltage and the pre-adjustment offset voltage, thus determining the adjustable resistor that needs to be connected in the adjustment resistor string. After determining the adjustable resistor that needs to be connected, the corresponding adjustment fuse is blown using techniques commonly used in this field, ultimately configuring the resistance value of resistor R4, which in turn configures the common-mode rejection ratio of the current sense amplifier.

[0112] In practical implementation, the common-mode rejection ratio of the current-sensing amplifier can be equivalently determined as: Where Gain is the gain of the current sense amplifier, and Vos out1 The output offset voltage when the common-mode voltage is VCM1, Vos out2 VCM1 is the output offset voltage when the input common-mode voltage is VCM2, VCM1 is the lowest input common-mode voltage of the current-sensing amplifier, and VCM2 is the highest input common-mode voltage of the current-sensing amplifier. When Vos out2 -Vos out1 When the value of CMMR2 is close to 0, the value of CMMR2 is relatively large; therefore, Vos can be... out2 -Vos out1 The magnitude of the common-mode rejection ratio (CMRR) is used as an indicator of the common-mode rejection ratio of the current sensing amplifier.

[0113] Therefore, as explained above, the adjustable resistor to be connected in the regulating resistor string is determined based on the relationship between the target offset voltage and the pre-adjustment offset voltage. In practical implementation, those skilled in the art will be able to obtain:

[0114]

[0115] When the resistance of resistor R4 changes by ΔR, then...

[0116]

[0117] When the resistance of resistor R4 changes by 2ΔR, then...

[0118]

[0119] When ΔR << R3 + R4

[0120] To achieve a high common-mode rejection ratio (CMMR2) in the current-sensing amplifier, it is required that... When the common-mode rejection ratio (CMMR2) of the current-sensing amplifier is 100dB, the resistance value deviation of any one of resistors R1 to R4 must be only 1 / 3. That is, the minimum accuracy of the resistance change ΔR of the configured resistor R4 is ΔR << R3 + R4.

[0121] Therefore, based on the above explanation, it can be considered that the change in resistance R4, ΔR, is related to its corresponding Vos. out2 The change is proportional. At this point, based on the change in resistance R4 ΔR and Vos... out2 After measuring the pre-adjustment offset voltage, the variable amount can be used to determine the adjustable resistor to be connected in the adjusting resistor string based on the target offset voltage.

Claims

1. A wide-range high-adaptability power conversion circuit, characterized by, The application relates to a current domain comparator (1) which receives and extracts an input common-mode voltage VCM through a VIN+ connection terminal and a VIN- connection terminal, and compares the extracted input common-mode voltage VCM with a power supply voltage VDD in a current domain, wherein when the input common-mode voltage VCM is greater than the power supply voltage VDD, a voltage comparison selection signal in a first level state is output; and when the input common-mode voltage VCM is not greater than the power supply voltage VDD, a voltage comparison selection signal in a second level state is output. The current domain comparator (1) comprises a common-mode voltage extraction unit (3) for extracting the input common-mode voltage VCM, a common-mode voltage conversion unit (4) for converting the input common-mode voltage VCM into a required current, a power supply voltage conversion unit (5) for converting the power supply voltage VDD into a required current, and a voltage comparison selection output unit (6) for outputting the voltage comparison selection signal, wherein The voltage selection driving circuit (2) is connected with the current domain comparator (1) and receives the voltage comparison selection signal output by the current domain comparator (1), wherein when the voltage comparison selection signal is in the first level state, the voltage selection driving circuit (2) selects the common-mode voltage VCM as the conversion output voltage V power ; when the voltage comparison selection signal is in the second level state, the voltage selection driving circuit (2) selects the power supply voltage VDD as the conversion output voltage V power . The common-mode voltage conversion unit (4), the power supply voltage conversion unit (5) and the voltage comparison selection output unit (6) are adaptively connected, when the current converted by the common-mode voltage conversion unit (4) is greater than the current converted by the power supply voltage conversion unit (5), the voltage comparison selection signal in the first level state with a high level is output through the voltage comparison selection output unit (6); When the current converted by the common-mode voltage conversion unit (4) is less than or equal to the current converted by the power supply voltage conversion unit (5), the voltage comparison selection signal in the second level state with a low level is output through the voltage comparison selection output unit (6); The common-mode voltage extraction unit (3) comprises a resistor R10 and a resistor R20, one end of the resistor R10 is connected with the VIN+ connection terminal, one end of the resistor R20 is connected with the VIN- connection terminal, and the other end of the resistor R10 and the other end of the resistor R20 are connected with each other to form a common-mode voltage extraction node; The common-mode voltage conversion unit (4) comprises an inverter N40, one end of the inverter N40 is connected with the common-mode voltage extraction node, and the other end of the inverter N40 is connected with the voltage comparison selection output unit (6) through a common-mode amplification current mirror, wherein the common-mode amplification current mirror comprises a triode Q1 and a triode Q2; The collector end of the triode Q1, the base end of the triode Q1 and the base end of the triode Q2 are all connected with the other end of the inverter N40, the emitter end of the triode Q1 and the emitter end of the triode Q2 are all grounded, and the collector end of the triode Q2 is adaptively connected with the voltage comparison selection output unit (6); The power supply voltage conversion unit (5) comprises an inverter N30 and a power supply amplification current mirror, the power supply amplification current mirror comprises a triode Q3 and a triode Q4, wherein one end of the inverter N30 is connected with the power supply voltage VDD, the other end of the inverter N30 is connected with the base end of the triode Q3, the collector end of the triode Q4 and the base end of the triode Q4, the emitter end of the triode Q3 and the emitter end of the triode Q4 are all grounded, and the collector end of the triode Q3 is adaptively connected with the voltage comparison selection output unit (6). ​ 2. The wide-range high-adaptability power conversion circuit according to claim 1, characterized by: The resistance R10 and the resistance R20 adopt resistances with same resistance value, and the resistance value formed by the inverter N30 is same as the resistance value formed by the inverter N40; The amplification multiple of the common-mode amplification current mirror is same as the amplification multiple of the power supply amplification current mirror.

3. The wide-range high-adaptive power conversion circuit according to claim 1, characterized by: The voltage comparison selection output part (6) comprises a current comparator U1 and a Schmitt trigger SCT1, the collector terminal of a transistor Q2 is connected with the non-inverting terminal of the current comparator U1, the collector terminal of a transistor Q3 is connected with the inverting terminal of the current comparator U1, the output terminal of the current comparator U1 is connected with the input terminal of the Schmitt trigger SCT1, and the output terminal of the Schmitt trigger SCT1 is connected with the voltage selection driving circuit (2). The power supply terminal of the current comparator U1 is connected with the positive terminal of an internal low-voltage source VCC_inner, and the negative terminal of the internal voltage source VCC_inner is grounded.

4. The wide-range high-adaptive power conversion circuit according to any one of claims 1 to 3, characterized by: The voltage selection driving circuit (2) comprises a high-voltage NMOS tube HVN1 for receiving a voltage comparison selection signal, a high-voltage PMOS tube HVP1 for adapting to connect a power supply voltage VDD, and a high-voltage PMOS tube HVP2 for adapting to connect an input common-mode voltage VCM, wherein, The source terminal of the high-voltage NMOS tube HVN1 is connected with the source terminal of a high-voltage NMOS tube HVN2, the drain terminal of the high-voltage NMOS tube HVN1 is connected with the gate terminal of a PMOS tube P2 and one end of a resistance R30, and the source terminal of the high-voltage NMOS tube HVN1 is grounded through a current source I3; The drain terminal of the high-voltage PMOS transistor HVP1 is connected to a power supply voltage VDD, and the source terminal of the high-voltage PMOS transistor HVP1 is connected to the other terminal of the resistor R30, the source terminal of the PMOS transistor P2, the emitter terminal of the transistor T1, the source terminal of the high-voltage PMOS transistor HVP2, and the emitter terminal of the transistor T4, to form a conversion voltage output terminal for outputting a conversion output voltage V power out. The gate terminal of the high-voltage PMOS tube HVP1 is connected with the drain terminal of the high-voltage NMOS tube HVN2, the drain terminal of the PMOS tube P2, the input terminal of an inverter INV1, the base terminal of a transistor T3 and the collector terminal of the transistor T3; The output of the inverter INV1 is connected with the gate terminal of the high-voltage PMOS tube HVP2, the emitter terminal of the transistor T3 is connected with the base terminal and the collector terminal of a transistor T2, the emitter terminal of the transistor T2 is connected with the base terminal and the collector terminal of a transistor T1, the base terminal of the transistor T4 and the collector terminal of the transistor T4 are both connected with the emitter terminal of a transistor T5, the base terminal of the transistor T5 and the collector terminal of the transistor T5 are both connected with the emitter terminal of a transistor T6, the base terminal of the transistor T6 and the collector terminal of the transistor T6 are both connected with the first power supply terminal of the inverter INV1 and the drain terminal of a high-voltage NMOS tube HVN3, and the second power supply terminal of the inverter INV1 is connected with a conversion voltage output terminal; The gate terminal of the high-voltage NMOS tube HVN3 and the gate terminal of the high-voltage NMOS tube HVN2 are both connected with a bias voltage NBIAS1, and the source terminal of the high-voltage NMOS tube HVN3 is grounded through a current source I4. ​ 5. The wide-range high-adaptive power conversion circuit according to any one of claims 1 to 3, characterized by: Also included is a current detection amplifier including an operational amplifier Al, wherein a conversion output voltage V power as a supply voltage of the operational amplifier Al; The non-inverting terminal of the operational amplifier A1 is connected with one end of the resistor R3 and one end of the resistor R4, the inverting terminal of the operational amplifier A1 is connected with one end of the resistor R1 and one end of the resistor R2, the other end of the resistor R3 is connected with the VIN+ connection terminal, the other end of the resistor R1 is connected with the VIN- connection terminal, the other end of the resistor R2 and the output terminal of the operational amplifier A1 are connected with each other to form a current detection amplifier current detection amplifier output terminal OUT, and the other end of the resistor R4 is connected with the reference connection terminal REF.

6. The wide-range high-adaptability power conversion circuit according to claim 5, characterized by: The resistor R4 is configured as a reference resistor R0, an adjusting resistor string, and a pre-adjusting resistor R6, wherein, The adjusting resistor string comprises m+1 adjusting resistors connected in series, one end of the first adjusting resistor in series forms a first end of the adjusting resistor string, one end of the last adjusting resistor in series forms a second end of the adjusting resistor string, the resistance values of the m+1 adjusting resistors increase in equal ratio along the series direction from the first adjusting resistor to the last adjusting resistor, and each adjusting resistor is connected in parallel with an adjusting fuse; One end of the reference resistor R0 is connected with one end of the pre-adjusting resistor R6 and the first end of the adjusting resistor string, the other end of the reference resistor R0 is connected with the resistor R3 and the non-inverting terminal of the operational amplifier A1, the other end of the pre-adjusting resistor R6 is connected with the adjusting test reference connection terminal REF_test, and the second end of the adjusting resistor string is connected with the reference connection terminal REF. When configuring the common-mode rejection ratio of the current detection amplifier, the pre-adjusting resistor R6 is connected, and a pre-adjusting offset voltage under the connection of the pre-adjusting resistor R6 is measured; According to the pre-adjusting offset voltage and a target offset voltage, a target adjusting resistor value of the adjusting resistor string is determined, and the corresponding adjusting fuses in the adjusting resistor string are blown to obtain an actual adjusting resistor value matched with the target adjusting resistor value.

7. The wide-range high-adaptive power conversion circuit according to claim 6, characterized by: The common ratio of the resistance values of adjacent adjusting resistors in the adjusting resistor string is two, the reference resistor R0 is smaller than the resistor R2, and the resistance value of the pre-adjusting resistor R6 is configured as the resistance value corresponding to the middle adjusting resistor in the adjusting resistor string.

Images