A MMC half-full bridge submodule topology

Abstract

The present invention provides an MMC semi-full bridge submodule topology, and the present invention relates to the technical field of modular multi-level converters. The present invention improves the connection mode between the internal switch device and the capacitor of the SFBSM by adding a small amount of power devices, and proposes a semi-full bridge submodule topology structure. The improved ISFBSM has the capabilities of DC fault ride-through, capacitor voltage balance and negative level output. The present invention proposes an improved semi-full bridge submodule topology structure with DC fault ride-through, capacitor voltage self-balance and negative level output capabilities. By adding a fast fault clearing module, the DC fault clearing speed of the SFBSM is doubled, the number of output levels is increased, and the control flexibility of the system is improved. In addition, combined with the characteristics of the submodule capacitors running in parallel, the ISFBSM can be independent of additional control means, and the problem of submodule capacitor voltage balance can be solved simply through the hardware topology structure.

Description

Technical Field

[0001] The invention relates to the technical field of modular multi-level converters, and in particular to an MMC semi-full bridge submodule topology. Background Art

[0002] The greatest advantages of modular multilevel converters (MMCs) are their highly modular topology, excellent harmonic characteristics, and efficient energy conversion. However, MMCs based solely on half-bridge submodules do not have the ability to ride through DC faults. How to design an MMC submodule topology that can effectively ride through DC faults is an urgent problem that needs to be solved.

[0003] Zhang Jianpo, Zhao Chengyong, Sun Haifeng, Huang Xiaoming, Lu Yi, Qiu Peng. Improved topology of modular multilevel converter and its application. A series-connected double sub-module (SDSM) topology is proposed. During the DC fault clearing process, the SDSM ensures the stable series connection of its two internal capacitors, has strong DC fault clearing capability, and low system investment and operation cost. Xue Shimin, Cui Miao, Lian Jie, Fan Boyang, Qi Jinlong. A new sub-module topology with DC fault self-clearing capability. Based on the SDSM, an improved reverse series double sub-module topology is proposed. This topology does not require external power devices, reducing the loss of the system during normal operation. Wang Chen, Tan Kaidong, Wang Yi, Guo Hanchen, Tao Jianye. MMC oblique connection full bridge sub-module topology with DC fault clearing and self-equalizing capability. A topology structure of oblique connection full bridge sub-module (OCFBSM) with both capacitor voltage self-equalizing and DC fault ride-through capability is proposed. Under normal operation, OCFBSM realizes the sub-module 2u by changing the three connection modes of two capacitors in series, parallel and bypass in the sub-module. c 、u cIn addition, the back electromotive force provided by the capacitor voltage of OCFBSM can effectively clear the short-circuit fault on the DC side of the system, but the number of internal switching devices is large, the system hardware cost is expensive, and the control is cumbersome. K.Ilves, L.Bessegato, L.Harnefors, S.Norrga and H..-P.Nee, "Semi-full-bridge submodule for modular multilevel converters," 2015 9th International Conference on Power Electronics and ECCE Asia proposed a semi-full-bridge submodule topology (Semi-full-bridge sub-module, SFBSM) structure, which is the same as OCFBSM. It can realize the self-balancing of the submodule capacitor voltage through the existence of the parallel state and has the ability to output negative level, but the DC fault crossing speed is slow. Therefore, how to speed up the DC fault clearing speed of the original topology structure on the basis of adding a small number of power devices is of great significance to the design of new submodule topology of MMC. Summary of the invention

[0004] The present invention improves the connection mode between the internal switch device and the capacitor of the SFBSM by adding a small amount of power devices, and proposes an improved semi-full-bridge sub-module (ISFBSM), which doubles the DC fault clearing speed of the SFBSM. At the same time, the improved ISFBSM has the capabilities of DC fault ride-through, capacitor voltage balancing and negative level output. The present invention provides an MMC semi-full-bridge sub-module topology, and the specific scheme is as follows:

[0005] An MMC semi-full bridge submodule, comprising: a switch tube T1, a switch tube T2, a switch tube T3, a switch tube T4, a switch tube T5, a switch tube T6, a switch tube T7, a switch tube T8, a capacitor C1, a capacitor C2, a diode D1, a diode D2, a diode D3, a diode D4, a diode D5, a diode D6, a diode D7, a diode D8 and a diode D9;

[0006] The switch tube T1 is connected in parallel with the diode D1, the switch tube T2 is connected in parallel with the diode D2, the switch tube T3 is connected in parallel with the diode D3, the switch tube T4 is connected in parallel with the diode D4, the switch tube T5 is connected in parallel with the diode D5, the switch tube T6 is connected in parallel with the diode D6, the switch tube T7 is connected in parallel with the diode D7, the switch tube T8 is connected in series with the diode D9, and the switch tube T8, the diode D9 and the diode D8 are connected in parallel;

[0007] One end of the switch tube T1 and the diode D1 connected in parallel is connected to one end of the switch tube T2 and the diode D2 connected in parallel, the other end of the switch tube T1 and the diode D1 connected in parallel is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to the other end of the switch tube T2 and the diode D2 connected in parallel, and one end of the capacitor C1 is connected to one end of the switch tube T3 and the diode D3 connected in parallel;

[0008] The other end of the capacitor C1 is connected to one end of the switch tube T8, the diode D9 and the diode D8 in parallel, the other end of the switch tube T3 and the diode D3 in parallel is connected to one end of the switch tube T4 and the diode D4 in parallel, and the other end of the switch tube T4 and the diode D4 in parallel is connected to the other end of the switch tube T8, the diode D9 and the diode D8 in parallel;

[0009] The other end of the switch tube T4 and the diode D4 connected in parallel is connected to one end of the switch tube T5 and the diode D5 connected in parallel, the other end of the switch tube T5 and the diode D5 connected in parallel is connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to one end of the switch tube T7 and the diode D7 connected in parallel, the other end of the switch tube T7 and the diode D7 connected in parallel is connected to one end of the switch tube T6 and the diode D6 connected in parallel, and the other end of the switch tube T6 and the diode D6 connected in parallel is connected to one end of the capacitor C2.

[0010] Furthermore, it also includes a switch tube T9, a diode D 10 and diode D 11 , the switch tube T9 and the diode D 11 Series connection, switch tube T9, diode D 11 and diode D 10 in parallel;

[0011] Switch tube T9, diode D 11 and diode D 10 One end of the parallel connection is connected to the switch tube T4 and the other end of the parallel connection of the diode D4. The switch tube T9 and the diode D 11 and diode D 10 One end of the parallel connection is connected to the other end of capacitor C2.

[0012] Furthermore, when the switch tube T8 and the switch tube T9 are closed, the current flows in both directions; when the switch tube T8 and the switch tube T9 are turned off, the current only flows through the branch where the single diode is located.

[0013] Furthermore, in the negative level output state, the output is -2u c , increasing the number of output levels.

[0014] Furthermore, by cutting off the flow path of the reverse current, two capacitors are connected in series to the fault circuit, and the back electromotive force provided by the capacitors is increased, thereby increasing the speed of clearing the DC fault.

[0015] Furthermore, the working status of the MMC half-full bridge submodule includes:

[0016] State 1: C1 and C2 are connected in series, T1, T4, T6, T8, and T9 are closed, and the output voltage is 2u c ;

[0017] State 2: C1 and C2 are connected in parallel, T1, T3, T5, T6, T8, and T9 are closed, and the output voltage is u c ;

[0018] State 3: C1 is switched on alone, T1, T5, T6, and T8 are closed, and the output voltage is u c ;

[0019] State 4: C2 is switched on alone, T1, T3, T6, and T9 are closed, and the output voltage is u c ;

[0020] State 5: C1 is negatively input alone, T2, T3, T7, T9 are closed, and the output voltage is -u c ;

[0021] State 6: C2 is negatively input alone, T2, T5, T7, T8 are closed, and the output voltage is -u c ;

[0022] State 7: C1 and C2 are connected in parallel and negative input, T2, T3, T5, T7, T8, and T9 are closed, and the output voltage is -u c ;

[0023] State 8: C1 and C2 are connected in series with negative input, T2, T3, T4, T5, and T7 are closed, and the output voltage is -2u c ;

[0024] State 9: State 1 is cut off, C1 and C2 are bypassed, T1, T3, T7, and T9 are closed, and the output voltage is 0;

[0025] State 10: State 2 is cut off, C1 and C2 are bypassed, T2, T5, T6, and T8 are closed, and the output voltage is 0;

[0026] State 11: Locked state, T1, T2, T3, T4, T5, T6, T7, T8, T9 are all turned off. sm >0, C1 and C2 are connected in series to the fault current loop, and the output voltage is 2u c ; when i sm <0, C1 and C2 are connected in reverse series to the fault current loop, and the output voltage is -2u c .

[0027] Beneficial effects:

[0028] The present invention proposes an improved semi-full bridge submodule topology structure with DC fault ride-through, capacitor voltage self-balancing and negative level output capabilities. By adding a fast fault clearing module, the DC fault clearing speed of SFBSM is doubled, and ISFBSM can output -2u c , -u c ,0,u c , 2u c Five levels increase the number of output levels and improve the control flexibility of the system. In addition, combined with the characteristics of parallel operation of sub-module capacitors, ISFBSM does not rely on additional control means and can solve the problem of sub-module capacitor voltage balance simply through hardware topology structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 To improve the topology diagram;

[0030] Figure 2 It is the current path diagram under each state of ISFBSM;

[0031] Figure 3 This is the simulation result diagram of the negative level output state of ISFBSM;

[0032] Figure 4 This is the simulation result diagram of ISFBSM DC fault ride-through. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] Combination Figures 1 to 4 As shown, the present invention provides an MMC semi-full bridge submodule topology, including: switch tube T1, switch tube T2, switch tube T3, switch tube T4, switch tube T5, switch tube T6, switch tube T7, switch tube T8, switch tube T9, capacitor C1, capacitor C2, diode D1, diode D2, diode D3, diode D4, diode D5, diode D6, diode D7, diode D8, diode D9, diode D 10 and diode D 11 ;

[0035] The switch tube T1 is connected in parallel with the diode D1, the switch tube T2 is connected in parallel with the diode D2, the switch tube T3 is connected in parallel with the diode D3, the switch tube T4 is connected in parallel with the diode D4, the switch tube T5 is connected in parallel with the diode D5, the switch tube T6 is connected in parallel with the diode D6, the switch tube T7 is connected in parallel with the diode D7, the switch tube T8 is connected in series with the diode D9, the switch tube T8, the diode D9 and the diode D8 are connected in parallel; the switch tube T9 and the diode D 11 Series connection, switch tube T9, diode D 11 and diode D 10 in parallel;

[0036] One end of the switch tube T1 and the diode D1 connected in parallel is connected to one end of the switch tube T2 and the diode D2 connected in parallel, the other end of the switch tube T1 and the diode D1 connected in parallel is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to the other end of the switch tube T2 and the diode D2 connected in parallel, and one end of the capacitor C1 is connected to one end of the switch tube T3 and the diode D3 connected in parallel;

[0037] The other end of the capacitor C1 is connected to one end of the switch tube T8, the diode D9 and the diode D8 in parallel, the other end of the switch tube T3 and the diode D3 in parallel is connected to one end of the switch tube T4 and the diode D4 in parallel, and the other end of the switch tube T4 and the diode D4 in parallel is connected to the other end of the switch tube T8, the diode D9 and the diode D8 in parallel;

[0038] The other end of the parallel connection of the switch tube T4 and the diode D4 is connected to one end of the parallel connection of the switch tube T5 and the diode D5, the other end of the parallel connection of the switch tube T5 and the diode D5 is connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to one end of the parallel connection of the switch tube T7 and the diode D7, the other end of the parallel connection of the switch tube T7 and the diode D7 is connected to one end of the parallel connection of the switch tube T6 and the diode D6, and the other end of the parallel connection of the switch tube T6 and the diode D6 is connected to one end of the capacitor C2. 11 and diode D 10 One end of the parallel connection is connected to the switch tube T4 and the other end of the parallel connection of the diode D4. The switch tube T9 and the diode D 11 and diode D 10 One end of the parallel connection is connected to the other end of capacitor C2.

[0039] Figure 1 (a) is the topological structure of SFBSM. Figure 2 (b) The ISFBSM topology can be formed by connecting a fast fault clearing module (FFCM) in series at the position shown. The FFCM consists of an IGBT and two diodes. When the IGBT is closed, the FFCM is equivalent to a wire, and the current can flow in both directions; when the IGBT is turned off, the current only flows through the branch where the single diode is located. Figure 1The red and blue dotted lines in the figure are the current flow paths when the SFBSM and ISFBSM are locked. After analysis, it can be seen that when all the submodules in the MMC are locked, the two capacitors in the SFBSM are connected in reverse parallel to the fault circuit. In the ISFBSM, due to the connection of the FFCM, the flow path of the reverse current is cut off, so that the two capacitors are connected in series to the fault circuit. Due to the increase in the back electromotive force provided by the capacitor, the DC fault clearing speed is increased. At the same time, in the negative level output state, the ISFBSM can output -2u c , while SFBSM can only output -u c ,The access of FFCM increases the number of SFBSM output levels and improves the control ,flexibility of the system.

[0040] ISFBSM's working status can be divided into the following 7 types:

[0041] State 1: C1 and C2 are connected in series, T1, T4, T6, T8, and T9 are closed, and the output voltage of ISFBSM is 2u c .

[0042] State 2: C1 and C2 are connected in parallel, T1, T3, T5, T6, T8, and T9 are closed, and the output voltage of ISFBSM is u c .

[0043] State 3: C1 is switched on alone, T1, T5, T6, and T8 are closed, and the output voltage of ISFBSM is u c .

[0044] State 4: C2 is switched on alone, T1, T3, T6, and T9 are closed, and the output voltage of ISFBSM is u c .

[0045] State 5: C1 is negatively input, T2, T3, T7, T9 are closed, and the output voltage of ISFBSM is -u c .

[0046] State 6: C2 is negatively input, T2, T5, T7, T8 are closed, and the output voltage of ISFBSM is -u c .

[0047] State 7: C1 and C2 are connected in parallel and negative input, T2, T3, T5, T7, T8, and T9 are closed, and the output voltage of ISFBSM is -u c .

[0048] State 8: C1 and C2 are connected in series and negative input, T2, T3, T4, T5, and T7 are closed, and the output voltage of ISFBSM is -2u c .

[0049] State 9: State 1 is cut off, C1 and C2 are bypassed, T1, T3, T7, and T9 are closed, and the ISFBSM output voltage is 0.

[0050] State 10: State 2 is cut off, C1 and C2 are bypassed, T2, T5, T6, and T8 are closed, and the ISFBSM output voltage is 0.

[0051] State 11: Locked state, T1, T2, T3, T4, T5, T6, T7, T8, T9 are all turned off. sm >0, C1 and C2 are connected in series to the fault current loop, and the output voltage of ISFBSM is 2u c ; when i sm <0, C1 and C2 are connected in reverse series to the fault current loop, and the output voltage of ISFBSM is -2u c .

[0052] Working Principle of ISFBSM

[0053] In order to analyze the working principle of ISFBSM more intuitively, the ISFBSM switch state table shown in Table 1 is listed and the Figure 2 The current path of the ISFBSM in each state is shown. Assume that the capacitor voltage is u c .

[0054] Table 1 ISFBSM switch status table

[0055]

[0056] ISFBSM Negative Level Output Characteristics Example

[0057] In order to verify the negative level output capability of the ISFBSM topology proposed in this paper, a three-phase ISFBSM-MMC and SFBSM-MMC rectifier simulation model was built on MATLAB / Simulink. c With -2u c The ISFBSM switches between states 7, 8 and 10. The modulation strategy uses carrier phase shift modulation, the simulation duration is 1s, and the simulation parameters are shown in Table 2:

[0058] Table 2 MMC simulation parameters

[0059]

[0060] Figure 3(a) and (b) are the output voltage and current waveforms of the ISFBSM-MMC AC side, respectively. (d) and (e) are the output voltage and current waveforms of the SFBSM-MMC AC side, respectively. It can be seen that the voltage and current amplitudes of the AC side are about 5800V and 220A. Since the ISFBSM-MMC can output -2u c The AC side output voltage waveform is approximately a five-level step wave, and SFBSM-MMC can only output -u c level, so the AC side voltage is approximately a three-level step wave. (g) and (h) are the total harmonic distortion analysis of the output voltage of the ISFBSM-MMC and SFBSM-MMC AC side, respectively. The THD of the ISFBSM-MMC AC side voltage is 18.63%, while the THD of the SFBSM-MMC is 37.33%, and the total harmonic distortion rate has dropped by about half. This is due to the increase in the number of output levels of the improved ISFBSM, and the step wave of the AC side output voltage is closer to a sine wave. (c) and (f) are the waveforms of the ISFBSM DC side output voltage and the submodule capacitor voltage, respectively, and their values ​​fluctuate around -12800V and -3200V. The above simulation analysis can prove that the ISFBSM-MMC can operate stably in the negative level output state, verifying the effectiveness of the negative level output state.

[0061] ISFBSM DC Fault Ride-Through Characteristics Example

[0062] To verify the DC fault ride-through characteristics of ISFBSM, the simulation model and parameters are the same as those of the negative level output simulation. ISFBSM operates in state 1, state 2 and state 9. A DC bipolar short-circuit fault occurs in the system at 0.7s. After the system detects the fault, it locks all IGBTs in the MMC after 2ms to complete the DC fault ride-through.

[0063] Figure 4(a) and (b) are the output voltage and current waveforms of the ISFBSM-MMC AC side. In normal operation, their values ​​are about 5800V and 220A. At 0.7s, a DC bipolar short circuit fault occurs in the system. At 0.702s, all IGBTs are locked, the AC side voltage becomes a standard sine wave, and the AC side current decays to 0A within 3ms. (c), (d) and (e) are the voltage and current waveforms of the ISFBSM-MMC DC side. In normal operation, the DC side voltage and current fluctuate around 12800V and 128A, respectively. After the fault occurs at 0.7s, the DC side voltage instantly decreases to 0V, and the DC side current rises rapidly. After all IGBTs are locked at 0.702s, the DC side current drops rapidly to 0A within 3ms, and the system completes the DC fault ride-through. (f) is the DC side current waveform of the SFBSM during the DC fault ride-through process. It can be seen that the SFBSM completes the DC fault ride-through within 6ms. The improved ISFBSM DC fault ride-through speed has increased by about one time. (g) and (h) are the voltage waveforms of the four capacitors in the upper bridge arm of phase a of the ISFBSM under normal operating conditions. Their values ​​fluctuate around 3200V. After all IGBTs are locked at 0.702s, the capacitors of the ISFBSM-MMC factor module are reversely put into the fault circuit, and the capacitors are charged to around the rated value. Due to the existence of the parallel state, the voltages of the two capacitors in the same ISFBSM are basically consistent. (i) is the capacitor voltage waveform when the ISFBSM operates in state 1, state 3, and state 9. It can be seen that the capacitor voltages of the four submodules are slightly different because they are not running in parallel. The above analysis proves the effectiveness of the ISFBSM capacitor voltage self-balancing and DC fault ride-through capability.

[0064] In summary, the present invention proposes an ISFBSM topology structure with DC fault ride-through, submodule capacitor voltage balancing and negative level output capabilities by connecting a fast fault clearing module to the SFBSM. According to the simulation results, the ISFBSM-MMC can operate stably under the negative level output state. When a DC side short circuit fault occurs in the system, the topology completes the DC fault ride-through in about 3ms. Compared with the unimproved SFBSM-MMC, the DC fault ride-through speed is accelerated, the number of output levels is increased, and the system control flexibility is improved.

[0065] The above is a detailed introduction to an MMC half-full bridge submodule topology provided by the present invention. The present invention uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. An MMC half-full bridge submodule, characterized in that: include: Switching tube T 1. Switching tube T 2. Switching tube T 3. Switching tube T 4. Switching tube T 5. Switching tube T 6. Switching tube T 7. Switching tube T 8. Capacitor C 1. Capacitor C 2. Diode D 1. Diode D 2. Diode D 3. Diode D 4. Diode D 5. Diode D 6. Diode D 7. Diode D 8 and diode D 9; Switching tube T 1 and diode D 1 in parallel, the switch tube T 2 and diode D 2 parallel, switch tube T 3 and diode D 3 parallel, switch tube T 4 and diode D 4 parallel, switch tube T 5 and diode D 5 parallel, switch tube T 6 and diode D 6 parallel, switch tube T 7 and diode D 7 in parallel, the switch tube T 8 and diode D 9 series connected, fast fault clearing module switch T 8 collector and diode D 9 is connected to the cathode of the diode D 9's positive pole and diode D 8 is connected to the cathode of diode D8 and T The emitter of 8 is connected; Switching tube T 1 and diode D 1. One end of the parallel connection is connected to the switch tube T 2 and diode D 2 One end of the parallel connection, the switch tube T 1 and diode D 1 The other end of the parallel connection is connected to the capacitor C 1, the capacitor C The other end of 1 is connected to the switch tube T 2 and diode D 2 The other end of the parallel connection, capacitor C One end of 1 is connected to the switch tube T 3 and diode D 3 one end of parallel connection; capacitance C The other end of 1 is connected to one end of the fast fault clearing module, and the switch tube T 3 and diode D 3. The other end of the parallel connection is connected to the switch tube T 4 and diode D 4 One end of the parallel connection, the switch tube T 4 and diode D 4 The other end of the parallel connection is connected to the other end of the fast fault clearing module; Switching tube T 4 and diode D 4 The other end of the parallel connection is connected to the switch tube T 5 and diode D 5 One end of the parallel connection, the switch tube T 5 and diode D 5. Connect the other end of the capacitor in parallel C 2, one end of the capacitor C The other end of 2 is connected to the switch tube T 7 and diode D 7 One end of the parallel connection, the switch tube T 7 and diode D 7 The other end of the parallel connection is connected to the switch tube T 6 and diode D 6 One end of the parallel connection, the switch tube T 6 and diode D 6 The other end of the parallel connection is connected to the capacitor C 2 one end; Also includes switch tube T 9. Diode D 10 and diode D 11 , the switch tube T 9 collector and diode D 11 The negative pole of the switch tube is connected T 9. Diode D 11 Connect in series and then with a diode D 10 In parallel, the diode D 11 The positive electrode and the diode D 10 The negative pole is connected; Switching tube T 9. Diode D 11 and diode D 10 One end of the parallel connection is connected to the switch tube T 4 and diode D 4 One end of the parallel connection, the switch tube T 9. Diode D 11 Connect in series and then with a diode D 10 Connect one end of the capacitor in parallel C 2 the other end.

2. An MMC half-full bridge submodule according to claim 1, characterized in that: When the switch T 8 and switch tube T 9 is closed, the current flows in both directions; when the switch tube T 8 and switch tube T 9 When turned off, the current only flows through the branch where the single diode is located.

3. An MMC half-full bridge submodule according to claim 2, characterized in that: In the negative level output state, the output is -2 u c , increasing the number of output levels.

4. The MMC half-full bridge submodule according to claim 3, characterized in that: By cutting off the flow path of the reverse current, two capacitors are connected in series to the fault circuit. The capacitors provide an increase in back electromotive force, which increases the speed of clearing the DC fault.

5. The MMC half-full bridge submodule according to claim 4, characterized in that: The working status of the MMC half-full bridge submodule includes: State 1: C 1. C 2 series input, T 1. T 4. T 6. T 8. T 9 is closed, the output voltage is 2 u c ; State 2: C 1. C 2 parallel input, T 1. T 3. T 5. T 6. T 8. T 9 is closed, the output voltage is u c ; State 3: C 1 Invest alone, T 1. T 5. T 6. T 8 is closed, the output voltage is u c ; State 4: C 2 Invest alone, T 1. T 3. T 6. T 9 is closed, the output voltage is u c ; State 5: C 1 negative input alone, T 2. T 3. T 7. T 9 is closed, the output voltage is - u c ; State 6: C 2 single negative input, T 2. T 5. T 7. T 8 is closed, the output voltage is - u c ; State 7: C 1. C 2 parallel negative inputs, T 2. T 3. T 5. T 7. T 8. T 9 is closed, the output voltage is - u c ; State 8: C 1. C 2 series connected negative input, T 2. T 3. T 4. T 5. T 7 is closed, the output voltage is -2 u c ; State 9: Remove state 1, C 1. C 2 are bypassed, T 1. T 3. T 7. T 9 is closed, the output voltage is 0; State 10: Remove state 2, C 1. C 2 are bypassed, T 2. T 5. T 6. T 8 is closed, the output voltage is 0; State 11: Locked state, T 1. T 2. T 3. T 4. T 5. T 6. T 7. T 8. T 9 are all off, when i sm >0, C 1. C 2 are connected in series to the fault current loop, and the output voltage is 2 u c ;when i sm <0, C 1. C 2 reverse series connected to the fault current loop, the output voltage is -2 u c .

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