Circuit devices and oscillators

Abstract

A circuit arrangement and an oscillator are provided, capable of suppressing the effects of the amplifier during oscillator inspection. The circuit arrangement includes: a first terminal connected to one end of the oscillator; a second terminal connected to the other end of the oscillator; an amplifying element that amplifies the signal from the first terminal and outputs it to the second terminal; a first resistive element disposed on the signal path between the input and output nodes of the amplifying element; a capacitive element disposed on the signal path between the first terminal and the input node; and a first switching element that switches the electrical connection between the input node and ground.

Description

Technical Field

[0001] This invention relates to circuit devices and oscillators. Background Technology

[0002] Quartz oscillators (piezoelectric oscillators) and MEMS (Micro Electro Mechanical Systems) oscillators undergo overdrive checks and drive level checks to examine their characteristics. In the overdrive check, a large current, voltage, or electrical AC signal is applied to drive the oscillator, and the frequency characteristics of the oscillator are checked. In the drive level check, a signal that causes the large current, voltage, or electrical AC signal to increase or decrease in stages is applied to drive the oscillator, and the changes in the frequency characteristics of the oscillator are checked.

[0003] Patent document 1 discloses an oscillator that has an internal switching circuit and can be checked using external terminals.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2015-088930

[0005] However, in the oscillator described in Patent Document 1, when the oscillator is being inspected, if the inspection signal is input to the amplifier via the feedback resistor and the conditions for the amplifier to operate are met, it may affect the inspection of the oscillator. Summary of the Invention

[0006] One embodiment of the circuit device of the present invention includes: a first terminal connected to one end of an oscillator; a second terminal connected to the other end of the oscillator; an amplifying element that amplifies the signal from the first terminal and outputs it to the second terminal; a first resistive element disposed on the signal path between the input node and the output node of the amplifying element; a capacitive element disposed on the signal path between the first terminal and the input node; and a first switching element that switches the electrical connection between the input node and ground.

[0007] One embodiment of the oscillator of the present invention includes: one embodiment of the circuit arrangement; and the oscillator. Attached Figure Description

[0008] Figure 1 It is a 3D diagram of the oscillator.

[0009] Figure 2 yes Figure 1 A cross-sectional view of the oscillator.

[0010] Figure 3 It is a diagram showing the schematic structure of an oscillator.

[0011] Figure 4This is a diagram showing the schematic structure of the oscillation circuit in the first embodiment.

[0012] Figure 5 This is a flowchart illustrating an example of the steps used to inspect an oscillator.

[0013] Figure 6 This is a diagram showing an example of the signal waveform at the external terminals of the oscillator when the oscillator is being inspected.

[0014] Figure 7 This is a diagram showing the schematic structure of the oscillation circuit in the second embodiment.

[0015] Figure 8 This is a diagram showing the schematic structure of the oscillation circuit in the third embodiment.

[0016] Figure 9 This is a diagram showing the schematic structure of the oscillation circuit in the fourth embodiment.

[0017] Figure 10 This is a diagram showing the schematic structure of the oscillator circuit in Modified Example 1.

[0018] Figure 11 This is a diagram showing the schematic structure of the oscillator in Modified Example 2.

[0019] Label Explanation

[0020] 1: Oscillator; 2: Circuit device; 3: Vibrator; 3a: Excitation electrode; 3b: Excitation electrode; 4: Package; 5: Cover; 6: External terminal; 7: Storage chamber; 10: Oscillator circuit; 11: Reference voltage circuit; 12: Bias current generation circuit; 12a: Constant current source; 13: Capacitor circuit; 13a: Capacitor element; 14: Capacitor circuit; 14a: Capacitor element; 15: Variable capacitor circuit; 16: Variable capacitor circuit; 17: Variable capacitor circuit; 18: Variable capacitor circuit; 20: Output circuit; 21: Waveform shaping circuit ; 22: Frequency divider circuit; 23: Pre-buffer; 24: Output buffer; 25: Pre-buffer; 26: Output buffer; 30: Temperature sensor; 32: Temperature compensation circuit; 34: Frequency control circuit; 36: Logic circuit; 40: Power supply circuit; 50: Storage circuit; 51: Register; 52: Non-volatile memory; 71: First switching element; 72: Second switching element; 73: Third switching element; 74: Fourth switching element; 81: First resistive element; 82: Second resistive element; 101: Bipolar transistor; 1 02: Capacitor element; 103: Capacitor element; 111: Resistor element; 112: Duty cycle adjustment circuit; 121: MOS transistor; 122: MOS transistor; 123: Constant current source; 131-1~131-k: Capacitor element; 132-1~132-k: Switching element; 141-1~141-k: Capacitor element; 142-1~142-k: Switching element; 151: Capacitor element; 152-1~152-n: Variable capacitor element; 153-1~153-n: Capacitor element; 154: 161: Resistor; 162-1~162-n: Variable capacitor; 163-1~163-n: Capacitor; 164: Resistor; 171: Capacitor; 172-1~172-m: Variable capacitor; 173-1~173-m: Capacitor; 174: Resistor; 181: Capacitor; 182-1~182-m: Variable capacitor; 183-1~183-m: Capacitor; 184: Resistor; 201: Input node; 202: Output node. Detailed Implementation

[0021] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. The drawings are provided for ease of explanation. Furthermore, the embodiments described below do not unduly limit the scope of the invention as described in the claims. Also, not all structures described below are essential structural elements of the present invention.

[0022] 1. First Implementation Method

[0023] 1-1. Structure of an oscillator

[0024] Figure 1 and Figure 2 This is a diagram illustrating an example of the construction of the oscillator 1 in this embodiment. Figure 1 This is a 3D view of oscillator 1. Figure 2 yes Figure 1 AA sectional view.

[0025] like Figure 1 and Figure 2 As shown, the oscillator 1 includes a circuit device 2, an oscillator 3, a package 4, a cover 5, and multiple external terminals 6. In this embodiment, the oscillator 3 is a quartz oscillator using quartz as the substrate material, such as an AT-cut quartz oscillator or a tuning fork-type quartz oscillator. The oscillator 3 can also be a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro Electro Mechanical Systems) oscillator. In addition to quartz, the substrate material of the oscillator 3 can also be piezoelectric materials such as lithium tantalate, lithium niobate, or piezoelectric ceramics such as lead zirconate titanate, or silicon semiconductor materials. As the excitation means of the oscillator 3, excitation based on the piezoelectric effect can be used, or electrostatic drive based on Coulomb force can be used. In addition, in this embodiment, the circuit device 2 is implemented by a single-chip integrated circuit (IC). However, at least a part of the circuit device 2 can also be composed of discrete components.

[0026] Package 4 houses the circuit device 2 and the oscillator 3 within the same space. Specifically, a recess is provided on package 4, which is covered by a cover 5 to form a housing chamber 7. Inside package 4 or on the surface of the recess, there are provided for respectively housing the two terminals of circuit device 2 (specifically, described later). Figure 3 The circuit 2 (X1 and XO terminals) is electrically connected to the two excitation electrodes 3a and 3b of the oscillator 3 via wiring not shown. Additionally, wiring not shown is provided inside the package 4 or on the surface of a recess for electrically connecting each terminal of the circuit device 2 to each external terminal 6 provided on the bottom surface of the package 4. Furthermore, the package 4 is not limited to a structure that houses the circuit device 2 and the oscillator 3 in the same space. For example, it could be a so-called H-type package where the circuit device 2 is mounted on one side of the package substrate and the oscillator 3 is mounted on the other side.

[0027] The oscillator 3 has metallic excitation electrodes 3a and 3b on its front and back sides, respectively, and oscillates at a desired frequency corresponding to the shape and mass of the oscillator 3 containing the excitation electrodes 3a and 3b.

[0028] Figure 3 This is a functional block diagram of the oscillator in the first embodiment. (Example) Figure 3As shown, the oscillator 1 in this embodiment includes a circuit device 2 and an oscillator 3. The circuit device 2 has VDD, VSS, OUT, VC, XI, and XO terminals as external connection terminals. The VDD, VSS, OUT, and VC terminals are respectively connected to... Figure 2 The multiple external terminals 6 of the oscillator 1 shown are electrically connected, namely terminals T1, T2, T3 and T4.

[0029] The XI terminal is electrically connected to one end of the oscillator 3, and the XO terminal is electrically connected to the other end of the oscillator 3. The VSS terminal is electrically connected to ground via the T2 terminal. Additionally, the VSS terminal is electrically connected to the XI terminal via the second switching element 72. The VC terminal is electrically connected to the XO terminal via the third switching element 73.

[0030] The second switching element 72 is turned on or off according to the switching control data. The switching control data is supplied to the second switching element 72 from the logic circuit 36. The second switching element 72 switches the electrical connection between the XI terminal and the VSS terminal.

[0031] The third switching element 73 is turned on or off according to the switching control data. The switching control data is supplied to the third switching element 73 from the logic circuit 36. The third switching element 73 switches the electrical connection between the XO terminal and the VC terminal.

[0032] When the second switching element 72 is turned on, the XI terminal and the VSS terminal are connected; when the second switching element 72 is turned off, the XI terminal and the VSS terminal are not connected. When the third switching element 73 is turned on, the XO terminal and the VC terminal are connected; when the third switching element 73 is turned off, the XO terminal and the VC terminal are not connected.

[0033] The XI terminal connected to one end of the oscillator 3 is an example of the first terminal, and the XO terminal connected to the other end of the oscillator 3 is an example of the second terminal. The VSS terminal connected to ground is an example of the third terminal, and the VC terminal connected to the XO terminal is an example of the fourth terminal.

[0034] In this embodiment, the circuit device 2 includes an oscillation circuit 10, an output circuit 20, a temperature sensor 30, a temperature compensation circuit 32, a frequency control circuit 34, a logic circuit 36, a power supply circuit 40, a storage circuit 50, a second switching element 72, and a third switching element 73. Furthermore, the circuit device 2 may be configured to omit or modify a portion of these elements, or to add other elements.

[0035] The power supply circuit 40 generates various constant voltages based on the power supply voltage supplied from the outside via the T1 terminal and the VDD terminal, and supplies them to various circuits. For example, the power supply circuit 40 may also include multiple regulators that generate constant voltages based on the output voltage of the bandgap reference circuit.

[0036] The oscillation circuit 10 is electrically connected to the XI terminal and the XO terminal, and is the circuit that causes the oscillator 3 to oscillate. Specifically, the oscillation circuit 10 receives the signal output from the oscillator 3 via the XI terminal, amplifies the signal, and provides it to the oscillator 3 via the XO terminal.

[0037] Temperature sensor 30 detects the temperature of circuit device 2 and outputs a temperature signal corresponding to the voltage, for example, by using a circuit that utilizes the temperature characteristics of a bandgap reference circuit.

[0038] The temperature compensation circuit 32 generates a temperature compensation voltage Vcomp for correcting the frequency-temperature characteristics of the oscillation signal output from the oscillation circuit 10 based on the temperature signal output from the temperature sensor 30 and the temperature compensation data corresponding to the frequency-temperature characteristics of the oscillator 3, and provides this voltage to the oscillation circuit 10. The temperature compensation data is supplied from the logic circuit 36 ​​to the temperature compensation circuit 32.

[0039] The frequency control circuit 34 is supplied with a frequency control signal input from the T4 terminal via the VC terminal. Then, the frequency control circuit 34 generates a frequency control voltage Vafc for controlling the oscillation frequency of the oscillation circuit 10 based on the voltage level of the frequency control signal, and provides it to the oscillation circuit 10.

[0040] Through the temperature compensation voltage Vcomp, the oscillation signal OSCO output by the oscillation circuit 10 becomes a roughly constant frequency corresponding to the frequency control voltage Vafc at any temperature within the specified temperature range. The oscillation signal OSCO is input to the output circuit 20.

[0041] In this embodiment, the output circuit 20 includes a waveform shaping circuit 21, a frequency divider circuit 22, a pre-buffer 23, an output buffer 24, a pre-buffer 25, and an output buffer 26.

[0042] The waveform shaping circuit 21 buffers the oscillation signal OSCO output from the oscillation circuit 10 and outputs a rectangular wave clock signal CK1.

[0043] Frequency divider circuit 22 outputs clock signal CK2, obtained by dividing the clock signal CK1 output from waveform shaping circuit 21 by a division ratio corresponding to the division ratio data. The division ratio data is supplied to frequency divider circuit 22 from logic circuit 36. Additionally, when the division ratio is 1, frequency divider circuit 22 outputs a buffered clock signal CK2 from the clock signal output from waveform shaping circuit 21. The clock signal CK2 output from frequency divider circuit 22 is fed into pre-buffer 23 and pre-buffer 25.

[0044] The pre-buffer 23 outputs a buffered clock signal CK3 from the clock signal CK2 output from the frequency divider circuit 22. The pre-buffer 23 also functions as a level shifter, outputting a clock signal CK3 with a voltage level that matches the input voltage level of the output buffer 24.

[0045] The output buffer 24 buffers the clock signal CK3 output from the pre-buffer 23 and outputs the clock signal of the CMOS output waveform.

[0046] The pre-buffer 25 outputs a buffered clock signal CK4, which is the clock signal CK2 output from the frequency divider circuit 22.

[0047] The output buffer 26 converts the clock signal CK4 output from the pre-buffer 25 into a clipped sine wave clock signal and outputs it.

[0048] In this embodiment, the output terminals of output buffer 24, output buffer 26, and OUT terminal are electrically connected. Furthermore, based on the clock selection data, at least one of the output terminals of output buffer 24 and output buffer 26 becomes high impedance. Clock selection data is supplied from logic circuit 36 ​​to output buffer 24 and output buffer 26.

[0049] When only the output terminal of output buffer 26 is at high impedance, the clock signal of the CMOS output waveform output from output buffer 24 is output to the outside of oscillator 1 as clock signal CKO via the OUT terminal and the T3 terminal. Alternatively, when only the output terminal of output buffer 24 is at high impedance, the clock signal of the clipped sine wave output from output buffer 26 is output to the outside of oscillator 1 as clock signal CKO via the OUT terminal and the T3 terminal.

[0050] Logic circuit 36 ​​controls the operation of each circuit. Specifically, logic circuit 36 ​​sets the operating mode of oscillator 1 or circuit device 2 to one of multiple modes, including external communication mode, normal operating mode, and various check modes, based on the control signal input to the terminals of circuit device 2, and performs control corresponding to the set operating mode. In this embodiment, if logic circuit 36 ​​inputs a control signal of a specified mode from VC terminal within a specified period from the start of supplying power voltage to VDD terminal, it sets the operating mode to external communication mode after the specified period has elapsed. For example, logic circuit 36 ​​can define the specified period as the period from when the oscillator 3 starts oscillating due to the supply of power voltage and when the oscillation stabilizes, or it can count the number of pulses of the oscillation signal, and determine that the specified period has elapsed if the count value reaches a specified value. Alternatively, logic circuit 36 ​​can measure the specified period based on the output signal of the RC time constant circuit that starts operating due to the supply of power voltage.

[0051] In external communication mode, logic circuit 36 ​​sets the outputs of output buffers 24 and 26 to high-impedance clock selection data, and sets the second switch element 72 and the third switch element 73 to open switch control data. In external communication mode, serial clock signals and serial data signals are synchronously input from the VC terminal and the OUT terminal. Logic circuit 36, in external communication mode, for example according to I... 2 The C (Inter-Integrated Circuit) bus standard samples the serial data signal at each edge of the serial clock signal. Furthermore, the logic circuit 36 ​​performs processing such as setting the operating mode, setting clock selection data and switch control data for each operating mode, and reading and writing data to register 51 or non-volatile memory 52 based on the sampled commands and data. In this embodiment, the logic circuit 36 ​​is, for example, an I... 2 It can function as an interface circuit for 2-wire buses such as the C (Inter-Integrated Circuit) bus, but it can also function as an interface circuit for 3-wire or 4-wire buses such as the SPI (Serial Peripheral Interface) bus.

[0052] For example, when logic circuit 36 ​​samples the normal operating mode setting command in external communication mode, it switches the operating mode from external communication mode to normal operating mode. In normal operating mode, logic circuit 36 ​​outputs only the clock selection data with high impedance for either output buffer 24 or 26, and outputs switch control data with both second switch element 72 and third switch element 73 set to open, thus making second switch element 72 and third switch element 73 open. As a result, the XI terminal and VSS terminal are electrically disconnected, and the XO terminal and third switch element 73 are electrically disconnected. Consequently, a clock signal CKO with a frequency corresponding to the voltage of the VC terminal is output to the outside from the OUT terminal via the T3 terminal. Furthermore, normal operating mode is an example of mode 1.

[0053] Furthermore, if the logic circuit 36 ​​does not input a control signal of the specified mode from the VC terminal within a specified period starting from the supply of the power supply voltage, it will not set the operating mode to the external communication mode after the specified period has elapsed, but will directly set it to the normal operating mode.

[0054] When logic circuit 36 ​​samples the oscillator check mode setting command in external communication mode, it switches the operating mode from external communication mode to oscillator check mode. In oscillator check mode, logic circuit 36 ​​outputs switch control data that sets both the second switch element 72 and the third switch element 73 to be on, thus turning on the second switch element 72 and the third switch element 73. As a result, the XI terminal is electrically connected to the VSS terminal via the second switch element 72, and the XO terminal is electrically connected to the VC terminal via the third switch element 73. As a result, the external device of oscillator 1 can supply signals for oscillating oscillator 3 from the T2 terminal connected to the VSS terminal and the T4 terminal connected to the VC terminal. Therefore, the check device, as an external device, can perform overdrive checks to check the characteristics by supplying a large amplitude check signal to oscillator 3, and drive level checks to check the excitation level dependence of oscillator 3. In addition, oscillator check mode is an example of the second mode.

[0055] The storage circuit 50 stores various types of information and includes a register 51 and a non-volatile memory 52. ​​The non-volatile memory 52 may be, for example, a MONOS (Metal Oxide Nitride Oxide Silicon) type memory or an EEPROM (Electrically Erasable Programmable Read-Only Memory). During the manufacturing process of the oscillator 1, various information such as temperature compensation data, frequency division ratio data, and clock selection data are stored in the non-volatile memory 52. ​​Furthermore, when the oscillator 1 is powered on, the various types of information stored in the non-volatile memory 52 are transferred to the register 51, and the various types of information stored in the register 51 are appropriately supplied to various circuits via the logic circuit 36.

[0056] 1-2. Structure of an oscillating circuit

[0057] Figure 4 This is a diagram illustrating an example of the structure of the oscillator circuit 10. For example... Figure 4 As shown, the oscillation circuit 10 includes a reference voltage circuit 11, a bias current generation circuit 12, capacitor circuits 13 and 14, variable capacitor circuits 15, 16, 17, and 18, a first switching element 71, a first resistive element 81, a bipolar transistor 101, and capacitor elements 102 and 103. Alternatively, the oscillation circuit 10 of this embodiment may be configured by omitting or modifying some of these elements, or by adding other elements.

[0058] The reference voltage circuit 11 includes multiple resistive elements 111 and a duty cycle adjustment circuit 112. The multiple resistive elements 111 are connected in series between the supply line of the power supply voltage VDDL and ground. The power supply voltage VDDL is supplied by the power supply circuit 40. The reference voltage circuit 11 outputs at least a portion of the multiple voltages obtained by dividing the voltage between the power supply voltage VDDL and the ground voltage using the multiple resistive elements 111, as n reference voltages VcgC[n:1] and m reference voltages VcgA[m:1]. n and m are integers greater than or equal to 2. The integers n and m can be the same or different. Furthermore, at least one of the n reference voltages VcgC[n:1] and at least one of the m reference voltages VcgA[m:1] can be the same. The reference voltages VcgC[n:1] are supplied to variable capacitor circuits 15 and 16. Additionally, the reference voltages VcgA[m:1] are supplied to variable capacitor circuits 17 and 18.

[0059] The duty cycle adjustment circuit 112 selects any one of the multiple voltages divided by multiple resistor elements 111, based on the duty cycle adjustment data, as the bias voltage Vrefb output. The duty cycle adjustment data is stored in non-volatile memory 52, and the logic circuit 36 ​​provides the duty cycle adjustment data transferred from non-volatile memory 52 to register 51 to the duty cycle adjustment circuit 112.

[0060] The bias current generation circuit 12 includes two P-channel MOS (Metal Oxide Semiconductor) transistors 121 and 122 and a constant current source 123.

[0061] The gate and drain of MOS transistor 121 are electrically connected, and its source is supplied with the power supply voltage VDDL. The gate of MOS transistor 122 is electrically connected to the gate of MOS transistor 121, its source is supplied with the power supply voltage VDDL, and its drain is electrically connected to the collector of bipolar transistor 101, which serves as an amplification element. The gate and drain of MOS transistor 121 are electrically connected to one end of constant current source 123. The other end of constant current source 123 is grounded.

[0062] In the bias current generation circuit 12 configured as described above, the reference current Iref flowing through the constant current source 123 is multiplied by a predetermined current through the current mirror circuit composed of MOS transistors 121 and 122, flowing between the source and drain of MOS transistor 122. This current is supplied to bipolar transistor 101 as the bias current Ibias.

[0063] One end of capacitor element 102 is electrically connected to the base of bipolar transistor 101, and the other end is electrically connected to one end of oscillator 3 via XI terminal. That is, capacitor element 102 is disposed on the signal path between XI terminal and the base of bipolar transistor 101. For example, capacitor element 102 functions as a DC coupling capacitor.

[0064] One end of capacitor element 103 is electrically connected to the gate of MOS transistor 121 and the gate of MOS transistor 122, and the other end is electrically connected to the base of bipolar transistor 101.

[0065] The base of bipolar transistor 101 is electrically connected to one end of capacitor element 102, the collector is electrically connected to the XO terminal, and the emitter is grounded. Bipolar transistor 101 is an example of an amplifying element. The base of bipolar transistor 101 is the input node 201, and the collector of bipolar transistor 101 is the output node 202.

[0066] Furthermore, a first resistor element 81 is connected between the base and collector of the bipolar transistor 101. That is, the first resistor element 81 is disposed on the signal path between the input node 201 and the output node 202 of the amplification element. The first resistor element 81 functions as a feedback resistor for the bipolar transistor 101. Moreover, a bias current Ibias is supplied to the collector of the bipolar transistor 101.

[0067] The signal input from the XI terminal is supplied to the base of the bipolar transistor 101 via capacitor element 102, and amplified by the bipolar transistor 101, which acts as an amplification element. The amplified signal is then supplied from the collector of the bipolar transistor 101 to the oscillator 3 via the XO terminal. That is, the bipolar transistor 101 amplifies the signal from the XI terminal and outputs it to the XO terminal. Alternatively, a MOS transistor or a CMOS inverter can be used instead of the bipolar transistor 101 as the amplification element.

[0068] The first switching element 71 is turned on or off according to the switching control data. The switching control data is supplied to the first switching element 71 from the logic circuit 36. The first switching element 71 switches the electrical connection between the input node 201 of the amplifier element and ground.

[0069] When the first switching element 71 is turned on, the base of the bipolar transistor 101 is connected to ground; when the first switching element 71 is turned off, the base of the bipolar transistor 101 is not connected to ground. Furthermore, the first switching element 71 can also be an n-type FET, a p-type FET, or a circuit combining these.

[0070] When the first switching element 71 is turned off, as described above, the bipolar transistor 101 amplifies the signal input from the XI terminal, which is input to the base via the input node 201. The amplified signal is then output from the collector of the bipolar transistor 101 to the XO terminal via the output node 202.

[0071] When the first switching element 71 is turned on, the base of the bipolar transistor 101 is connected to ground. The emitter of the bipolar transistor 101 is also connected to ground. Because the on-resistance of the first switching element 71 is very small, the potential difference Vbe between the base and emitter of the bipolar transistor 101 is near 0V. Therefore, the bipolar transistor 101 is turned off. Ideally, the on-resistance of the first switching element 71 should be zero, and the potential difference Vbe should be 0V.

[0072] The oscillation circuit 10 outputs the signal generated at the node between the XI terminal and the other end of the capacitor element 102 as the oscillation signal OSCO. A bias voltage Vrefb is supplied to this node from the duty cycle adjustment circuit 112 of the reference voltage circuit 11. Therefore, the oscillation signal OSCO becomes a waveform that oscillates around the bias voltage Vrefb and is input to the waveform shaping circuit 21 of the output circuit 20. Consequently, the duty cycle of the clock signal CK1 output from the waveform shaping circuit 21 varies according to the bias voltage Vrefb, and as a result, the duty cycle of the clock signal CKO output from the output circuit 20 also varies. Since the bias voltage Vrefb is a voltage corresponding to the duty cycle adjustment data supplied from the logic circuit 36, by setting appropriate duty cycle adjustment data in the non-volatile memory 52, the duty cycle of the clock signal CKO can be made close to 50%.

[0073] The capacitor circuit 13 includes k capacitor elements 131-1 to 131-k and k switching elements 132-1 to 132-k. k is an integer greater than or equal to 2. For each integer i between 1 and k, one end of capacitor element 131-i is electrically connected to terminal XI, and the other end is electrically connected to one end of switching element 132-i. The other end of switching element 132-i is electrically connected to ground.

[0074] The capacitor circuit 14 includes k capacitor elements 141-1 to 141-k and k switching elements 142-1 to 142-k. For each integer i greater than 1 and less than k, one end of capacitor element 141 to i is electrically connected to the XO terminal, and the other end is electrically connected to one end of switching element 142 to i. The other end of switching element 142-i is electrically connected to ground.

[0075] Switching elements 132-1 to 132-k are switched on or off according to the value of each bit of the frequency adjustment data. When switching element 132-i is on, capacitor element 131-i is connected between terminal XI and ground. Similarly, switching elements 142-1 to 142-k are switched on or off according to the value of each bit of the frequency adjustment data. When switching element 142-i is on, capacitor element 141-i is connected between terminal XO and ground. The frequency adjustment data is stored in non-volatile memory 52, and logic circuit 36 ​​provides the frequency adjustment data transferred from non-volatile memory 52 to register 51 to capacitor circuits 13 and 14.

[0076] The capacitance value of capacitor circuit 13 is the sum of the capacitance values ​​of the capacitor elements 131-1 to 131-k connected between terminal XI and ground. Similarly, the capacitance value of capacitor circuit 14 is the sum of the capacitance values ​​of the capacitor elements 141-1 to 141-k connected between terminal XO and ground. Therefore, the capacitance values ​​of capacitor circuits 13 and 14 change according to the frequency adjustment data. Capacitor circuits 13 and 14 function as load capacitors for oscillator 3, and the frequency of the oscillation signal OSCO changes according to the capacitance values ​​of capacitor circuits 13 and 14. As a result, the frequency of the clock signal CKO changes. Therefore, by setting appropriate frequency adjustment data in the non-volatile memory 52, the difference between the frequency of the clock signal CKO at the reference temperature and the target frequency can be minimized. The reference temperature can be, for example, 25°C.

[0077] The variable capacitor circuit 15 includes a capacitor element 151, n variable capacitor elements 152-1 to 152-n, n capacitor elements 153-1 to 153-n, and a resistor element 154. One end of capacitor element 151 is electrically connected to terminal XI, and the other end is electrically connected to one end of each of the variable capacitor elements 152-1 to 152-n and one end of resistor element 154. For each integer i between 1 and n, the other end of variable capacitor element 152-i is electrically connected to one end of capacitor element 153-i, and the other end of capacitor element 153-i is electrically connected to ground. Furthermore, a reference voltage VcgC[i] is supplied to the other end of variable capacitor element 152-i and one end of capacitor element 153-i. In addition, a temperature compensation voltage Vcomp is supplied to one end of each of the variable capacitor elements 152-1 to 152-n via resistor element 154.

[0078] The variable capacitor circuit 16 includes a capacitor element 161, n variable capacitor elements 162-1 to 162-n, n capacitor elements 163-1 to 163-n, and a resistor element 164. One end of capacitor element 161 is electrically connected to the XO terminal, and the other end is electrically connected to one end of each of the variable capacitor elements 162-1 to 162-n and one end of resistor element 164. For each integer i between 1 and n, the other end of variable capacitor element 162-i is electrically connected to one end of capacitor element 163-i, and the other end of capacitor element 163-i is electrically connected to ground. Furthermore, a reference voltage VcgC[i] is supplied to the other end of variable capacitor element 162-i and one end of capacitor element 163-i. In addition, a temperature compensation voltage Vcomp is supplied to one end of each of the variable capacitor elements 162-1 to 162-n via resistor element 164.

[0079] The capacitance values ​​of variable capacitor elements 152-1 to 152-n vary according to the temperature compensation voltage Vcomp. Similarly, the capacitance values ​​of variable capacitor elements 162-1 to 162-n vary according to the temperature compensation voltage Vcomp. Therefore, the capacitance values ​​of variable capacitor circuits 15 and 16 vary according to the temperature compensation voltage Vcomp. Variable capacitor circuits 15 and 16 function as load capacitors for oscillator 3, and the frequency of the oscillation signal OSCO varies according to the capacitance values ​​of variable capacitor circuits 15 and 16. As a result, the frequency of the clock signal CKO varies. Therefore, by setting appropriate temperature compensation data in the non-volatile memory 52, the difference between the frequency of the clock signal CKO at any temperature within a specified temperature range and the target frequency can be minimized.

[0080] The variable capacitor circuit 17 includes a capacitor element 171, m variable capacitor elements 172-1 to 172-m, m capacitor elements 173-1 to 173-n, and a resistor element 174. One end of capacitor element 171 is electrically connected to the XI terminal, and the other end is electrically connected to one end of each of the variable capacitor elements 172-1 to 172-m and one end of the resistor element 174. For each integer i between 1 and m, the other end of variable capacitor element 172-i is electrically connected to one end of capacitor element 173-i, and the other end of capacitor element 173-i is electrically connected to ground. Furthermore, a reference voltage VcgA[i] is supplied to the other end of variable capacitor element 172-i and one end of capacitor element 173-i. In addition, a frequency control voltage Vafc is supplied to one end of each of the variable capacitor elements 172-1 to 172-m via the resistor element 174.

[0081] The variable capacitor circuit 18 includes a capacitor element 181, m variable capacitor elements 182-1 to 182-m, m capacitor elements 183-1 to 183-n, and a resistor element 184. One end of capacitor element 181 is electrically connected to the XO terminal, and the other end is electrically connected to one end of each of the variable capacitor elements 182-1 to 182-m and one end of resistor element 184. For each integer i between 1 and m, the other end of variable capacitor element 182-i is electrically connected to one end of capacitor element 183-i, and the other end of capacitor element 183-i is electrically connected to ground. Furthermore, a reference voltage VcgA[i] is supplied to the other end of variable capacitor element 182-i and one end of capacitor element 183-i. In addition, a frequency control voltage Vafc is supplied to one end of each of the variable capacitor elements 182-1 to 182-m via resistor element 184.

[0082] The capacitance values ​​of variable capacitor elements 172-1 to 172-m vary according to the frequency control voltage Vafc. Similarly, the capacitance values ​​of variable capacitor elements 182-1 to 182-m vary according to the frequency control voltage Vafc. Therefore, the capacitance values ​​of variable capacitor circuits 17 and 18 vary according to the frequency control voltage Vafc. Variable capacitor circuits 17 and 18 function as load capacitors for oscillator 3, and the frequency of the oscillation signal OSCO varies according to the capacitance values ​​of variable capacitor circuits 17 and 18. As a result, the frequency of the clock signal CKO varies. Therefore, the frequency of the clock signal CKO can be varied according to the voltage applied to terminal T4.

[0083] For example, capacitor elements 102, 103, 131-1~131-k, 141-1~141-k, 151, 153-1~153-n, 161, 163-1~163-n, 171, 173-1~173-m, 181, 183-1~183-m can be MIM (Metal Insulator Metal) type capacitors using metal in both electrodes, or PIP (Poly Insulator Poly) type capacitors using polysilicon in both electrodes. Furthermore, variable capacitor elements 152-1~152-n, 162-1~162-n, 172-1~172-m, and 182-1~182-m can also be varactor diodes obtained by connecting the source and drain of a MOS transistor.

[0084] 1-3. Inspection of the oscillator

[0085] Figure 5 This is a flowchart illustrating an example of the steps for providing a check signal to oscillator 1 for overdrive checking. Additionally, Figure 6 It means until it is passed. Figure 5 The flowchart is a diagram of an example of the signal waveforms of terminals T1, T2, T3, and T4 up to the point where a check signal is supplied to oscillator 1.

[0086] exist Figure 5 In the example, firstly, the device checks the power supply voltage supplied to terminal T1 of oscillator 1 (step S1). For example... Figure 6 As shown, through step S1, the voltage at terminal T1 rises from ground to the desired voltage.

[0087] Next, the inspection device supplies a control signal to terminal T4 of oscillator 1, setting oscillator 1 to external communication mode (step S2). That is, as... Figure 6As shown, the inspection device supplies a signal of a predetermined pattern to the T4 terminal of the oscillator 1 within a specified period starting from the supply of power voltage to the T1 terminal, thereby setting the oscillator 1 to external communication mode.

[0088] Next, the inspection device supplies control signals to terminals T3 and T4 of oscillator 1, setting oscillator 1 to oscillator inspection mode (step S3). That is, as... Figure 6 As shown, in external communication mode, the inspection device supplies a serial clock signal to terminal T3 and a serial data signal to terminal T4 as an oscillator inspection command, thus setting oscillator 1 to oscillator inspection mode. Figure 6 As shown, through step S3, the oscillator 1 changes from external communication mode to oscillator check mode, thereby changing the control signals of the first switching element 71, the second switching element 72, and the third switching element 73 from low level to high level. Consequently, the first switching element 71, the second switching element 72, and the third switching element 73 are all turned on, the X1 terminal is connected to ground, and the XO terminal is connected to the T4 terminal.

[0089] Then, the inspection device supplies an inspection signal to terminal T4 for overdrive inspection. For example... Figure 6 As shown, the check signal is a signal with maximum amplitude that periodically oscillates between the power supply voltage supplied to terminal T1 and the ground voltage supplied to terminal T2. The frequency of the check signal is approximately equal to the resonant frequency of oscillator 3, which resonates when the check signal is supplied.

[0090] Therefore, for example, before performing a characteristic check on oscillator 1, the inspection device supplies an inspection signal to oscillator 1 in oscillator inspection mode, thereby shaking off foreign matter such as metal sheets remaining on oscillator 3 during the formation of excitation electrodes 3a and 3b. Furthermore, for example, during the characteristic check of oscillator 1, after adjusting the frequency of clock signal CKO to the target frequency, the inspection device switches oscillator 1 to oscillator inspection mode and supplies an inspection signal to terminal T3. Then, the inspection device switches oscillator 1 to normal operating mode and measures the frequency of clock signal CKO output from terminal T3. For example, if foreign matter such as metal sheets remaining on oscillator 3 was not sufficiently shaken off before the characteristic check of oscillator 1, and some of the remaining foreign matter is shaken off by the inspection signal, the characteristics of oscillator 1 change, and the frequency of clock signal CKO differs significantly from the target frequency. Therefore, if the difference between the measured frequency and the target frequency exceeds a predetermined threshold, the inspection device determines that the characteristics of oscillator 1 have changed before and after overdrive, and can classify oscillator 1 as defective.

[0091] In addition, Figure 5 as well as Figure 6In the oscillator inspection mode, the inspection device supplies a check signal for overdrive inspection to terminal T4, but it can also supply a check signal for drive level inspection. For example, this check signal is a signal whose amplitude changes at regular intervals. The inspection device measures the frequency of the clock signal CKO output from terminal T3 whenever the amplitude of the check signal changes. Furthermore, if the frequency of the clock signal CKO exceeds a predetermined range within the range of changes in the amplitude of the check signal—that is, if the frequency of the clock signal CKO changes significantly at a predetermined excitation level—the inspection device determines that oscillator 3 has a structural defect and can classify oscillator 1 as faulty.

[0092] 1-4. Effects

[0093] Assuming that in the oscillator inspection mode, the first switching element 71 is off or absent, the inspection signal supplied from terminal T4 to terminal XO via the third switching element 73 is input to the base of bipolar transistor 101 via the first resistor element 81, which serves as a feedback resistor. As a result, the conditions for bipolar transistor 101 to operate are met, and bipolar transistor 101 generates a signal that blocks the inspection signal, potentially preventing the inspection device from applying a large-amplitude inspection signal to terminal T4. In contrast, in the oscillator 1 of this embodiment, in the oscillator inspection mode, bipolar transistor 101 can be turned off by turning on the first switching element 71, thus reducing the possibility of bipolar transistor 101 affecting the inspection signal.

[0094] Furthermore, in the oscillator check mode, if the bipolar transistor 101 is turned off, the same effect as described above can be obtained. Therefore, when the first switching element 71 is turned on, it is preferable that the potential difference Vbe between the base of the bipolar transistor 101 and ground is less than the diffusion potential of the silicon PN junction. Specifically, in an environment where the ambient temperature of the oscillator 1 is 25°C, the potential difference Vbe is preferably 0V or more and less than 0.6V. This allows for more reliable turn-off of the bipolar transistor 101.

[0095] Furthermore, when the first switching element 71 is turned on, the second switching element 72 and the third switching element 73 are also turned on. That is, in the oscillator check mode, the first switching element 71, the second switching element 72, and the third switching element 73 are turned on, the bipolar transistor 101 is turned off, the T2 terminal is electrically connected to the XI terminal, and the T4 terminal is electrically connected to the XO terminal. As a result, overdrive checks and drive level checks can be performed. Conversely, when the first switching element 71 is turned off, the second switching element 72 and the third switching element 73 are also turned off. That is, in the normal operating mode, the first switching element 71, the second switching element 72, and the third switching element 73 are turned off, the bipolar transistor 101 is turned on, the T2 terminal is electrically disconnected from the XI terminal, and the T4 terminal is electrically disconnected from the XO terminal. As a result, even if a certain control voltage is input to the T4 terminal, the bipolar transistor 101 can still cause the oscillator 3 to oscillate. Thus, in the oscillator 1 of this embodiment, the external terminals T2 and T4 of the oscillator 1, which are used in normal operating mode, can be used for both overdrive checking and drive level checking. Therefore, the structure of the circuit device 2 can be simplified.

[0096] 2. Second Implementation Method

[0097] The oscillation circuit 10 of the second embodiment will be described. When describing the oscillation circuit 10 of the second embodiment, the same reference numerals are used for structures that are the same as those in the oscillation circuit 10 of the first embodiment, and their descriptions are omitted or simplified.

[0098] Figure 7 This is a diagram illustrating a structural example of the oscillation circuit 10 according to the second embodiment. (As shown...) Figure 7 As shown, the oscillation circuit 10 includes a second resistive element 82. Alternatively, the oscillation circuit 10 of the second embodiment may be configured to omit or modify a portion of these elements, or to add other elements.

[0099] One end of the second resistor element 82 is electrically connected to the base of the bipolar transistor 101, and the other end of the second resistor element 82 is electrically connected to one end of the first switching element 71. One end of the first switching element 71 is electrically connected to the second resistor element 82, and the other end of the first switching element 71 is electrically connected to ground. That is, the second resistor element 82 is placed on the signal path between the input node 201 of the amplifying element and ground.

[0100] In the oscillator check mode of the second embodiment, the first switching element 71 is turned on, the second resistive element 82 is electrically connected to ground, and the potential of the input node 201 becomes ground. Since the on-resistance of the first switching element 71 is very small, the potential difference Vbe between the base and emitter of the bipolar transistor 101 is near 0V. Therefore, the bipolar transistor 101 is turned off. Ideally, the on-resistance of the first switching element 71 is zero, and the potential difference Vbe is 0V. Therefore, the same effect as in the first embodiment described above can be obtained.

[0101] For example, when a transistor such as a FET is used as the first switching element 71, the impedance of the input node 201 may sometimes decrease due to the parasitic capacitance of the transistor. This can potentially cause a decrease in the amplitude and frequency of the oscillation signal OSCO output from the oscillation circuit 10. Furthermore, this parasitic capacitance can become a path for leakage current. In the oscillator inspection mode of the second embodiment, the impedance of the input node 201 can be increased by the second resistive element 82, thus reducing the aforementioned possibilities. Therefore, oscillator inspection can be performed in a more stable state.

[0102] 3. Third Implementation Method

[0103] The oscillation circuit 10 of the third embodiment will be described. When describing the oscillation circuit 10 of the third embodiment, the same reference numerals are used for structures that are the same as those in the oscillation circuit 10 of the first embodiment, and their descriptions are omitted or simplified.

[0104] Figure 8 This is a diagram illustrating a structural example of the oscillation circuit 10 according to the third embodiment. (See diagram below.) Figure 8 As shown, the oscillation circuit 10 includes a second resistive element 82 and a fourth switching element 74. Alternatively, the oscillation circuit 10 of the third embodiment may be configured by omitting or modifying a portion of these elements, or by adding other elements.

[0105] One end of the second resistor element 82 is electrically connected to the base of the bipolar transistor 101, and the other end of the second resistor element 82 is electrically connected to the first switch element 71 and the fourth switch element 74. The first resistor element 81 and the second resistor element 82 function as feedback resistors for the bipolar transistor 101.

[0106] The fourth switching element 74 is turned on or off according to the switching control data. The switching control data is supplied to the fourth switching element 74 from the logic circuit 36. That is, the fourth switching element 74 switches the electrical connection between the first resistive element 81 and the second resistive element 82.

[0107] One end of the fourth switching element 74 is electrically connected to the first resistive element 81, and the other end of the fourth switching element 74 is electrically connected to both the first switching element 71 and the second resistive element 82. When the fourth switching element 74 is turned on, the first resistive element 81 and the second resistive element 82 are conductive; when the fourth switching element 74 is turned off, the first resistive element 81 and the second resistive element 82 are not conductive.

[0108] In normal operating mode, the fourth switching element 74 is turned on; in oscillator check mode, the fourth switching element 74 is turned off. In normal operating mode, the first resistive element 81 and the second resistive element 82 function as feedback resistors of the bipolar transistor 101; in oscillator check mode, the first resistive element 81 and the second resistive element 82 are electrically cut off and do not function as feedback resistors of the bipolar transistor 101.

[0109] In the oscillator check mode of the third embodiment, the first switching element 71 is turned on, the second resistive element 82 is connected to ground, and the potential of the input node 201 becomes ground. Therefore, the potential difference Vbe becomes 0V, which can turn off the bipolar transistor 101. Thus, the same effect as in the first embodiment described above can be obtained.

[0110] In the oscillator inspection mode of the third embodiment, since the feedback resistor of the bipolar transistor 101 is electrically cut off, the bipolar transistor 101 can be turned off more reliably.

[0111] 4. Fourth Implementation Method

[0112] The oscillation circuit 10 of the fourth embodiment will be described. When describing the oscillation circuit 10 of the fourth embodiment, the same reference numerals are used for structures that are the same as those in the oscillation circuit 10 of the first embodiment, and their descriptions are omitted or simplified.

[0113] Figure 9 This is a diagram illustrating a structural example of the oscillation circuit 10 according to the fourth embodiment. (See diagram for example.) Figure 9 As shown, the oscillation circuit 10 includes a second resistive element 82. Alternatively, the oscillation circuit 10 of the fourth embodiment may be configured to omit or modify a portion of these elements, or to add other elements.

[0114] One end of the first resistor element 81 is electrically connected to the output node 202, and the other end of the first resistor element 81 is electrically connected to the first switching element 71 and the second resistor element 82. The first resistor element 81 and the second resistor element 82 constitute the feedback resistor of the bipolar transistor 101.

[0115] In the oscillator check mode of the fourth embodiment, the first switching element 71 is turned on, the second resistive element 82 is electrically connected to ground, and the potential of the input node 201 becomes ground. Since the on-resistance of the first switching element 71 is very small, the potential difference Vbe between the base and emitter of the bipolar transistor 101 is near 0V. Therefore, the bipolar transistor 101 is turned off. Ideally, the on-resistance of the first switching element 71 is zero, and the potential difference Vbe is 0V. Therefore, the same effect as in the first embodiment described above can be obtained. Furthermore, unlike the third embodiment, the fourth switching element 74, which electrically connects the first resistive element 81 and the second resistive element 82, is omitted, thus simplifying the structure of the circuit device 2.

[0116] 5. Variation Example 1

[0117] Figure 10 This is a diagram showing a schematic structure of the oscillation circuit 10 in Modified Example 1. The circuit device 2 in Modified Example 1 omits the temperature sensor 30, the temperature compensation circuit 32, and the frequency control circuit 34. Along with this omission, in... Figure 10 In the oscillation circuit 10 of the modified example 1 shown, capacitor circuits 13 and 14 are replaced with capacitor elements 13a and 14a, bias current generation circuit 12 is replaced with constant current source 12a, and variable capacitor circuits 17 and 18 are omitted.

[0118] In the oscillator inspection mode of Modified Example 1, the first switching element 71 is turned on, and the potential of the input node 201 becomes ground. Therefore, the potential difference Vbe becomes near 0V, which can turn off the bipolar transistor 101. Thus, the same effect as in the first embodiment described above can be obtained.

[0119] 6. Variation Example 2

[0120] Figure 11 This is a diagram showing the schematic structure of the oscillator 1 in modified example 2. Figure 11The oscillator 1 shown outputs multiple output signals. Specifically, the output circuit 20 of the circuit device 2 outputs clock signals CKO1, CKO2, and CKO3. These clock signals CKO1, CKO2, and CKO3 are output from the oscillator 1 via terminals T31, T32, and T33, respectively. In such an oscillator 1 that outputs multiple signals, the oscillation circuit 10 of the above embodiment can be applied. Therefore, in the oscillator 1 of the modified example 2, switching between a normal operating mode and an oscillator check mode is also possible. In the oscillator check mode, the first switching element 71 is turned on, and the potential of the input node 201 becomes ground. Therefore, the potential difference Vbe becomes close to 0V, and the bipolar transistor 101 can be turned off. Therefore, the same effect as in the first embodiment described above can be obtained. Furthermore, the oscillator circuit 10 applied to the modified example 2 can also have a second resistive element 82 as in the second embodiment. Furthermore, the effects of the second embodiment can also be obtained.

[0121] 7. Effects

[0122] As described above, in the oscillator inspection mode, the circuit device 2 in this embodiment can turn off the amplification element. Therefore, a stable inspection can be performed without being affected by the amplification element.

[0123] The embodiments and variations have been described above, but the present invention is not limited to these embodiments and can be implemented in various ways without departing from its spirit. For example, the above embodiments can also be appropriately combined.

[0124] This invention includes structures that are substantially the same as those described in the embodiments (e.g., structures with the same function, method, and result, or structures with the same purpose and effect). Furthermore, this invention includes structures obtained by replacing non-essential parts of the structures described in the embodiments. Furthermore, this invention includes structures capable of achieving the same function or effect as the structures described in the embodiments, or achieving the same purpose. Furthermore, this invention includes structures incorporating known techniques into the structures described in the embodiments.

[0125] Based on the above implementation methods and variations, the following content is derived.

[0126] One embodiment of the circuit arrangement includes: a first terminal connected to one end of an oscillator; a second terminal connected to the other end of the oscillator; an amplifying element that amplifies the signal from the first terminal and outputs it to the second terminal; a first resistive element disposed on the signal path between the input node and the output node of the amplifying element; a capacitive element disposed on the signal path between the first terminal and the input node; and a first switching element that switches the electrical connection between the input node and ground.

[0127] According to this circuit arrangement, the amplifier's input node can be connected to ground via the first switching element, causing the amplifier to stop. Therefore, a signal can be input between the first and second terminals to check the oscillator without being affected by the amplifier. For example, a large-amplitude signal can be input between the first and second terminals to check the oscillator.

[0128] In one embodiment of the circuit arrangement, it may also include: a third terminal; a fourth terminal; a second switching element that switches the electrical connection between the first terminal and the third terminal; and a third switching element that switches the electrical connection between the second terminal and the fourth terminal. In a first mode, the first, second, and third switching elements are disconnected, and in a second mode, the first, second, and third switching elements are connected.

[0129] According to this circuit arrangement, the on / off state of the first, second, and third switching elements can be switched, thereby allowing the circuit arrangement to operate in a first mode and a second mode. In the first mode, since the first switching element is off, the amplifier's input node is not electrically connected to ground, and the amplifier operates normally. Therefore, signals can be input to the first, second, third, and fourth terminals respectively to cause the circuit arrangement to operate normally. Furthermore, since the terminals used in both the first and second modes are shared, the structure of the circuit arrangement can be simplified. In the second mode, since the first switching element is on, the amplifier's input node is electrically connected to ground, and the amplifier stops. Therefore, a signal for checking the oscillator can be supplied between the third terminal (electrically connected to the first terminal) and the fourth terminal (electrically connected to the second terminal) to check the oscillator.

[0130] In one embodiment of the circuit arrangement, the circuit arrangement may have a second resistive element disposed on the signal path between the input node and the ground, one end of the first switching element being electrically connected to the second resistive element, and the other end of the first switching element being electrically connected to the ground.

[0131] According to this circuit arrangement, the impedance of the input node can be increased by using the second resistive element. That is, the second resistive element can suppress the influence of impedance fluctuations at the input node caused by the first switching element. As a result, the operation of the circuit arrangement is stable.

[0132] In one embodiment of the circuit device, the circuit device may also have a fourth switching element that switches the electrical connection between the first resistive element and the second resistive element. One end of the fourth switching element is electrically connected to the first resistive element, and the other end of the fourth switching element is electrically connected to both the first switching element and the second resistive element.

[0133] According to this circuit arrangement, the first and second resistive elements, which electrically connect the output and input nodes of the amplifying element, are electrically disconnected when the fourth switch is turned off. Therefore, the electrical connection between the input and output nodes of the amplifying element can be electrically severed. This allows for more reliable shutdown of the amplifying element.

[0134] In one embodiment of the circuit arrangement, the fourth switching element may be turned on in the first mode and turned off in the second mode.

[0135] According to this circuit arrangement, in the second mode, the fourth switch is open, and the first and second resistive elements are electrically cut off. In the second mode, since the amplifier's feedback resistor is electrically cut off, the amplifying element can be more reliably cut off. Furthermore, in the first mode, the fourth switch is closed, and the first and second resistive elements function as feedback resistors. Therefore, in both the first and second modes, the circuit arrangement can operate in a more optimal state.

[0136] In one embodiment of the circuit arrangement, one end of the first resistive element may be electrically connected to the output node, and the other end of the first resistive element may be electrically connected to the first switching element and the second resistive element.

[0137] According to this circuit arrangement, since the switching element that electrically connects the first and second resistive elements is omitted, the structure of the circuit arrangement can be simplified. Furthermore, since the first switching element can be used to switch between the first and second modes, the structure of the circuit arrangement can be simplified while maintaining functionality.

[0138] In one embodiment of the circuit arrangement, the amplifying element may be a bipolar transistor, the input node may be the base of the bipolar transistor, and the output node may be the collector of the bipolar transistor.

[0139] According to this circuit arrangement, in the bipolar transistor, a current a predetermined multiple of the current flowing through the base flows through the collector, thus enabling easy control. Furthermore, by using a bipolar transistor as the amplifying element, the structure of the circuit arrangement can be simplified.

[0140] In one embodiment of the circuit arrangement, when the first switching element is turned on, the potential difference between the base and the ground is less than the diffusion potential of the PN junction.

[0141] According to this circuit arrangement, in the first mode, the amplifying element stops, thus turning off the bipolar transistor. The base and emitter of the bipolar transistor are composed of a PN junction, and in the first mode, the bipolar transistor can be turned off by making the potential difference between the base and ground less than the diffusion potential of the PN junction.

[0142] In one embodiment of the circuit arrangement, the potential difference may be greater than 0V and less than 0.6V in an environment with an ambient temperature of 25°C.

[0143] According to this circuit arrangement, by setting the potential difference between the base of the bipolar transistor and ground to be greater than 0V and less than 0.6V, the bipolar transistor can be turned off more reliably.

[0144] One configuration of the oscillator includes: one configuration of the circuit arrangement; and the oscillator.

[0145] According to this oscillator, by connecting the amplifier's input node to ground via the first switching element, the amplifier can be stopped. Therefore, a signal can be input between the first and second terminals for oscillator inspection without being affected by the amplifier. For example, a large-amplitude signal can be input between the first and second terminals for oscillator inspection.

Claims

1. A circuit arrangement, wherein, The circuit device has: a first terminal connected to one end of the vibrator; a second terminal connected to the other end of the vibrator; an amplifying element amplifying a signal from the first terminal and outputting to the second terminal; a first resistance element provided on a signal path between an input node and an output node of the amplifying element; a capacitance element provided on a signal path between the first terminal and the input node; a first switch element switching electrical connection of the input node to a ground; a third terminal; a fourth terminal; a second switch element switching electrical connection of the first terminal to the third terminal; and a third switch element switching electrical connection of the second terminal to the fourth terminal, in a first mode, the first switch element, the second switch element, and the third switch element are open, in a second mode, the first switch element, the second switch element, and the third switch element are closed.

2. The circuit device according to claim 1, wherein the circuit device has a second resistance element provided on a signal path between the input node and the ground, one end of the first switch element is electrically connected to the second resistance element, the other end of the first switch element is electrically connected to the ground.

3. The circuit device according to claim 2, wherein the circuit device has a fourth switch element switching electrical connection of the first resistance element to the second resistance element, one end of the fourth switch element is electrically connected to the first resistance element, the other end of the fourth switch element is electrically connected to the first switch element and the second resistance element.

4. The circuit device according to claim 3, wherein in the first mode, the fourth switch element is closed, in the second mode, the fourth switch element is open.

5. The circuit device according to claim 2, wherein one end of the first resistance element is electrically connected to the output node, the other end of the first resistance element is electrically connected to the first switch element and the second resistance element.

6. The circuit device according to any one of claims 1 to 5, wherein the amplifying element is a bipolar transistor, the input node is a base of the bipolar transistor, the output node is a collector of the bipolar transistor.

7. The circuit device according to claim 6, wherein when the first switch element is closed, a potential difference between the base and the ground is less than a diffusion potential of a PN junction.

8. The circuit device according to claim 7, wherein in an environment where a temperature around is 25°C, the potential difference is 0 V or more and less than 0.6 V. The oscillator has:

9. An oscillator wherein, the circuit device according to any one of claims 1 to 8; and the vibrator. ​

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