A differential pair circuit with improved linearity
By setting the type of bias tube in the differential pair circuit to be opposite to that of the differential pair and connecting its source to the common source terminal to provide a variable bias current, the problem of linearity deterioration in the traditional differential pair circuit in an unbalanced state is solved, and higher linearity and flexibility are achieved.
Patent Information
- Application Number
- CN202210785012.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-07-05
- Publication Date
- 2025-09-26
- Estimated Expiration
- 2042-07-05
AI Technical Summary
When a traditional differential pair circuit is in an unbalanced state, the common source voltage Vs varies greatly, resulting in deteriorated linearity. In addition, the bias current is easily affected by temperature, process, and input common-mode level, resulting in low flexibility.
A differential pair circuit with improved linearity is adopted. By setting the type of bias tube to be opposite to the type of the differential pair and connecting the source of the bias tube to the common source terminal, a bias current that can vary with the differential mode input voltage is provided.
In the unbalanced state, the change of the common source voltage Vs decreases, and the sum of the drain currents flowing through the input pair tubes increases, thereby improving the linearity between the output current Io and the input voltage Vi.
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Figure CN115276571B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a differential pair circuit with improved linearity. Background Art
[0002] A differential pair is a pair of source-coupled input transistors. Its input is essentially voltage and its output is current. It is equivalent to a transconductance used to convert voltage into current.
[0003] like Figure 1 The figure shows a traditional differential pair circuit, consisting of an NMOS differential pair and a current source. The current source provides a fixed tail current bias. When the differential pair is in an unbalanced state, that is, the gate input voltages of the two input transistors are unequal, the sum of the drain currents required by the two input transistors increases, raising the voltage level at the common source of the NMOS differential pair, and deteriorating the linearity between the input and output of the differential pair. Theoretically, linearity is optimal when the sources of the two input transistors are directly grounded. However, this bias current is susceptible to temperature, process, and input common-mode level, resulting in a wide bias current fluctuation range. Alternatively, the sources of the two input transistors are grounded through a bias resistor. The smaller the bias resistor impedance, the better the linearity. Given a fixed bias current level, achieving a certain linearity requires a sufficiently small bias resistor, which in turn limits the value of the input common-mode level. Therefore, there is a trade-off between the input common-mode level and the bias resistor, resulting in limited flexibility. Furthermore, the bias resistor value is also susceptible to process fluctuations, resulting in a wide bias current fluctuation range. Summary of the Invention
[0004] In order to solve the above technical problems, the present invention provides a differential pair circuit with improved linearity.
[0005] The technical problem solved by the present invention can be achieved by adopting the following technical solutions:
[0006] A differential pair circuit with improved linearity, comprising:
[0007] A differential pair, the differential pair comprising:
[0008] a first input transistor pair, controllably connected between a first node and a common source terminal under the action of a first input voltage;
[0009] a second input pair of transistors controllably connected between a second node and the common source terminal under the action of a second input voltage;
[0010] A bias transistor, wherein the source of the bias transistor is connected to the common source terminal, and the type of the bias transistor is opposite to that of the differential pair, and is controllably connected to the common source terminal under the action of a bias voltage.
[0011] Preferably, the first pair of input tubes and the second pair of input tubes are of the same type.
[0012] Preferably, the bias tube is of opposite type to the first input pair tube;
[0013] The bias transistor is of opposite type to the second input pair transistors.
[0014] Preferably, the first input pair transistors are any one of an NMOS transistor, a PMOS transistor, an NPN bipolar junction transistor, a PNP bipolar junction transistor, a combination of an NMOS transistor and a resistor, or a combination of a PMOS transistor and a resistor.
[0015] Preferably, the second input pair transistors are any one of an NMOS transistor, a PMOS transistor, an NPN bipolar junction transistor, a PNP bipolar junction transistor, a combination of an NMOS transistor and a resistor, or a combination of a PMOS transistor and a resistor.
[0016] Preferably, when the differential pair is in an unbalanced state, the first input voltage is not equal to the second input voltage.
[0017] Preferably, it also includes:
[0018] A first resistor is connected between the drain of the first input pair transistor and the power supply terminal, with the drain of the first input pair transistor serving as the first node;
[0019] The second resistor is connected between the drain of the second input pair of transistors and the power supply terminal, and the drain of the second input pair of transistors serves as the second node.
[0020] Preferably, the device further comprises: a bias generating circuit for generating the bias voltage, wherein the bias generating circuit specifically comprises:
[0021] a first transistor, wherein a gate and a drain of the first transistor are connected to a power supply terminal via a reference current source, and a source of the first transistor is connected to the ground terminal;
[0022] a second transistor, wherein a gate of the second transistor is connected to the gate of the first transistor, a source of the second transistor is connected to the ground terminal, a drain of the second transistor is connected to a first connection node, and the bias voltage is output from the first connection node;
[0023] a third transistor, wherein a gate and a drain of the third transistor are connected to the first connection node;
[0024] A fourth transistor, wherein a gate of the fourth transistor is connected to a gate common mode voltage, a source of the fourth transistor is connected to the source of the third transistor, and a drain of the fourth transistor is connected to the power supply terminal.
[0025] Preferably, the gate common-mode voltage is a common-mode voltage of the first input voltage and the second input voltage.
[0026] The advantages or beneficial effects of the technical solution of the present invention are:
[0027] The present invention sets the type of bias tube to be opposite to that of the differential pair, and connects the source of the bias tube to the common source terminal of the differential pair. The bias tube provides a bias current that can change with the differential input voltage to the two input pairs of the differential pair. Compared with the traditional differential pair circuit, the change of the common source terminal voltage Vs of the circuit of the present invention is smaller in the unbalanced state, and the sum of the drain terminal currents flowing through the two input pairs of tubes is increased, thereby improving the output current Io (i.e., I D1 -I D2 ) and the input voltage Vi (ie V in1 -V in2 ) between the linearity. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 A circuit diagram of a traditional differential pair in the prior art;
[0029] Figure 2 1 is a circuit diagram of a differential pair circuit in a preferred embodiment of the present invention;
[0030] Figure 3 FIG. 1 is a circuit diagram of a differential pair circuit in a preferred embodiment of the present invention. DETAILED DESCRIPTION
[0031] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.
[0032] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.
[0033] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.
[0034] like Figure 1 In the traditional differential pair circuit shown, a current source is used to provide a fixed bias current. When the differential pair is in a balanced state, the input voltage Vin=Vin1-Vin2=0, V in1 =V in2 =Vcom (Vcom>Vth), where Vcom represents the first input voltage Vin1 and the second input voltage V in2 Vth represents the common mode voltage of the first input pair tube M1 or the second input pair tube M2.
[0035] According to Kirchhoff's current law KCL, the first current I flowing through the first input transistor M1 is D1 and the second current I flowing through the second input transistor M2 D2 The sum must be equal to the bias current Iss. Ignoring the channel length modulation effect and the body effect, it is:
[0036]
[0037] Where K = μCox, μ represents the carrier mobility, and Cox represents the gate oxide capacitance per unit area.
[0038] W represents the channel width of transistors M1 and M2;
[0039] L represents the channel length of transistors M1 and M2;
[0040] Vcom represents the first input voltage V in1 and the second input voltage V in2 Common-mode voltage;
[0041] Vs represents the voltage at the common source terminal;
[0042] V th Indicates the threshold voltage of the first input transistor M1 or the second input transistor M2;
[0043] Iss represents the bias current provided by the current source.
[0044] When the traditional differential pair is in an unbalanced state, that is, Vin=V in1 -V in2 =Vi(Vi≠0), then V in1 =Vcom+0.5*Vi, Vin2=Vcom-0.5*Vi. According to Kirchhoff's current law KCL, the first current I flowing through the first input transistor M1 is D1 and the second current I flowing through the second input transistor M2 D2 The sum must be equal to the bias current Iss. Ignoring the channel length modulation effect and the body effect, it can be written as:
[0045]
[0046] Subtracting formula (1) from formula (2) yields the following solution:
[0047]
[0048] Among them, V ov =V com -V s -V th ;
[0049] Vi represents the input voltage of the two input pairs of tubes in an unbalanced state;
[0050] △V S Indicates the change in common source voltage.
[0051] According to the above formula (3), the change of the common source voltage Vs of the differential pair in the unbalanced state is △V compared with the equilibrium state. S It is positive, that is, when the differential pair is in an unbalanced state, it is inevitable that the common source voltage Vs will increase.
[0052] Furthermore, when the conventional NMOS differential pair circuit is in an unbalanced state, the first current I D1 and the second current I flowing through the second input transistor M2 D2 The sum of will increase, that is, the required I D1 +I D2 Will increase. At this time, since the common source terminal Vs is connected to a current source, its current is equivalent to a fixed value, so it is necessary to raise the Vs voltage to reduce the required I D1 +I D2 The Vs lifting adjustment amount is larger than that of the differential pair structure of the present invention.
[0053] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a differential pair circuit with improved linearity is provided, which belongs to the field of integrated circuit technology. Figure 2 As shown, including:
[0054] A differential pair, which includes:
[0055] A first input transistor M1, at a first input voltage V in1 Under the action of S between;
[0056] A second input transistor M2, at a second input voltage V in2 Under the action of the controllable connection between the second node and the common source terminal V S between;
[0057] A bias tube M0, the source of which is connected to the common source terminal V S , and the type of bias tube is opposite to that of the differential pair, at a bias voltage V b Under the action of the controllable connection common source terminal V S .
[0058] Specifically, in this embodiment, the first input pair transistor M1 and the second input pair transistor M2 are used as the main input pair transistors of the differential pair, and the gate of the first input pair transistor M1 is connected to the first input voltage V in1 The gate of the second input pair tube M2 is connected to the second input voltage V in2 , the first input voltage V in1 and the second input voltage V in2 An input module (not shown in the figure) is provided. The source of the bias tube M0 is connected to the source of the first input pair tube M1 and the source of the second input pair tube M2. The bias tube M0 is used to provide tail current. The gate of the bias tube M0 is connected to the bias voltage V b , the bias voltage is given by the bias generating circuit below, the bias voltage V b Determined by the input common-mode voltage, the drain of the bias tube M0 can be connected to the ground terminal gnd, and its drain-drain voltage Vd is a fixed level; it can also be connected to an impedance device, and its drain-drain voltage Vd is a variable level.
[0059] As a preferred embodiment, the first input pair of pipes M1 and the second input pair of pipes M2 are of the same type.
[0060] As a preferred embodiment, the bias tube M0 is of opposite type to the first input pair tube M1;
[0061] The bias transistor M0 is of the opposite type to the second input pair transistor M2.
[0062] As a preferred embodiment, the first input pair transistor M1 is any one of an NMOS transistor, a PMOS transistor, an NPN bipolar junction transistor, a PNP bipolar junction transistor, a combination of an NMOS transistor and a resistor, or a combination of a PMOS transistor and a resistor.
[0063] As a preferred embodiment, the second input pair transistor M2 is any one of an NMOS transistor, a PMOS transistor, an NPN bipolar junction transistor, a PNP bipolar junction transistor, a combination of an NMOS transistor and a resistor, or a combination of a PMOS transistor and a resistor.
[0064] Specifically, the first input pair transistors M1 and the second input pair transistors M2 may be NMOS transistors, PMOS transistors, bipolar junction transistors (including NPN and PNP types), or other equivalent input pair transistors such as an NMOS transistor + resistor Res, a PMOS transistor + resistor Res, etc. The bias transistor M0 may be of a type opposite to that of the input pair transistors of the differential pair. For example, in the embodiment of the present invention, the input pair transistors are NMOS transistors, and the bias transistor M0 is a PMOS transistor.
[0065] As a preferred embodiment, when the differential pair is in an unbalanced state, the first input voltage V in1 Not equal to the second input voltage V in2 .
[0066] As a preferred embodiment, wherein Figure 3 As shown, it also includes:
[0067] A first resistor R1 is connected between the drain of the first input transistor M1 and the power supply terminal Vdd, with the drain of the first input transistor serving as the first node;
[0068] The second resistor R2 is connected between the drain of the second input transistor M2 and the power supply terminal Vdd, with the drain of the second input transistor serving as the second node.
[0069] Specifically, in this embodiment, the first resistor R1 and the second resistor R2 serve as loads for converting the output current into voltage.
[0070] As a preferred embodiment, wherein Figure 3 As shown, it also includes: a bias generating circuit for generating a bias voltage, and the bias generating circuit specifically includes:
[0071] The first transistor Mb0 has a gate and a drain connected to the power supply terminal Vdd via a reference current source, and a source connected to the ground terminal gnd. The reference current source is used to provide a bias current I b ;
[0072] a second transistor Mb1, wherein a gate of the second transistor Mb1 is connected to the gate of the first transistor Mb0, a source of the second transistor Mb1 is connected to the ground terminal gnd, a drain of the second transistor Mb1 is connected to a first connection node, and a bias voltage is output from the first connection node;
[0073] a third transistor Mb2, wherein a gate and a drain of the third transistor Mb2 are connected to the first connection node;
[0074] The fourth transistor Mb3 has a gate connected to a gate common mode voltage Vcom, a source connected to the source of the third transistor Mb2, and a drain connected to the power supply terminal Vdd.
[0075] As a preferred embodiment, the gate common mode voltage Vcom is the first input voltage V in1 and the second input voltage V in2 common-mode voltage.
[0076] It should be noted that if the bias transistor of the present invention is of the same type as the differential pair, with its drain connected to the common source and its source grounded, the bias transistor's current has a very weak modulation relationship with the voltage at the common source of the differential pair. Therefore, the bias transistor can be roughly considered equivalent to a tail current source with a fixed current magnitude, and thus cannot achieve the linearity improvement effect of the present invention.
[0077] Example 1
[0078] like Figure 2 As shown, the differential pair of the present invention is an NMOS differential pair, that is, the first input pair transistor M1 and the second input pair transistor M2 are NMOS transistors, and the bias transistor M0 is a PMOS transistor.
[0079] According to Kirchhoff's current law KCL of the traditional NMOS differential pair circuit, when the NMOS differential pair is in an unbalanced state, the gate voltages of the two input pairs change, resulting in the sum of the drain currents I D1 +I D2 Increase, the voltage Vs at the common source terminal will inevitably increase. However, since the traditional differential pair provides a fixed bias current, and the bias current provided by the bias tube M0 of the present invention changes with the change of the common source terminal voltage, the change of the common source terminal voltage Vs of the circuit of the present invention is smaller than that of the traditional differential pair circuit, and the sum of the drain terminal currents flowing through the two input pair tubes increases. That is, due to the increase of the voltage Vs at the common source terminal, the absolute value of the gate-source voltage Vgs of the bias tube M0 becomes larger, and the bias current Iss increases, thereby avoiding further deterioration of the output linearity, thereby improving the output current Io (i.e., I D1 -I D2 ) and the input voltage Vi (ie V in1 -V in2 ) between the linearity.
[0080] Example 2
[0081] Compared with the first embodiment, the second embodiment of the present invention changes the first input pair transistor M1, the second input pair transistor M2 and the bias transistor M0, that is, the first input pair transistor M1 and the second input pair transistor M2 are PMOS transistors, and the bias transistor M0 is an NMOS transistor. The connection method is the same as that of the first embodiment and will not be repeated here.
[0082] Since the current flow directions of the PMOS differential pair and the NMOS differential pair are exactly opposite, based on the KCL principle, it can be seen that the change in the common source voltage Vs of the PMOS differential pair in the unbalanced state is △V compared to the equilibrium state. S It is negative, that is, the common-source voltage Vs decreases when the PMOS differential pair is in an unbalanced state. The formula will not be listed here for explanation.
[0083] Since the traditional differential pair provides a fixed bias current, and the bias transistor of the present invention can provide a bias current that varies with the differential mode input voltage, the drop in the common source terminal voltage of the PMOS differential pair of the present invention in the unbalanced state is smaller, and the sum of the drain terminal currents flowing through the two input pair transistors increases. That is, due to the drop in the voltage Vs at the common source terminal, the absolute value of the gate-source voltage Vgs of the bias transistor M0 increases, and the bias current Iss increases, thereby avoiding further deterioration of the output linearity, thereby improving the output current Io (i.e., I D1 -I D2 ) and the input voltage Vi (ie V in1 -V in2 ) between the linearity.
[0084] The above technical solution has the following advantages or beneficial effects: the type of the bias tube is set to be opposite to the type of the differential pair, and the source of the bias tube is connected to the common source terminal of the differential pair. The bias tube provides a bias current that can change with the differential input voltage to the two input pairs of the differential pair. Compared with the traditional differential pair circuit, the change of the common source terminal voltage Vs of the circuit of the present invention is smaller in the unbalanced state, and the sum of the drain currents flowing through the two input pairs of tubes increases, thereby improving the linearity between the output current Io and the input voltage Vi.
[0085] The above description is only a preferred embodiment of the present invention and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included in the protection scope of the present invention.
Claims
1. A differential pair circuit with improved linearity, characterized in that: include: A differential pair, the differential pair comprising: a first input transistor pair, controllably connected between a first node and a common source terminal under the action of a first input voltage; a second input pair of transistors controllably connected between a second node and the common source terminal under the action of a second input voltage; a bias transistor, the source of which is connected to the common source terminal, and the type of the bias transistor is opposite to that of the differential pair, and the bias transistor is controllably connected to the common source terminal under the action of a bias voltage that varies with the common-mode voltage of the input voltage of the differential pair; The device further comprises: a bias generating circuit for generating the bias voltage, wherein the bias generating circuit specifically comprises: a first transistor, wherein a gate and a drain of the first transistor are connected to a power supply terminal via a reference current source, and a source of the first transistor is connected to a ground terminal; a second transistor, wherein a gate of the second transistor is connected to the gate of the first transistor, a source of the second transistor is connected to the ground terminal, a drain of the second transistor is connected to a first connection node, and the bias voltage is output from the first connection node; a third transistor, wherein a gate and a drain of the third transistor are connected to the first connection node; A fourth transistor, wherein a gate of the fourth transistor is connected to a gate common mode voltage, a source of the fourth transistor is connected to the source of the third transistor, and a drain of the fourth transistor is connected to the power supply terminal.
2. The differential pair circuit with improved linearity according to claim 1, wherein: The first input pair of tubes and the second input pair of tubes are of the same type.
3. The differential pair circuit with improved linearity according to claim 1, wherein: The bias tube is of opposite type to the first input pair tube; The bias transistor is of opposite type to the second input pair transistors.
4. The differential pair circuit with improved linearity according to claim 1, wherein: The first input pair of transistors is any one of an NMOS transistor, a PMOS transistor, an NPN bipolar junction transistor, a PNP bipolar junction transistor, a combination of an NMOS transistor and a resistor, or a combination of a PMOS transistor and a resistor.
5. The differential pair circuit with improved linearity according to claim 1, wherein: The second input pair of transistors is any one of an NMOS transistor, a PMOS transistor, an NPN bipolar junction transistor, a PNP bipolar junction transistor, a combination of an NMOS transistor and a resistor, or a combination of a PMOS transistor and a resistor.
6. The differential pair circuit with improved linearity according to claim 1, wherein: When the differential pair is in an unbalanced state, the first input voltage is not equal to the second input voltage.
7. The differential pair circuit with improved linearity according to claim 1, wherein: Also includes: A first resistor is connected between the drain of the first input pair transistor and the power supply terminal, with the drain of the first input pair transistor serving as the first node; The second resistor is connected between the drain of the second input pair of transistors and the power supply terminal, and the drain of the second input pair of transistors serves as the second node.
8. The differential pair circuit with improved linearity according to claim 1, wherein: The gate common mode voltage is a common mode voltage of the first input voltage and the second input voltage.