A high-reliability latch with dual-node flip tolerance

Abstract

The present invention belongs to the field of semiconductor and integrated circuit technology, specifically a high-reliability latch that tolerates dual-node upsets. It features low cost and high reliability. Its core is a cross-coupled Schmitt trigger structure, with four additional high-threshold transistors integrated to mitigate the impact of transient voltage changes on adjacent transistors, achieving DNU fault tolerance. The latch can be widely applied in various fields requiring high reliability. Compared to existing technologies, the present invention offers advantages in that, through the cross-coupled Schmitt trigger and four high-threshold transistors, it effectively tolerates both dual-node upsets and single-node upsets, while also exhibiting a low power-delay product.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit multi-node flip-resistant reinforced fault-tolerant design, and in particular relates to a high-reliability latch that tolerates dual-node flips. Background Art

[0002] With the continuous advancement of CMOS processes, transistor feature sizes and operating voltages are shrinking. While this improves circuit performance, it also increases circuit susceptibility to radiation exposure. Sequential elements within circuits, such as latches and registers, are becoming increasingly sensitive to single-event effects (SEEs). Their contribution to the overall circuit soft error rate (SER) is now comparable to that of SRAM circuits. This is because the shrinking distance between devices exacerbates the charge sharing effect, causing multiple sensitive nodes in the unit circuit to simultaneously collect charge deposited by high-energy particles, resulting in multiple node upsets (MNUs). Furthermore, the continuous reduction in supply voltage and device parasitic capacitance reduces the critical charge (Qcrit) for a single-event upset (SEU) to occur in the circuit, which in turn increases the probability of SEUs occurring in sequential elements. Traditional hardening techniques for single-node upsets (SNUs) are no longer effective.

[0003] In existing sequential cell hardening designs, classic single-node upset (SNU)-tolerant sequential cells like DICE have significantly reduced fault tolerance in nanometer-scale processes. Literature on sequential cells tolerant to multiple-node upsets (MNU) is relatively limited, and existing latches or registers of this type suffer from two major issues: high area cost and significant power consumption. For example, hardened latches such as DONUT, Delta-DICE, and DNURHL, which utilize classic C-cells or DICE cells for redundant design, incur area costs several or even dozens of times greater than those of standard registers. Therefore, a dual-node upset-tolerant latch that can overcome this significant circuit parameter overhead is particularly important. Summary of the Invention

[0004] In response to the shortcomings of the existing technology, the present invention aims to provide a highly reliable latch that tolerates dual-node upsets. The latch's core structure is a cross-coupled Schmitt trigger structure integrated with four high-threshold transistors. The high-threshold transistors can mitigate the effects of transient voltage changes on adjacent transistors, achieving DNU fault tolerance. The latch has low cost and high reliability, resolving the issues of excessive area and power consumption associated with existing multi-node upset-resistant reinforced latches.

[0005] The technical solution of the present invention is specifically described as follows.

[0006] A high-reliability latch tolerant to dual-node flipping, comprising an integrated structure of a cross-coupled Schmitt trigger and four high-threshold transistors, three transmission gates, a clock-gated inverter for controlling input and output, and an inverter for generating a reverse clock signal; the inverter for generating the reverse clock signal has a signal input connected to a clock input CLK of the high-reliability latch tolerant to dual-node flipping, and a signal output outputting a reverse clock signal CLKB for controlling the conduction of the three transmission gates; the clock-gated inverter has an input connected to an output port E of the integrated structure of the cross-coupled Schmitt trigger and four high-threshold transistors, and an output connected to an output port Q of the high-reliability latch tolerant to dual-node flipping; wherein:

[0007] The integrated structure of the cross-coupled Schmitt trigger and four high-threshold transistors consists of eight PMOS transistors and eight NMOS transistors. The eight PMOS transistors are respectively a first PMOS transistor Tp1, a second PMOS transistor Tp2, a third PMOS transistor Tp3, a fourth PMOS transistor Tp4, a fifth PMOS transistor Tp5, a sixth PMOS transistor Tp6, a seventh PMOS transistor Tp7, and an eighth PMOS transistor Tp8; the eight NMOS transistors are respectively a first NMOS transistor Tn1, a second NMOS transistor Tn2, a third NMOS transistor Tn3, a fourth NMOS transistor Tn4, a fifth NMOS transistor Tn5, a sixth NMOS transistor Tn6, a seventh NMOS transistor Tn7, and an eighth NMOS transistor Tn8.

[0008] Tp6, Tp8, Tn5 and Tn7 are high-threshold transistors, and Tp1, Tp2, Tp3, Tp4, Tp5, Tp7, Tn1, Tn2, Tn3, Tn4, Tn6 and Tn8 form a cross-coupled Schmitt trigger; wherein:

[0009] The gate of Tp1, the gate of Tn1, the drain of Tp3, the source of Tp4, and the drain of Tp7 are connected together, and the connection point is marked as node D; the gate of Tp2, the gate of Tn2, the drain of Tn3, the source of Tn4, and the drain of Tn8 are connected together, and the connection point is marked as node F; the gate of Tp3, the gate of Tn3, the drain of Tp1, the source of Tp2, and the drain of Tp5 are connected together, and the connection point is marked as node A; the gate of Tp4, the gate of Tn4, the drain of Tn1, the source of Tn2, and the drain of Tn6 are connected together, and the connection point is marked as node C;

[0010] The drain of Tp2, the drain of Tp6, the source of Tn1, and the source of Tn5 are connected together, and the connection point is marked as node B; the drain of Tp4, the drain of Tp8, the source of Tn3, and the source of Tn7 are connected together, and the connection point is the output port of the integrated structure of the cross-coupled Schmitt trigger and the four high-threshold transistors, which is marked as node E;

[0011] The gate of Tp5 and the source of Tp6 are connected together; the gate of Tp7 and the source of Tp8 are connected together; the drain of Tn5 and the gate of Tn6 are connected together; the drain of Tn7 and the gate of Tn8 are connected together; the source of Tp1, the source of Tp3, the source of Tn6, and the source of Tn8 are connected to the power supply; the drain of Tn2, the drain of Tn4, the drain of Tp5, and the drain of Tp7 are grounded; the substrates of all PMOS tubes are connected to the power supply, and the substrates of all NOMS tubes are grounded.

[0012] In the present invention, the three transmission gates have the same clock, namely the first transmission gate TG1, the second transmission gate TG2 and the third transmission gate TG3. The signal input ends of TG1 and TG2 are connected to the signal input end of TG3, and the connection point serves as the data input end IN of the latch. The output end of the first transmission gate TG1 is connected to the A node, and the output end of the second transmission gate TG2 is connected to the C node, which serve as inputs of other structures respectively; the output end of the third transmission gate TG3 is connected to the output port Q of the latch.

[0013] In the present invention, the inverter is composed of Tp1 and Tn1, the source of Tp1 is connected to the power supply, the drain is connected to the drain of Tn1 as the output OUT, the gate of Tp1 is connected to the gate of Tn1 as the input IN, and the source of Tn1 is grounded.

[0014] In the present invention, the clock-gated inverter includes an input terminal IN, Tp1, Tp2, Tn1 and Tn2 of the clock-gated inverter and an output terminal OUT of the clock-gated inverter; wherein: the gates of Tp1 and Tn1 are connected to the clock input terminal CLK of the latch; the gates of Tp2 and Tn2 are connected to the input terminal IN of the clock-gated inverter; the source of Tp1 is connected to the power supply, and the drain is connected to the source of Tp2; the drain of Tp2 is connected to the source of Tn1, and the connection point is the output terminal OUT of the clock-gated inverter; the drain of Tn1 is connected to the source of Tn2, and the drain of Tn2 is grounded.

[0015] In the present invention, during CLK=0, the three transmission gates are open, the clock-gated inverter is closed, and the entire high-reliability latch that tolerates dual-node flipping is in a transparent state. At this time, the output port Q of the latch is driven only by the transmission gate, and the delay from the latch input port IN to the output port Q is greatly reduced. During the CLK=1 stage, the three transmission gates are closed, the clock-gated inverter is open, and the entire latch is in a holding stage, which is also a stage where erroneous flipping may occur.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The present invention provides a high-reliability latch that tolerates dual-node flipping. The integrated structure of a cross-coupled Schmitt trigger and four high-threshold transistors in the circuit uses a Schmitt trigger (ST) as its basic structural unit. The threshold voltage of the Schmitt trigger varies when the output flips from a high voltage to a low voltage or vice versa. When the input signal to the Schmitt trigger is small, the output signal remains stable at its original state. Simultaneously, the conventional threshold transistors in the coupled structure are replaced with high-threshold voltage transistors, enhancing the reliability of the Schmitt trigger structure. Even large voltage disturbances will not affect the on or off state of the eight stacked transistors, and the cross-coupled Schmitt trigger structure can perform mutual error correction.

[0018] The high-reliability latch provided by the present invention has four transistors introduced into its circuit that are normally-on high-threshold transistors, which are used to reduce the influence of a flip node on an adjacent sensitive node.

[0019] The high-reliability latch of the present invention can effectively tolerate the influence caused by the flipping of one or two nodes in the structure, and has low power consumption and area overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a diagram of a traditional Schmitt trigger.

[0021] Figure 2 FIG. 4 is a diagram of a high-reliability latch that tolerates double-node upset according to the present invention.

[0022] Figure 3 Schematic diagram of the structure of the inverter in the circuit structure of the present invention.

[0023] Figure 4 Schematic diagram of the transmission gate structure in the circuit structure of the present invention.

[0024] Figure 5 1 is a structural diagram of a clock-gated inverter in the circuit structure of the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0026] like Figure 1 As shown, a traditional Schmitt trigger consists of three N-type metal oxide semiconductors (NMOS) and three P-type metal oxide semiconductors (PMOS): the first PMOS (Tp1), the second PMOS (Tp2), and the third PMOS (Tp3), and the first NMOS (Tn1), the second NMOS (Tn2), and the third NMOS (Tn3). The three PMOS transistors generate the low-threshold switching voltage, while the three NMOS transistors generate the high-threshold switching voltage. Connecting the third PMOS (Tp3) and the third NMOS (Tn3) to the output provides feedback to eliminate excess noise at the output when the input signal amplitude does not change by more than the switching threshold voltage. This ensures that the output signal remains stable when the input signal IN does not change significantly.

[0027] Figure 2 The core of the invented high-reliability latch, which tolerates dual-node flipping, is an integrated structure of a cross-coupled Schmitt trigger and four high-threshold transistors. In addition, there are three transmission gates and a clock-gated inverter to control the input and output, and an inverter to generate the inverse clock signal.

[0028] like Figure 3 As shown, the inverter consists of a PMOS transistor and an NMOS transistor. The source of the PMOS transistor (Tp1) is connected to VDD, and the drain is connected to the drain of the NMOS transistor (Tn1) as the output OUT. The gate of the PMOS transistor (Tp1) is connected to the gate of the NMOS transistor (Tn1) as the input IN, and the source of the NMOS transistor (Tn1) is grounded (GND). The inverter is connected to the clock signal input terminal CLK of the latch and outputs the inverse of the clock signal CLKB, which is used to control the conduction of the transmission gate.

[0029] like Figure 4 As shown, three transmission gates have the same clock, namely the first transmission gate (TG1), the second transmission gate (TG2), and the third transmission gate (TG3), and their signal input ends are all the data input ends IN of the latch. The output end of the first transmission gate (TG1) is connected to the A node, and the output end of the second transmission gate (TG2) is connected to the C node, respectively serving as inputs of other structures; the output end of the third transmission gate (TG3) is connected to the output port Q of the latch.

[0030] like Figure 5As shown, the clock-gated inverter is composed of two PMOS transistors and two NMOS transistors, namely a first PMOS transistor (Tp1), a second POMOS transistor (Tp2), a first NMOS transistor (Tn1), and a second NMOS transistor (Tn2); wherein the gates of the first PMOS transistor (Tp1) and the first NMOS transistor (Tn1) are connected to the clock input terminal CLK of the latch; the gates of the second POMOS transistor (Tp2) and the second NMOS transistor (Tn2) are connected to the input terminal IN of the clock-gated inverter; the source of the first PMOS transistor (Tp1) is connected to the power supply (VDD), and the drain is connected to the source of the second POMOS transistor (Tp2); the drain of the second POMOS transistor (Tp2) is connected to the source of the first NMOS transistor (Tn1), and the connection point is the output terminal OUT of the clock-gated inverter; the drain of the first NMOS transistor (Tn1) is connected to the source of the second NMOS transistor (Tn2), and the drain of the second NMOS transistor (Tn2) is connected to ground. The input port of the clock-gated inverter is connected to the output port E of the integrated structure of a cross-coupled Schmitt trigger and four high-threshold transistors. The output port is connected to the output port of the latch. During CLK = 0, the three transmission gates are open, the clock-gated inverter is closed, and the entire latch is in a transparent state. At this time, the output port Q of the latch is driven only by the transmission gates, greatly reducing the delay from the latch input port IN to the output port Q. During CLK = 1, the three transmission gates are closed, the clock-gated inverter is open, and the entire latch is in the hold phase, which is also the stage where false flips may occur.

[0031] The integrated structure of the cross-coupled Schmitt trigger and four high-threshold transistors consists of eight PMOS transistors and eight NMOS transistors, wherein the eight PMOS transistors are the first PMOS transistor (Tp1), the second PMOS transistor (Tp2), the third PMOS transistor (Tp3), the fourth PMOS transistor (Tp4), the fifth PMOS transistor (Tp5), the sixth PMOS transistor (Tp6), the seventh PMOS transistor (Tp7), and the eighth PMOS transistor (Tp8); and the eight NMOS transistors are the first NMOS transistor (Tn1), the second NMOS transistor (Tn2), the third NMOS transistor (Tn3), the fourth NMOS transistor (Tn4), the fifth NMOS transistor (Tn5), the sixth NMOS transistor (Tn6), the seventh NMOS transistor (Tn7), and the eighth NMOS transistor (Tn8).

[0032] The gate of the first PMOS transistor (Tp1), the gate of the first NMOS transistor (Tn1), the drain of the third POMS transistor (Tp3), the source of the fourth POMS transistor (Tp4) and the drain of the seventh POMS transistor (Tp7) are connected together, and the connection point is marked as node D; the gate of the second PMOS transistor (Tp2), the gate of the second NMOS transistor (Tn2), the drain of the third NMOS transistor (Tn3), the source of the fourth NMOS transistor (Tn4) and the drain of the eighth NMOS transistor (Tn8) are connected together, and the connection point is marked as node F; the gate of the third PMOS transistor (Tp3), the gate of the third NMOS transistor (Tn3), the drain of the first POMS transistor (Tp1), the source of the second POMS transistor (Tp2) and the drain of the fifth POMS transistor (Tp5) are connected together, and the connection point is marked as node A; the gate of the fourth PMOS transistor (Tp4), the gate of the fourth NMOS transistor (Tn4), the drain of the first NMOS transistor (Tn1), the source of the second NMOS transistor (Tn2) and the drain of the sixth NMOS transistor (Tn6) are connected together, and the connection point is marked as node C.

[0033] The drain of the second PMOS transistor (Tp2), the drain of the sixth PMOS transistor (Tp6), the source of the first NOMS transistor (Tn1), and the source of the fifth NOMS transistor (Tn5) are connected together, and the connection point is marked as node C; the drain of the fourth PMOS transistor (Tp4), the drain of the eighth PMOS transistor (Tp8), the source of the third NOMS transistor (Tn3), and the source of the seventh NOMS transistor (Tn7) are connected together, and the connection point is marked as node E.

[0034] In addition, the gate of the fifth PMOS transistor (Tp5) and the source of the sixth PMOS transistor (Tp6) are connected together; the gate of the seventh PMOS transistor (Tp7) and the source of the eighth PMOS transistor (Tp8) are connected together; the drain of the fifth NMOS transistor (Tn5) and the gate of the sixth NMOS transistor (Tn6) are connected together; and the drain of the seventh NMOS transistor (Tn7) and the gate of the eighth NMOS transistor (Tn8) are connected together. The source of the first PMOS transistor (Tp1), the source of the third PMOS transistor (Tp3), the source of the sixth NMOS transistor (Tn6), and the source of the eighth NMOS transistor (Tn8) are connected to a power supply; the drain of the second NMOS transistor (Tn2), the drain of the fourth NMOS transistor (Tn4), the drain of the fifth PMOS transistor (Tp5), and the drain of the seventh PMOS transistor (Tp7) are grounded. The substrates of all PMOS transistors are connected to a power supply, and the substrates of all NMOS transistors are grounded.

[0035] The following first describes the working principle of the high-reliability latch that tolerates dual-node flips provided in this example when no node flips occur. The specific working principle is as follows:

[0036] During CLK = 0, the three transmission gates are open, the clock-gated inverter is closed, and the entire latch is in a transparent state. Since output Q is driven solely by the transmission gates, the delay from input IN to output Q is significantly reduced. During CLK = 1, the three transmission gates are closed, the clock-gated inverter is open, and the entire latch is in the hold phase, which is also the critical stage for false flips.

[0037] Next, the fault tolerance mechanism of the latch provided in this embodiment working in the latch mode is discussed:

[0038] In order to illustrate the fault tolerance mechanism of the latch in the holding phase, the case of input IN=1 is taken as an example. The Tp3 and Tp4 transistors are turned off, while Tn3 and Tn4 are turned on after the input signal is transmitted directly from the transmission gate to node A and node C. Therefore, the E and F nodes are at a low voltage level. In addition, due to the synergistic feedback effect of the Tp7 and Tp8 transistors, the D node is also at a low voltage level. It is not difficult to infer that due to the existence of the coupling structure, the A, B, and C nodes will be at a high voltage level. Correspondingly, the Tp1 and Tp2 transistors are turned on, and Tn1 and Tn2 are cut off. Then, from the working status of different transistors, when IN=1, the four nodes B, C, D, and E are key sensitive nodes. If enough charge is collected, it will cause a flip error. In other words, there are four cases for SNU. For DNU, due to the large physical layout spacing of the node pairs, only<B,C> and<D,E> Two situations.

[0039] Next, we will analyze the fault tolerance mechanism of single-node flipping SNU and dual-node flipping DNU.

[0040] 1)<B, C> Both nodes flip from high to low simultaneously. Node C flips from high to low, turning Tp4 on and Tn4 off. This does not affect the states of D, E, and F, which remain low. The stable state of node D means Tp1 remains on. Simultaneously, the flip of node B causes Tp5 to turn on. If the normally-on transistor Tp6 were absent, the voltage at node B would be directly transferred to the gate of Tp5, causing Tp5 to operate in the linear region. This means that node A would be forced directly to GND, turning Tp3 on and flipping the latch's output state accordingly. However, due to the presence of the normally-on transistor Tp6, the gate voltage of Tp5 is slightly above GND, placing Tp5 in the saturation region. The P-stack structure formed by Tp5, Tp1, and Tp1 and Tp2 causes node A to enter a weak "1" state. Tp3 remains off, so nodes D, E, and F remain unchanged. This P-stack structure containing high-threshold transistors is the key design of the DNU.

[0041] 2)<D, E> Both nodes flip from low voltage to high voltage simultaneously. Similar to the fault tolerance principle in case 1, the flip of node E does not change the states of nodes A, B, and C. Furthermore, when node E flips, node F is in a weak "0" state due to the N-stacked structure, meaning that Tp2 remains off and the output remains unchanged.

[0042] 3) <c>A single node flips from high to low voltage. Tp4 turns on, but nodes D, E, and F remain unchanged. This means Tn1 is off, so the flip of node C has no effect on the states of nodes A and B. Feedback is sent to the right half of the latch, and nodes D, E, F and the output remain in their original states.

[0043] 4) A single node flips from high voltage to low voltage. TP5 turns on, but as previously analyzed, due to the P-stacked structure, node A is in a weak "1" state, causing TP3 to remain "off" and the output unchanged.

[0044] 5) <d>A single node flips from low to high voltage. Tn1 turns on, and Tp1 turns off. Meanwhile, nodes A, B, and C remain low. Therefore, Tp4 remains off, and the flip of node D has no effect on nodes E and F. This means that output Q remains in its original state.

[0045] 6) <e>A single node flips from low to high voltage. Similar to Case 4, Tn8 will be turned on. Due to the N-stacked structure comprising Tn3, Tn4, Tn7, and Tn8, node F will remain in a weak "0" state. Consequently, Tn2 will remain "off." The three sensitive nodes on the left will maintain their original states. Feedback to the right half of the latch also maintains the output in its original state.

[0046] The above fault tolerance mechanism is based on the case where the latch value is "1". For the case where the latch value is "0", due to the symmetric nature of this structure, the sensitive nodes will become four nodes A, B, E, and F. Similarly, SNU also has four cases, namely 、 、 <e>and <f>For DNU, there are two cases,<A, B> and<E, F> Its fault tolerance mechanism is the same as that of maintaining "1", except that the P stacking structure consists of Tp3, Tp4, Tp7, and Tp8, and the N stacking structure consists of Tn1, Tn2, Tn5, and Tn6.

[0047] In summary, the present invention provides a latch circuit design that can tolerate dual-node flips, thereby improving the reliability of the latch circuit. Analysis and verification have shown that the latch can tolerate not only dual-node flips but also single-node flips. Furthermore, the use of a smaller number of transistors and clock gating technology reduces the latch's area overhead and power consumption. This invention is suitable for high-reliability integrated circuits and systems, and can be widely used in fields such as aerospace, where high latch reliability and power requirements are required.

[0048] The above examples are only for illustrating the technical concept and features of the present invention. Their purpose is to more clearly explain the purpose, technical solutions and advantages of the present invention, and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.< / f> < / e> < / e> < / d> < / c>

Claims

1. A high-reliability latch that tolerates double-node upset, characterized in that: It includes an integrated structure of a cross-coupled Schmitt trigger and four high-threshold transistors, three transmission gates, a clock-gated inverter, and an inverter; the signal input end of the inverter is connected to the clock input end CLK of a high-reliability latch that tolerates dual-node flipping, and the signal output end outputs an inverted clock signal CLKB for controlling the conduction of the three transmission gates; the clock-gated inverter has an input port connected to the output port E of the integrated structure of the cross-coupled Schmitt trigger and four high-threshold transistors, and an output port connected to the output port Q of the high-reliability latch that tolerates dual-node flipping; wherein: The integrated structure of the cross-coupled Schmitt trigger and four high-threshold transistors consists of eight PMOS transistors and eight NMOS transistors. The eight PMOS transistors are respectively a first PMOS transistor Tp1, a second PMOS transistor Tp2, a third PMOS transistor Tp3, a fourth PMOS transistor Tp4, a fifth PMOS transistor Tp5, a sixth PMOS transistor Tp6, a seventh PMOS transistor Tp7, and an eighth PMOS transistor Tp8. The eight NMOS transistors are respectively a first NMOS transistor Tn1, a second NMOS transistor Tn2, a third NMOS transistor Tn3, a fourth NMOS transistor Tn4, a fifth NMOS transistor Tn5, a sixth NMOS transistor Tn6, a seventh NMOS transistor Tn7, and an eighth NMOS transistor Tn8. Tp6, Tp8, Tn5, and Tn7 are high-threshold transistors. Tp1, Tp2, Tp3, Tp4, Tp5, Tp7, Tn1, Tn2, Tn3, Tn4, Tn6, and Tn8 form a cross-coupled Schmitt trigger. The gate of Tp1, the gate of Tn1, the drain of Tp3, the source of Tp4, and the drain of Tp7 are connected together, and the connection point is marked as node D; the gate of Tp2, the gate of Tn2, the drain of Tn3, the source of Tn4, and the drain of Tn8 are connected together, and the connection point is marked as node F; the gate of Tp3, the gate of Tn3, the drain of Tp1, the source of Tp2, and the drain of Tp5 are connected together, and the connection point is marked as node A; the gate of Tp4, the gate of Tn4, the drain of Tn1, the source of Tn2, and the drain of Tn6 are connected together, and the connection point is marked as node C; The drain of Tp2, the drain of Tp6, the source of Tn1, and the source of Tn5 are connected together, and the connection point is marked as node B; the drain of Tp4, the drain of Tp8, the source of Tn3, and the source of Tn7 are connected together, and the connection point is the output port of the integrated structure of the cross-coupled Schmitt trigger and the four high-threshold transistors, marked as node E; The gate of Tp5 and the source of Tp6 are connected together; the gate of Tp7 and the source of Tp8 are connected together; the drain of Tn5 and the gate of Tn6 are connected together; the drain of Tn7 and the gate of Tn8 are connected together; the source of Tp1, the source of Tp3, the source of Tn6, and the source of Tn8 are connected to the power supply; the drain of Tn2, the drain of Tn4, the drain of Tp5, and the drain of Tp7 are grounded; the substrates of all PMOS tubes are connected to the power supply, and the substrates of all NOMS tubes are grounded.

2. The high-reliability latch capable of withstanding double-node upsets according to claim 1, wherein: The three transmission gates have the same clock, namely the first transmission gate TG1, the second transmission gate TG2 and the third transmission gate TG3. The signal input ends of TG1 and TG2 are connected to the signal input end of TG3, and the connection point serves as the data input end IN of a high-reliability latch that tolerates double-node flips. The output end of the first transmission gate TG1 is connected to the A node, and the output end of the second transmission gate TG2 is connected to the C node, respectively serving as the input of the integrated structure of the cross-coupled Schmitt trigger and the four high-threshold transistors; the output end of the third transmission gate TG3 is connected to the output port Q of the latch.

3. The high-reliability latch capable of withstanding double-node upsets according to claim 1, wherein: The inverter is composed of Tp1 and Tn1. The source of Tp1 is connected to the power supply, the drain is connected to the drain of Tn1 as the output OUT, the gate of Tp1 is connected to the gate of Tn1 as the input IN, and the source of Tn1 is grounded.

4. The high-reliability latch capable of withstanding double-node upsets according to claim 1, wherein: The clock-gated inverter includes an input terminal IN, Tp1, Tp2, Tn1 and Tn2 of the clock-gated inverter and an output terminal OUT of the clock-gated inverter; wherein: the gates of Tp1 and Tn1 are connected to the clock input terminal CLK of the latch; the gates of Tp2 and Tn2 are connected to the input terminal IN of the clock-gated inverter; the source of Tp1 is connected to the power supply, and the drain is connected to the source of Tp2; the drain of Tp2 is connected to the source of Tn1, and the connection point is the output terminal OUT of the clock-gated inverter; the drain of Tn1 is connected to the source of Tn2, and the drain of Tn2 is grounded.

5. The high-reliability latch capable of withstanding double-node upsets according to claim 1, wherein: During CLK=0, three The transmission gates are opened, the clock-gated inverter is closed, and the entire high-reliability latch that tolerates dual-node flips is in a transparent state. At this time, the output port Q of the latch is only driven by the transmission gate, and the delay from the input port IN of the latch to the output port Q will be greatly reduced. In the CLK=1 stage, the three transmission gates are closed, the clock-gated inverter is opened, and the entire latch is in the holding stage, which is also the stage where erroneous flips may occur.

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