Detection chip, temperature detection system and humidity detection system

Abstract

This invention provides a detection chip, a temperature detection system, and a humidity detection system. By utilizing the chip's existing I / O structure's output drive circuit and input Schmitt trigger circuit, along with a digital control logic module and peripheral sensors, temperature and humidity testing functions can be achieved. The structure is simple and easy to implement, requires fewer additional circuit components, improves testing accuracy, and the reference resistor can be designed inside the chip, resulting in a smaller area and lower cost.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to a detection chip, a temperature detection system, and a humidity detection system. Background Technology

[0002] Temperature and humidity detection are two of the most common detection tasks in the field of intelligent measurement and control. Traditional temperature and humidity detection circuits mainly have two implementation methods. One method uses a bandgap reference circuit to generate a reference voltage VREF, which is then divided by a thermistor and a reference resistor. The voltage signal after voltage division is then converted by an A / D converter and the corresponding temperature is found in a lookup table (ROM). The disadvantage of this method is that the bandgap reference voltage VREF is easily affected by changes in power supply voltage and external temperature, which in turn affects the accuracy of the final detection. In addition, the detection accuracy is highly dependent on the stability and accuracy of the A / D conversion, resulting in low reliability.

[0003] Another approach is to use an RC oscillation circuit. First, a reference resistor oscillates, and the time required to count the oscillations up to value A is recorded. Then, a thermistor oscillates, and the number of oscillations within the same time frame is recorded. The corresponding temperature or humidity is then obtained by looking up a table. Compared to the first approach, this method offers higher detection accuracy, is independent of power supply voltage, does not require A / D conversion or a bandgap reference, and is more stable. However, existing RC oscillation circuits all require additional analog circuitry to achieve resistance / capacitance-frequency conversion. Furthermore, the discharge time is very short compared to the charging time; insufficient discharge or potential instability can lead to unstable oscillation frequencies, resulting in high cost, complex circuitry, and poor stability.

[0004] Therefore, how to reduce costs while ensuring the accuracy of temperature and humidity detection has become one of the problems that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a detection chip, a temperature detection system, and a humidity detection system to solve the problems of low accuracy, complex circuitry, and high cost in the prior art for temperature and humidity detection.

[0006] To achieve the above and other related objectives, the present invention provides a detection chip, the detection chip comprising at least:

[0007] The first I / O structure includes a first Schmitt trigger circuit and a first I / O pin; the input terminal of the first Schmitt trigger circuit is connected to the first I / O pin, the output terminal is connected to the input terminal of an inverter, and the enable terminal is connected to a first enable signal; the inverter outputs an oscillation signal.

[0008] The second IO structure includes a first driving circuit and a second IO pin; the input terminal of the first driving circuit is connected to the output terminal of the inverter, the output terminal is connected to the second IO pin, and the enable terminal is connected to a second enable signal.

[0009] The third IO structure includes a second driving circuit and a third IO pin; the input of the second driving circuit is connected to the output of the inverter, the output is connected to the third IO pin, and the enable is connected to a third enable signal.

[0010] To achieve the above and other related objectives, the present invention provides a detection chip, the detection chip comprising at least:

[0011] The fourth IO structure includes a second Schmitt trigger circuit and a fourth IO pin; the input of the second Schmitt trigger circuit is connected to the fourth IO pin, the output is connected to the first input of a NOR gate, and the enable is connected to a fourth enable signal; the NOR gate outputs an oscillation signal.

[0012] The fifth IO structure includes a third Schmitt trigger circuit and a fifth IO pin; the input terminal of the third Schmitt trigger circuit is connected to the fifth IO pin, the output terminal is connected to the second input terminal of the NOR gate, and the enable terminal is connected to the fifth enable signal.

[0013] The sixth IO structure includes a third driving circuit and a sixth IO pin; the input terminal of the third driving circuit is connected to the output terminal of the NOR gate, the output terminal is connected to the sixth IO pin, and the enable terminal is connected to the sixth enable signal.

[0014] The seventh IO structure includes a fourth driving circuit and a seventh IO pin; the input of the fourth driving circuit is connected to the output of the NOR gate, the output is connected to the seventh IO pin, and the enable is connected to the seventh enable signal.

[0015] Alternatively, each driving circuit includes an enable control unit, a PMOS transistor, and an NMOS transistor; the enable control unit receives a corresponding enable signal and the oscillation signal, and when the enable signal is valid, the oscillation signal is output from the enable control unit; the PMOS transistor and the NMOS transistor are connected in series between the power supply voltage and the reference ground, the gates of the PMOS transistor and the NMOS transistor are connected to the output terminal of the enable control unit, and the drains of the PMOS transistor and the NMOS transistor serve as the output terminals of the driving circuit.

[0016] Alternatively, the enable control unit is a NAND gate; the input terminals of the NAND gate are respectively connected to the oscillation signal and the enable signal.

[0017] Alternatively, the detection chip may further include a digital control logic module; the digital control logic module provides various enable signals and receives the oscillation signal, and obtains the detection result based on the oscillation signal.

[0018] Alternatively, the detection chip is an MCU chip.

[0019] To achieve the above and other related objectives, the present invention provides a temperature detection system, the temperature detection system comprising at least:

[0020] First reference resistor, thermistor, first capacitor and the above-mentioned detection chip;

[0021] The lower plate of the first capacitor is connected to the reference ground, and the upper plate is connected to the first IO pin of the detection chip;

[0022] One end of the first reference resistor is connected to the first IO pin of the detection chip, and the other end is connected to the second IO pin of the detection chip;

[0023] One end of the thermistor is connected to the first IO pin of the detection chip, and the other end is connected to the third IO pin of the detection chip.

[0024] Optionally, the first reference resistor is built into the detection chip.

[0025] To achieve the above and other related objectives, the present invention provides a humidity detection system, the humidity detection system comprising at least:

[0026] The second reference resistor, humidity-sensitive resistor, second capacitor, and the aforementioned detection chip;

[0027] The lower plate of the second capacitor is connected to the reference ground, and the upper plate is connected to the first IO pin of the detection chip;

[0028] One end of the second reference resistor is connected to the first IO pin of the detection chip, and the other end is connected to the second IO pin of the detection chip;

[0029] One end of the humidity-sensitive resistor is connected to the first IO pin of the detection chip, and the other end is connected to the third IO pin of the detection chip.

[0030] Optionally, the second reference resistor is built into the detection chip.

[0031] To achieve the above and other related objectives, the present invention provides a humidity detection system, the humidity detection system comprising at least:

[0032] Resistor, reference capacitor, humidity-sensitive capacitor, and the aforementioned detection chip;

[0033] One end of the resistor is connected to the sixth IO pin of the detection chip, and the other end is connected to the seventh IO pin of the detection chip.

[0034] The lower plate of the reference capacitor is connected to the reference ground, and the upper plate is connected to the seventh IO pin of the detection chip.

[0035] The lower plate of the humidity-sensitive capacitor is connected to the reference ground, and the upper plate is connected to the sixth IO pin of the detection chip.

[0036] The input terminal of the second Schmitt circuit and the output terminal of the fourth driving circuit are connected inside or outside the detection chip, and the input terminal of the third Schmitt circuit and the output terminal of the third driving circuit are connected inside or outside the detection chip.

[0037] Optionally, the resistor is built into the detection chip.

[0038] As described above, the detection chip, temperature detection system, and humidity detection system of the present invention have the following beneficial effects:

[0039] The detection chip, temperature detection system, and humidity detection system of this invention utilize the output drive circuit and input Schmitt circuit of the chip's original IO structure, combined with digital control logic module and peripheral sensor devices, to realize temperature and humidity testing functions. The structure is simple and easy to implement, requires fewer circuit components, improves testing accuracy, and the reference resistor can be designed inside the chip, resulting in a smaller area and lower cost. Attached Figure Description

[0040] Figure 1 The diagram shown is a structural schematic of the detection chip of the present invention.

[0041] Figure 2 The diagram shown is a structural schematic of the temperature detection system of the present invention.

[0042] Figure 3 The diagram shown is a schematic representation of the oscillation circuit of this invention.

[0043] Figure 4 The diagram shown illustrates the working principle of the oscillation circuit of this invention.

[0044] Figure 5 The diagram shown is a structural schematic of the humidity detection system of the present invention.

[0045] Figure 6 This is a schematic diagram of another structure of the detection chip of the present invention.

[0046] Figure 7 This is a schematic diagram of another structure of the humidity detection system of the present invention.

[0047] Component designation explanation

[0048] 1. Detection chip

[0049] 10 First I / O Structure

[0050] 101 First Schmitt Circuit

[0051] 102 First I / O pin

[0052] 11 Second I / O Structure

[0053] 111 First driving circuit

[0054] 112 Second I / O pin

[0055] 12 Third I / O Structure

[0056] 121 Second drive circuit

[0057] 122 Third I / O pin

[0058] 13 Inverters

[0059] 14 Digital Control Logic Module

[0060] 15. Fourth I / O Structure

[0061] 151 Second Schmitt Circuit

[0062] 152 Fourth I / O pin

[0063] 16. Fifth I / O Structure

[0064] 161 Third Schmitt Circuit

[0065] 162 Fifth I / O pin

[0066] 17. Sixth I / O Structure

[0067] 171 Third drive circuit

[0068] 172 Sixth I / O pin

[0069] 18. Seventh I / O Structure

[0070] 181 Fourth Drive Circuit

[0071] 182 Seventh I / O pin

[0072] 19 NOR gate Detailed Implementation

[0073] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0074] Please see Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0075] Example 1

[0076] like Figure 1 As shown, this embodiment provides a detection chip 1, which includes:

[0077] First IO structure 10, second IO structure 11 and third IO structure 12.

[0078] like Figure 1 As shown, the first IO structure 10 includes a first Schmitt trigger circuit 101 and a first IO pin 102.

[0079] Specifically, the input of the first Schmitt trigger circuit 101 is connected to the first IO pin 102, the output is connected to the input of the inverter 13, and the enable terminal is connected to the first enable signal EN1. When the first enable signal EN1 is valid, the first Schmitt trigger circuit 101 operates as a toggle control circuit; as an example, the first enable signal EN1 is active low.

[0080] like Figure 1 As shown, the second IO structure 11 includes a first driving circuit 111 and a second IO pin 112.

[0081] Specifically, the input terminal of the first driving circuit 111 is connected to the output terminal of the inverter 13, the output terminal is connected to the second IO pin 112, and the enable terminal is connected to the second enable signal EN2. When the second enable signal EN2 is valid, the output driving transistor in the first driving circuit 111 acts as a charging / discharging transistor; as an example, the second enable signal EN2 is active low.

[0082] More specifically, such as Figure 3As shown, the first driving circuit 111 includes an enable control unit, a PMOS transistor P1, and an NMOS transistor N1. The enable control unit receives a second enable signal EN2 and is connected to the output terminal of the inverter 13. When the second enable signal EN2 is valid, the enable control unit transmits an oscillation signal SC_IN. As an example, the enable control unit is implemented using a NAND gate, and the input terminals of the NAND gate are respectively connected to the second enable signal EN2 and the output terminal of the inverter 13. In actual use, a suitable logic device can be selected as the enable control unit according to the valid level of the enable signal, which will not be elaborated here. The source of the PMOS transistor P1 is connected to the power supply voltage VDD. The gates of both the PMOS transistor P1 and the NMOS transistor N1 are connected to the output terminal of the enable control unit. The drains of the PMOS transistor P1 and the NMOS transistor N1 are connected together as the output terminal of the first driving circuit 111, and the source of the NMOS transistor N1 is connected to reference ground.

[0083] like Figure 1 As shown, the third IO structure 12 includes a second driving circuit 121 and a third IO pin 122.

[0084] Specifically, the input terminal of the second driving circuit 121 is connected to the output terminal of the inverter 13, the output terminal is connected to the third IO pin 122, and the enable terminal is connected to the third enable signal EN3. When the third enable signal EN3 is valid, the output driving transistor in the second driving circuit 121 acts as a charging / discharging transistor; as an example, the third enable signal EN3 is active low.

[0085] It should be noted that in this embodiment, the circuit structure of the second driving circuit 121 is the same as that of the first driving circuit 111, and will not be described in detail here. In actual use, the circuit structures of the second driving circuit 121 and the first driving circuit 111 may be different, as long as the function of the present invention can be achieved, and this embodiment is not the limitation.

[0086] like Figure 1As shown, in one implementation of the present invention, the detection chip 1 further includes a digital control logic module 14. The digital control logic module 14 provides various enable signals (including but not limited to a first enable signal EN1, a second enable signal EN2, and a third enable signal EN3), and receives an oscillation signal, acquiring the detection result based on the oscillation signal. As an example, the digital control logic module 14 includes a control unit, a fractional frequency divider, a counter, and a frequency division coefficient lookup table ROM; the control unit generates various enable signals; the fractional frequency divider receives the oscillation signal and divides the oscillation signal by frequency; the counter is connected to the output terminal of the fractional frequency divider and counts the output signal of the fractional frequency divider; the input terminal of the frequency division coefficient lookup table ROM is connected to the output terminal of the counter, and the output terminal is connected to the fractional frequency divider, controlling the fractional frequency divider based on the counting result.

[0087] It should be noted that the oscillation signal received by the digital control logic module 14 can be the output signal of the inverter 13, or it can be the signal output by any node in the oscillation loop that can output a square wave, and is not limited to the examples listed in this embodiment.

[0088] like Figure 1 As shown, in one implementation of the present invention, the detection chip 1 is an MCU chip, and the digital control logic module 14 is implemented using the internal main control circuit of the MCU chip. In practical use, any chip including the first IO structure 10, the second IO structure 11, and the third IO structure 12 described in this embodiment is applicable to the present invention. The digital control logic module 14 can be implemented using the internal circuit of the detection chip 1, or it can be implemented using other chips or circuits, which will not be elaborated here.

[0089] Example 2

[0090] like Figure 2 As shown, this embodiment provides a temperature detection system, which includes:

[0091] The first reference resistor RF1, the thermistor RS, the first capacitor Co1, and the detection chip 1 of Embodiment 1.

[0092] like Figure 2 As shown, the lower plate of the first capacitor Co1 is connected to reference ground, and the upper plate is connected to the first IO pin 102 of the detection chip 1. One end of the first reference resistor RF1 is connected to the first IO pin 102 of the detection chip 1, and the other end is connected to the second IO pin 112 of the detection chip 1. One end of the thermistor RS is connected to the first IO pin 102 of the detection chip 1, and the other end is connected to the third IO pin 122 of the detection chip 1.

[0093] In another implementation of the present invention, the first reference resistor RF1 can be built into the detection chip 1, thereby simplifying the peripheral circuit structure of the chip. In yet another implementation of the present invention, the detection chip 1 is provided with an optional reference resistor. For example, the reference resistor can be connected to or disconnected between the input terminal of the first Schmitt trigger circuit 101 and the output terminal of the first drive circuit 111 via a switch; that is, the internal reference resistor of the chip can be used as the first reference resistor (in which case there is no need to set an external reference resistor), or an external reference resistor can be used as the first reference resistor (in which case the internal reference resistor is disconnected).

[0094] The working principle of the temperature detection system is as follows:

[0095] 1. In standby mode, each IO structure in the detection chip 1 is used as a normal IO.

[0096] 2. Enter temperature detection mode:

[0097] 1) When the first enable signal EN1 is valid, the first Schmitt trigger circuit 101 in the first I / O structure 10 is selected as the switching control circuit; a valid enable signal is issued by the timer TIMER0 using the clock sys_clk, making the second enable signal EN2 (reference resistor oscillation enable signal) valid, and the output driver transistor in the second I / O structure 11 is selected as the charging / discharging transistor. At this time, the circuit forms an oscillation loop, and the first reference resistor RF1 generates an oscillation signal, such as... Figure 3 As shown, initially, the output signal SMT of the first Schmitt trigger circuit 101 is low, the PMOS transistor P1 is turned on, and the first capacitor Co1 is charged through the first reference resistor RF1. When the level of the upper plate SC of the first capacitor Co1 reaches the positive switching level VTH of the first Schmitt trigger circuit 101, the output signal SMT of the first Schmitt trigger circuit 101 flips to a high level. At this time, the NMOS transistor N1 is turned on, and the first capacitor Co1 discharges through the first reference resistor RF1 and the NMOS transistor N1. When the level of the upper plate SC of the first capacitor Co1 drops to the negative switching level VTL of the first Schmitt trigger circuit 101, the output signal SMT of the first Schmitt trigger circuit 101 flips to a low level. This charging and discharging process continues, and the upper plate SC of the first capacitor Co1 generates a triangular wave oscillation signal, such as... Figure 4 As shown; finally, the square wave signal SC_IN (oscillation signal) is output through the first Schmitt circuit 101 and the inverter 13.

[0098] 2) When the number of oscillations of the square wave signal SC_IN reaches a fixed value A (which can be set according to actual needs), the second enable signal EN2 of the timer TIMER2 of the square wave signal SC_IN is invalidated, the first reference resistor RF1 stops oscillating, and the count value B of TIMER0 at this time is recorded (representing the time T taken for the oscillation signal generated by the first reference resistor RF1 to oscillate A times).

[0099] 3) A valid enable signal is issued by the timer TIMER0 of the clock sys_clk, making the third enable signal EN3 (thermistor oscillation enable signal) valid, and selecting the output driver transistor in the third IO structure 12 as the charging and discharging transistor. Similarly, at this time, the circuit forms an oscillation loop, and the thermistor RS generates an oscillation signal. The specific principle will not be elaborated here.

[0100] 4) When the timer TIMER0 of the clock sys_clk counts to B, the third enable signal EN3 of the timer TIMER2 using the square wave signal SC_IN is invalidated, the thermistor RS stops oscillating, and the current count value of TIMER2 is read.

[0101] 5) The oscillation time of the first reference resistor RF1 is equal to the oscillation time of the thermistor RS, that is, T RF1 ×X RF1 =t RS ×X RS , among which, T RF1 X is the period of oscillation of the first reference resistor RF1. RF1 t is the number of oscillations of the first reference resistor RF1. RS X is the period of the RS oscillation of the thermistor. RS Let RS be the number of oscillations of the thermistor. Substituting the RC charging and discharging formula into the above equation, we get:

[0102]

[0103] The first reference resistor RF1 and the thermistor RS have the same positive and negative switching levels and capacitance (the first capacitor Co1). After simplification, the formula is as follows:

[0104] R RF1 ×X RF1 =R RS ×X RS ,

[0105] Among them, X RF1 =A, then According to the final X RS Use a table to determine the current temperature.

[0106] Example 3

[0107] like Figure 5 As shown, this embodiment provides a humidity detection system, which includes:

[0108] The second reference resistor RF2, the humidity-sensitive resistor RSB, the second capacitor Co2, and the detection chip 1 of Example 1.

[0109] like Figure 5 As shown, the lower plate of the second capacitor RF2 is connected to reference ground, and the upper plate is connected to the first IO pin 102 of the detection chip 1. One end of the second reference resistor RF2 is connected to the first IO pin 102 of the detection chip 1, and the other end is connected to the second IO pin 112 of the detection chip 1. One end of the humidity-sensitive resistor RSB is connected to the first IO pin 102 of the detection chip 1, and the other end is connected to the third IO pin 122 of the detection chip 1.

[0110] Specifically, the working principle of the humidity detection system is similar to that of Embodiment 2. When the first enable signal EN1 is active (the first Schmitt trigger circuit 101 acts as a switching control circuit), the second enable signal EN2 (reference resistor oscillation enable signal) is also active (the output drive transistor in the second IO structure 11 acts as a charging / discharging transistor). The second reference resistor RF2 oscillates, and after counting to A times, the second enable signal EN2 becomes inactive, the second reference resistor RF2 stops oscillating, and the required time T is recorded. Then, the third enable signal EN3 (humidity-sensitive resistor oscillation enable signal) is active (the output drive transistor in the third IO structure 12 acts as a charging / discharging transistor), the humidity-sensitive resistor RSB oscillates, and after time T, the third enable signal EN3 becomes inactive, the humidity-sensitive resistor RSB stops oscillating, and the number of oscillations is recorded. The current humidity is determined by looking up a table. For the specific working process, please refer to Embodiment 2, which will not be elaborated here.

[0111] It should be noted that, as another example, the second reference resistor RF2 can be built into the detection chip 1. As yet another example, an optional reference resistor can be provided inside the detection chip 1. When the internal reference resistor is used as the first reference resistor, there is no need to set an external reference resistor; when an external reference resistor is used as the first reference resistor, the internal reference resistor is disconnected. These distinctions will not be elaborated upon here.

[0112] It should be noted that Embodiment 2 and Embodiment 3 can be combined in the same circuit to realize temperature and humidity detection. The first IO structure 10 and the second IO structure 11 are shared, and two third IO structures 12 are set up for the oscillation of the thermistor RS and the humidity sensor RSB, respectively. These will not be described in detail here.

[0113] Example 4

[0114] like Figure 6 As shown, this embodiment provides a detection chip 1, which includes:

[0115] Fourth IO structure 15, fifth IO structure 16, sixth IO structure 17 and seventh IO structure 18.

[0116] like Figure 6 As shown, the fourth IO structure 15 includes a second Schmitt trigger circuit 151 and a fourth IO pin 152.

[0117] Specifically, the input of the second Schmitt trigger circuit 151 is connected to the fourth IO pin 152, the output is connected to the first input of the NOR gate 19, and the enable terminal is connected to the fourth enable signal EN4. When the fourth enable signal EN4 is valid, the second Schmitt trigger circuit 151 operates as a toggle control circuit; as an example, the fourth enable signal EN4 is active low.

[0118] It should be noted that any circuit structure that can realize or not logic is applicable to this invention, and will not be described in detail here.

[0119] like Figure 6 As shown, the fifth IO structure 16 includes a third Schmitt trigger circuit 161 and a fifth IO pin 162.

[0120] Specifically, the input of the third Schmitt trigger circuit 161 is connected to the fifth IO pin 162, the output is connected to the second input of the NOR gate 19, and the enable terminal is connected to the fifth enable signal EN5. When the fifth enable signal EN5 is valid, the third Schmitt trigger circuit 161 operates as a toggle control circuit; as an example, the fifth enable signal EN5 is active low.

[0121] like Figure 6 As shown, the sixth IO structure 17 includes a third driving circuit 171 and a sixth IO pin 172.

[0122] Specifically, the input terminal of the third driving circuit 171 is connected to the output terminal of the NOR gate 19, the output terminal is connected to the sixth IO pin 172, and the enable terminal is connected to the sixth enable signal EN6. When the sixth enable signal EN6 is valid, the output driving transistor in the third driving circuit 171 acts as a charging / discharging transistor; as an example, the sixth enable signal EN6 is active low.

[0123] It should be noted that in this embodiment, the circuit structure of the third driving circuit 171 is the same as that of the first driving circuit 111 in Embodiment 1, and will not be described in detail here. In actual use, the circuit structure of the third driving circuit 171 and the first driving circuit 111 may be different, as long as the function of the present invention can be achieved, and it is not limited to this embodiment.

[0124] like Figure 6 As shown, the seventh IO structure 18 includes a fourth driving circuit 181 and a seventh IO pin 182.

[0125] Specifically, the input terminal of the fourth driving circuit 181 is connected to the output terminal of the NOR gate 19, the output terminal is connected to the seventh IO pin 182, and the enable terminal is connected to the seventh enable signal EN7. When the seventh enable signal EN7 is valid, the output driving transistor in the fourth driving circuit 181 acts as a charging / discharging transistor; as an example, the seventh enable signal EN7 is active low.

[0126] It should be noted that in this embodiment, the circuit structure of the fourth driving circuit 181 is the same as that of the first driving circuit 111 in Embodiment 1, and will not be described in detail here. In actual use, the circuit structure of the fourth driving circuit 181 and the first driving circuit 111 may be different, as long as the function of the present invention can be achieved, and it is not limited to this embodiment.

[0127] It should be noted that the detection chip 1 also includes a digital control logic module 14; it can be implemented using any chip including the fourth IO structure 15, the fifth IO structure 16, the sixth IO structure 17 and the seventh IO structure 18 described in this embodiment; see Embodiment 1, which will not be described in detail here.

[0128] Example 5

[0129] like Figure 7 As shown, this embodiment provides a humidity detection system, which includes:

[0130] Resistor R, reference capacitor CR, humidity-sensitive capacitor CS, and detection chip 1 of Example 4.

[0131] like Figure 7As shown, one end of the resistor R is connected to the sixth IO pin 172 of the detection chip 1, and the other end is connected to the seventh IO pin 182 of the detection chip 1. The lower plate of the reference capacitor CR is connected to the reference ground, and the upper plate is connected to the seventh IO pin 182 of the detection chip 1. The lower plate of the humidity-sensitive capacitor CS is connected to the reference ground, and the upper plate is connected to the sixth IO pin 172 of the detection chip 1. As an example, the input terminal of the second Schmitt trigger circuit 151 and the output terminal of the fourth driving circuit 181 are connected externally to the detection chip 1, and the input terminal of the third Schmitt trigger circuit 161 and the output terminal of the third driving circuit 171 are connected externally to the detection chip 1; that is, the fourth IO pin 152 and the seventh IO pin 182 are connected through an external wire, and the fifth IO pin 162 and the sixth IO pin 172 are connected through an external wire. As another example, the input terminal of the second Schmitt circuit 151 and the output terminal of the fourth driving circuit 181 are connected inside the detection chip 1 by wires, and the input terminal of the third Schmitt circuit 161 and the output terminal of the third driving circuit 171 are connected inside the detection chip 1 by wires.

[0132] Specifically, the working principle of the humidity detection system is similar to that of Embodiment 3. When the fifth enable signal EN5 is active (the third Schmitt trigger circuit 161 acts as a switching control circuit), it simultaneously controls the sixth enable signal EN6 (reference capacitor oscillation enable signal) to be active (the output drive transistor in the sixth IO structure 17 acts as a charging / discharging transistor). The reference capacitor CR oscillates. After counting to A times, the sixth enable signal EN6 becomes inactive, the reference capacitor CR stops oscillating, and the required time T is recorded. Then, the fourth enable signal EN4 becomes active (the second Schmitt trigger circuit 151 acts as a switching control circuit), simultaneously controlling the seventh enable signal EN7 (humidity-sensitive capacitor oscillation enable signal) to be active (the output drive transistor in the seventh IO structure 18 acts as a charging / discharging transistor). The humidity-sensitive capacitor CS oscillates. After time T, the seventh enable signal EN7 becomes inactive, the humidity-sensitive capacitor CS stops oscillating, and the number of oscillations is recorded. The current humidity is determined by looking up a table. For the specific working process, please refer to Embodiment 2, which will not be elaborated here.

[0133] It should be noted that, as another example, the resistor R can be built into the detection chip 1. As yet another example, an optional resistor can be provided inside the detection chip 1. When the internal resistor is used as the resistor R, no external resistor is needed; when an external resistor is used as the resistor R, the internal resistor is disconnected. These distinctions will not be elaborated further here.

[0134] This invention utilizes the chip's existing I / O structure and peripheral devices to form an oscillation circuit. The resistance / capacitance changes with temperature / humidity, and the resistance / capacitance value changes accordingly. Through resistance-frequency conversion and capacitance-frequency conversion, the change in resistance or capacitance is converted into a change in frequency. The change in temperature / humidity is then measured based on the change in frequency. The structure is simple and easy to implement, requires fewer circuit components, improves testing accuracy, and the reference resistor can be designed inside the chip, resulting in a smaller area and lower cost.

[0135] In summary, the present invention provides a detection chip, a temperature detection system, and a humidity detection system, comprising: a first I / O structure, including a first Schmitt trigger circuit and a first I / O pin; the input terminal of the first Schmitt trigger circuit is connected to the first I / O pin, the output terminal is connected to the input terminal of an inverter, and the enable terminal is connected to a first enable signal; the inverter outputs an oscillation signal; a second I / O structure, including a first driving circuit and a second I / O pin; the input terminal of the first driving circuit is connected to the output terminal of the inverter, the output terminal is connected to the second I / O pin, and the enable terminal is connected to a second enable signal; a third I / O structure, including a second driving circuit and a third I / O pin; the input terminal of the second driving circuit is connected to the output terminal of the inverter, the output terminal is connected to the third I / O pin, and the enable terminal is connected to a third enable signal. The system may include a fourth I / O structure, comprising a second Schmitt trigger circuit and a fourth I / O pin; the input of the second Schmitt trigger circuit is connected to the fourth I / O pin, the output is connected to the first input of a NOR gate, and the enable signal is connected to a fourth enable signal; the NOR gate outputs an oscillation signal; a fifth I / O structure, comprising a third Schmitt trigger circuit and a fifth I / O pin; the input of the third Schmitt trigger circuit is connected to the fifth I / O pin, the output is connected to the second input of the NOR gate, and the enable signal is connected to a fifth enable signal; a sixth I / O structure, comprising a third driving circuit and a sixth I / O pin; the input of the third driving circuit is connected to the output of the NOR gate, the output is connected to the sixth I / O pin, and the enable signal is connected to a sixth enable signal; and a seventh I / O structure, comprising a fourth driving circuit and a seventh I / O pin; the input of the fourth driving circuit is connected to the output of the NOR gate, the output is connected to the seventh I / O pin, and the enable signal is connected to a seventh enable signal. The detection chip, temperature detection system, and humidity detection system of this invention utilize the chip's existing I / O structure's output drive circuit and input Schmitt trigger circuit, combined with a digital control logic module and peripheral sensors, to achieve temperature and humidity testing functions. The structure is simple and easy to implement, requires fewer additional circuit components, improves testing accuracy, and the reference resistor can be designed internally within the chip, resulting in a smaller area and lower cost. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0136] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A detection chip, characterized in that, The detection chip includes at least: The first I / O structure includes a first Schmitt trigger circuit and a first I / O pin; the input terminal of the first Schmitt trigger circuit is connected to the first I / O pin, the output terminal is connected to the input terminal of an inverter, and the enable terminal is connected to a first enable signal; the inverter outputs an oscillation signal. The second IO structure includes a first driving circuit and a second IO pin; the input terminal of the first driving circuit is connected to the output terminal of the inverter, the output terminal is connected to the second IO pin, and the enable terminal is connected to a second enable signal; wherein, when the second enable signal is valid, the output driving transistor in the first driving circuit acts as a charging and discharging transistor. The third IO structure includes a second driving circuit and a third IO pin; the input terminal of the second driving circuit is connected to the output terminal of the inverter, the output terminal is connected to the third IO pin, and the enable terminal is connected to a third enable signal; wherein, when the third enable signal is valid, the output driving transistor in the second driving circuit acts as a charging and discharging transistor.

2. A detection chip, characterized in that, The detection chip includes at least: The fourth IO structure includes a second Schmitt trigger circuit and a fourth IO pin; the input of the second Schmitt trigger circuit is connected to the fourth IO pin, the output is connected to the first input of a NOR gate, and the enable is connected to a fourth enable signal; the NOR gate outputs an oscillation signal. The fifth IO structure includes a third Schmitt trigger circuit and a fifth IO pin; the input terminal of the third Schmitt trigger circuit is connected to the fifth IO pin, the output terminal is connected to the second input terminal of the NOR gate, and the enable terminal is connected to the fifth enable signal. The sixth IO structure includes a third driving circuit and a sixth IO pin; the input terminal of the third driving circuit is connected to the output terminal of the NOR gate, the output terminal is connected to the sixth IO pin, and the enable terminal is connected to the sixth enable signal; wherein, when the sixth enable signal is valid, the output driving transistor in the third driving circuit acts as a charging and discharging transistor. The seventh IO structure includes a fourth driving circuit and a seventh IO pin; the input terminal of the fourth driving circuit is connected to the output terminal of the NOR gate, the output terminal is connected to the seventh IO pin, and the enable terminal is connected to a seventh enable signal; wherein, when the seventh enable signal is valid, the output driving transistor in the fourth driving circuit acts as a charging and discharging transistor.

3. The detection chip according to claim 1 or 2, characterized in that: Each driving circuit includes an enable control unit, a PMOS transistor, and an NMOS transistor; the enable control unit receives a corresponding enable signal and the oscillation signal, and when the enable signal is valid, the oscillation signal is output from the enable control unit; the PMOS transistor and the NMOS transistor are connected in series between the power supply voltage and the reference ground, the gates of the PMOS transistor and the NMOS transistor are connected to the output terminal of the enable control unit, and the drains of the PMOS transistor and the NMOS transistor serve as the output terminals of the driving circuit.

4. The detection chip according to claim 3, characterized in that: The enable control unit is a NAND gate; the input terminals of the NAND gate are respectively connected to the oscillation signal and the enable signal.

5. The detection chip according to claim 1 or 2, characterized in that: The detection chip also includes a digital control logic module; the digital control logic module provides various enable signals, receives the oscillation signal, and obtains the detection result based on the oscillation signal.

6. The detection chip according to claim 1 or 2, characterized in that: The detection chip is an MCU chip.

7. A temperature detection system, characterized in that, The temperature detection system includes at least: A first reference resistor, a thermistor, a first capacitor, and the detection chip as described in claim 1; The lower plate of the first capacitor is connected to the reference ground, and the upper plate is connected to the first IO pin of the detection chip; One end of the first reference resistor is connected to the first IO pin of the detection chip, and the other end is connected to the second IO pin of the detection chip; One end of the thermistor is connected to the first IO pin of the detection chip, and the other end is connected to the third IO pin of the detection chip.

8. The temperature detection system according to claim 7, characterized in that: The first reference resistor is built into the detection chip.

9. A humidity detection system, characterized in that, The humidity detection system includes at least: The second reference resistor, the humidity-sensitive resistor, the second capacitor, and the detection chip as described in claim 1; The lower plate of the second capacitor is connected to the reference ground, and the upper plate is connected to the first IO pin of the detection chip; One end of the second reference resistor is connected to the first IO pin of the detection chip, and the other end is connected to the second IO pin of the detection chip; One end of the humidity-sensitive resistor is connected to the first IO pin of the detection chip, and the other end is connected to the third IO pin of the detection chip.

10. A humidity detection system, characterized in that, The humidity detection system includes at least: Resistor, reference capacitor, humidity-sensitive capacitor and the detection chip as described in claim 2; One end of the resistor is connected to the sixth IO pin of the detection chip, and the other end is connected to the seventh IO pin of the detection chip. The lower plate of the reference capacitor is connected to the reference ground, and the upper plate is connected to the seventh IO pin of the detection chip. The lower plate of the humidity-sensitive capacitor is connected to the reference ground, and the upper plate is connected to the sixth IO pin of the detection chip. The input terminal of the second Schmitt circuit and the output terminal of the fourth driving circuit are connected inside or outside the detection chip, and the input terminal of the third Schmitt circuit and the output terminal of the third driving circuit are connected inside or outside the detection chip.

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