An interface circuit with hysteresis and level shifting characteristics

Abstract

The application discloses an interface circuit with hysteresis and level shift characteristics, comprising a VCC power supply end, a COM end, an amplification circuit and a load circuit arranged in sequence between the VCC power supply end and the COM end, and a bias generation circuit connected with the amplification circuit and the load circuit; the bias generation circuit is also connected with the VCC power supply end and the COM end; the amplification circuit and the load circuit are connected with an output node VO; the output node VO is connected with an input end of an inverter or a Schmidt trigger; and an output end of the inverter or the Schmidt trigger is connected with the amplification circuit and the load circuit. The application can realize the hysteresis characteristic of the interface circuit, improve the noise resistance and interference resistance of the interface circuit, directly realize the level shift operation of signals, greatly simplify the circuit structure, improve the circuit reliability, and has the characteristics of simple structure, few required devices and low circuit design difficulty.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of high-voltage gate drive IC design of power semiconductors, and particularly relates to an interface circuit with hysteresis and level shift characteristics. BACKGROUND

[0002] The high-voltage gate drive chip is an important bridge for connecting the controller and the power transistor (MOSFET, IGBT, GaN, SiC et.al.). The control chip sends a PWM switching signal to the power transistor. Since the working voltage of the controller chip is low (generally 3.3V or 5V) and the output current capacity is weak, and the controller is difficult to withstand the electrical noise (dv / dt, di / dt, etc.) in the switching process of the power device, a high-voltage gate drive chip is needed to amplify the switching signal in power to drive the switching of the power device, and to perform intelligent protection (including under-voltage protection, over-temperature protection, anti-through protection, etc.) on the power device.

[0003] The working voltage of the high-voltage gate drive chip VCC is 10-20V (commonly 15V), and the HIN and LIN input ports are compatible with 3.3V, 5V and 15V logic levels. A commonly used interface circuit scheme is to use a Schmitt trigger (SMT) together with a 15V to 5V regulator to realize reading of the input signal. Figure 1 In this circuit scheme, the hysteresis characteristic of the Schmitt trigger enables the interface circuit to have a certain noise immunity. In order to be compatible with 3.3V logic input, the positive trigger voltage (VSMT,T+) of the Schmitt trigger needs to be lower than 3.3V. Since the positive trigger voltage of the Schmitt trigger varies with the supply voltage of the chip, it is difficult to realize compatibility with 3.3V logic level in the voltage range of 10-20V. Therefore, a 15V to 5V Regulator circuit is needed. After the input PWM signal is read into the gate drive chip by the interface circuit, a level shift circuit is needed to change the 0-5V voltage rail signal to 0-VCC voltage rail.

[0004] Due to the operations of power supply voltage conversion and signal level shift, the circuit has the problems of complex structure, many required devices, slow circuit response, and large delay. SUMMARY

[0005] The present application aims to overcome the defects in the prior art and provide an interface circuit with hysteresis and level shift characteristics, which has the characteristics of simple structure, few required devices, and low circuit design difficulty.

[0006] To achieve the above objectives, the technical solution of the present invention is to design an interface circuit with hysteresis and level shifting characteristics, including a VCC power supply terminal, a COM terminal, an amplifier circuit and a load circuit arranged sequentially between the VCC power supply terminal and the COM terminal, and a bias generating circuit connected to both the amplifier circuit and the load circuit; the bias generating circuit is also connected to both the VCC power supply terminal and the COM terminal; the amplifier circuit and the load circuit are both connected to the output node VO, the output node VO is connected to the input terminal of an inverter or a Schmitt trigger, and the output terminal of the inverter or Schmitt trigger is connected to both the amplifier circuit and the load circuit.

[0007] A further technical solution is that the voltage at the VCC power supply terminal is VCC; the voltage swing of the output node VO of the amplifier circuit and the load circuit is 0 to VCC.

[0008] A further technical solution is that the amplifier circuit is a common-source amplifier circuit or a common-gate amplifier circuit.

[0009] A further technical solution is that the common-source amplifier circuit is a simple common-source amplifier, including a first common-source amplifier transistor and a second common-source amplifier transistor connected to the VIN terminal respectively. The first common-source amplifier transistor and the second common-source amplifier transistor are connected in parallel. The feedback switch transistor is connected to the second common-source amplifier transistor and is also connected to the output node VO. The output node VO is also connected to the first common-source amplifier transistor. Both the first common-source amplifier transistor and the second common-source amplifier transistor are connected to the COM terminal.

[0010] A further technical solution is that the common-source amplifier circuit is a common-source single-stage amplifier circuit with a source resistor Rs; including a first common-source amplifier transistor connected to the VIN terminal, the first common-source amplifier transistor being connected to the output node VO and the feedback switch transistor respectively, the source of the first common-source amplifier transistor being connected to the COM terminal through the resistor Rs, and the feedback switch transistor being connected to the COM terminal.

[0011] A further technical solution is that the load circuit includes a first current mirror load transistor PM1 disposed between the output node VO and the VCC power supply terminal, a second current mirror load transistor PM2 and a hysteresis switch transistor PM3 connected in parallel with the first current mirror load transistor PM1, and the second current mirror load transistor PM2 and the hysteresis switch transistor PM3 are connected in sequence.

[0012] A further technical solution is that the load circuit includes a first load resistor RL1 and a second load resistor RL2 connected in sequence between the output node VO and the VCC power supply terminal, and a hysteresis switch PM4 connected in parallel with the first load resistor RL1.

[0013] The advantages and beneficial effects of this invention are as follows:

[0014] 1. According to the interface circuit design architecture proposed in this invention, the hysteresis characteristics of the interface circuit can be realized, thereby improving the interface circuit's ability to withstand noise and resist interference.

[0015] 2. According to the interface circuit design architecture proposed in this invention, signal level shifting operation can be directly realized. Compared with the interface circuit of traditional high-voltage gate driver chips, no additional regulator or level shifter circuit is required, which greatly simplifies the circuit structure and improves the circuit reliability.

[0016] 3. The interface circuit design architecture proposed in this invention includes Amplifier, Load, and Bias circuit modules. Each module has low design difficulty and diverse circuit structures. Through the optimized design of each module, high circuit design performance (such as interface circuits with excellent performance such as low temperature drift and low PVT dependence) can be achieved. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the interface circuit structure of a gate driver chip in the prior art;

[0018] Figure 2 This is a schematic diagram of the structure of an interface circuit with hysteresis and level shifting characteristics according to the present invention.

[0019] Figure 3 It is an amplifier circuit with hysteresis characteristics designed based on a common-source amplifier.

[0020] Figure 4 It is an amplifier circuit with hysteresis characteristics designed based on a common-source amplifier.

[0021] Figure 5 It is a load circuit with hysteresis characteristics;

[0022] Figure 6 This is a schematic diagram of a common-source amplifier with hysteresis and a current source load with hysteresis as an interface circuit with hysteresis and level shifting characteristics, according to Embodiment 1 of the present invention.

[0023] Figure 7 This is a schematic diagram of an interface circuit with low PVT dependence and hysteresis and level shifting characteristics according to an embodiment of the present invention. Detailed Implementation

[0024] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings and examples. The following examples are only used to more clearly illustrate the technical solutions of the present invention and should not be construed as limiting the scope of protection of the present invention.

[0025] This invention is an interface circuit with hysteresis and level shifting characteristics. The circuit design scheme is as follows:Figure 2 Considering that the input signal shares a common ground with the high-voltage gate driver chip, and that the input signal VIN has multiple amplitude values, a combination of amplifier and load circuits is used under the VCC and COM power rails to smoothly transmit the switching signal into the chip. The voltage swing of the output node VO of the amplifier and load circuits needs to be 0 to VCC. The signal at point VO is transmitted to point FB by an inverter or SMT. The FB signal is fed back to the amplifier and load circuits to change their states (impedance, gain, bias current, etc.) to achieve the positive feedback hysteresis characteristic of the interface circuit. The bias circuit is the bias generation circuit, which provides the static operating point for the amplifier and load. Based on the above working principle, the design objectives of interface circuit hysteresis and level shifting can be achieved. It should be noted that the FB feedback needs to satisfy the hysteresis positive feedback polarity of the circuit, and the node of the FB feedback should be selected reasonably according to the actual circuit. In addition, the hysteresis characteristic can be generated by the Load, or by the Amplifier, or by both the Amplifier and the Load. The circuit design of the Load and the Amplifier needs to be selected according to the actual circuit design requirements.

[0026] Based on the circuit design schemes described above, the following will detail typical application design examples of the Amplifier, Load, overall interface, and Bias circuit modules, but are not limited to the circuit schemes mentioned below.

[0027] Amplifier circuit design:

[0028] Because the output voltage swing at point VO is required to be between 0 and VCC, the amplifier needs sufficient pull-down capability to pull the voltage at point VO down to COM. Therefore, commonly used simple amplifiers, such as common-source amplifiers and common-gate amplifiers, can all be used as amplifiers. The design of a simple common-source amplifier will be used as an example for illustration. Figure 3 and Figure 4 .

[0029] like Figure 3A common-source single-stage amplifier NM1 is used as the input transistor for VIN. NM2 is also a common-source amplifier connected in parallel with NM1. NM3 is used as a feedback switch. When the high or low level of VIN is input to the circuit, the feedback FB controls the switching of NM3. When VIN receives a rising edge, FB is low, and NM3 is off. As the VIN voltage rises and reaches VT+, NM1 pulls the VO voltage down to COM. The FB voltage then feeds back to a high level, and NM3 turns on, further pulling VO low to stabilize the low-level state of VO. When the falling edge of VIN arrives, because NM1 and NM2 jointly pull down VO, VIN needs to drop to a voltage VT- lower than VT+ to close the pull-down circuit. This creates a hysteresis characteristic.

[0030] like Figure 4 This paper presents another common-source single-stage amplifier circuit with a source resistor Rs. NM1 is the common-source amplifier transistor, and NM4 is used as a feedback switch. Similarly, when the high or low level of VIN is input to the circuit, the switching of NM4 is controlled by the feedback FB. When VIN receives a rising edge, FB is required to be low, NM4 is cut off, and Rs is connected in series with NM1 to ground. As the VIN voltage rises and reaches VT+, NM1 pulls the VO voltage down to COM. The FB voltage then feeds back to high, NM4 turns on, the Rs resistor is short-circuited, and the impedance of VO to ground is reduced, further stabilizing the low-level state of VO. When the falling edge of VIN arrives, because the source of NM1 is directly connected to COM, VIN needs to drop to a voltage VT- lower than VT+ to close the pull-down circuit, thus forming a hysteresis characteristic.

[0031] Load circuit design

[0032] The load circuit, acting as an amplifier, exhibits different UI characteristics depending on the load type. Common loads include resistors, current mirrors, and diode-connected MOSFETs. The hysteresis design of the load circuit is similar to that described above. Figure 5 A current mirror and a resistor are given as a simple and typical hysteretic load; PM1 and PM2 are current mirror load transistors, PM3 and PM4 are hysteretic switching transistors used to adjust the load output current, RL1 and RL2 are load resistors, and the impedance of VO to VCC is changed by the switching of feedback transistor PM4.

[0033] Example 1:

[0034] Typical Design Examples of Interface Circuits Based on the Invention

[0035] This invention uses a common-source amplifier with hysteresis characteristics and a current source load with hysteresis as typical application circuits, such as... Figure 6As shown, NM1 and NM2 are common-source input amplifier transistors, NM3 and PM3 are hysteresis switching transistors, PM1 and PM2 are current mirror loads, and PM4 is a current mirror replica transistor. When VIN is low, FB is low, NM3 is cut off, PM3 is turned on, and the VO node has a charging current of ID,PM1 + ID,PM2. When the VIN input voltage signal rises, NM1 changes from the cutoff region to saturation conduction as the VIN voltage increases. When the pull-down current of NM1 equals the sum of the currents of PM1 and PM2, the voltage of the VO node will be pulled down from the high level to the low level. When VO flips, the current relationship satisfies equation ①, where ID,PM1 and ID,PM2 are α and β times the Ib current, respectively, and ID,NM1 satisfies the square law, as shown in equation ②. According to equations ① and ②, the input toggle threshold VT+ is obtained when VIN input rises, as shown in equation ③. When VO voltage toggles to low level, FB becomes high level. At this time, NM3 is turned on, PM3 is turned off, and VO state is stabilized at low level. When VIN inputs at the falling edge, when the current of NM1 and NM2 equals the current of PM1, the VO voltage is pulled up to VCC, as shown in equation ④. At this time, the corresponding low-level input toggle threshold VT- is obtained. When VGS = VT-, the currents of NM1 and NM2 follow a square law, as shown in equation ⑤. The expression for VT- can be solved from equations ④ and ⑤, as shown in equation ⑥. The hysteresis window VIN,hys = VT+ - VT-, as shown in equation ⑦. By reasonably adjusting parameters such as (W / L)NM1, (W / L)NM2, Ib, α, and β, the required interface circuit can be designed.

[0036] I D，NM1 =I D，PM1 +I D，PM2 =αI b +βI b =(α+β)I b ①

[0037]

[0038] I D，NM1 +I D，NM2 =I D，PM1 =αI b ④

[0039]

[0040]

[0041] Equations ③, ⑥, and ⑦ show that μnCox and Vth,n exist in the expressions for VT+, VT-, and VIN,hys, indicating that the circuit characteristics are significantly affected by PVT (Process, Voltage, and Temperature). This invention can also reduce or eliminate the dependence of VT+ and VT- on PVT by optimizing the design of the bias circuit.

[0042] Example 2: The difference from Example 1 lies in the typical design example of the low PVT dependency interface circuit based on the present invention.

[0043] like Figure 7 This paper provides a typical design example of an interface circuit with low PVT dependence based on the present invention. DZ is a Zener diode. PM7, PM8, DZ, R1, R2, R3, NM2, NM3, PM3, and PM6 constitute a bias circuit, and PM1, PM2, PM4, and PM5 constitute a load circuit. When VIN is low, FB1 is also low, FB2 is high, PM2 is turned on, and PM5 is turned off. There is a constant pull-up current of ID,PM1 at node VO. If we assume that the width-to-length ratio of PM1 and PM3 is equal, the width-to-length ratio of PM4 and PM6 is also equal, and ignore the channel length modulation effect, then ID,PM1 = ID,NM2, ID,PM4 = ID,NM3, and the voltage at point Z is the Zener breakdown voltage VZ. Then we have formulas ⑧ and ⑨. The rising edge switching condition is that when the current of NM1 equals the current of PM1, the VO voltage flips from high to low, as shown in equation ⑩. If NM2, NM1, and NM3 are set to have the same dimensions, then VT+ will have... According to the formula, after VO toggles to low, FB1 goes high, FB2 goes low, PM2 is cut off, and PM5 is turned on. The VO node has a constant pull-up current equal to ID and PM4. When VIN provides a falling edge signal, the VO toggle condition is that the current in NM1 equals ID and PM4. Similarly, there are formulas... and The relationship is as follows: After optimizing the bias design circuit, VT+ and VT- are immune to the influence of the process corner of MOS, and the resistance term exists in the expression in a proportional form, so it is also basically immune to the threshold deviation caused by the resistance. The PVT deviation of the flip threshold is mainly affected by Zener, which greatly reduces the dependence of the circuit characteristics on PVT.

[0044]

[0045] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An interface circuit with hysteresis and level shifting characteristics, characterized in that, It includes a VCC power supply terminal, a COM terminal, an amplifier circuit and a load circuit arranged sequentially between the VCC power supply terminal and the COM terminal, and a bias generating circuit connected to both the amplifier circuit and the load circuit; the bias generating circuit is also connected to both the VCC power supply terminal and the COM terminal; the amplifier circuit and the load circuit are both connected to the output node VO, the output node VO is connected to the input terminal of the feedback circuit, and the output terminal of the feedback circuit generates feedback signals FB1 and FB2, which are respectively connected to the controllable switching device in the load circuit; The load circuit consists of PM1 and PM2 connected in series; the source of PM1 is connected to VCC, the drain of PM1 is connected to the source of PM2, and the drain of PM2 is connected to the output node VO. PM4 and PM5 are connected in series; the source of PM4 is connected to VCC, the drain of PM4 is connected to the source of PM5, and the drain of PM5 is connected to the output node VO, forming a symmetrical load branch. The source of PM3 is connected to VCC, the drain of PM3 is connected to the gate of PM1, the source of PM6 is connected to VCC, and the drain of PM6 is connected to the gate of PM4. The bias generation circuit provides two bias currents for the gates of PM3 and PM6. The gate of PM2 receives feedback signal FB2, and the gate of PM5 receives feedback signal FB1. The conduction state of the load branch is controlled by FB1 and FB2. The amplifier circuit includes NM1, whose gate receives the input voltage VIN, whose source is connected to the COM terminal, and whose drain is connected to the node VO. The feedback circuit includes a Schmitt trigger SMT, a first inverter INV1, and a second inverter INV2. The input of the Schmitt trigger SMT is connected to the output node VO, and its output is connected to the input of INV1. The output of INV1 generates a feedback signal FB1 and is connected to the gate of PM5. The output of INV1 is also connected to the input of INV2, and the output of INV2 generates a feedback signal FB2 and is connected to the gate of PM2. When VIN is low, FB1 is low and FB2 is high. At this time, PM2 is turned on and PM5 is turned off. The output node VO is pulled up to high by the constant pull-up current ID provided by PM1. When the VIN voltage rises, making the drain current of NM1 equal to the pull-up current ID provided by PM1, the output node VO voltage flips from high level to low level. After VO flips to a low level, the feedback circuit causes FB1 to become high and FB2 to become low, which in turn causes PM2 to be cut off and PM5 to be turned on. At this time, the output node VO is pulled up by the constant current ID provided by the pull-up transistor PM4. When the VIN voltage drops, causing the drain current of NM1 to equal the pull-up current ID,PM4 provided by PM4, the output node VO voltage flips from low to high. Assume that PM1 and PM3 have the same width-to-length ratio, and PM4 and PM6 have the same width-to-length ratio. Ignore the channel length modulation effect, such that ID,PM1 = ID,NM2, and ID,PM4 = ID,NM3. The voltage at node Z is determined by the breakdown voltage VZ of the Zener diode DZ. The rising edge switching condition is that when the current of NM1 equals the current of PM1, the VO voltage flips from high to low. If NM2, NM1, and NM3 have the same dimensions, after VO flips to low, FB1 becomes high, FB2 becomes low, PM2 is cut off, and PM5 is turned on. The VO node has a constant pull-up current of ID,PM4. When VIN provides a falling edge signal, the VO switching condition is that the current of NM1 equals ID,PM4.

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