A maximum voltage automatic selection circuit
By using NMOS transistor energy storage capacitors and current comparison technology in analog circuits, combined with Schmitt triggers, the problems of insufficient speed and stability of traditional voltage selection circuits are solved, achieving low power consumption and high precision maximum voltage selection.
Patent Information
- Application Number
- CN202310762536.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-27
- Publication Date
- 2026-01-02
- Estimated Expiration
- 2043-06-27
AI Technical Summary
Traditional voltage selection circuits have limited speed, low stability, and lack low-power processing, making it impossible to quickly and accurately select the maximum voltage, which affects the performance of analog circuit systems.
By replacing ordinary metal capacitors with NMOS transistors and energy storage capacitors, and combining current comparison and Schmitt triggers, a reference current circuit and a common-source cascode current mirror circuit are designed to improve the speed and accuracy of voltage comparison. Complementary CMOS switches are used to achieve voltage selection.
It significantly reduces the circuit layout area, improves circuit stability and speed, consumes very little power, and enables precise and fast maximum voltage selection.
Smart Images
Figure CN117032386B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of analog integrated circuit design, and particularly relates to a maximum voltage automatic selection circuit. BACKGROUND
[0002] In analog chip applications, such as PMIC, EEPROM, SOC, OTP and other analog circuit systems, multiple power supplies will occur in many cases. Some circuit modules have minimum requirements for the supply voltage, and cannot work normally below a certain value. Therefore, the maximum voltage automatic selection circuit can track and select among multiple power supplies to select the maximum voltage for the required circuit module. If the maximum voltage selection circuit cannot quickly and accurately select the maximum voltage, the performance of the analog circuit system will be affected. The traditional voltage selection circuit usually realizes the output of the selected voltage through a conduction switch, which is limited in speed and has low stability, and does not have low power consumption processing for the circuit. SUMMARY
[0003] In view of the above problems, the application provides a maximum voltage automatic selection circuit, which uses an NMOS tube energy storage capacitor instead of an ordinary metal capacitor, can greatly reduce the layout area of the circuit, converts the voltage comparison into a current comparison mode, and uses a Schmitt trigger, which not only increases the speed and accuracy of voltage comparison, but also improves the stability of the circuit. The current generated by the reference current circuit and the branch current of the mirror circuit are both in the order of nanoamperes, so the total power consumption of the entire circuit is extremely small.
[0004] In view of the prior art and the above problems, the application is realized through the following design scheme:
[0005] A maximum voltage automatic selection circuit includes a bias circuit (100), a common-source common-gate current mirror circuit (200), a maximum voltage comparison circuit (300), a Schmitt trigger, and maximum voltage selection switches (400, 500).
[0006] The bias circuit (100) includes a reference current generating circuit (101) and a bias voltage generating circuit (102) for generating a reference current and a bias voltage. The common-source common-gate current mirror circuit (200) adopts a common-source common-gate current mirror structure to copy the reference current as a current source of the maximum voltage comparison circuit (300). The maximum voltage comparison circuit (300) is composed of a common-source common-gate current source, a protection resistor, and an energy storage capacitor MNC. The Schmitt trigger reshapes the result of the maximum voltage comparison circuit and then drives the maximum voltage selection switch. The maximum voltage selection switch (400, 500) adopts a complementary CMOS structure and transmits the maximum voltage to the output terminal after conduction.
[0007] Further, the reference current generating circuit (101) is composed of NMOS MN1, resistor RS, PMOS MP1 and PMOS MP2. The gate of NMOS MN1 is connected to the ideal voltage bias VREF, the source is connected to resistor RS to form source negative feedback, the drain is connected to the drain of PMOS MP1 and the gate of PMOS MP2; one end of resistor RS is connected to the source of NMOS MN1 and the other end is connected to ground; the source of PMOS MP1 is connected to the drain of PMOS MP2 and the gate of PMOS MP1 is connected to bias voltage VBP2; the source of PMOS MP2 is connected to power supply voltage VINA.
[0008] Further, the bias generating circuit (102) is composed of PMOS MP3, PMOS MP4, PMOS MP5, NMOS MN2 and NMOS MN3. The source of PMOS MP3 is connected to power supply voltage VINA, the gate is connected to bias voltage VBP1, and the drain is connected to the source of PMOS MP4; the gate of PMOS MP4 is connected to bias voltage VBP2, and the drain is connected to the drain of NMOS MN2; the gate and the drain of PMOS MP5 are connected to the drain of NMOS MN3 after being shorted, and the source is connected to power supply voltage VINA; the gate of PMOS MP4 and the gate of NMOS MN3 are connected to the drain of NMOS MN2 after being shorted, and the source is connected to ground; the source of NMOS MN3 is connected to ground.
[0009] Further, the common source common gate current mirror circuit (200) is composed of PMOS MP6, PMOS MP7, NMOS MN4, NMOS MN5, NMOS MN6, NMOS MN7, NMOS MN8 and NMOS MN9. The source of PMOS MP6 is connected to power supply voltage VINA, the gate is connected to bias voltage VBP1, and the drain is connected to the source of PMOS MP7; the gate of PMOS MP7 is connected to bias voltage VBP2, and the drain is connected to the drain of NMOS MN4 and the gate of NMOS MN5; the gate of NMOS MN4 is connected to bias voltage VBN1, and the source is connected to the drain of NMOS MN5; the source of NMOS MN5 is connected to ground; the gates of NMOS MN7 and NMOS MN9 are both connected to bias voltage VBN2, and the sources are both connected to ground, the drain of NMOS MN7 is connected to the source of NMOS MN6, and the drain of NMOS MN9 is connected to the source of NMOS MN8; the gates of NMOS MN6 and NMOS MN8 are both connected to bias voltage VBN1, the drain of NMOS MN6 is connected to node VG, and the drain of NMOS MN8 is connected to node VC.
[0010] Further, the maximum voltage comparison circuit (300) is composed of a resistor RN, a resistor RP, a PMOS tube MP8, a PMOS tube MP9, an energy storage capacitor MNC and two common-source and common-gate current sources. One end of the resistor RN is connected with the input voltage VIN, and the other end is connected with the source of the PMOS tube MP8; one end of the resistor RP is connected with the input voltage VIP, and the other end is connected with the source of the PMOS tube MP9; the PMOS tube MP8 is connected with the gate of the PMOS tube MP9 after the gate-drain of the PMOS tube MP8 is shorted; the sources of the PMOS tube MP8 and the PMOS tube MP9 are connected with one common-source and common-gate current source respectively; the energy storage capacitor MNC is a MOS capacitor, which is formed by connecting the source-drain of an NMOS tube with the ground and connecting the gate with the VC node.
[0011] Further, the maximum voltage comparison circuit (300) is composed of a resistor RN, a resistor RP, a PMOS tube MP8, a PMOS tube MP9, an energy storage capacitor MNC and two common-source and common-gate current sources. One end of the resistor RN is connected with the input voltage VIN, and the other end is connected with the source of the PMOS tube MP8; one end of the resistor RP is connected with the input voltage VIP, and the other end is connected with the source of the PMOS tube MP9; the PMOS tube MP8 is connected with the gate of the PMOS tube MP9 after the gate-drain of the PMOS tube MP8 is shorted; the sources of the PMOS tube MP8 and the PMOS tube MP9 are connected with one common-source and common-gate current source respectively; the energy storage capacitor MNC is a MOS capacitor, which is formed by connecting the source-drain of an NMOS tube with the ground and connecting the gate with the VC node.
[0012] Further, the maximum voltage selection switch (400, 500) is a complementary CMOS switch; wherein the VIN branch switch (400) is composed of an NMOS tube MN10 and a PMOS tube MP10; wherein the VIP branch switch (500) is composed of an NMOS tube MN11 and a PMOS tube MP11; the gate of the NMOS tube MN10 is connected with the SB signal, the gate of the PMOS tube MP10 is connected with the SA signal, the drain of the NMOS tube MN10 and the source of the PMOS tube MP10 are connected with the input signal VIN, and the source of the NMOS tube MN10 and the drain of the PMOS tube MP10 are connected with the output signal VOUT; the gate of the NMOS tube MN11 is connected with the SA signal, the gate of the PMOS tube MP11 is connected with the SB signal, the drain of the NMOS tube MN11 and the source of the PMOS tube MP11 are connected with the input signal VIP, and the source of the NMOS tube MN11 and the drain of the PMOS tube MP11 are connected with the output signal VOUT.
[0013] Further, the supply voltage of the Schmidt trigger, the inverter INV1 and the inverter INV2 is the output voltage VOUT.
[0014] The maximum voltage automatic selection circuit provided by the application has the following advantages:
[0015] (1) The NMOS tube energy storage capacitor is used to replace the ordinary metal capacitor, which can greatly reduce the layout area of the circuit.
[0016] (2) The way of converting voltage comparison into current comparison and the use of Schmitt trigger not only increase the speed and accuracy of voltage comparison, but also improve the stability of the circuit.
[0017] (3) The currents generated by the reference current circuit and the mirror circuit are both in nano-ampere level, so the total power consumption of the whole circuit is extremely small. BRIEF DESCRIPTION OF DRAWINGS
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. The drawings in the following description are only some embodiments recorded in the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the premise of not paying additional creative labor.
[0019] Figure 1 is a structure diagram of a bias-free circuit of a maximum voltage automatic selection circuit of the present application;
[0020] Figure 2 is a complete circuit structure diagram of a maximum voltage automatic selection circuit of the present application;
[0021] Figure 3 is a schematic diagram of the relationship between the MOS capacitor value MNC and its gate voltage VG in the present application;
[0022] Figure 4 is a final simulation result diagram of a maximum voltage automatic selection circuit of the present application; DETAILED DESCRIPTION
[0023] In order to make the purpose, technical solutions and advantages of the present application more clear, the specific embodiments of the present application will be described in detail below with reference to the drawings. The examples of these preferred embodiments are illustrated in the drawings. The embodiments of the present application shown in the drawings are only exemplary and are not limited to these embodiments.
[0024] In addition, it also needs to be explained that, in order to avoid the unnecessary details from obscuring the present application, only the structures and / or processing steps closely related to the scheme according to the present application are shown in the drawings, and other details not closely related to the present application are omitted.
[0025] In the description of the present application, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.
[0026] Please refer to the circuit structure Figure 1 The embodiment of the present application comprises: a bias circuit (100), a common-source common-gate current mirror circuit (200), a maximum voltage comparison circuit (300), a Schmitt trigger, and a maximum voltage selection switch (400, 500).
[0027] The bias circuit (100) comprises a reference current generating circuit (101) and a bias voltage generating circuit (102) for generating reference current and bias voltage; the common-source common-gate current mirror circuit (200) adopts a common-source common-gate current mirror structure to copy the reference current as a current source of the maximum voltage comparison circuit (300); the maximum voltage comparison circuit (300) is composed of a common-source common-gate current source, a protection resistor, and an energy storage capacitor MNC; the Schmitt trigger reshapes the result of the maximum voltage comparison circuit and then drives the maximum voltage selection switch; the maximum voltage selection switch (400, 500) adopts a complementary CMOS structure and transmits the maximum voltage to the output end after being turned on.
[0028] Further, the reference current generating circuit (101) is composed of an NMOS tube MN1, a resistor RS, a PMOS tube MP1, and a PMOS tube MP2. The gate of the NMOS tube MN1 is connected to an ideal voltage bias VREF, the source is connected to the resistor RS to form source negative feedback, and the drain is connected to the drain of the PMOS tube MP1 and the gate of the PMOS tube MP2; one end of the resistor RS is connected to the source of the NMOS tube MN1, and the other end is connected to ground; the source of the PMOS tube MP1 is connected to the drain of the PMOS tube MP2, and the gate of the PMOS tube MP1 is connected to a bias voltage VBP2; the source of the PMOS tube MP2 is connected to a power supply voltage VINA.
[0029] Further, the bias generation circuit (102) is composed of PMOS MP3, PMOS MP4, PMOS MP5, NMOS MN2, NMOS MN3. The source of PMOS MP3 is connected to the power supply voltage VINA, the gate is connected to the bias voltage VBP1, and the drain is connected to the source of PMOS MP4; the gate of PMOS MP4 is connected to the bias voltage VBP2, and the drain is connected to the drain of NMOS MN2; PMOS MP5 is connected to the drain of NMOS MN3 after the gate-drain short circuit, and the source is connected to the power supply voltage VINA; NMOS MN2 is connected to the gate of PMOS MP4 and the drain of NMOS MN3 after the gate-drain short circuit, and the source is connected to the ground; and the source of NMOS MN3 is connected to the ground.
[0030] Further, the common-source common-gate current mirror circuit (200) is composed of PMOS MP6, PMOS MP7, NMOS MN4, NMOS MN5, NMOS MN6, NMOS MN7, NMOS MN8, NMOS MN9. The source of PMOS MP6 is connected to the power supply voltage VINA, the gate is connected to the bias voltage VBP1, and the drain is connected to the source of PMOS MP7; the gate of PMOS MP7 is connected to the bias voltage VBP2, and the drain is connected to the drain of NMOS MN4 and the gate of NMOS MN5; the gate of NMOS MN4 is connected to the bias voltage VBN1, and the source is connected to the drain of NMOS MN5; the source of NMOS MN5 is connected to the ground; the gates of NMOS MN7 and NMOS MN9 are both connected to the bias voltage VBN2, and the sources are both connected to the ground, the drain of NMOS MN7 is connected to the source of NMOS MN6, and the drain of NMOS MN9 is connected to the source of NMOS MN8; the gates of NMOS MN6 and NMOS MN8 are both connected to the bias voltage VBN1, the drain of NMOS MN6 is connected to the VG node, and the drain of NMOS MN8 is connected to the VC node.
[0031] Further, the maximum voltage comparison circuit (300) is composed of a resistor RN, a resistor RP, a PMOS MP8, a PMOS MP9, an energy storage capacitor MNC, and two common-source common-gate current sources. One end of the resistor RN is connected to the input voltage VIN, and the other end is connected to the source of the PMOS MP8; one end of the resistor RP is connected to the input voltage VIP, and the other end is connected to the source of the PMOS MP9; the PMOS MP8 is connected to the gate of the PMOS MP9 after the gate-drain short circuit; the sources of the PMOS MP8 and the PMOS MP9 are respectively connected to one of the common-source common-gate current sources; and the energy storage capacitor MNC is a MOS capacitor formed by connecting the source and the drain of the NMOS to the ground and connecting the gate to the VC node.
[0032] Further, the maximum voltage comparison circuit is a Schmitt trigger, and the output of the Schmitt trigger after the voltage at both ends of the energy storage capacitor MNC is shaped and enters the inverter INV1 is recorded as SA; the output of the inverter INV2 after the SA signal enters is recorded as SB; therefore, SA and SB are a pair of logic signals opposite to each other.
[0033] Further, the maximum voltage selection switch (400, 500) is a complementary CMOS switch; wherein the VIN branch switch (400) is composed of an NMOS tube MN10 and a PMOS tube MP10; wherein the VIP branch switch (500) is composed of an NMOS tube MN11 and a PMOS tube MP11; the gate of the NMOS tube MN10 is connected to the SB signal, the gate of the PMOS tube MP10 is connected to the SA signal, the drain of the NMOS tube MN10 and the source of the PMOS tube MP10 are connected and connected to the input signal VIN, and the source of the NMOS tube MN10 and the drain of the PMOS tube MP10 are connected and connected to the output signal VOUT; the gate of the NMOS tube MN11 is connected to the SA signal, the gate of the PMOS tube MP11 is connected to the SB signal, the drain of the NMOS tube MN11 and the source of the PMOS tube MP11 are connected and connected to the input signal VIP, and the source of the NMOS tube MN11 and the drain of the PMOS tube MP11 are connected and connected to the output signal VOUT.
[0034] Further, the power supply voltage of the Schmitt trigger, the inverter INV1 and the inverter INV2 is the output voltage VOUT.
[0035] The maximum voltage automatic selection circuit provided by the application has the following beneficial effects:
[0036] (1) The NMOS tube energy storage capacitor is used instead of the ordinary metal capacitor, which can greatly reduce the layout area of the circuit.
[0037] (2) The voltage comparison is converted into a current comparison mode and the Schmitt trigger is used, which not only increases the speed and accuracy of the voltage comparison, but also improves the stability of the circuit.
[0038] (3) The currents generated by the reference current circuit and the mirror circuit are both in the order of nanoamperes, so the total power consumption of the entire circuit is extremely small.
[0039] In this embodiment, the purpose of the maximum voltage automatic selection circuit is to accurately and quickly select the maximum voltage from the two input voltages that are constantly changing and transmit it to the output end.
[0040] As Figure 2The principle of the reference current generating circuit (101) in the embodiment is shown in the complete circuit structure diagram. The ideal voltage bias VREF is added to the gate of the NMOS tube MN1, and the source voltage VS generated after the conduction of MN1 generates the reference current through the resistance RS. The value of the reference current can be reduced to the nanampere level by increasing the resistance value of RS. The voltage-current relationship is shown in the following two equations:
[0041]
[0042]
[0043] The principle of the bias voltage generating circuit (102) in the embodiment is as follows. The common-source common-gate current mirror composed of the PMOS tube MP3 and the PMOS tube PM4 proportionally copies the reference current IREF, and then the bias voltage VBN1 is generated after flowing through the gate-drain shorted NMOS tube MN2. The NMOS tube MN2 proportionally copies the reference current IREF to the NMOS tube MN3, and then the bias voltage VBP2 is generated after flowing through the gate-drain shorted PMOS tube MP5. The voltage-current relationship is shown in the following two equations:
[0044]
[0045]
[0046] The principle of the maximum voltage comparison circuit (300) in the embodiment is as follows. The reference current IREF is proportionally copied twice through the common-source common-gate current mirror and then serves as the current source of the maximum voltage comparison circuit (300). Due to the current source, the branch current of the input voltage VIN is always maintained at IREF. The branch current of the input voltage VIP is different. At this time, if the input voltage VIP> the input voltage VIN, the source voltage of the PMOS tube MP9 will be greater than that of the PMOS tube MP9, and the current on the PMOS tube MP9 will also be greater than that of the current source below. The excess current flows to the energy storage capacitor MNC, and the voltage of the VC node is pulled up. If the input voltage VIP< the input voltage VIN, the source voltage of the PMOS tube MP9 will be less than that of the PMOS tube MP9, and the current on the PMOS tube MP9 will also be greater than that of the current source below. The energy storage capacitor MNC discharges to the current source branch until the voltage of the VC node is pulled down. Therefore, there is the following relationship: when VIP> VIN, the VC voltage is high; when VIP< VIN, the VC voltage is low.
[0047] From the above analysis, when the VC node voltage is high, the high-level SA signal is obtained after the low-level output of the Schmitt trigger shaping and the high-level output of the inverter INV1, and the low-level SB signal is obtained after the high-level SA signal is inverted by the inverter INV2; when the VC node voltage is low, the low-level SA signal is obtained after the high-level output of the Schmitt trigger shaping and the low-level output of the inverter INV1, and the high-level SB signal is obtained after the low-level SA signal is inverted by the inverter INV2.
[0048] The principle of the maximum voltage selection switch (400, 500) in the embodiment is as follows: when the SA is high and the SB is low, the voltage selection switch (500) is turned on, the voltage selection switch (400) is turned off, and VOUT=VIP; when the SA is low and the SB is high, the voltage selection switch (400) is turned on, the voltage selection switch (500) is turned off, and VOUT=VIN.
[0049] Through the above analysis, the relationship between the voltage signals of each node in the circuit is finally sorted out as shown in Table 1:
[0050] Input relationship VC SA SB Switch 400 Switch 500 VOUT VIN > VIP Low Low High On Off VIN VIN < VIP High High Low Off On VIP
[0051] Table 1
[0052] Figure 3 The figure is a schematic diagram of the relationship between the MOS capacitor value MNC and the gate voltage VG in the application. The curve in the figure shows the relationship between the MOS capacitor value MNC and the voltage applied to the gate. Although the capacitor value is not constant during the change of the gate voltage, it does not affect the normal function of the maximum voltage automatic selection circuit of the application.
[0053] Figure 4 The figure is a schematic diagram of the final simulation result of the maximum voltage automatic selection circuit of the application. The curve in the figure shows that the maximum voltage automatic selection circuit of the application can accurately and quickly select the maximum voltage from the two continuously changing input voltages and transmit it to the output end.
[0054] In addition, it should be noted that in the present specification, "including", "containing" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.
[0055] It should be understood that although the present specification describes the embodiments in the form of a single independent technical solution, the specification is described in this way only for the sake of clarity, and the skilled person should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that the skilled person can understand.
Claims
1. A maximum voltage automatic selection circuit, characterized by, The application relates to a maximum voltage selection circuit, which comprises a bias circuit (100), a common-source common-gate current mirror circuit (200), a maximum voltage comparison circuit (300), a Schmitt trigger, maximum voltage selection switches (400, 500); the bias circuit (100) comprises a reference current generating circuit (101) and a bias voltage generating circuit (102) for generating reference current and bias voltage; the common-source common-gate current mirror circuit (200) adopts a common-source common-gate current mirror structure to copy the reference current as a current source of the maximum voltage comparison circuit (300); the maximum voltage comparison circuit (300) is composed of a common-source common-gate current source, a protection resistor and an energy storage capacitor MNC; the Schmitt trigger reshapes the result of the maximum voltage comparison circuit and then drives the maximum voltage selection switches; The maximum voltage selection switches (400, 500) adopt a complementary CMOS structure and transmit the maximum voltage to an output end after being turned on; the Schmitt trigger reshapes the result of the maximum voltage comparison circuit, that is, the voltage between the energy storage capacitor MNC, and then the output of the inverter INV1 after the SA signal enters the inverter INV2 is recorded as SB; therefore, SA and SB are a pair of logic opposite signals; the supply voltage of the Schmitt trigger, the inverter INV1 and the inverter INV2 is the maximum voltage in the two input voltages, that is, VOUT; The reference current generating circuit (101) is composed of an NMOS tube MN1, a resistor RS, a PMOS tube MP1 and a PMOS tube MP2; the gate of the NMOS tube MN1 is connected with an ideal voltage bias VREF, the source is connected with the resistor RS to form source negative feedback, and the drain is connected with the drain of the PMOS tube MP1 and the gate of the PMOS tube MP2; one end of the resistor RS is connected with the source of the NMOS tube MN1, and the other end is connected with the ground; the source of the PMOS tube MP1 is connected with the drain of the PMOS tube MP2, and the gate of the PMOS tube MP1 is connected with a bias voltage VBP2; the source of the PMOS tube MP2 is connected with a power voltage VINA; The maximum voltage comparison circuit (300) is composed of a resistor RN, a resistor RP, a PMOS tube MP8, a PMOS tube MP9, an energy storage capacitor MNC and two common-source common-gate current sources; one end of the resistor RN is connected with an input voltage VIN, and the other end is connected with the source of the PMOS tube MP8; one end of the resistor RP is connected with an input voltage VIP, and the other end is connected with the source of the PMOS tube MP9; the PMOS tube MP8 is connected with the gate of the PMOS tube MP9 after the gate-drain of the PMOS tube MP8 is short-circuited; the sources of the PMOS tube MP8 and the PMOS tube MP9 are respectively connected with one common-source common-gate current source; the energy storage capacitor MNC is a MOS capacitor which is formed by connecting the source and the drain of the NMOS tube with the ground and connecting the gate with a VC node; The maximum voltage selection switches (400, 500) are complementary CMOS switches. The VIN branch switch (400) is composed of NMOS MN10 and PMOS MP10; the VIP branch switch (500) is composed of NMOS MN11 and PMOS MP11; the gate of NMOS MN10 is connected with the SB signal, the gate of PMOS MP10 is connected with the SA signal, the drain of NMOS MN10 and the source of PMOS MP10 are connected and connected with the input signal VIN, the source of NMOS MN10 and the drain of PMOS MP10 are connected and connected with the output signal VOUT; the gate of NMOS MN11 is connected with the SA signal, the gate of PMOS MP11 is connected with the SB signal, the drain of NMOS MN11 and the source of PMOS MP11 are connected and connected with the input signal VIP, the source of NMOS MN11 and the drain of PMOS MP11 are connected and connected with the output signal VOUT.
2. The maximum voltage automatic selection circuit of claim 1, wherein: The bias voltage generating circuit (102) is composed of PMOS MP3, PMOS MP4, PMOS MP5, NMOS MN2 and NMOS MN3; the source of PMOS MP3 is connected with the power voltage VINA, the gate is connected with the bias voltage VBP1, the drain is connected with the source of PMOS MP4; the gate of PMOS MP4 is connected with the bias voltage VBP2, the drain is connected with the drain of NMOS MN2; the gate and the drain of PMOS MP5 are connected after being short-circuited, the source is connected with the drain of NMOS MN3, and the source is connected with the power voltage VINA; the gate and the drain of NMOS MN2 are short-circuited, the source is connected with the drain of PMOS MP4 and the gate of NMOS MN3, and the source is connected with the ground; the source of NMOS MN3 is connected with the ground.
3. The maximum voltage automatic selection circuit of claim 1, wherein: The common-source common-gate current mirror circuit (200) is composed of PMOS MP6, PMOS MP7, NMOS MN4, NMOS MN5, NMOS MN6, NMOS MN7, NMOS MN8 and NMOS MN9; the source of PMOS MP6 is connected to a source voltage VINA, the gate is connected to a bias voltage VBP1, and the drain is connected to the source of PMOS MP7; the gate of PMOS MP7 is connected to a bias voltage VBP2, the drain is connected to the drain of NMOS MN4 and the gate of NMOS MN5; the gate of NMOS MN4 is connected to a bias voltage VBN1, the source is connected to the drain of NMOS MN5; the source of NMOS MN5 is connected to the ground; the gates of NMOS MN7 and NMOS MN9 are both connected to a bias voltage VBN2, the sources are both connected to the ground, the drain of NMOS MN7 is connected to the source of NMOS MN6, and the drain of NMOS MN9 is connected to the source of NMOS MN8; the gates of NMOS MN6 and NMOS MN8 are both connected to a bias voltage VBN1, the drain of NMOS MN6 is connected to a VG node, and the drain of NMOS MN8 is connected to a VC node.
Citation Information
Patent Citations
Maximum voltage automatic selection circuit
CN220603913U