An ultra-high resolution analog-to-digital converter

Abstract

The present application provides an ultra-high resolution analog-to-digital converter, which includes a second-order Delta-Sigma modulation and demodulation unit and a digital filtering unit; the second-order Delta-Sigma modulation and demodulation unit includes a signal conditioning circuit, a first-stage integrator circuit, a second-stage integrator circuit, an analog-to-digital conversion unit, a first digital-to-analog conversion unit, a second digital-to-analog conversion unit, and a processing unit; multi-bit digital-to-analog conversion units and analog-to-digital conversion units are used to achieve multi-bit quantization and multi-bit feedback, effectively reducing quantization noise and circuit noise and improving the signal-to-noise ratio; the digital signal output by the second-order Delta-Sigma modulation and demodulation unit is decimated and filtered by the digital filtering unit, and then a high-resolution digital signal is output, enabling high-resolution and large-dynamic-range data acquisition.

Description

Technical Field

[0001] One or more embodiments of this specification relate to the technical field of high-resolution instrumentation, and particularly to an analog-to-digital converter with ultra-high resolution. Background Art

[0002] With the development of electronic technology, the resolution and dynamic response range of analog-to-digital converters have both increased. Currently, some analog-to-digital converters produced by companies can reach a maximum of 23.5 effective bits, and the dynamic range is less than 144 dB. However, in some fields of high-precision instrument measurement, a larger dynamic range is often required. For example, for a seismic data collector used to collect seismic observation data, the dynamic range of the output signal of the seismic observation instrument to be measured is above 150 dB, and the existing analog-to-digital converters are still difficult to meet such requirements. Summary of the Invention

[0003] In view of this, the purpose of one or more embodiments of this specification is to propose an analog-to-digital converter with ultra-high resolution, which can obtain output signals with ultra-high resolution and large dynamic range.

[0004] Based on the above purpose, one or more embodiments of this specification provide an analog-to-digital converter with ultra-high resolution, including a second-order Delta-Sigma modulation and demodulation unit and a digital filtering unit;

[0005] The second-order Delta-Sigma modulation and demodulation unit includes a signal conditioning circuit, a first-stage integrator circuit, a second-stage integrator circuit, an analog-to-digital conversion unit, a first digital-to-analog conversion unit, a second digital-to-analog conversion unit, and a processing unit;

[0006] Differential analog signals are input to the signal conditioning circuit. The differential output terminal of the signal conditioning circuit is connected to the differential inverting input terminal of the first-stage integrator circuit. The output terminal of the first-stage integrator circuit is connected to the differential inverting input terminal of the second-stage integrator circuit. The differential output terminal of the second-stage integrator circuit is connected to the differential input terminal of the analog-to-digital conversion unit. The output terminal of the analog-to-digital conversion unit is connected to the signal input terminal of the processing unit. One signal output terminal of the processing unit is connected to the input terminal of the first digital-to-analog conversion unit through an inverter. The differential output terminal of the first digital-to-analog conversion unit is connected to the differential inverting input terminal of the first-stage integrator. The other signal output terminal of the processing unit is connected to the input terminal of the second digital-to-analog conversion unit. The differential output terminal of the second digital-to-analog conversion unit is connected to the differential inverting input terminal of the second-stage integrator. The digital signal output terminal of the processing unit is connected to the input terminal of the digital filtering unit. The digital filtering unit filters the input digital signal and then outputs the converted digital signal.

[0007] Optionally, the processing unit performs primary filtering on the received digital signal and transmits the digitally filtered signal to the digital filtering unit.

[0008] Optionally, the signal conditioning circuit includes two operational amplifiers. The differential analog signals are respectively connected to the non-inverting input terminals of the two operational amplifiers through resistors R1. The inverting input terminals of the two operational amplifiers are respectively grounded through resistors 4R, and the inverting input terminals of the two operational amplifiers are respectively connected to the output terminals of the operational amplifiers through resistors 2R. The two output terminals of the two operational amplifiers form a differential output terminal, which is connected to the differential input terminal of the first-stage integrator circuit.

[0009] Optionally, a TVS protection circuit is provided at the differential input terminal of the signal conditioning circuit.

[0010] Optionally, the first-stage integrator circuit includes two operational amplifiers U3 and U4. The differential output terminal of the signal conditioning circuit is respectively connected to the inverting input terminals of the two operational amplifiers U3 and U4 through resistors 3R. The non-inverting input terminals of the two operational amplifiers U3 and U4 are respectively grounded through resistors R2. The differential signal output terminals of the first digital-to-analog converter are respectively connected to the inverting input terminals of the two operational amplifiers U3 and U4 through resistors 2R. The output terminals of the two operational amplifiers U3 and U4 are respectively connected to the inverting input terminals of the two operational amplifiers U3 and U4 through capacitors;

[0011] The second-stage integrator circuit includes two operational amplifiers U5 and U6. The output terminals of the two operational amplifiers U3 and U4 are respectively connected to the inverting input terminals of the two operational amplifiers U5 and U6 through resistors 2R. The non-inverting input terminals of the two operational amplifiers U5 and U6 are respectively grounded through resistors R3. The differential signal output terminals of the second digital-to-analog converter are respectively connected to the inverting input terminals of the two operational amplifiers U5 and U6 through resistors 2R. The output terminals of the two operational amplifiers U5 and U6 are respectively connected to the inverting input terminals of the two operational amplifiers U5 and U6 through capacitors; the output terminals of the two operational amplifiers U5 and U6 form a differential output terminal, which is connected to the input terminal of the analog-to-digital conversion unit.

[0012] Optionally, the analog-to-digital conversion unit uses a 16-bit ADC chip; the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are respectively formed by paralleling two 16-bit DAC chips, and the four 16-bit DAC chips have the same model.

[0013] Optionally, the output signals of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are calibrated using preset calibration parameters, and the calibrated signals are respectively input into the first-stage integrator circuit and the second-stage integrator circuit.

[0014] Optionally, the method for determining the calibration parameters is to divide the output voltage range of the DAC chip into multiple voltage intervals according to a predetermined voltage interval. For each voltage interval, by inputting different digital signals and measuring the corresponding output analog voltage signals, fitting processing is performed according to the relationship between the input digital signals and the output analog voltage signals to obtain the calibration coefficient and calibration offset corresponding to this voltage interval;

[0015] The relationship between the input digital signal D and the output analog voltage signal Vout is:

[0016] Vout = k × D × VR / 2^N + b (1)

[0017] where VR is the reference voltage input to the DAC chip, N is the number of bits of the DAC chip, k is the calibration coefficient, and b is the calibration offset.

[0018] Optionally, the digital filter unit is configured with a multi-stage filter, and the multi-stage filter is used to output digital signals with variable sampling rates.

[0019] Optionally, the multi-stage filter includes a first-stage filter and a second-stage filter. The first-stage filter is a first-stage linear-phase filter, and the second-stage filter includes a second-stage linear-phase filter and a second-stage minimum-phase filter. After the digital signal output by the processing unit is filtered by the first-stage linear-phase filter, it is respectively filtered by the second-stage linear-phase filter and the second-stage minimum-phase filter to obtain a linear-phase digital signal and a minimum-phase digital signal.

[0020] As can be seen from the above, the ultra-high-resolution analog-to-digital converter provided by one or more embodiments of this specification builds a second-order Delta-Sigma modulation and demodulation unit with discrete electronic components such as a second-order integrator circuit, a multi-bit digital-to-analog conversion unit, and an analog-to-digital conversion unit. The multi-bit digital-to-analog conversion unit and the analog-to-digital conversion unit are used to achieve multi-bit quantization and multi-bit feedback, effectively reducing quantization noise and circuit noise, improving the signal-to-noise ratio. The feedback loop uses a multi-bit DAC chip with a parallel structure, which can reduce the noise impact introduced by non-linearity. After the digital signal output by the second-order Delta-Sigma modulation and demodulation unit is decimated and filtered by the digital filter unit, a digital signal with ultra-high resolution and large dynamic range can be output. Description of the Drawings

[0021] To more clearly illustrate the technical solutions in one or more embodiments of this specification or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only one or more embodiments of this specification. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 is the structural block diagram of the analog-to-digital converter for one or more embodiments of this specification;

[0023] Figure 2 is the structural block diagram of the second-order Delta-Sigma modulation and demodulation unit for one or more embodiments of this specification;

[0024] Figure 3 is the structural schematic diagram of the signal conditioning circuit for one or more embodiments of this specification;

[0025] Figure 4 is the structural schematic diagram of the second-order integrator circuit for one or more embodiments of this specification;

[0026] Figure 5 is the structural schematic diagram of the digital filter unit for one or more embodiments of this specification. Specific Embodiments

[0027] To make the purpose, technical solutions, and advantages of this disclosure clearer and more understandable, the following will further elaborate on this disclosure in detail with reference to specific embodiments and the accompanying drawings.

[0028] It should be noted that unless otherwise defined, the technical terms or scientific terms used in one or more embodiments of this specification should have the ordinary meaning understood by those of ordinary skill in the field to which this disclosure belongs. The "first", "second", and similar terms used in one or more embodiments of this specification do not represent any order, quantity, or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "up", "down", "left", "right", etc. are only used to represent relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0029] Such as Figure 1 、 2As shown, one or more embodiments of this specification provide an ultra-high-resolution analog-to-digital converter, including a second-order Delta-Sigma modulation and demodulation unit and a digital filtering unit;

[0030] The second-order Delta-Sigma modulation and demodulation unit includes a signal conditioning circuit, a first-stage integrator circuit, a second-stage integrator circuit, an analog-to-digital conversion unit, a first digital-to-analog conversion unit, a second digital-to-analog conversion unit, and a processing unit;

[0031] The differential analog signal is input to the signal conditioning circuit. The differential output terminal of the signal conditioning circuit is connected to the differential inverting input terminal of the first-stage integrator circuit. The output terminal of the first-stage integrator circuit is connected to the differential inverting input terminal of the second-stage integrator circuit. The differential output terminal of the second-stage integrator circuit is connected to the differential input terminal of the analog-to-digital conversion unit. The output terminal of the analog-to-digital conversion unit is connected to the signal input terminal of the processing unit. One signal output terminal of the processing unit is connected to the input terminal of the first digital-to-analog conversion unit through an inverter. The differential output terminal of the first digital-to-analog conversion unit is connected to the differential inverting input terminal of the first-stage integrator. Another signal output terminal of the processing unit is connected to the input terminal of the second digital-to-analog conversion unit. The differential output terminal of the second digital-to-analog conversion unit is connected to the differential inverting input terminal of the second-stage integrator. The digital signal output terminal of the processing unit is connected to the input terminal of the digital filtering unit. The digital filtering unit filters the input digital signal and then outputs the converted digital signal.

[0032] The differential analog signal is input to the signal conditioning circuit through the differential input terminal. The signal conditioning circuit amplifies the input differential analog signal. The amplified differential analog signal and the differential analog signal output by the first digital-to-analog conversion unit are input to the first-stage integrator circuit. The first-stage integrator circuit integrates the input signal and outputs a differential analog signal. The differential analog signal and the differential analog signal output by the second digital-to-analog conversion unit are input to the second-stage integrator circuit. The second-stage integrator circuit integrates the input signal and outputs a differential analog signal that is input to the analog-to-digital conversion unit. The analog-to-digital conversion unit converts the input differential analog signal into a digital signal and then inputs it to the processing unit.

[0033] The processing unit receives the digital signal from the analog-to-digital conversion unit. On the one hand, the received digital signal is directly output through one signal output terminal. This path of digital signal is inverted by an inverter and then input into the first digital-to-analog conversion unit. The first digital-to-analog conversion unit converts the inverted digital signal into an analog signal and inputs this analog signal into the first-stage integrator circuit. On the other hand, the received digital signal is directly output through another signal output terminal. This path of digital signal is input into the second digital-to-analog conversion unit. The second digital-to-analog conversion unit converts this path of digital signal into an analog signal and inputs this analog signal into the second-stage integrator circuit. On the third hand, the processing unit performs primary filtering on the received digital signal and transmits the digitally filtered signal to the digital filtering unit. The digital filtering unit further performs filtering and decimation on the input digital signal and finally outputs the required digital signal.

[0034] The ultra-high-resolution analog-to-digital converter provided in this embodiment. The second-order Delta-Sigma modulation and demodulation unit is composed of discrete electronic components such as a two-stage integrator circuit, a multi-bit digital-to-analog conversion unit, and an analog-to-digital conversion unit. The two-stage integrator circuit is built based on a low-noise operational amplifier. The multi-bit digital-to-analog conversion unit and the analog-to-digital conversion unit are used to achieve multi-bit quantization and multi-bit feedback, effectively reducing quantization noise and circuit noise and improving the signal-to-noise ratio. After the digital signal output by the second-order Delta-Sigma modulation and demodulation unit is decimated and filtered by the digital filtering unit, a high-resolution digital signal is output, enabling ultra-high-resolution and large dynamic range data acquisition.

[0035] As Figure 3 shown, the signal conditioning circuit is in a completely symmetric circuit form. The signal conditioning circuit includes two operational amplifiers U1 and U2. The differential analog signals are respectively connected to the non-inverting inputs of the two operational amplifiers U1 and U2 through resistors R1 (with a resistance value of 1K ohm each). The inverting inputs of the two operational amplifiers U1 and U2 are respectively grounded through resistors 4R. The inverting inputs of the two operational amplifiers U1 and U2 are respectively connected to the output terminals of the operational amplifiers U1 and U2 through resistors 2R. The two output terminals of the two operational amplifiers U1 and U2 form a differential output terminal, which is connected to the differential input terminal of the first-stage integrator circuit. The resistors in the circuit form matching resistors, which can ensure the stability of the circuit and amplify the input differential analog signal by a specific amplification factor.

[0036] In some ways, the output signal of the seismic observation instrument is a differential analog signal. The amplitude range of this differential analog signal is -20V - 20V. This differential analog signal is input to the differential signal input terminals IN+ and IN- of the signal conditioning circuit. The differential analog signal is amplified 1.5 times by the matching resistors. The amplitude range of the differential signal output from the differential output terminals Vin+ and Vin- of the signal conditioning circuit is -30V - 30V. Optionally, a TVS protection circuit can also be set at the differential input terminals of the signal conditioning circuit to suppress possible transient interference.

[0037] As Figure 4 shown, the first-stage integrator circuit and the second-stage integrator circuit are cascaded to form a two-stage integrator circuit. The two-stage integrator circuit is in a completely symmetric circuit form. Specifically, the first-stage integrator circuit includes two operational amplifiers U3 and U4. The differential output terminals Vin+ and Vin- of the signal conditioning circuit are respectively connected to the inverting input terminals of the two operational amplifiers U3 and U4 through resistors 3R. The non-inverting input terminals of the two operational amplifiers U3 and U4 are respectively grounded through resistors R2 (with a resistance value of 1 kΩ). The output terminals of the two operational amplifiers U3 and U4 are respectively connected to the inverting input terminals of the operational amplifiers U3 and U4 through capacitors.

[0038] The second-stage integrator circuit includes two operational amplifiers U5 and U6. The output terminals of the two operational amplifiers U3 and U4 in the first-stage integrator circuit are respectively connected to the inverting input terminals of the two operational amplifiers U5 and U6 in the second-stage integrator circuit through resistors 2R. The non-inverting input terminals of the two operational amplifiers U5 and U6 are respectively grounded through resistors R3 (with a resistance value of 1 kΩ). The output terminals of the two operational amplifiers U5 and U6 are respectively connected to the inverting input terminals of the operational amplifiers U5 and U6 through capacitors.

[0039] The output terminals of the two operational amplifiers U5 and U6 form differential output terminals ADC_P and ADC_N, which are connected to the input terminal of the analog-to-digital conversion unit. The analog-to-digital conversion unit converts the input analog signal into a digital signal and transmits the digital signal to the processing unit.

[0040] In some ways, the analog-to-digital conversion unit uses a 16-bit ADC chip. The selected ADC chip should meet the requirements that the dynamic range is greater than 90 dB, the INL (Integral Nonlinearity) is less than 0.5 LSB, the power consumption is about 10 mW, the bandwidth should be adapted to the bandwidth of the analog-to-digital converter, and the reference source of the ADC chip should be well filtered to ensure low voltage noise and stable and reliable amplitude. Optionally, ADC chips that meet the above requirements can be selected, such as AD7688, AD1273, AD7693, etc. Taking AD7693 as an example, it is a 16-bit successive approximation analog-to-digital converter with a dynamic range of 96.5 dB, a THD (Total Harmonic Distortion) that can reach -120 dB at 1 kHz, a power consumption of about 4 mW at a sampling rate of 100 kHz, and a maximum conversion rate of 500 K. Optionally, the sampling rate of the ADC chip is set to 64 kHz.

[0041] In some ways, the first and second digital-to-analog conversion units use four 16-bit DAC chips of the same model. Among them, the first digital-to-analog conversion unit is composed of two 16-bit DAC chips in parallel, and the other two 16-bit DAC chips are in parallel to form the second digital-to-analog conversion unit. Using a digital-to-analog conversion unit with a parallel structure in the feedback loop can cancel the random noise generated by the DAC and reduce the problems of noise and harmonic distortion introduced by DAC non-linearity, ensuring the performance of the modem. Optionally, 16-bit DAC chips with a larger output range can be selected. For example, the output range of the AD5781 chip is -10V - 10V.

[0042] In some embodiments, the output signals of the first and second digital-to-analog conversion units are calibrated using preset calibration parameters, and the calibrated signals are respectively input into the first and second-stage integrator circuits. The calibrated signals can reduce the influence of noise and distortion introduced by DAC non-linearity.

[0043] Among them, the method for determining the calibration parameters is as follows: Let the digital signal input to the DAC chip be D, the analog voltage signal output by the DAC chip be Vout, the reference voltage input to the DAC chip be VR, and the number of bits of the DAC chip be N. Then the relationship between the input digital signal and the output analog voltage signal can be obtained as:

[0044] Vout = k × D × VR / 2^N + b (1)

[0045] Where k is the calibration coefficient and b is the calibration offset.

[0046] The output voltage range of the DAC chip is divided into multiple voltage intervals according to a predetermined voltage interval. For each voltage interval, by inputting different digital signals and measuring the corresponding output analog voltage signals, fitting processing of the input signal and the output signal is performed according to formula (1) to obtain the calibration coefficient and calibration offset of this voltage interval. The calibration coefficients and calibration offsets of each voltage interval are obtained according to the above method. The first and second digital-to-analog conversion units determine the corresponding voltage interval, calibration coefficient and calibration offset according to the input digital signal, and obtain the calibrated output analog voltage signal according to the calibration coefficient, calibration offset and the input digital signal according to formula (1).

[0047] For example, the output voltage range of the DAC chip is -10V - 10V. The output voltage range is divided into multiple voltage intervals according to a voltage interval of 100mV. For each voltage interval, different digital signals are input to the DAC chip, and the actual output voltage values corresponding to every 10mV are measured using a voltage measuring instrument. Based on the different digital signals and the measured actual output voltage values, the calibration coefficient and calibration offset corresponding to this voltage interval are obtained through fitting. Optionally, the fitting method can be linear fitting or polynomial fitting, and the specific method is not limited.

[0048] The processing unit receives the digital signal output by the analog-to-digital conversion unit through the SPI interface. On the one hand, the received digital signal is output to the inverter through the SPI interface. The inverter inverts the digital signal and inputs it to the first digital-to-analog conversion unit. The output terminals DAC1_N and DAC1_P of the first digital-to-analog conversion unit are connected to the inverting input terminals of operational amplifiers U3 and U4 through resistors 2R. On the second hand, the received digital signal is output to the second digital-to-analog conversion unit through the SPI interface. The output terminals DAC2_P and DAC2_N of the second digital-to-analog conversion unit are connected to the inverting input terminals of operational amplifiers U5 and U6 through resistor R2. On the third hand, the received digital signal is subjected to primary filtering, and the primarily filtered signal is input to the digital filter through the SPI interface.

[0049] In some ways, the processing unit performs half-band filtering processing on the received digital signal to achieve primary filtering of the digital signal. Since half of the filtering coefficients of half-band filtering are 0, the computational amount of the processing unit can be greatly reduced, and the data processing rate can be improved. Optionally, the analog-to-digital conversion unit outputs a digital signal of 64KHz, and the processing unit extracts a 2KHz signal from the 64KHz digital signal to achieve primary filtering. It can also increase the sampling rate of the analog-to-digital conversion unit according to specific application requirements. For example, the analog-to-digital conversion unit outputs a digital signal of 512KHz, and the processing unit extracts a 16KHz digital signal from the 512KHz digital signal.

[0050] Combined with Figure 4As shown, the inputs and outputs of operational amplifiers U3 and U4 of the first-stage integrator circuit are in the form of a completely symmetric differential circuit. The non-inverting inputs of operational amplifiers U3 and U4 are respectively grounded through resistors with the same resistance value. The differential signal output terminals Vin+ and Vin+ of the signal conditioning circuit are respectively connected to the inverting inputs of operational amplifiers U3 and U4 through resistors 3R. The differential signal output terminals DAC1_N and DAC1_P of the first digital-to-analog converter are respectively connected to the inverting inputs of operational amplifiers U3 and U4 through resistors 2R. The resistance value relationship of the matching resistors is 3:2, and the amplitude of the input differential analog signal is adjusted to the input range of the operational amplifier.

[0051] The inputs and outputs of operational amplifiers U5 and U6 of the second-stage integrator circuit are in the form of a completely symmetric differential circuit. The non-inverting inputs of operational amplifiers U5 and U6 are respectively grounded through resistors with the same resistance value. The differential signal output terminals of the first-stage integrator circuit are respectively connected to the inverting inputs of operational amplifiers U5 and U6 through resistors 2R. The differential signal output terminals DAC2_P and DAC2_N of the second digital-to-analog converter are respectively connected to the inverting inputs of operational amplifiers U5 and U6 through resistors 2R. After the second-stage integrator circuit adjusts the input signal, the output differential analog signal range is the signal amplitude range of 0V - 5V suitable for processing by the analog-to-digital conversion unit.

[0052] In some embodiments, to implement filtering calculation, the digital filtering unit can be implemented using a 32-bit floating-point operation processor. The digital filter unit can configure multiple-stage filters and the filtering coefficients of each filter, so as to output digital signals with variable sampling rates using the multiple-stage filters. In some ways, the multiple-stage filter includes a first-stage filter and a second-stage filter. The first-stage filter is a first-stage linear-phase filter, and the second-stage filter includes a second-stage linear-phase filter and a second-stage minimum-phase filter. After the digital signal output by the processing unit is filtered by the first-stage linear-phase filter, it is respectively filtered by the second-stage linear-phase filter and the second-stage minimum-phase filter to obtain a linear-phase digital signal and a minimum-phase digital signal.

[0053] Such as Figure 5As shown, in some embodiments, the digital filter unit includes a first-order filter FIR-L0 and two second-order filters FIR-L1 and FIR-M. The digital signal output by the processing unit is input to the data filter unit for two-stage FIR filtering. Specifically, taking the 2000-point sampled data output by the processing unit as an example, the 2000-point sampled data first passes through the first-order filter FIR-L0 for filtering, with a decimation ratio of 5, to obtain 400-point sampled data. The first-order filter FIR-L0 is a linear-phase filter, and its output bandwidth is much higher than the output bandwidth of the analog-to-digital converter. Therefore, a filter with fewer filter coefficients can be used to reduce the computational load. For example, the stopband attenuation is 60 dB, and the passband flatness is 1%. The 400-point sampled data output by the first-order filter FIR-L0 passes through the second-order filter FIR-L1 for filtering. The second-order filter FIR-L1 is a linear-phase filter, with a decimation ratio of 2, to obtain 200-point sampled data, and then passes through the second-order filter FIR-L1 for filtering again to obtain 100-point sampled data. The 400-point sampled data output by the first-order filter FIR-L0 passes through the second-order filter FIR-M for filtering. The second-order filter FIR-M is a minimum-phase filter, with a decimation ratio of 2, to obtain 200-point sampled data, and then passes through the second-order filter FIR-M for filtering again to obtain 100-point sampled data. In this way, through the filtering process of the digital filter unit, two types of data, namely 100-point minimum-phase data and 100-point linear-phase data, can be obtained as the observation data output, and the user can select the required type of observation data according to the needs.

[0054] Combined with Figure 1 As shown, the clock signal terminal of the analog-to-digital converter is used to input a clock signal. The clock signal can use a non-return-to-zero clock signal, which can eliminate the influence of clock jitter on the converter. The reset signal terminal of the analog-to-digital converter is used to input a reset synchronization signal, which can realize the synchronous reset of multiple analog-to-digital converters. The reference voltage range input to the reference voltage terminal of the analog-to-digital converter is ±10 V, which can control the gain of the converter at about 1:1.

[0055] The ultra-high-resolution analog-to-digital converter provided by the embodiments of the present application builds a second-order Delta-Sigma modulation and demodulation unit from electronic components such as a second-order integrator circuit, a multi-bit analog-to-digital converter, and a digital-to-analog converter. By multi-bit quantization and multi-bit feedback, the quantization noise and circuit noise are effectively reduced, and the signal-to-noise ratio is improved. A parallel-structured digital-to-analog conversion unit is used in the feedback loop, and the output signal of the digital-to-analog conversion unit is calibrated to reduce the white noise and harmonic distortion introduced by non-linearity. Circuit structures such as the signal conditioning circuit and the second-order integrator circuit all adopt a differential input and output and completely symmetric circuit structure, ensuring that the circuit stably reaches the expected performance. By matching the symmetric resistors and capacitors in the differential circuit, the common-mode rejection ratio is improved, and the anti-interference ability is enhanced. The matching coefficient of the matched symmetric resistors can reach 0.03%.

[0056] In the seismic observation scenario, the sampling rate required for seismic observation is relatively low, usually less than 500 Hz. The analog-to-digital converter can adopt a relatively low oversampling rate, such as 64 KHz, and the clock frequency can also be significantly reduced, thereby simplifying the circuit structure, reducing the circuit complexity, reducing the radiation impact of the high-speed clock on the circuit, and reducing noise. Designing an analog-to-digital converter that meets the seismic observation requirements according to the circuit structure provided in this application can output digital signals with ultra-high resolution and achieve seismic data acquisition with a dynamic range exceeding 160 dB.

[0057] Those of ordinary skill in the art should understand that: the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples; under the concept of the present disclosure, the technical features between the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of one or more embodiments of the present specification as described above, and they are not provided in detail for the sake of brevity.

[0058] In addition, for the sake of simplicity of description and discussion, and in order not to make one or more embodiments of this specification difficult to understand, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. In addition, the device may be shown in block diagram form to avoid making one or more embodiments of this specification difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which one or more embodiments of this specification will be implemented (that is, these details should be completely within the understanding of those skilled in the art). In the case where specific details (such as circuits) are set forth to describe the exemplary embodiments of the present disclosure, it will be apparent to those skilled in the art that one or more embodiments of this specification can be implemented without these specific details or with variations of these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0059] Although the present disclosure has been described in connection with specific embodiments of the present disclosure, many substitutions, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art based on the foregoing description. For example, other memory architectures (such as dynamic RAM (DRAM)) can be used with the embodiments discussed.

[0060] One or more embodiments of this specification are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification shall be included within the protection scope of the present disclosure.

Claims

1. An ultra-high resolution analog-to-digital converter, characterized in that, It includes a second-order Delta-Sigma modulation and demodulation unit and a digital filtering unit; The second-order Delta-Sigma modulation and demodulation unit includes a signal conditioning circuit, a first-stage integrator circuit, a second-stage integrator circuit, an analog-to-digital conversion unit, a first digital-to-analog conversion unit, a second digital-to-analog conversion unit, and a processing unit; A differential analog signal is input into the signal conditioning circuit. The differential output terminal of the signal conditioning circuit is connected to the differential inverting input terminal of the first-stage integrator circuit. The output terminal of the first-stage integrator circuit is connected to the differential inverting input terminal of the second-stage integrator circuit. The differential output terminal of the second-stage integrator circuit is connected to the differential input terminal of the analog-to-digital conversion unit. The output terminal of the analog-to-digital conversion unit is connected to the signal input terminal of the processing unit. One signal output terminal of the processing unit is connected to the input terminal of the first digital-to-analog conversion unit through an inverter. The differential output terminal of the first digital-to-analog conversion unit is connected to the differential inverting input terminal of the first-stage integrator. The other signal output terminal of the processing unit is connected to the input terminal of the second digital-to-analog conversion unit. The differential output terminal of the second digital-to-analog conversion unit is connected to the differential inverting input terminal of the second-stage integrator. The digital signal output terminal of the processing unit is connected to the input terminal of the digital filtering unit. The digital filtering unit filters the input digital signal and then outputs the converted digital signal; The output signals of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are calibrated using preset calibration parameters, and the calibrated signals are respectively input into the first-stage integrator circuit and the second-stage integrator circuit; Among them, the method for determining the calibration parameters is to divide the output voltage range of the DAC chip into multiple voltage intervals according to a predetermined voltage interval. For each voltage interval, by inputting different digital signals and measuring the corresponding output analog voltage signals, fitting processing is performed according to the relationship between the input digital signals and the output analog voltage signals to obtain the calibration coefficient and calibration offset corresponding to this voltage interval; The relationship between the input digital signal D and the output analog voltage signal Vout is: Vout = k×D×VR / 2N + b (1) Where, VR is the reference voltage input into the DAC chip, N is the number of bits of the DAC chip, k is the calibration coefficient, and b is the calibration offset.

2. The analog-to-digital converter according to claim 1, wherein The processing unit performs primary filtering on the received digital signal and transmits the primarily filtered digital signal to the digital filtering unit.

3. The analog-to-digital converter according to claim 1, characterized in that, The signal conditioning circuit includes two operational amplifiers. The differential analog signal is respectively connected to the non-inverting input terminals of the two operational amplifiers through resistors R1. The inverting input terminals of the two operational amplifiers are respectively grounded through resistors 4R. The inverting input terminals of the two operational amplifiers are respectively connected to the output terminals of the operational amplifiers through resistors 2R. The two output terminals of the two operational amplifiers form a differential output terminal and are connected to the differential input terminal of the first-stage integrator circuit.

4. The analog-to-digital converter according to claim 3, wherein, A TVS protection circuit is provided at the differential input end of the signal conditioning circuit.

5. The analog-to-digital converter according to claim 1, characterized in that, The first-stage integrator circuit includes two operational amplifiers U3 and U4. The differential output ends of the signal conditioning circuit are respectively connected to the inverting input ends of the two operational amplifiers U3 and U4 through resistors 3R. The non-inverting input ends of the two operational amplifiers U3 and U4 are respectively grounded through resistors R2. The differential signal output ends of the first digital-to-analog converter are respectively connected to the inverting input ends of the two operational amplifiers U3 and U4 through resistors 2R. The output ends of the two operational amplifiers U3 and U4 are respectively connected to the inverting input ends of the two operational amplifiers U3 and U4 through capacitors. The second-stage integrator circuit includes two operational amplifiers U5 and U6. The output ends of the two operational amplifiers U3 and U4 are respectively connected to the inverting input ends of the two operational amplifiers U5 and U6 through resistors 2R. The non-inverting input ends of the two operational amplifiers U5 and U6 are respectively grounded through resistors R3. The differential signal output ends of the second digital-to-analog converter are respectively connected to the inverting input ends of the two operational amplifiers U5 and U6 through resistors 2R. The output ends of the two operational amplifiers U5 and U6 are respectively connected to the inverting input ends of the two operational amplifiers U5 and U6 through capacitors. The output ends of the two operational amplifiers U5 and U6 form differential output ends and are connected to the input end of the analog-to-digital conversion unit.

6. The analog-to-digital converter according to claim 1, wherein, The analog-to-digital conversion unit uses a 16-bit ADC chip. The first digital-to-analog conversion unit and the second digital-to-analog conversion unit are respectively formed by paralleling two 16-bit DAC chips, and the four 16-bit DAC chips have the same model.

7. The analog-to-digital converter according to claim 1, characterized in that The digital filtering unit is configured with a multi-stage filter, and the multi-stage filter is used to output a digital signal with a variable sampling rate.

8. The analog-to-digital converter according to claim 7, wherein The multi-stage filter includes a first-stage filter and a second-stage filter. The first-stage filter is a first-stage linear-phase filter. The second-stage filter includes a second-stage linear-phase filter and a second-stage minimum-phase filter. The digital signal output by the processing unit is filtered by the first-stage linear-phase filter, and then filtered by the second-stage linear-phase filter and the second-stage minimum-phase filter respectively to obtain a linear-phase digital signal and a minimum-phase digital signal.

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