Component carrier and method of manufacturing the same

Abstract

The present application provides a component carrier (100) and a method of manufacturing a component carrier (100), the component carrier (100) comprising: a layer body (102) comprising at least one electrically conductive layer structure (104) and / or at least one electrically insulating layer structure (106); a component (108) embedded in the layer body (102); and at least one galvanic connection stack (110) at least partially on at least part of at least one main surface (130, 132) of the layer body (102); wherein at least one of a bottom main surface (126) and a top main surface (128) of the embedded component (108) is electrically connected to the at least one galvanic connection stack (110).

Description

Technical Field

[0001] This invention relates to component carriers and methods for manufacturing component carriers. Background Technology

[0002] As product functionality increases, and the miniaturization of component carriers containing one or more electronic components grows, along with the increasing number of components to be mounted on or embedded in component carriers such as printed circuit boards, increasingly robust arrays of components or packages with multiple contacts or connections, where the spacing between these contacts is becoming increasingly smaller, are being adopted. Removing the heat generated during operation by these components and the component carriers themselves is becoming an increasingly prominent issue. Simultaneously, the component carriers must be mechanically stable and electrically reliable to operate even under harsh conditions.

[0003] To embed components within a stack, through-holes can be formed in the stack and sealed from the bottom using temporary carriers such as adhesive tape. A dielectric layer can be laminated on top of the component and the stack. The temporary carrier is then released. Copper foil can also be laminated, and / or, copper-filled laser vias can be formed. However, electrically connecting the embedded components remains a challenge. Summary of the Invention

[0004] A component carrier with embedded parts that is easy to manufacture and has high reliability may be needed.

[0005] According to an exemplary embodiment of the present invention, a component carrier is provided, the component carrier comprising: a layer body including at least one electrically conductive layer structure and / or at least one electrically insulating layer structure; a component embedded in the layer body; and at least one current-connection stack, the at least one current-connection stack being at least partially on at least a portion of at least one main surface of the layer body, wherein at least one of the bottom main surface and the top main surface of the embedded component is electrically connected to the at least one current-connection stack.

[0006] According to another exemplary embodiment of the present invention, a method for manufacturing a component carrier is provided, wherein the method includes: providing a layer body including at least one electrically conductive layer structure and / or at least one electrically insulating layer structure; embedding a component in the layer body; forming at least one current-connection stack on at least a portion of at least one main surface of the layer body; and electrically connecting the at least one current-connection stack to at least one of a bottom main surface and a top main surface of the embedded component.

[0007] In the context of this application, the term "component carrier" can specifically refer to any support structure capable of accommodating one or more components on and / or within a component carrier to provide mechanical support and / or electrical connection. In other words, a component carrier can be configured as a mechanical and / or electronic carrier for a component. A component carrier can include a laminated layer body, such as a laminated stack. In particular, a component carrier can be one of a printed circuit board, an organic interposer, and an IC (integrated circuit) substrate. A component carrier can also be a hybrid board combining different component carriers of the above types.

[0008] In the context of this application, the term "layer body" can specifically refer to a flat or plate-like body. For example, a layer body can be a laminate, and more particularly, a laminated laminate or a laminated structure. Such a laminate can be formed by joining multiple layers together by applying mechanical pressure and / or heat.

[0009] In the context of this application, the term "layer structure" may specifically refer to a continuous layer, a patterned layer, or a plurality of discontinuous islands in the same plane.

[0010] In the context of this application, the term "component" may specifically refer to, for example, an inlay that performs electronic and / or thermal tasks. For instance, the component may be an electronic component. Such an electronic component may be an active component, such as a semiconductor chip comprising a semiconductor material, particularly as a primary or basic material. The semiconductor material may be, for example, a type IV semiconductor, such as silicon or germanium, or a type III-V semiconductor material, such as gallium arsenide. In particular, a semiconductor component may be a semiconductor chip, such as a bare die or a molded die.

[0011] In the context of this application, the term "electro-connected stack" can specifically refer to a layered arrangement of multiple planar layer structures formed parallel to each other in a manner one on top of another and configured for electrically connecting embedded components, wherein the stack is formed at least partially by electrodeposition, and in particular, at least partially by electroplating. For the electrodeposition or electroplating of one or more layer structures of the electro-connected stack, an aqueous solution or electrolyte containing a metal to be deposited as ions (e.g., as a dissolved metal salt) can be used. The electric field between the first electrode (particularly the anode) and the preform of the component carrier to be manufactured as the second electrode (particularly the cathode) can force (particularly positively charged) metal ions to move to the second electrode (at a particular cathode), where the metal ions relinquish their charge and deposit themselves as a metallic material on the surface of the preform of the component carrier (more specifically on the layer body and / or the surface of the embedded component), thereby forming layers of the electro-connected stack. While one or more layers of a current-connection stack can be formed by current-deposition, at least one additional layer of the current-connection stack can be formed by another process, such as sputtering or electroless deposition. For example, a metal seed layer—which can serve as an electrode for a preform of a component carrier to be coated by current-deposition—can be formed by sputtering or electroless deposition. The current-connection stack can be a sequence of multiple parallel layers; in particular, the current-connection stack can be at least two parallel layers, and more particularly, the current-connection stack can be at least three parallel layers.

[0012] According to an exemplary embodiment of the present invention, a component carrier having embedded components (particularly active electronics) is provided, wherein the components can be electrically connected by a current-connection stack formed on the layer body of the component carrier (e.g., a laminated stack), preferably, the components can also be electrically connected by a current-connection stack formed directly on the embedded components. Such at least partially electrically conductive current-connection stacks can therefore form the electrical connections of the embedded components in the component carrier (e.g., a printed circuit board) in a highly precise manner (e.g., using a simple photolithography process to define the lateral constraints of the current-connection stacks). Furthermore, at least a portion of the current-connection stack formed by current-electrodeposition can therefore efficiently allow the current-connection stack to be formed on two opposite main surfaces of the layer body of the component carrier. Moreover, current-electrodeposition allows for the free design of the desired thickness of the current-connection stack within a wide range, which allows for the free adjustment of the desired electrical conductivity and / or thermal conductivity of the current-connection stack. Therefore, it is possible to provide precisely manufacturable component carriers with excellent electrical, mechanical, and thermal reliability and performance. Such a manufacturing structure also allows for robust fan-out capability provided by at least one electrically connected stack. In exemplary embodiments, processes for electrically and / or thermally connecting the embedded electronic components, such as laser via formation and / or copper foil lamination, may become optional or non-essential.

[0013] Detailed description of exemplary embodiments

[0014] In the following sections, further exemplary embodiments of the manufacturing method and component carrier will be described.

[0015] In one embodiment, at least one electroplating interconnect includes an electrodeposited master layer, which is made of, for example, copper. The electrodeposited master layer can be formed, for example, by electroplating or galvanic plating. One or more plating stages can be performed to adjust the thickness of the electrodeposited master layer, and, particularly optionally, to form multiple sublayers of the electrodeposited master layer.

[0016] In an embodiment, at least one electrostatically connected stack includes a seed layer. For example, the seed layer includes at least one of a chemically deposited seed layer (particularly a palladium substrate and a copper layer grown on the palladium substrate) or a physically deposited seed layer (particularly a sputtered seed layer). This seed layer can be used as an electrode to which current can be applied during the formation of the aforementioned electrostatically deposited main layer. This seed layer can be formed, for example, by electroless deposition or sputtering deposition (also called sputtering). Electroless plating (also referred to as chemical plating) can refer to a chemical process used to produce a metal coating, such as by autocatalytic chemical reduction of metal cations in a liquid bath. Sputtering can refer to a deposition process in which microscopic particles of a solid material are ejected from the surface of the solid material after the material itself has been bombarded by high-energy particles—such as plasma or gas. In particular, the seed layer can be formed by a chemical or physical deposition process.

[0017] In this implementation, the seed layer is disposed below the main layer for electrodeposition. In other words, the seed layer can serve as an electrically conductive base for electrodeposition of the main layer onto this electrically conductive base.

[0018] In one embodiment, at least one current-connection stack includes an adhesion-promoting layer, which may include, for example, titanium and / or chromate. The adhesion-promoting layer may be made of a material that enhances adhesion between the seed layer and the layer body. Providing an adhesion-promoting layer can suppress delamination of the individual layer structures of the component carrier, particularly in laminated types.

[0019] In this embodiment, an adhesion-promoting layer is disposed below the seed layer. The adhesion-promoting layer allows the seed layer to remain fixed to the rest of the component carrier.

[0020] In one embodiment, at least one current-connection stack includes a barrier layer. The barrier layer can be configured to prevent oxidation and / or migration between materials below and above the barrier layer. Providing a barrier layer may be particularly advantageous for the semiconductor material of the component and can prevent undesirable phenomena such as surface oxidation of the semiconductor material, material migration to and / or out of the semiconductor material, etc. Therefore, providing a barrier layer can enhance the mechanical and chemical integrity of the embedded component.

[0021] In one embodiment, the barrier layer is disposed below the adhesion-promoting layer; specifically, the barrier layer is disposed between the component and the adhesion-promoting layer. Alternatively, the barrier layer can be directly disposed on the component to provide appropriate protection.

[0022] In an embodiment, at least one current-connection stack has a rectangular cross-section. Specifically, the current-connection stack can be laterally defined on one or both opposing main surfaces of the layer body and / or component by generally vertical sidewalls, which can be defined, for example, by patterning a sequence of layers of consecutive current-connection stacks. For example, patterning can be accomplished by applying a patterned photomask followed by etching. Thus, the arrangement of the current-connection stack can be specifically limited to surface regions of the component carrier that relate to the main surface of the embedded component to be cooled, to the pad of the embedded component to be electrically contacted, and / or to a surface portion of the layer body where the laterally limited portion of the current-connection stack contacts a vertically penetrating connection extending through the dielectric material of the layer body. This photolithographic definition of the laterally limited portion of the current-connection stack allows for a precise and simple spatial definition of the function of the current-connection stack.

[0023] The bottom main surface of the component and the bottom main surface of the layer body can be coplanar, that is, the bottom main surface of the component and the bottom main surface of the layer body can lie in the same plane. Additionally or alternatively, the top main surface of the component and the top main surface of the layer body can be coplanar, that is, the top main surface of the component and the top main surface of the layer body can lie in the same plane. This facilitates a compact design of the component's support structure.

[0024] Apart from the vertical through-connection, the layer body in which the component is embedded can be a pure dielectric. The only electrically conductive connection structures required in this implementation are the vertical through-connection and the current-current connection stacks located above and below the layer body.

[0025] In an embodiment, at least one hydroelectric connection stack comprises a mirror-symmetric sequence of layers located on two opposite main surfaces of the layer body, and the layer sequences may coexist. For example, the outermost layer of each hydroelectric connection stack may be a hydroelectrically deposited main layer, followed by a seed layer and an adhesion-promoting layer. This mirror-symmetric sequence of layers on two opposite main surfaces allows for the fabrication of the hydroelectric connection stack on opposite main surfaces through simultaneous layer formation processes and thus in an efficient manner. However, a barrier layer may only need to be located on one of the opposite main surfaces of the component carrier; that is, the barrier layer may only need to be located on the main surface of the component carrier where the embedded component is disposed of exposed semiconductor material. A protective layer (e.g., made of polyimide) may be provided on the main surface of the semiconductor component, including the pad, making the barrier layer unnecessary on that side.

[0026] In one embodiment, at least one current-connection stack is laterally constrained on the main surface of the component and located within the area where at least one pad of the component is disposed. If more than one pad is disposed on one main surface of the component, multiple lateral constraints of the current-connection stack can be defined, thereby electrically isolating portions. This lateral constraint of the corresponding portions of the current-connection stack allows for the spatial definition of the designated function of the current-connection stack.

[0027] In one embodiment, the main surface of the component on which at least one pad of the component is disposed is the bottom main surface. Therefore, the embedded component can be positioned downwards. This has the advantage that, for example, when manufacturing the component carrier using a temporary carrier attached to the bottom side of the component, no additional process of exposing the pads on the bottom side is required. Alternatively, the embedded component can be positioned upwards, i.e., one or more pads are located on the upper main surface of the component. In yet another embodiment, the embedded component may have pads on each of the two opposite main surfaces of the component. In this case, corresponding laterally restricting portions of the current-connection stack can be disposed on each of the two opposite main surfaces of the component to contact all pads. In the aforementioned cases, for example, one or more pads located on the bottom side may also be contacted by at least one laterally restricting portion of the current-connection stack, while one or more pads located on the top side may be contacted by metal-filled vias (particularly copper-filled laser vias).

[0028] In one embodiment, at least one hydrocoupler stack covers the entire main surface of the component's unattached pad. Advantageously, the non-electroactive main surface of the component can be completely covered by the hydrocoupler stack, for example, the entire main surface of the component can be completely covered by the hydrocoupler stack. In this embodiment, the hydrocoupler stack can be used to remove heat from the embedded component, i.e., for cooling. The hydrocoupler stack can also be configured for heat dissipation, for example, it can be configured to dissipate heat within a 45° angular range in each direction. Therefore, the hydrocoupler stack can achieve a dual function: electrically connecting the pad of the embedded component on one side, and removing heat generated by the component carrier during component carrier operation on the opposite side. Thus, thermal stress can be suppressed by appropriately removing heat from the embedded component through a hydrocoupler stack with full-surface heat removal.

[0029] In one embodiment, at least one hydroelectric connection stack covering the non-electroactive main surface of the component (i.e., without a pad) protrudes laterally beyond the main surface of the component. In this case, the heat removal capability of the hydroelectric connection stack directly disposed on the non-electroactive main surface of the embedded component can be further suppressed by increasing the heat removal material of the hydroelectric connection stack. Furthermore, extending the hydroelectric connection stack laterally beyond the lateral limit of the embedded component can also allow for improved heat distribution on the component carrier, and in particular, allows heat to be dissipated laterally from the embedded component.

[0030] In an embodiment, at least one electrically conductive layer structure includes at least one vertical through-connection that extends vertically through the entire layer body, i.e., the vertical through-connection extends entirely between opposite main surfaces of the layer body. Specifically, at least one vertical through-connection can be electrically connected to at least one of at least one current-connection stack, particularly at two opposite main surfaces of the layer body. For example, one or more through-holes can be formed in the layer body, which can be, for example, a dielectric core. The formation of the through-holes can be accomplished, for example, by mechanical drilling or laser drilling. The through-holes can then be filled with an electrically conductive material, such as copper, for example, by plating. Alternatively, the metallic vertical through-connection can also be a metal pillar, such as a copper pillar. Advantageously, the electrically conductive vertical through-connection extending through the layer body can be contacted by a current-connection stack on one main surface or two opposite main surfaces of the layer body. This allows for the formation of an electrically conductive connection structure with a generally I-shaped cross-sectional view.

[0031] In an embodiment, at least one of the at least one current-connection stack provides a heat dissipation structure, and in particular, at least one of the at least one current-connection stack provides a 45° heat dissipation structure. More specifically, the current-connection stack may be disposed on a main surface of the embedded component such that heat generated by the component is removed by the current-connection stack within a spatial range corresponding to heat flow occurring in a conical or truncated conical region having an opening angle of ±45° or greater.

[0032] In embodiments, the layer body includes a core comprising a fully cured dielectric material. In the context of this application, the term "core" can specifically refer to a rigid plate structure for a component carrier comprising a preferably fully cured dielectric body (e.g., a central plate), which may optionally have corresponding electrically conductive layer structures, such as patterned metal layers, coated on one or both opposite main surfaces of the dielectric body. For example, the dielectric body may comprise a resin (e.g., epoxy resin) and reinforcing particles (e.g., glass fiber or glass spheres), and the dielectric body may be, for example, FR4. Optionally, the two opposite main surfaces of the core may be electrically coupled to each other by vertical through-connections, such as copper-plated laser vias or mechanically drilled and copper-plated vias. More specifically, the core of a component carrier, such as a printed circuit board (PCB), may be a rigid base material, which may optionally be copper-laminated on one or both sides. Such a core can be used to manufacture single-sided and double-sided boards, but can also be used to produce multilayer component carriers (especially PCBs).

[0033] Components can be embedded in the core (see...) Figures 2 to 18 (Implementation method). In an alternative implementation, the component may be embedded in a coreless component carrier (see [implementation method]). Figures 19 to 29 Implementation method).

[0034] In an embodiment, at least a portion of the component is directly surrounded by at least one of at least one electrically insulating layer structure, which is functionalized as a buffer structure for buffering stress. Preferably, the buffer structure comprises a material with a Young's modulus value of less than 8 GPa, particularly less than 3 GPa, and more particularly less than 1 GPa, or the buffer structure is composed of a material with a Young's modulus value of less than 8 GPa, particularly less than 3 GPa, and more particularly less than 1 GPa. Such a material can be used as a mechanical buffer structure, i.e., as a mechanically relatively flexible or elastic electrically insulating structure. This makes the material very suitable (particularly directly) for embedding around a component carrier. For example, in the case of thermal stress, such a mechanical buffer structure can have a locally reduced Young's modulus value and can therefore be used as a mechanical damping or force balancing structure. Thus, excellent results can be obtained when the component is embedded in a dielectric with a lower Young's modulus. The dielectric buffer structure can have a lower Young's modulus value than any other dielectric material of at least one electrically insulating layer structure of the component carrier.

[0035] In one embodiment, the at least one electrostatically connected stack has a hardness gradient, which decreases in hardness from the laminate body toward the outer portion of the component carrier. For example, a barrier layer and / or adhesion-promoting layer disposed directly on or near the laminate body can be harder than the outer electrostatically deposited master layer, which is softer and / or has plastic deformation properties. It has been shown that the corresponding spatial stiffness gradient in the vertical direction of the component carrier improves the overall mechanical integrity of the component carrier and suppresses artificial phenomena such as delamination and warping.

[0036] In this embodiment, at least one of the bottom main surface and the top main surface of the embedded component is in direct physical contact with the at least one current-connection stack. Therefore, direct mechanical contact can be formed between the embedded component and the current-connection stack.

[0037] In this implementation, the layer body is a laminate, i.e., a sequence of layers interconnected by the application of mechanical pressure and / or heat.

[0038] In one embodiment, the component includes at least one pad, which is formed by at least a portion of at least one of the at least one current-connection stacks. Therefore, a padless component can be formed by embedding a padless component in the layer body and applying current connections to the padless component, particularly after the component is embedded in the layer body.

[0039] In one embodiment, at least one current connection stack disposed on at least one pad at the main surface of the component forms a redistribution structure. This redistribution structure can redistribute electrical connection wiring in a plane immediately below the embedded component, and can thereby provide traces, leads, and / or other circuitry for distributing electrical signals and / or power within said plane. For example, the redistribution structure may include fan-out and / or fan-in structures. The redistribution structure or layer may be configured as a flat (or at least substantially flat) patterned current connection stack.

[0040] In one embodiment, at least one of the at least one current-connection stacks extends on the main surface of the component and extends laterally beyond the component, and has a portion including a corrugated structure, such as a lateral end portion (e.g., a portion extending laterally beyond the component). Specifically, this corrugated portion of the current-connection stack that protrudes laterally beyond the sidewall of the component can be formed with at least one notch having a wavy shape. The corrugated structure has proven effective in protecting the electrical traces of the component carrier from scratches and mechanical damage, and in cushioning tensions caused by CTE (coefficient of thermal expansion) mismatch in the material of the component carrier.

[0041] However, it should be mentioned that the corrugated structure does not necessarily have to be the lateral end portion near the component, but can also connect to any other pads away from the component. Therefore, the traces can also travel across the cavity sidewalls. More generally, the corrugated portion of the current-connected stack can extend beyond the main surface of the component and can be electrically connected to another electrically conductive element facing away from the component, such as a pad. In other words, the corrugated portion can extend laterally between the component and the electrically conductive element.

[0042] In this embodiment, the vertical amplitude of the corrugated structure is in the range of 1 μm to 20 μm, particularly in the range of 2 μm to 10 μm. Specifically, the notches in the corrugated structure having the aforementioned dimensions can appropriately buffer stress.

[0043] In one embodiment, the component carrier includes a dielectric support that engages with the sidewalls of the embedded component and the connection portions of the bottom and top main surfaces. For example, the dielectric support may have a generally C-shaped cross-section. Advantageously, anchoring, clamping, or gripping the embedded component laterally with the dielectric support can improve stability and facilitate surface leveling.

[0044] In this embodiment, the dielectric support engages with the sidewalls and connecting portions along the entire circumference of the component. Therefore, the support can be a ring-shaped structure that completely anchors, grips, or clamps the component in the circumference. This results in excellent stability.

[0045] In an embodiment, at least a portion of the dielectric support is a buffer structure for buffering stress, wherein, in particular, the buffer structure comprises a material having a Young's modulus value of less than 8 GPa, particularly less than 3 GPa, and more particularly less than 1 GPa, or the buffer structure is composed of a material having a Young's modulus value of less than 8 GPa, particularly less than 3 GPa, and more particularly less than 1 GPa. Such a material can be used as a flexible or elastic buffer structure, for example, as a mechanical damping or force balancing structure in the case of thermal stress.

[0046] In this embodiment, at least 60% of the bottom main surface of the embedded component is covered by one of the at least one current-connection stacks. In other words, the area of ​​the bottom main surface of the component covered by the current-connection stack divided by the total area of ​​the bottom main surface of the component can be at least 60%. Additionally or alternatively, at least 90%, and particularly 100%, of the top main surface of the embedded component is covered by one of the at least one current-connection stacks. In other words, a large portion or even the entire area of ​​the top main surface of the component can be covered by the current-connection stack. This high copper coverage ensures reliable current connection of the component and effectively facilitates thermal removal. Furthermore, this high copper coverage helps to effectively shield electromagnetic radiation within the component carrier.

[0047] Surface roughness can be defined and measured as the average height Ra of the centerline. Ra is the arithmetic mean of all distances from the profile to the centerline. However, surface roughness can also be defined and measured as the average roughness depth Rz. Rz can be determined by sampling a reference length from the roughness curve in the direction of the average line, and can represent the distance between the top profile peak and the bottom profile valley on that sampled portion, which is measured in the longitudinal direction of the roughness curve (e.g., Rz can be determined by averaging five separate measurement paths). For example, the measurement or determination of roughness Ra and Rz can be performed according to DIN EN ISO 4287:2010.

[0048] In embodiments, the roughness Ra of the top main surface of the embedded component (e.g., the silicon surface of the component when the component is implemented as a silicon chip) is in the range of 20 nm to 130 nm, and / or the roughness Rz of the top main surface of the embedded component is in the range of 200 nm to 1500 nm. Additionally or alternatively, the roughness Ra of at least one pad located on the main surface of the component is in the range of 20 nm to 130 nm, and / or the roughness Rz of at least one pad located on the main surface of the component is in the range of 500 nm to 1500 nm. Additionally or alternatively, the roughness Ra of the electrically insulating protective layer (particularly the electrically insulating protective ring surrounding the pad) located on the main surface of the component is in the range of 10 nm to 40 nm, and / or the roughness Rz of the electrically insulating protective layer located on the main surface of the component is in the range of 50 nm to 250 nm. Advantageously, the aforementioned roughness values ​​can ensure uniform deposition of the applied (particularly sputtered) adhesion promoter and / or seed layer. This reliably prevents undesirable phenomena such as delamination and warping.

[0049] In an embodiment, the component includes at least one circumferentially closed electrically insulating protective layer (particularly an electrically insulating protective ring surrounding a pad), for example, said at least one circumferentially closed electrically insulating protective layer having a stepped structure surrounding at least one pad located on the main surface of the component. For example, such an electrically insulating protective layer can be formed as part of the component and can surround a corresponding metal pad on the component. Preferably, such an electrically insulating protective layer can be made of polyimide. In particular, when a stepped annular structure surrounding the pad of the component is formed, the electrically insulating protective layer can serve as a foot or bottom-side protrusion for anchoring the embedded component in the surrounding stacked material.

[0050] In one embodiment, the component includes at least one electrically insulating protective layer located on the main surface of the component and having at least one protruding anchoring foot. Specifically, such an anchoring foot, which can project downwards, can anchor the embedded component in the surrounding material of the component carrier to suppress delamination.

[0051] In one embodiment, the component includes at least one pad connected to at least one of the at least one current connection stacks and having a circular or non-circular, particularly rectangular, shape. As for the structure of the pad, it can be formed to have any shape, such as a square pad. Advantageously, such pads can be joined at the same level using the described method via sputtering.

[0052] In one embodiment, the component includes a plurality of pads connected to at least one of the at least one current connection stack, wherein at least two of the pads are electrically connected to each other via a portion of the at least one current connection stack. Advantageously, the plurality of pads can be combined by metallizing them together (see [link to documentation]). Figure 30 Figure 120', where four pads are covered by a metal film applied thereon and connected accordingly, or see Figure 120'. Figure 36 ).

[0053] In one embodiment, embedding the component includes: temporarily attaching the component to a temporary carrier, and removing the temporary carrier before the component carrier is fully manufactured. For example, such a temporary carrier may be an adhesive tape or sheet that can be removed after the assembled component is embedded in a through-hole in a stack or core. The temporary carrier temporarily defines the position of the component within the component carrier being manufactured and provides temporary stability until permanent stability is achieved through lamination. The temporary carrier can then be separated from the component carrier or a prefabricated component carrier.

[0054] In this embodiment, the polar component of the surface energy of the attachment surface of the temporary support is less than 10 mN / m, particularly less than or equal to 5 mN / m. The polar component is the component of the surface free energy of the surface material of the temporary support resulting from polar interactions. In this embodiment, the dispersive component of the surface energy of the attachment surface of the temporary support is in the range of 15 mN / m to 30 mN / m, particularly in the range of 20 mN / m to 25 mN / m. The dispersive (or dispersive) component is the component of the surface free energy of the surface material of the temporary support resulting from dispersive interactions. In this embodiment, the total surface energy of the attachment surface of the temporary support (i.e., particularly the sum of the polar and dispersive components of the surface energy) is in the range of 15 mN / m to 40 mN / m, particularly in the range of 21 mN / m to 26 mN / m. The aforementioned material selection can promote adhesion between the assembled component and the temporary support to avoid slippage and displacement of the component during processing.

[0055] In embodiments, the flexural strength of the material of the temporary support is in the range of 0.1 MPa to 5 MPa, particularly in the range of 0.4 MPa to 1.2 MPa. In the context of this application, the term "flexural strength" (which may also be expressed as modulus of fracture, flexural strength, or transverse fracture strength) can refer to a material property that defines the stress in the material immediately preceding yielding in a flexural test. A transverse bending test can be used to determine the flexural strength, wherein a three-point flexural test technique is used to bend a specimen with a circular or rectangular cross-section until it breaks or yields. The material selection used to achieve the aforementioned flexural strength values ​​avoids wrinkles on the temporary support and tilting of the assembled components.

[0056] In the following sections, different embedding techniques that can be used to embed components in a layer body according to exemplary embodiments will be described:

[0057] In one embodiment, a method of manufacturing a component carrier includes: embedding the component into an opening in a layer body (particularly a laminated component), wherein, during embedding, the opening is temporarily closed at least on the bottom side by an adhesive layer (see [link to documentation]). Figures 2 to 18(Implementation methods). In the context of this application, the term "sticky layer" may specifically refer to a strip, film, foil, sheet, or plate having an adhesive surface. In use, the adhesive layer may be used to adhere to the main surface of the layer body to close an opening extending through the layer body. A component to be embedded may be adhered to the adhesive layer to define the position of the component in the opening and thus define the position of the component relative to the layer body. When the adhesive layer is removed from the layer body before the manufacturing of the component carrier is completed, the adhesive layer may be referred to as a temporary carrier. However, in other embodiments, the adhesive layer may form part of an easily manufactured component carrier. By adhering the component to the adhesive strip during the embedding process, the spatial accuracy of the component embedding can be significantly improved.

[0058] In another embodiment, the method includes: mounting a component onto at least one layer of a layered structure or onto a temporary support; and subsequently covering the component with a layered structure or another layer of a layered structure, wherein at least one layer of the layered structure has an opening for receiving the component. For example, the opening of the respective layered structure can be cut into the respective layered structure as a through hole. Alternatively, the component attached to the temporary support or one or more layered structures can be covered with a flowable medium such as resin. Further details regarding these embodiments can be found in... Figures 19 to 29 The implementation method.

[0059] In another embodiment, the method includes: embedding a release layer in the layer body; subsequently forming an opening in the layer body by removing a segment of the layer body defined on its underside by the release layer; and subsequently accommodating a component in the opening. For example, such a release layer can be made of a material that exhibits poor adhesive properties relative to the surrounding layer body material. Suitable materials for the release layer, for example, are polytetrafluoroethylene (PTFE, Teflon) or waxy compounds. The method may include: forming a circumferentially cut groove in the layer body that extends to the release layer to thereby separate the segment from the remainder of the layer body. Cutting the groove can be done, for example, by laser drilling or mechanical drilling.

[0060] In another embodiment, the method includes: forming an opening in the layer body by routing (preferably deep routing); and subsequently receiving a component on the bottom surface of the routing layer body and within the opening. Routing is a suitable and simple mechanism for precisely defining blind-hole-type openings for subsequent receiving of components.

[0061] In an embodiment, the layer body includes a stack of at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier may be a laminate of the aforementioned electrically insulating and electrically conductive layer structures, formed particularly by applying mechanical pressure and / or thermal energy. The aforementioned stack can provide a plate-like component carrier capable of providing a large mounting surface for other components while remaining very thin and compact.

[0062] In this implementation, the component carrier is formed as a plate. This contributes to a compact design, whereby, despite this, the component carrier still provides a large base for the mounting components on it. Furthermore, in particular, a bare die, as an example of an embedded electronic component, can be easily embedded into a thin plate, such as a printed circuit board, due to its small thickness.

[0063] In one embodiment, the component carrier is configured as one of a printed circuit board, a substrate (particularly an IC substrate), and an interposer.

[0064] In the context of this application, the term "printed circuit board" (PCB) can specifically refer to a plate-shaped component carrier formed by laminating multiple electrically conductive layer structures with multiple electrically insulating layer structures, for example, by applying pressure and / or by supplying heat. As preferred materials for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures may include resin and / or glass fiber, so-called prepreg, or FR4 material. Holes through the laminate can be formed, for example, by laser drilling or mechanical drilling, and these holes can be partially or completely filled with an electrically conductive material (particularly copper) to form vias or any other through-hole connections, allowing the various electrically conductive layer structures to be connected to each other in a desired manner. The filled holes either connect the entire stack (through-hole connections extending through multiple layers or the entire stack), or the filled holes connect at least two electrically conductive layers, and are referred to as vias. Similarly, optical interconnects can be formed through the various layers of the stack to receive electro-optical circuit boards (EOCBs). In addition to one or more components that can be embedded in a printed circuit board, a printed circuit board is typically configured to house one or more components on one or both opposite surfaces of the board-shaped printed circuit board. The one or more components can be soldered to their respective main surfaces. The dielectric portions of the PCB can be made of resin with reinforcing fibers (e.g., glass fiber).

[0065] In the context of this application, the term "substrate" can specifically refer to a small component carrier. A substrate can be a relatively small component carrier relative to a PCB, on which one or more components can be mounted and which can serve as a connection medium between one or more chips and another PCB. For example, a substrate can have approximately the same size as the components (particularly electronic components) to be mounted on it (e.g., in the case of chip-scale packages (CSPs)). More specifically, a substrate can be understood as a carrier for electrical connections or electrical networks, and a component carrier with a relatively high density of lateral and / or vertically arranged connectors, comparable to a printed circuit board (PCB). Lateral connectors are, for example, conductive channels, while vertical connectors can be, for example, drilled holes. These lateral and / or vertical connectors are arranged within the substrate and can be used to provide electrical, thermal, and / or mechanical connections between accommodated or unaccommodated components (e.g., bare wafers), particularly IC chips, and printed circuit boards or intermediate printed circuit boards. Therefore, the term "substrate" also includes "IC substrate." The dielectric portion of the substrate can be made of resin with reinforcing particles (e.g., reinforcing spheres, especially glass spheres).

[0066] The substrate or interlayer may include or consist of at least one of the following: glass; silicon (Si); and / or a photosensitive or dry-etchable organic material, such as an epoxy-based laminate (e.g., an epoxy-based laminated film); or a polymer compound (which may or may not include photosensitive and / or thermosensitive molecules), such as polyimide or polybenzoxazole.

[0067] In embodiments, at least one electrically insulating layer structure comprises at least one of the following: resins or polymers (such as epoxy resins, cyanate ester resins, benzocyclobutene resins, bismaleimide-triazine resins), polyphenylene derivatives (e.g., based on polyphenylene ether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymers (LCP), polytetrafluoroethylene (PTFE), and / or combinations thereof. Reinforcing materials, such as meshes, fibers, or spheres or other types of filler particles, made of glass (multilayer glass), may also be used to form the composite. The semi-cured resin combined with the reinforcing agent, such as fibers impregnated with the aforementioned resins, is called a prepreg. These prepregs are typically named according to the flame-retardant properties described in the prepreg, such as FR4 or FR5. Although prepregs, particularly FR4, are generally preferred for rigid PCBs, other materials may also be used, particularly epoxy-based laminated materials (such as laminated films) or photo-imageable dielectric materials. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate resins may be preferred. In addition to these polymers, low-temperature co-fired ceramics (LTCC) or other low-DK, very low-, or ultra-low-DK materials can be used as electrical insulation structures in component carriers.

[0068] In an embodiment, at least one electrically conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, tungsten, and magnesium. Although copper is generally preferred, other materials or coating variations thereof, particularly those coated with superconducting materials or conductive polymers, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT), are also possible.

[0069] At least one additional component may be embedded in and / or surface-mounted onto the component carrier. The component and / or at least one additional component may be selected from the group consisting of: non-conductive inlays, conductive inlays (e.g., metallic inlays, preferably copper or aluminum), heat transfer units (e.g., heat pipes), optical guiding elements (e.g., optical waveguides or optical conductor connectors), electronic components, or combinations thereof. The inlay may be, for example, a metal block with or without an insulating material coating (IMS-inlay), which may be embedded or surface-mounted for the purpose of facilitating heat dissipation. Suitable materials are defined by their thermal conductivity, which should be at least 2 W / mK. Such materials are typically based on, but not limited to, metals, metal oxides, and / or ceramics, such as copper, alumina (Al₂O₃), or aluminum nitride (AlN). Other geometries with increased surface area are also frequently used to increase heat exchange capacity. In addition, components can be active electronic components (having at least one implemented pn junction), passive electronic components such as resistors, inductors, or capacitors, electronic chips, storage devices (such as DRAM or other data memories), filters, integrated circuits (such as field-programmable gate arrays (FPGAs), programmable array logic (PALs), general-purpose array logic (GALs), and complex programmable logic devices (CPLDs)), signal processing components, and power management components (such as field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS), and junction field-effect transistors (JFETs)). These components, whether insulated-gate field-effect transistors (IGFETs) or insulated-gate field-effect transistors, are based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), and / or any other suitable inorganic compound), optoelectronic interface elements, light-emitting diodes, optocouplers, voltage converters (e.g., DC / DC converters or AC / DC converters), cryptographic components, transmitters and / or receivers, electromechanical converters, sensors, actuators, microelectromechanical systems (MEMS), microprocessors, capacitors, resistors, inductors, batteries, switches, cameras, antennas, logic chips, and energy harvesting units. However, other components can be embedded within component carriers. For example, magnetic components can be used as assemblies. Such magnetic components can be permanent magnet components (e.g., ferromagnetic elements, antiferromagnetic elements, multiferromagnetic elements, or ferrimagnetic elements, such as ferrite cores) or paramagnetic elements. However, components can also be IC substrates, interposers, or other component carriers, such as those in a board-in-board configuration. The component may be surface-mounted on the component carrier and / or embedded within the component carrier. Furthermore, other components, particularly those that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment, may also be used as components.

[0070] In one embodiment, the component carrier is a laminated component carrier. In this embodiment, the component carrier is a multilayer composite structure that is stacked and connected together by applying pressure and / or heat.

[0071] After the internal layer structure of the component carrier is fabricated, one or more additional electrically insulating and / or electrically conductive layer structures (particularly by lamination) can be used to symmetrically or asymmetrically cover one main surface or two opposite main surfaces of the fabricated layer structure. In other words, stacking can continue until the desired number of layers is achieved.

[0072] After the formation of the stacked component with an electrically insulating layer structure and an electrically conductive layer structure is completed, the obtained layer structure or component carrier can be surface treated.

[0073] Specifically, in terms of surface treatment, an electrically insulating solder resist can be applied to one or both opposing main surfaces of the laminate or component carrier. For example, a solder resist can be formed over the entire main surface and then the solder resist layer can be patterned to expose one or more electrically conductive surface portions, which will be used to electrically couple the component carrier to electronic peripherals. The solder resist-covered surface portions of the component carrier, particularly those containing copper, can be effectively protected against oxidation or corrosion.

[0074] In terms of surface treatment, a surface treatment portion can be selectively applied to the exposed electrically conductive surface portion of the component carrier. This surface treatment portion can be an electrically conductive covering material on the exposed electrically conductive layer structure (e.g., pads, conductive traces, etc., particularly including or composed of copper) on the surface of the component carrier. If this exposed electrically conductive layer structure is not protected, the exposed electrically conductive component carrier material (especially copper) will oxidize, resulting in lower reliability of the component carrier. Furthermore, the surface treatment portion can be formed, for example, as a joint between a surface-mount component and the component carrier. The surface treatment portion functions to protect the exposed electrically conductive layer structure (especially copper circuitry), and the surface treatment portion can be joined to one or more components, for example, by soldering. Examples of suitable materials for the surface treatment portion are organic solderable corrosion inhibitors (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium immersion gold (ENIPIG), gold (especially hard gold), electroless tin, nickel-gold, nickel-palladium, etc.

[0075] The above-defined aspects and other aspects of the present invention will become apparent by way of examples of embodiments described below and will be explained with reference to these examples of embodiments. Attached Figure Description

[0076] Figure 1A cross-sectional view of a component carrier according to an exemplary embodiment of the present invention is shown.

[0077] Figures 2 to 18 An exemplary embodiment of the present invention is shown in the execution Figure 18 A cross-sectional view of the structure obtained during the method of manufacturing the component carrier shown.

[0078] Figures 19 to 29 Another exemplary embodiment of the invention is shown in the process of manufacturing. Figure 29 The cross-sectional view of the structure obtained during the method of the component carrier shown.

[0079] Figure 30 A bottom view of a portion of a component carrier according to an exemplary embodiment of the present invention is shown.

[0080] Figure 31 A cross-sectional view of a component carrier according to an exemplary embodiment of the present invention is shown.

[0081] Figure 32 A bottom view showing details of a component carrier according to an exemplary embodiment of the present invention is shown.

[0082] Figure 33 A cross-sectional view of a component carrier according to an exemplary embodiment of the present invention is shown.

[0083] Figure 34 and Figure 35 A cross-sectional view of the structure obtained during the manufacture of a component carrier according to an exemplary embodiment of the present invention is shown.

[0084] Figure 36 A bottom view of a component embedded in a component carrier according to an exemplary embodiment of the present invention is shown.

[0085] Figure 37 A cross-sectional view of the structure obtained during the manufacture of a component carrier according to an exemplary embodiment of the present invention is shown. Detailed Implementation

[0086] The illustrations in the accompanying drawings are schematic. In different drawings, similar or identical elements have the same reference numerals.

[0087] Before referring to the accompanying drawings, exemplary embodiments will be described in more detail, and some basic considerations will be summarized based on exemplary embodiments of the present invention that have been developed.

[0088] Conventionally, embedded component packages are manufactured using single-sided component connectors. This can limit the overall functionality of the manufactured component carrier, and in particular, its use in power packages. For power applications, conventional component carriers may be limited in terms of thermal performance and current carrying capacity, and / or may be limited by precision and material constraints.

[0089] According to an exemplary embodiment of the present invention, a component carrier is provided, wherein a component (particularly a semiconductor chip, such as a power semiconductor chip) embedded in a layer body (particularly a laminated stack) is connected to a current-connected stack on one main surface or two opposite main surfaces.

[0090] For example, such a current-connection stack can provide a fan-out function on a main surface, such as the bottom side. To achieve this, current-connection stacks can be selectively formed on one or more pads of a semiconductor chip-type component, particularly on the aforementioned bottom side. The current-connection stack can provide a thermal removal function, for example, on the top side of the embedded component. For this purpose, the entire main surface of the embedded component can be made in thermal contact with the thermal removal current-connection stack. Alternatively, a component with pads on two opposite main surfaces can be provided, wherein these pads can be electrically connected by current-connection stacks formed on each of the opposite main surfaces. In yet another embodiment, one or more pads can be formed as current-connection stacks on one main surface or two opposite main surfaces of the component, such that the current-connection stack can be embodied as current-connection pads. All of these embodiments can also be combined.

[0091] For example, one or more current-connect stacks may include a sputtered or chemically formed seed layer (e.g., comprising titanium and / or copper), on which a current-deposited master layer (e.g., an electroplated copper layer formed by current-connection processing) may be formed. Furthermore, current-connect stacks with a barrier layer (e.g., made of titanium nitride) may be provided for separating components (particularly semiconductor surface materials of components) from the seed layer.

[0092] The manufacturing architecture of exemplary embodiments of the present invention allows for the connection of one or both main surfaces of an embedded (particularly active electronic) component to a current-connection stack. This allows for the creation of electrical and / or thermal connections of the embedded component with high precision, and allows for the promotion of appropriate electrical performance and reliability, as well as thermal performance and reliability. Particularly advantageously, the use of seed layers and current-layer series of connections in the form of current-connection stacks provides greater freedom in selecting the pad material of the component. This manufacturing architecture can be advantageously applied to any layer concept for manufacturing component carriers such as printed circuit boards (PCBs).

[0093] Advantageously, an electrically conductive vertical through-connection extending through the layer body (particularly the fully cured core) can also be formed, which serves to redistribute signal paths from the bottom side to the top side of the electronic component. More advantageously, such a vertical through-connection can be electrically coupled to one or more of the aforementioned current-connection stacks on one main surface or two opposite main surfaces of the layer body.

[0094] According to an exemplary embodiment of the invention, a high-precision electrolithography component connector on the front side can be combined with a full-surface back-side component connector for excellent heat transfer and high-current component sources. This hybrid use of different connection technologies provides the opportunity to embed virtually any type of component and helps to provide a simple and precise embedding process. In particular, a fan-out architecture can be implemented for components with high input / output counts and / or high input / output densities. Furthermore, low package resistance can be achieved, and excellent heat transfer makes the component carrier suitable for power applications. Highly advantageously, it is possible to combine the precise fan-out concept with a full-surface component connector in an embedded package in the form of a PCB-type component carrier.

[0095] The exemplary embodiments of the present invention offer the following advantages: First, there are virtually no component design limitations in terms of input / output count density. Furthermore, the exemplary embodiments of the present invention provide the possibility of enlarging the component pads through a flow lithography process to increase the registration tolerance of the high-density integration (HDI) connections in the next layer. Additionally, the exemplary embodiments can provide active thermal management by providing flow-electrolytic component back-side connections. Moreover, due to the higher possible input / output density, the exemplary embodiments can reduce the component footprint. The exemplary embodiments of the present invention are particularly suitable for high-frequency (HF) applications because they utilize PVD (physical vapor deposition) sputtering techniques or other layer deposition techniques instead of using a rough base copper foil. This can reduce losses at high frequencies due to the skin effect. Furthermore, component carriers manufactured according to the exemplary embodiments of the present invention can have significantly reduced thickness and can therefore be manufactured with greater compactness and less effort. Furthermore, the exemplary embodiments achieve a direct fan-out architecture with adequate thermal transfer.

[0096] Advantageously, exemplary embodiments of the present invention can provide a component carrier that combines a high-density fan-out concept with a full-surface component connection in an embedded package.

[0097] In this implementation, the joint between the prepreg and the component copper can be avoided, thus suppressing delamination. Furthermore, the laser process for electrically connecting the components in the laminated component carrier can be omitted, preventing thermal damage to the component passivation layer. Additionally, exemplary embodiments of the invention offer the possibility of increasing the registration tolerance of HDI connections on subsequent layers by generating component pad enlargement through photostructuring processes (e.g., when performing subtractive or semi-additive manufacturing processes). Moreover, excellent heat transfer can be ensured by creating PVD and hydroelectric full-surface component connections. Exemplary embodiments are particularly suitable for HF applications because they implement sputtering techniques (especially PVD) instead of using rough copper foil that easily causes significant high-frequency signal loss. Furthermore, component carriers with one or more embedded components that are highly compact, particularly in the vertical direction, can be obtained. Therefore, exemplary embodiments are particularly compatible with high-power applications, high-frequency applications, fan-out applications, and sensor applications.

[0098] Exemplary embodiments of the present invention enable high-precision flow lithography back-side component connections that integrate with full-surface front-side component connections. The manufacturing architecture according to exemplary embodiments of the present invention provides the opportunity to embed virtually any type of active component and allows for the production of component carriers through a simple embedding process.

[0099] Exemplary implementations allow for the manufacture of component carriers with embedded components and electrically connected stacks with less effort, particularly without copper foil, laser processing, and optionally prepreg boards.

[0100] For example, a component with 180 aluminum-terminated input / output terminals and a 95µm pad size has been embedded. Using PVD sputtering technology and a mechanical planarization process, a 40µm line / space fan-out layer can be achieved on both FR4 and polyimide surfaces.

[0101] Figure 1 A cross-sectional view of a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0102] according to Figure 1 The component carrier 100 can be constructed as a generally plate-shaped printed circuit board (PCB). Therefore, Figure 1The component carrier 100 shown may be highly compact in the vertical direction. More specifically, the component carrier 100 may include a layer body 102 comprising one or more electrically conductive layer structures 104 and / or one or more electrically insulating layer structures 106. Each electrically conductive layer structure 104 may include a multi-layer portion (see reference numeral 110) and a vertical through-connection, such as a copper-filled via formed by drilling and plating. The electrically insulating layer structure 106 may include a suitable resin (e.g., a suitable epoxy resin), preferably comprising reinforcing particles (e.g., glass fibers or glass spheres). For example, the electrically insulating layer structure 106 may be made of FR4.

[0103] In the illustrated embodiment, the layer body 102 includes a core 124 of fully cured FR4 material and a vertical through-connection 122 made of copper that extends vertically through the core 124.

[0104] Furthermore, the component carrier 100 includes a component 108 embedded in the layer body 102. For example, the component 108 may be an active electronic component, such as a semiconductor chip (e.g., a silicon chip). For example, the component 108 may be configured for power applications and / or high-frequency applications. In the illustrated embodiment, the component 108 has two metal-containing pads 120 on its lower main surface. An electrically insulating protective layer 138 is formed on the lower main surface of the component 108 but leaves at least a portion of the pads 120 exposed for electrical connection of the pads 120; the electrically insulating protective layer 138 is made, for example, of a plastic, such as polyimide. The protective layer 138 protects the semiconductor material of the component 108 from undesirable phenomena such as oxidation or material migration. In the illustrated embodiment, there are no pre-installed pads 120 and protective layer 138 on the upper main surface 128 of the component 108, such that the upper main surface 128 of the component 108 may be defined by a semiconductor material such as silicon. Therefore, component 108 can be provided in a face-down configuration.

[0105] A corresponding multilayer current-connection stack 110 is formed on the defined surface portion of each of the opposite main surfaces 130, 132 of the layer body 102 and on the defined surface portion of each of the opposite main surfaces 126, 128 of the component 108. The current-connection stack 110 has different lateral confining portions (in the illustrated embodiment, there are three lateral confining portions on the top side and four lateral confining portions on the bottom side).

[0106] More specifically, two laterally confined sections of one of the current connection stacks 110 are laterally confined on the lower main surface 126 of component 108 and in the surrounding portion of component 108 in two regions where a corresponding one of the two pads 120 of component 108 is arranged. Since two pads 120 are provided on the bottom main surface 126 of component 108, two laterally confined sections of the bottom-side current connection stack 110, respectively assigned to a corresponding one of the pads 120, are thus provided.

[0107] Alternatively, the pad 120 of component 108 may be formed from a corresponding portion of the bottom-side current-connection stack 110 (not shown). In other words, the padless component 108 may be embedded in the layer body 102, and the pad may be formed after the component 108 is embedded by directly forming the laterally restricted portion of the current-connection stack 110 on the surface portion of component 108 where the pad 120 should be formed.

[0108] Similarly, Figure 1 As shown, an additional laterally confined portion of the additional current-connection stack 110 covers the entire upper main surface 128 (without pads) of component 108. Therefore, the central portion of the top-side current-connection stack 110 directly covers the exposed semiconductor material of component 108. In the illustrated embodiment, the lateral extension of the central portion of the top-side current-connection stack 110 extends laterally beyond the sidewalls of component 108 to the layer body 102. Therefore, the laterally confined portion of the top-side current-connection stack 110 protrudes laterally beyond the left and right boundaries of the upper main surface 128 of component 108. The laterally confined portion of the top-side current-connection stack 110 is in direct physical contact with the electrically inactive side of component 108. However, the central laterally confined portion of the top-side current-connection stack 110 serves to dissipate heat generated by component 108 during operation of component carrier 100. The central portion of the highly thermally conductive top-side current-connection stack 110 on component 108 vertically removes heat from component 108 (see vertical arrow 140), while the lateral portion of the central portion of the top-side current-connection stack 110 extending beyond the side portion of component 108 dissipates heat in other spatial directions (see oblique arrow 142).

[0109] Similarly, Figure 1 As shown, the layer body 102 includes a vertically penetrating connection 122, which serves as an electrically conductive layer structure 104, extending vertically through the entire core 124 of the layer body 102. The vertically penetrating connection 122 can be a copper-filled through-hole in the core 124. Figure 1 As shown, each vertical through-connector 122 is electrically connected to a corresponding laterally restricted portion of the top and bottom current-connection stack 110, thereby forming an I-shaped structure. This allows electrical signals from the bottom pad 120 to be redirected to portions of the top current-connection stack 110 via portions of the bottom current-connection stack 110 and via the vertical through-connectors 122. In other words, the redistribution of electrical signals from the bottom to the top of the component carrier 100 can be supported by the current-connection stack 110 in conjunction with the vertical through-connectors 120.

[0110] Each part of the current connection stack 110 in Figure 1 All cross-sectional views exhibit a rectangular shape. This geometry can be defined by depositing a continuous, planar layer constituting the hydroelectric interconnect stack 110; and subsequently constructing the layer sequence, for example, by lithography and etching. Furthermore, the corresponding three outermost layers of the hydroelectric interconnect stack 110 form a mirror-symmetric layer sequence on two opposite main surfaces 130, 132 of the layer body 102 (see reference numerals 116, 114, 112). Advantageously, this allows the hydroelectric interconnect stack 110 to be formed simultaneously on the two opposite main surfaces 130, 132 of the layer body 102 and on the two opposite main surfaces 126, 128 of the component 108.

[0111] Next, the construction of the current connection stack 110 will be described in further detail. The top-side current connection stack 110 includes a barrier layer 118 that directly covers the component 108 and thereby protects the semiconductor material of the component 108 from oxidation and material migration. Given the protective structure 138 on the bottom side of the component 108, the barrier layer 118 can be omitted on the bottom side.

[0112] The top-side current-connection stack 110 also includes an adhesion-promoting layer 116 on the barrier layer 118. The bottom-side current-connection stack 110 also has an adhesion-promoting layer 116; however, the adhesion-promoting layer 116 of the bottom-side current-connection stack is formed directly on the bottom main surface 130 of the layer body 102 and the bottom main surface 102 of the component 108. For example, the adhesion-promoting layer 116 may be made of titanium or chromate. The adhesion-promoting layer 116 improves the adhesion of the seed layer 114, which will be described subsequently, and thereby inhibits delamination.

[0113] As already mentioned, each current connection stack in the current connection stack 110 includes a corresponding seed layer 114 on a corresponding adhesion promoting layer 116. The seed layer 114 may, for example, comprise a palladium substrate and a copper layer grown on the palladium substrate by a chemical process (not shown). Alternatively, the seed layer 114 may be a physically deposited copper layer, for example, the seed layer 114 may be a sputtered copper layer.

[0114] Furthermore, each of the current-current interconnect stacks 110 includes a current-current deposited master layer 112, which may be made of an electrically conductive material such as copper. Each master layer 112 can be formed directly on a corresponding seed layer 114 by current-current plating, thereby using the seed layer 114 to apply a voltage. Depending on the desired thickness, the master layer 112 can be formed through one or more plating stages.

[0115] With the aforementioned configuration of the hydrocoupler stack 110, the hydrocoupler stack can advantageously form a hardness gradient, wherein the hardness decreases from the layer body 102 toward the outer portion of the component carrier 100. Descriptively, the hardness of the hydrocoupler stack 110 decreases in the direction of arrow 144, wherein the barrier layer 118 and the adhesion promoting layer 116 can be the hardest, while the main layer 112 can be the softest (and may even have plastic properties). It has been demonstrated that the described hardness gradient improves the mechanical properties of the component carrier 100, and in particular, the described hardness gradient suppresses delamination and warping.

[0116] For example Figure 1 As shown, the entire sidewall and a portion of the bottom side of component 108 are directly surrounded by an electrically insulating layer structure 106, which is functionalized as a buffer structure 134 for buffering mechanical and / or thermal stresses. Advantageously, the buffer structure 134 comprises or is composed of a material having a Young's modulus value lower than that of the dielectric material of the electrically insulating layer structure 106 (particularly below 3 GPa, and preferably below 1 GPa). Thermal stresses generated during the manufacture and / or operation of component carrier 100 can be buffered by the flexible buffer structure 134, thereby protecting the embedded component 108 and the current-connection stack 110.

[0117] Advantageously, the component carrier 100 does not require an additional electrical insulation layer structure, such as an electrical insulation structure made of prepreg, on the current connection stack 110. This ensures a compact design of the component carrier 100, and in particular, a compact design of the component carrier 100 in the vertical direction.

[0118] according to Figure 1Another advantage of the component carrier 100 is that the current-connection stack 110 can be freely designed in terms of thickness and material selection to fine-tune the desired electrical and thermal characteristics of the component carrier. Therefore, the component carrier 100 is well-suited for power applications. The current-connection stack 110 is simple and reliable to manufacture and does not require laser processing. Due to the manufacturing process of the current-connection stack 110, it can have a smooth, low-roughness surface, making the component carrier 100 more suitable for low-loss, high-frequency applications compared to component carriers with attached copper foil.

[0119] Still refer to Figure 1 The portion of the bottom main surface 126 of the embedded component 108 covered by the bottom side portion of the current-connection stack 110 can be 60% or more. Furthermore, 100% of the top main surface 128 of the embedded component 108 can be covered by the top side current-connection stack 110. This allows for reliable electrical connection of the component carrier 100, as well as excellent heat removal and heat dissipation capabilities.

[0120] Figures 2 to 18 An exemplary embodiment of the present invention is shown in the process of manufacturing. Figure 18 A cross-sectional view of the structure obtained during the method of the component carrier 100 shown.

[0121] The bottom main surface 126 of component 108 and the bottom main surface 130 of layer body 102 can be substantially coplanar, that is, they can lie essentially in a common plane. The top main surface 128 of component 108 and the top main surface 132 of layer body 102 can be completely coplanar, that is, they can lie in a common plane. This facilitates a compact design of component carrier 100.

[0122] Apart from the vertical through-connection 122, the layer body 102 into which the component 108 is embedded can be purely dielectric. The only electrical conductive connection structures required in this embodiment are the vertical through-connection 122 and the current-current connection stacks 110 located above and below the layer body 102. Advantageously, additional electrical conductive structures (such as lead frames, copper-filled laser vias, etc.) can be omitted in this embodiment.

[0123] Reference Figure 2 The diagram shows a double-sided copper-clad FR4 core 124, i.e. a fully cured plate-shaped central electrical insulating layer structure 106, wherein the copper layer, which serves as an electrical conductive layer structure 104, is located on two opposite main surfaces of the electrical insulating layer.

[0124] Reference Figure 3 ,exist Figure 2The layer body 102 may have a registration hole 146 (which may also be referred to as an alignment hole) and a functional hole 148 (which may be used to provide a connection from the front side to the back side). For example, this can be accomplished by mechanically drilling the layer body 102.

[0125] refer to Figure 4 , can Figure 3 A metallic material 150 is applied to the exposed surface of the structure shown. Specifically, this can be done by copper plating. This allows the functional holes 148 to be completely filled with the metallic material.

[0126] refer to Figure 5 , Figure 4 The electrically conductive materials on the two opposite main surfaces of the structure shown can be patterned to expose the defined surface portion of the electrically insulating layer structure 106 in the groove 152. This can be achieved by performing a conformal mask photo process to define the cavity.

[0127] refer to Figure 6 ,exist Figure 5 A cavity 154 can be formed in the structure shown, which will later be used to embed the component 108. For example, a carbon dioxide (CO2) laser cutting process can be implemented to form the cavity 154 in the layer body 102.

[0128] refer to Figure 7 , Figure 6 The metallic material on the surface of the structure shown can be removed. For example, this can be done by copper etching. Only the functional hole 148 remains filled with an electrically conductive material, namely copper in the illustrated embodiment, thereby forming an electrically conductive vertical through-connection 122 that extends vertically through the entire dielectric core 124 to provide a front-to-back electrical connection.

[0129] refer to Figure 8 , Figure 7 A temporary support 156, such as tape, can be attached to the bottom side of the structure shown, thereby sealing the bottom of the cavity 154. For example, the attachment of the temporary support 156 can be accomplished by lamination.

[0130] refer to Figure 9 The component 120, having pad 120, is inserted into the cavity 154 and attached to the adhesive surface of the temporary carrier 156 only on its bottom side—which is partially covered by the protective structure 138. Descriptively speaking, the assembly of component 108 is performed in a face-down configuration. This face-down configuration may be advantageous because it makes the process of exposing pad 120 via laser processing unnecessary.

[0131] refer to Figure 10The dielectric buffer structure 134 is used to fill the gap according to the application of dielectric buffer structure 134. Figure 9 The gap in the cavity 154 between component 108 and core 124, and the application of a dielectric buffer structure 134 on top of the layer body 102. For example, a suitable resin can be applied to fill the cavity 154 and to hold the component 108 in place within the cavity 154. Preferably, the buffer structure 134 is made of a soft, low Young's modulus material. The buffer structure 134 can be constructed by laminating a flowable epoxy resin or resin layer onto the core. Figure 9 The structure shown is formed on top of the top.

[0132] refer to Figure 11 Temporary support component 156 can be obtained from Figure 10 The remaining parts of the structure shown are removed. Alternatively, it can also be done by performing according to Figure 12 After the process, the temporary support 156 will be removed.

[0133] refer to Figure 12 It can be seen from Figure 11 Material is removed from the top side of the structure shown to planarize the top side portion. This process exposes the upper main surface 128 of the embedded component 108. This can be accomplished, for example, by mechanical grinding or by chemical mechanical polishing (CMP).

[0134] refer to Figure 13 Additional registration holes 160 can be formed in the layer body 102, for example, by mechanical drilling.

[0135] refer to Figure 14 Only Figure 13 A barrier layer 118 is deposited on the upper main surface of the structure shown. The barrier layer 118 is used to protect the semiconductor material exposed on the top side of the embedded component 108. For example, the barrier layer 118 can be implemented as a titanium nitride layer formed by PVD (physical vapor deposition). Since the bottom side of the component 108 is covered by the pad 120 and the protective structure 138, the barrier layer 118 is not required on the bottom side.

[0136] Subsequently, on the upper main surface of barrier layer 118 and Figure 13 An adhesion promoting layer 116 is formed on the lower main surface of the structure shown. For example, the adhesion promoting layer 116 can be a titanium layer formed by PVD, i.e. by sputtering.

[0137] refer to Figure 15 ,exist Figure 14 On the opposite side of the structure shown, a corresponding seed layer 114 is formed on the adhesion-promoting layer 116 of each main surface. For example, the seed layer 114 can be formed of copper deposited by PVD, or it can be formed of chemically deposited copper. Thus, the electrically conductive seed layer 114 can be formed by a non-electrical process.

[0138] refer to Figure 16 ,exist Figure 15 On the opposite side of the structure shown, a corresponding electrically conductive electrodeposited main layer 112 is formed on the seed layer 114 of each main surface. The main layer 112 can be formed by electrodeposition or electroplating, particularly by plating copper using a current and an electrolyte. This completes the deposition of material for the layer sequence used to form the electrostatically connected stack 110.

[0139] refer to Figure 17 Then you can Figure 16 The full-surface current-connection stack 110 shown is patterned in Figure 16 On each of the two opposite main surfaces of the structure shown. This can be achieved, for example, by photostructuring, i.e., by photolithography. More specifically, it can be... Figure 16 Photoresist is deposited on each of the opposite main surfaces of the structure shown. The defined sub-regions of the photoresist can then be irradiated. The irradiated or unirradiated portions of the photoresist can then be selectively removed by etching. This etching can also remove the exposed surface portions of the two outermost layers 112, 114 of each current-connection stack 110. The photoresist can then be stripped.

[0140] refer to Figure 18 Then, the exposed portions of the remaining layers 116, 118 of the corresponding current connection stack 110 can be removed by etching.

[0141] The central portion of the obtained structure corresponds to the above reference. Figure 1 The described component is the carrier 100.

[0142] Figures 19 to 29 Another exemplary embodiment of the present invention is shown in the process of manufacturing. Figure 29 A cross-sectional view of the structure obtained during the method of the component carrier 100 shown. Although Figures 2 to 18 The implementation method is based on embedding component 108 into core 124, but Figures 19 to 29 The implementation method involves a coreless design.

[0143] refer to Figure 19 The process begins with providing a temporary support 156, such as tape.

[0144] refer to Figure 20 Component 108 (this component may have a reference) Figure 1The described characteristics) can be attached face down to the temporary support 156, for example, it can be adhered to the adhesive surface of the temporary support 156. The metal insert that subsequently forms the electrically conductive vertical through-connection 122 can also be attached to the temporary support 156, for example, it can be attached to the adhesive surface of the temporary support 156. Therefore, Figure 20 The assembly of component 108 and the upper insert is shown.

[0145] refer to Figure 21 An electrically insulating layer structure 106 is formed on the temporary support 156 to cover the component 108 and the vertical through connection 122. This can be achieved, for example, by applying a dielectric resin, such as by coating with a flowable medium (which can then be cured by a curing process) or by laminating a solid sheet.

[0146] refer to Figure 22 It can be obtained from Figure 21 Material is removed from the top side of the structure shown to planarize and thin it. This material removal process can be stopped when the upper main surface 128 of component 108 is exposed. The material removal process can be performed, for example, by grinding or by chemical mechanical polishing.

[0147] refer to Figure 23 The temporary support 156 can be removed, for example, it can be peeled off. The resulting structure is similar to... Figure 12 The structure shown (although according to) Figure 23 The buffer structure (134) can be omitted.

[0148] refer to Figure 24 For example, a registration hole 160 (or alignment hole) is formed by mechanical drilling. The resulting... Figure 24 The central structure shown is Figure 13 The central structure shown is similar.

[0149] refer to Figure 25 Layers 116 and 118, forming the current-connected stack 110, are referenced above. Figure 14 As stated above.

[0150] refer to Figure 26 This forms a seed layer 114 for the current-connected stack 110, as described above. Figure 15 As stated above.

[0151] refer to Figure 27 This forms the main layer 112 of the current-electrodeposited current-electrode stack 110, as described above. Figure 16 As stated above.

[0152] refer to Figure 28The two outermost layers 112 and 114 of the full-surface preform of the laterally restricted current-connected stack 110 are structured, as referenced above. Figure 17 As stated above.

[0153] refer to Figure 29 The exposed surface portions of layers 116 and 118 were removed, as referenced above. Figure 18 As stated above.

[0154] The resulting component carrier 100 is similar to Figure 1 The component carrier shown.

[0155] Figure 30 A bottom view of a portion of a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0156] More specifically, Figure 30 A pad 120 is arranged at the bottom main surface 126 of component 108, in which component 108 is embedded. Figure 30 A plan view of the bottom-side current-connection stack 110 on the connection 120' of such pad 120 is shown. Advantageously, the patterned current-connection stack 110 forms a redistribution structure 170, thereby rearranging the paths of electrical signals propagating in a specified horizontal plane. The redistribution structure 170 thus forms a planar redistribution layer and can form fan-out and / or fan-in structures in various embodiments. Therefore, the planar redistribution structure 170 can be formed directly on the chip plane. This connection architecture in a plane can allow for the electrical combination of different pads 120, can allow for improved registration or alignment, and thereby can allow for the implementation of component carriers 100 with smaller pads 120. Furthermore, this can simultaneously combine multiple embedded components 108 on a single plane.

[0157] Figure 31 A cross-sectional view of a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0158] As shown, the substantially horizontal current-connection stack 110 extends on the upper main surface 128 of component 108 and laterally beyond component 108, and has lateral end portions shaped as a corrugated structure 172. The corrugated structure 172 at the edge of the front cavity 154 may be copper tracks that suppress delamination. Preferably, the vertical amplitude value 174 of the corrugated structure 172 is in the range of 2µm to 10µm. The corrugated structure 172 around the cavity region of component carrier 100 can be obtained by performing the manufacturing method described above, and is particularly noticeable when the low Young's modulus material of the buffer structure 134 is located below the lateral protrusion of the current-connection stack 110. As shown, the corrugated structure 172 oscillates in the horizontal direction. Figure 31In the direction of the paper surface, the corrugated structure 172 can define recessed channel-shaped indentations. The corrugated structure 172 in the cavity region can protect the electrical conduction traces from scratches and mechanical damage. Furthermore, the corrugated structure 172 can suppress mechanical tension triggered by CTE mismatch between different materials (especially FR4, epoxy resin, silicone, etc.) of the component carrier 100. Additionally, the corrugated structure 172 can promote adhesion within the component carrier 100.

[0159] Figure 32 A bottom view showing details of a component carrier 100 according to an exemplary embodiment of the present invention is illustrated. Figure 33 A cross-sectional view of a component carrier 100 according to an exemplary embodiment of the present invention is shown. Component 108 is based on... Figure 32 and Figure 33 Embedded in the component carrier 100, it may be, for example, an electronic component (such as a semiconductor chip, especially a silicon chip) or a non-electronic inlay (such as a copper block or a ceramic block, especially a block with a metal cladding on at least a portion of at least one of its two opposite main surfaces, such as an AlN (aluminum nitride) inlay clad in copper).

[0160] Figure 32 The ellipse and Figure 33 The roughly C-shaped dashed line in the figure indicates that the component carrier 100 may include a dielectric support 176, which engages with the vertical sidewall 178 of the embedded component 108 and the horizontal connecting portions 180, 182 of the bottom main surface 126 and the top main surface 128. Although in Figure 33 Not shown, but the dielectric support 176 can engage the sidewalls 178 and connecting portions 180, 182 in a clamping or anchoring manner along the entire circumference of the component 108. In other words, the dielectric support 176 can have an annular shape surrounding the component 108. More specifically, the horizontal bottom portion and the vertical central portion of the dielectric support 176 can be made of a low Young's modulus buffer structure 134 to buffer stress. The buffer structure 134 can be made of a material with a Young's modulus value, for example, below 3 GPa. The horizontal top portion of the dielectric support in the area indicated by reference numeral 190 can be made of resin (e.g., epoxy resin).

[0161] The clamping or anchoring effect of the dielectric support 176 on the component 108 and the ability of the dielectric support 176 to adapt to the surfaces of the component 108 and the cavity 154 increase the stability of the component carrier 100. Preferably, the resin clamping structure in the form of the dielectric support 176 is fiber-free, thereby enhancing resin flow. The provision of the dielectric support 176 improves stability and contributes to surface flatness. As shown, the upper portion of the dielectric support 176 vertically separates the component 108 relative to the wavy lateral portion of the current-connection stack 110 by a distance 192. For example, the distance 192 can be in the range of 1 μm to 40 μm, preferably in the range of 2 μm to 20 μm. The distance 192 can help shield electrical signals in relation to the shielding of the component 108.

[0162] Preferably, the dielectric support 176 may be present on all four sides of the embedded component 108. The height of the dielectric support 176 may depend on the characteristics of the temporary support 156 used during manufacturing (compared to...). Figure 34 and Figure 35 Furthermore, the pressure during the assembly process of component 108 may affect the characteristics of dielectric support 176.

[0163] Figure 34 and Figure 35 A cross-sectional view of the structure obtained during the manufacture of a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0164] During the insertion of component 108, the cavity 154 formed in the layer body 102 may be closed on the bottom side by a temporary support 156, such as adhesive tape or adhesive sheet. See [link to documentation]. Figure 34 After that, as Figure 35 As shown, component 108 can then be attached to the adhesive attachment surface 184 of temporary support 156. After component 108 is embedded into the material of component support 100 being manufactured, temporary support 156 can be removed (e.g., peeled off) before the manufacturing of component support 100 is completed.

[0165] Very preferably, the temporary carrier 156 can be configured such that the polar component of the surface energy of the attachment surface 184 of the temporary carrier 156 is less than or equal to 5 mN / m, that is, the dispersive component of the surface energy of the attachment surface 184 of the temporary carrier 156 is in the range of 20 mN / m to 25 mN / m, and the overall surface energy of the attachment surface 184 is in the range of 21 mN / m to 26 mN / m. This can promote adhesion between the assembled component 108 and the temporary carrier 156 to prevent the component 108 from sliding and shifting during processing. The above-described characteristics of the temporary carrier 156 can also advantageously define the characteristics of the dielectric support 176.

[0166] Still referencing Figure 34 and Figure 35 It may be highly advantageous to select the flexural strength of the material of the temporary support 156 in the range of 0.4 MPa to 1.2 MPa. This can avoid wrinkles in the material of the temporary support 156 and can prevent the component 108 from tilting during and after assembly.

[0167] Figure 36 A bottom view of a component 108 embedded in a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0168] In the following text and reference Figure 36 This will describe the connection tolerances between the pads 120 of component 108 relative to the PCB design layer. Advantageously, the specification can be such that the tolerance of the component pads 120 relative to the PCB design layer can be greater than or equal to 10 μm. This ensures reliable component connections. Figure 36 Various tolerances are indicated by the reference numeral 194 in the attached figure.

[0169] The aforementioned design allows for leadless connection of traces of the current-connection stack 110 to corresponding pads 120 of component 108 (see reference numeral 196). Other traces of the current-connection stack 110 can be electrically connected to corresponding pads 120 of component 108 via connecting pads 195 (see reference numeral 197). Further traces of the current-connection stack 110 can be electrically connected to multiple corresponding pads 120 of component 108 via combined connecting pads 198 (see reference numeral 199).

[0170] Figure 37 A cross-sectional view of the structure obtained during the manufacture of component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0171] Figure 37The diagram shows that component 108 may include an annular or circumferentially closed electrical insulating protective layer 138 at its bottom main surface 126. This protective layer 138 has a stepped configuration that surrounds and exposes pad 120 at the bottom main surface 126 of component 108. The bottom-side protruding feet thus formed by the electrical insulating protective layer 138 and indicated by reference numeral 139 can be made, for example, of polyimide. When the anchor feet 139 are embedded in component carrier 100, they can facilitate clamping or anchoring connections of component 108 within component carrier 100, and thus provide additional stability. Furthermore, the annular and downwardly projecting electrical insulating protective layer 138 surrounding the respective pad 120 allows for precise guidance of the conductive pad 120 for electrical connections on the bottom side. Additionally, the anchor feet 139 can advantageously prevent delamination. During manufacturing, anchor feet 139 can be attached to temporary support members 156, thereby leaving an empty space between the temporary support members 156 and the component 108. During lamination, the empty space can be filled with resin, so anchor feet 139 also contribute to the formation of the aforementioned dielectric support 176.

[0172] Excellent results can be obtained in terms of uniform deposition of sputtering binder and seed layer when the following roughness conditions are met (especially before physical vapor deposition (PVD) processes): the roughness Ra of the top main surface 128 of the embedded component 108 (e.g., a semiconductor, especially a silicon chip) is preferably in the range of 20 nm to 130 nm, and the roughness Rz (see reference numeral 181) of the top main surface 128 of the embedded component 108 is preferably in the range of 200 nm to 1500 nm. Furthermore, the external roughness Ra of the metal pad 120 of the component 108 is preferably in the range of 20 nm to 130 nm, and the roughness Rz (see reference numeral 183) of the pad 120 is preferably in the range of 500 nm to 1500 nm. Furthermore, the roughness Ra of the outer surface of the electrical insulating protective layer 138 is preferably in the range of 10 nm to 40 nm, and the roughness Rz of the outer surface of the electrical insulating protective layer 138 (see reference numeral 185) is preferably in the range of 50 nm to 250 nm.

[0173] It should be noted that the term "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude multiple. Elements described in association with different embodiments can also be combined.

[0174] It should also be noted that the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

[0175] The embodiments of the present invention are not limited to those shown in the accompanying drawings and the preferred embodiments described above. Instead, various variations of the solutions and principles shown in the present invention can be used, even in fundamentally different implementations.

Claims

1. A component carrier (100), wherein, The component carrier (100) includes: The layer body (102) includes at least one electrically conductive layer structure (104) and / or at least one electrically insulating layer structure (106). The component (108) embedded in the layer body (102); and At least one electrostatic connection stack (110) is a plurality of planar layer structures formed parallel to each other and formed at least partially by electrostatic deposition, the plurality of planar layer structures being located at least partially on at least a portion of at least one of the bottom main surface and the top main surface of the layer body (102); In this embodiment, at least one of the bottom main surface and the top main surface of the embedded component (108) is electrically connected to the at least one current-connection stack (110). The at least one current-connection stack (110) includes a seed layer (114), and In this embodiment, at least one of the at least one current connection stack (110) is arranged on at least one pad (120) at at least one of the bottom main surface and the top main surface of the component (108) and forms a flat redistribution structure (170).

2. The component carrier (100) according to claim 1, wherein, The at least one electrostatic connection stack (110) includes an electrostatically deposited master layer (112).

3. The component carrier (100) according to claim 1, wherein, The at least one electrostatic connection stack (110) includes an electrostatically deposited main layer (112), wherein the electrostatically deposited main layer (112) is disposed on the seed layer (114).

4. The component carrier (100) according to claim 1, wherein, The seed layer (114) includes at least one of a chemically deposited seed layer or a physically deposited seed layer.

5. The component carrier (100) according to claim 1, wherein, The seed layer (114) includes a chemically deposited seed layer, which is a palladium base layer and a copper layer grown on the palladium base layer.

6. The component carrier (100) according to claim 1, wherein, The seed layer (114) includes a physically deposited seed layer, which is a sputtered seed layer.

7. The component carrier (100) according to claim 1, wherein, The at least one current-connection stack (110) includes an adhesion-promoting layer (116).

8. The component carrier (100) according to claim 7, wherein, The at least one current-connection stack (110) includes a seed layer (114), wherein the seed layer (114) is disposed on the adhesion-promoting layer (116).

9. The component carrier (100) according to claim 1, wherein, The at least one current connection stack (110) includes a barrier layer (118).

10. The component carrier (100) according to claim 9, wherein, The barrier layer (118) is disposed directly on the component (108).

11. The component carrier (100) according to claim 9, wherein, The at least one current-connection stack (110) further includes an adhesion-promoting layer (116), and the barrier layer (118) is disposed directly between the component (108) and the adhesion-promoting layer (116).

12. The component carrier (100) according to claim 1, wherein, The at least one current-connection stack (110) has a rectangular cross-section.

13. The component carrier (100) according to claim 1, wherein, The at least one current-connection stack (110) comprises a mirror-symmetric layer sequence on opposite bottom and top main surfaces of the layer body (102).

14. The component carrier (100) according to claim 1, wherein, At least one of the at least one current connection stack (110) includes at least one laterally restricted portion on at least one pad (120) disposed on at least one of the bottom main surface and the top main surface of the component (108).

15. The component carrier (100) according to claim 14, wherein, The main surface of the component (108) on which the at least one pad (120) is arranged is the bottom main surface.

16. The component carrier (100) according to claim 1, wherein, At least one of the at least one current connection stack (110) completely covers the corresponding main surfaces of the bottom main surface and the top main surface of the component (108) where the pad (120) is not disposed of.

17. The component carrier (100) according to claim 16, wherein, The at least one current-connection stack (110) protrudes laterally beyond the corresponding main surfaces of the bottom main surface and the top main surface of the component (108) where the pad (120) of the component (108) is not disposed.

18. The component carrier (100) according to claim 1, wherein, The at least one electrically conductive layer structure (104) includes at least one vertically penetrating connection (122) extending vertically through the layer body (102).

19. The component carrier (100) according to claim 18, wherein, The at least one vertical through-connection (122) is electrically connected to at least one of the at least one current connection stack (110).

20. The component carrier (100) according to claim 18, wherein, The at least one vertical through connection (122) is electrically connected to at least one of the at least one current connection stacks (110) at the bottom main surface and the top main surface opposite to the layer body (102).

21. The component carrier (100) according to claim 1, wherein, At least one of the at least one current connection stack (110) provides a heat dissipation structure.

22. The component carrier (100) according to claim 1, wherein, At least one of the at least one current connection stack (110) provides a heat dissipation structure of at least 45°.

23. The component carrier (100) according to claim 1, wherein, The layer body (102) includes a core (124) comprising a fully cured dielectric material.

24. The component carrier (100) according to claim 1, wherein, At least a portion of the component (108) is directly surrounded by at least one electrically insulating layer structure of the at least one electrically insulating layer structure (106) that is functionalized as a buffer structure (134) for buffering stress.

25. The component carrier (100) according to claim 24, wherein, The buffer structure (134) comprises a material having a Young's modulus value of less than 8 GPa.

26. The component carrier (100) according to claim 24, wherein, The buffer structure (134) comprises a material having a Young's modulus value of less than 3 GPa.

27. The component carrier (100) according to claim 24, wherein, The buffer structure (134) comprises a material having a Young's modulus value of less than 1 GPa.

28. The component carrier (100) according to claim 24, wherein, The buffer structure (134) is made of a material with a Young's modulus value of less than 8 GPa.

29. The component carrier (100) according to claim 24, wherein, The buffer structure (134) is made of a material with a Young's modulus value of less than 3 GPa.

30. The component carrier (100) according to claim 24, wherein, The buffer structure (134) is made of a material with a Young's modulus value of less than 1 GPa.

31. The component carrier (100) according to claim 1, wherein, The at least one current-connection stack (110) has a hardness gradient, the hardness gradient having a decreasing hardness from the layer body (102) toward the outer side of the component carrier (100).

32. The component carrier (100) according to claim 1, wherein, At least one of the bottom main surface and the top main surface of the embedded component (108) is in direct physical contact with the at least one current-connection stack (110).

33. The component carrier (100) according to claim 1, wherein, The layer body (102) is a laminate.

34. The component carrier (100) according to claim 1, wherein, The at least one pad (120) of the component (108) is formed by at least a portion of at least one of the at least one current connection stacks (110).

35. The component carrier (100) according to claim 1, wherein, At least one of the at least one current connection stack (110) extends over the component (108) and extends laterally beyond the component (108), and has a portion including a wavy structure (172).

36. The component carrier (100) according to claim 35, wherein, The vertical wave amplitude (174) of the wave structure (172) is in the range of 1 μm to 20 μm.

37. The component carrier (100) according to claim 35, wherein, The vertical amplitude (174) of the wave structure (172) is in the range of 2 μm to 10 μm.

38. The component carrier (100) according to claim 1, wherein, The component carrier (100) includes a dielectric support (176) that engages with the vertical sidewall (178) of the embedded component (108) and the horizontal connecting portion (180, 182) of the bottom main surface and the top main surface of the component (108).

39. The component carrier (100) according to claim 38, wherein, The dielectric support (176) engages with the vertical sidewall (178) and the connecting horizontal portions (180, 182) along the entire circumference of the component (108).

40. The component carrier (100) according to claim 38, wherein, At least a portion of the dielectric support (176) is formed by a buffer structure (134) for buffering stress.

41. The component carrier (100) according to claim 40, wherein, The buffer structure (134) comprises a material having a Young's modulus value of less than 8 GPa.

42. The component carrier (100) according to claim 40, wherein, The buffer structure (134) comprises a material having a Young's modulus value of less than 3 GPa.

43. The component carrier (100) according to claim 40, wherein, The buffer structure (134) comprises a material having a Young's modulus value of less than 1 GPa.

44. The component carrier (100) according to claim 40, wherein, The buffer structure (134) is made of a material with a Young's modulus value of less than 8 GPa.

45. The component carrier (100) according to claim 40, wherein, The buffer structure (134) is made of a material with a Young's modulus value of less than 3 GPa.

46. ​​The component carrier (100) according to claim 40, wherein, The buffer structure (134) is made of a material with a Young's modulus value of less than 1 GPa.

47. The component carrier (100) according to claim 1, wherein, The component carrier (100) includes at least one of the following features: Wherein, at least 60% of the bottom main surface of the embedded component (108) is covered by one of the at least one current connection stack (110); Of which, more than 90% of the top main surface of the embedded component (108) is covered by one of the at least one current connection stack (110).

48. The component carrier (100) according to claim 1, wherein, The portion of the top main surface of the embedded component (108) covered by one of the at least one current connection stacks (110) is 100%.

49. The component carrier (100) according to claim 1, wherein, The component carrier (100) includes at least one of the following features: Wherein, the roughness Ra of the top main surface of the embedded component (108) is in the range of 20 nm to 130 nm, and / or, the roughness Rz of the top main surface of the embedded component (108) is in the range of 200 nm to 1500 nm. Wherein, the roughness Ra of at least one pad (120) at at least one of the bottom main surface and the top main surface of the component (108) is in the range of 20 nm to 130 nm, and / or, the roughness Rz of at least one pad (120) at at least one of the bottom main surface and the top main surface of the component (108) is in the range of 500 nm to 1500 nm; Wherein, the roughness Ra of the electrically insulating protective layer (138) of the component (108) at at least one of the bottom main surface and the top main surface of the component (108) is in the range of 10 nm to 40 nm, and / or, the roughness Rz of the electrically insulating protective layer (138) of the component (108) at at least one of the bottom main surface and the top main surface of the component (108) is in the range of 50 nm to 250 nm.

50. The component carrier (100) according to claim 1, wherein, The component (108) includes at least one circumferentially closed electrical insulating protective layer (138).

51. The component carrier (100) according to claim 50, wherein, The at least one circumferentially closed electrical insulating protective layer has a vertically stepped structure surrounding at least one pad (120) at at least one of the bottom main surface and the top main surface of the component (108).

52. The component carrier (100) according to claim 1, wherein, The component (108) includes at least one electrically insulating protective layer (138) formed on at least one of the bottom main surface and the top main surface of the component (108) and having at least one protruding anchor foot (139).

53. The component carrier (100) according to claim 1, wherein, The at least one pad (120) of the component (108) is connected to at least one of the at least one current connection stacks (110) and has a circular or non-circular shape.

54. The component carrier (100) according to claim 1, wherein, The at least one pad (120) of the component (108) is connected to at least one of the at least one current connection stacks (110) and has a rectangular shape.

55. The component carrier (100) according to claim 1, wherein, The component (108) includes a plurality of pads (120) connected to at least one of the at least one current connection stacks (110), wherein at least two of the pads (120) are electrically connected to each other through portions of the at least one current connection stack (110).

56. A method for manufacturing a component carrier (100), wherein, The method includes: A layer body (102) is provided, comprising at least one electrically conductive layer structure (104) and / or at least one electrically insulating layer structure (106). Embedding component (108) into the layer body (102); and At least one electro-connection stack (110) is formed at least partially on at least one of the bottom main surface and the top main surface of the layer body (102) by electro-deposition, and the at least one electro-connection stack (110) is electrically connected to at least one of the bottom main surface and the top main surface of the embedded component (108), the at least one electro-connection stack (110) being a plurality of planar layer structures formed parallel to each other, wherein the at least one electro-connection stack (110) includes a seed layer (114), and at least one of the at least one electro-connection stacks (110) is disposed on at least one pad (120) at at least one of the bottom main surface and the top main surface of the component (108) and forms a flat redistribution structure (170).

57. The method according to claim 56, wherein, Embedding the component (108) into the layer body (102) includes: temporarily attaching the component (108) to a temporary support (156), and removing the temporary support (156) before the manufacturing of the component support (100) is completed.

58. The method according to claim 57, wherein, The method includes using a temporary support (156) having at least one of the following characteristics: The polar component of the surface energy of the attachment surface (184) of the temporary support (156) is less than 10 mN / m; The dispersive component of the surface energy of the attachment surface (184) of the temporary support (156) is in the range of 15 mN / m to 30 mN / m. The total surface energy of the attachment surface (184) of the temporary support (156) is in the range of 15 mN / m to 40 mN / m; The flexural strength of the material of the temporary support (156) is in the range of 0.1 MPa to 5 MPa.

59. The method according to claim 57, wherein, The method includes using a temporary support (156) having at least one of the following characteristics: The polar component of the surface energy of the attachment surface (184) of the temporary support (156) is less than or equal to 5 mN / m; The dispersive component of the surface energy of the attachment surface (184) of the temporary support (156) is in the range of 20 mN / m to 25 mN / m. The total surface energy of the attachment surface (184) of the temporary support (156) is in the range of 21 mN / m to 26 mN / m; The flexural strength of the material of the temporary support (156) is in the range of 0.4 MPa to 1.2 MPa.

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