Semiconductor device with a buffer layer

Abstract

A wafer-level buffer layer is disclosed. The wafer-level buffer layer is configured to prevent the back-end-of-line (BEOL) dielectric from cracking during wafer dicing. The wafer-level buffer layer is a composite wafer-level buffer layer with a vibration damping agent. The vibration damping agent includes a polymer-based bottom layer with fillers. The damping agent absorbs or suppresses the vibration of the saw blade during the dicing process to prevent the back-end-of-line (BEOL) dielectric from cracking.

Description

[0001] Cross-reference

[0002] This application is a continuation-in-part of U.S. patent application Ser. No. 17 / 346,310, filed Jul. 14, 2021, which is a divisional application of U.S. patent application Ser. No. 15 / 826,268, filed Nov. 29, 2017, now U.S. Pat. No. 11,049,734. This application also claims the priority of Singapore application No. 10202006768U, filed Jul. 15, 2020, and U.S. Provisional Application No. 63 / 114,536, filed Nov. 27, 2020. All disclosures are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure generally relates to integrated circuits (ICs). More specifically, the present disclosure relates to preventing or reducing cracking of ICs during wafer dicing. Background Art

[0004] Integrated circuits (ICs) require interconnects to provide external connections to internal components. Typically, the interconnects in an IC are formed among multiple dielectric layers. The ongoing demand for low cost and high performance, such as faster operating speeds, lower interconnect delays, smaller feature sizes, and higher density or functionality, is driving the use of copper for interconnects and low-k or ultra-low-k dielectrics (e.g., having a dielectric constant k less than 3.0) as insulators. For example, technology nodes of 65 nanometers (nm) or shorter use copper wires and vias with low-k or ultra-low-k dielectrics as insulators to achieve electrical insulation. Additionally, to meet this demand, ICs use thicker inter-layer dielectric stacks and higher metal densities.

[0005] However, we have noticed that reliability issues with thicker low-k dielectric devices can only be detected during field testing and package reliability testing. Through investigation, we found that the cause of the failure was due to micro-cracks in the low-k dielectric layer within the active die region of the die seal ring. For example, the die seal ring isolates the active region of the die from the saw street. Since they are hidden beneath the upper surface of the wafer, micro-cracks or hair-like defects are almost impossible to detect.

[0006] Although not bound by theory, it is generally believed that due to the brittle nature of the low-k dielectric on the semiconductor wafer, micro-cracks occur in the active die region. The brittleness of the low-k dielectric leads to micro-cracks that originate from the dicing process of cutting the wafer into dice, propagate under the die seal ring, and enter the active die region. For example, cracks originating from the saw street propagate under the die seal ring and into the active die region, resulting in failures of die-level interconnects and having a negative impact on the yield.

[0007] Figure 1a is a simplified diagram depicting the dicing process 100a on a wafer. As shown, the wafer 101 is attached to a wafer dicing tape 122. For example, the wafer has circuit components and a back-end-of-line dielectric 130 with multiple metal layers formed on its active surface, the multiple metal layers having low-k inter-layer and / or intra-layer dielectrics, as well as metal lines and via contacts.

[0008] As shown in the figure, the saw blade 177 rotates and descends onto the edge of the wafer, and starts the cutting process along the saw lane or cutting lane in the x or y direction. The saw blade includes diamond grits 179 embedded in its circumference for cutting the wafer. The initial contact point of the saw blade is located on the BEOL dielectric. As the saw blade rotates and continues to descend into the wafer, the wafer will be cut along the saw lane. The vibration from the saw blade causes cracks 189 to form in the BEOL dielectric. As described above, even if it only occurs at the grain edges of the wafer, the cracks 189 will have a negative impact on the yield and package reliability.

[0009] To prevent the cracks 189, a groove can be formed first along the saw lane of the wafer using a laser. Figure 1b A simplified diagram of a process 100b for forming a laser groove 126 along the saw lane 120 of a wafer 101 is shown. The wafer with a low-k BEOL dielectric 130 is mounted on a wafer dicing tape 122. The laser groove 126 is formed by a laser 192. The laser groove 126 penetrates the BEOL dielectric 130 and enters the wafer 101. Since the laser is non-mechanical, no vibration is generated to cause cracks 189 in the low-k BEOL dielectric 130. After forming the laser groove 126, the process 100b continues to cut the wafer 101 using a diamond saw blade 177, as Figure 1c shown in process 100c.

[0010] Although the laser groove can reduce the cracks 189 in the low-k BEOL dielectric 130, in terms of equipment cost and production time, using a laser will significantly increase the manufacturing cost. For example, laser equipment is expensive, and the process of forming a laser groove is much slower than using only the saw blade 177. Using both a laser groove and mechanical sawing will significantly extend the processing time of each wafer 101. In some cases, even when using both a laser groove and a mechanical saw blade, wafer chipping can still be observed at the grain edges.

[0011] Therefore, based on the above discussion, the present disclosure will provide a lower-cost solution for preventing cracks from occurring in the BEOL dielectric of a device during the process of dicing a wafer into individual devices. Summary of the Invention

[0012] The present disclosure generally relates to semiconductor devices or integrated circuits (ICs). More specifically, the present disclosure relates to preventing or reducing the chipping of ICs during the wafer dicing process.

[0013] In one embodiment, a semiconductor package includes a die having an active side and an inactive side. The active side includes die pads on a back-end-of-line (BEOL) dielectric. A buffer layer is disposed on the active side of the die. The buffer layer includes a vibration damping composition for preventing the BEOL dielectric from cracking during wafer dicing. The buffer layer has a plurality of via openings for exposing the die pads. A plurality of via contacts are disposed on the via openings for providing electrical connection to the die pads.

[0014] In another embodiment, a semiconductor package includes a die having an active side and an inactive side. The active side includes die pads on a back-end-of-line (BEOL) dielectric. A buffer layer is disposed on the active side of the die. The buffer layer includes a Young's modulus and a fracture strength for preventing the BEOL dielectric from cracking during wafer dicing; the buffer layer has a plurality of via openings located in the buffer layer for exposing the die pads. A plurality of via contacts disposed on the via openings for providing electrical connection to the die pads.

[0015] In another embodiment, a method of processing a semiconductor wafer includes providing a semiconductor wafer having an active side. The active side is processed to have a plurality of dies, and a top die surface of the plurality of dies includes die pads on a back-end-of-line (BEOL) dielectric. The method further includes forming a buffer layer on the semiconductor wafer covering the top die surface. The buffer layer includes a vibration damping composition for preventing the BEOL dielectric from cracking during wafer dicing.

[0016] Advantages and features of the embodiments disclosed herein will become apparent by reference to the following description and the drawings. Further, it should be understood that the features of the various embodiments described herein are not mutually exclusive and may exist in various combinations and permutations. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings incorporated herein and forming a part of the specification, show preferred embodiments of the disclosure and together with the description are used to explain the principles of the various embodiments of the disclosure, where like numerals represent like parts.

[0018] Figure 1a A simplified diagram showing a wafer being diced along a saw street by a mechanical saw blade;

[0019] Figure 1b - 1c A diagram showing a wafer being diced along a saw street using laser scribing and a mechanical saw blade;

[0020] Figure 2a - 2e A simplified cross-sectional view showing various embodiments of a semiconductor package;

[0021] Figure 2f Images showing a top view of a wafer with a buffer layer and an enlarged view of a portion of the buffer layer;

[0022] Figure 2g - 2h Examples of processes for forming a composite buffer layer are shown;

[0023] Figure 3a Stress / strain curves are shown;

[0024] Figure 3b - 3c A cross-sectional view of a wafer cut along a scribe line is shown;

[0025] Figure 3d A cross-sectional view of a conventional wafer without a buffer layer perpendicular to the scribe line being cut is shown;

[0026] Figure 3e A cross-sectional view of a wafer with a buffer layer perpendicular to the scribe line being cut is shown;

[0027] Figure 3f The effect of cutting a wafer with a buffer layer having an oversized filler is shown;

[0028] Figure 4a A simplified top view of a processed semiconductor wafer is shown;

[0029] Figure 4b A simplified top view of a portion of a wafer along a scribe line between two die is shown;

[0030] Figure 4c 、 4e and 4g show simplified cross-sectional views of various examples of a portion of a processed wafer;

[0031] Figure 4d 、 4f and 4h show simplified cross-sectional views of die corresponding to the wafers in Figure 4c 、 4e and 4g;

[0032] Figure 5a - 5c Examples of various process flows for processing a wafer are shown;

[0033] Figure 6a A top view of a process for processing multiple wafers is shown;

[0034] Figure 6b - 6j A cross-sectional view of a process for processing multiple wafers is shown;

[0035] Figure 7 Examples of process flows for processing a wafer are shown;

[0036] Figure 8a Shows a top view of a processing panel assembly;

[0037] Figure 8b - 8j Shows a cross-sectional view of a process for a processing panel assembly;

[0038] Figure 9 Shows a process flow for forming a redistribution layer (RDL) structure

[0039] Figure 10a - 10c Shows images of wafers with and without a composite buffer layer before and after dicing. Detailed Description

[0040] Embodiments generally relate to devices, such as semiconductor devices or integrated circuits (ICs). In particular, the present disclosure relates to a buffer layer for preventing or reducing cracking and chipping of low-k back-end-of-line (BEOL) dielectrics on a wafer caused by a dicing process.

[0041] Figure 2a - 2e Shows a simplified cross-sectional view of various embodiments of a semiconductor package 200. Among them, Figure 2a - 2c Shows a simplified cross-sectional view of different embodiments of a fan-in semiconductor package; Figure 2d - 2e Shows a simplified cross-sectional view of different embodiments of a fan-out package. Referring to Figure 2a - 2e , the semiconductor package 200 includes a die 210. The die 210 includes first and second main die faces 211 and 212 and side die faces 213. The first main die face 211 may be referred to as the active die face. And the second main die face 212 may be referred to as the non-active die face. For example, the die is separated from a processed wafer having a plurality of dies, such as a silicon wafer. Other types of wafers are also possible. For example, the wafer may be a silicon carbide (SiC) wafer, a gallium nitride (GaN) wafer, a gallium arsenide (GaAs) wafer, or an indium phosphide (InP) wafer. Other types of wafers are also possible. A bare die or an unprocessed wafer can serve as the substrate of the die (i.e., the die substrate).

[0042] The die substrate can be processed with circuit components or elements. The circuit components can include active and passive circuit elements. The active elements can include, for example, transistors, diodes, and triodes, while the passive elements include voltage elements, capacitors, resistors, and inductors. Other types of active and passive elements can also be included. The circuit elements can be formed through a series of processes such as doping (e.g., implantation or diffusion), deposition (e.g., oxidation, chemical vapor deposition (CVD), electroplating, and sputtering), and patterning (e.g., lithography and etching). Other techniques can also be used to form the circuit elements.

[0043] Form a BEOL dielectric having multiple interconnect levels on the die substrate, the interconnect levels having conductive lines coupled to via contacts. For example, the BEOL dielectric covers the surface of the die substrate having the circuit components. In one embodiment, the BEOL dielectric includes a low-k dielectric or dielectric layer for insulating the conductive lines located at different layer interconnect levels. The low-k dielectric layer can also include an ultra-low-k dielectric layer. The low-k dielectric or dielectric layer can refer to the low-k dielectric or dielectric layer and the ultra-low-k dielectric or dielectric layer. Other types of dielectric layers can also be used.

[0044] The top of the BEOL dielectric can include a dielectric passivation layer 244 having a pad opening for exposing the conductive die contact pad 242. The contact pad can also be referred to as a die pad or a bond pad. For example, the contact pad can be an aluminum (Al) contact pad. Other types of contact pads can also be used, such as copper (Cu), nickel (Ni), palladium (Pd), gold (Au), chromium (Cr), or a combination or alloy thereof, such as Al-Cu.

[0045] The dielectric passivation layer 244 can be a passivation stack having multiple dielectric layers. For example, the passivation stack can include a combination of dielectric layers, such as silicon oxide and silicon nitride layers. Other types of dielectric layers can also be used. In one embodiment, the pad opening is smaller than the contact pad. For example, the upper surface of the dielectric passivation layer 244 is above the upper surface of the contact pad, and the pad opening is smaller than the contact pad. As shown, the dielectric passivation layer 244 covers the edge portion of the contact pad. The pad opening can be formed by, for example, anisotropic etching, such as reactive ion etching. Other types of etching can also be used to form the pad opening.

[0046] In one embodiment, the exposed portions of the upper surfaces of the BEOL dielectric, the passivation layer, and the contact pads constitute the wafer active surface. In some cases, the wafer active surface may include the top of the BEOL dielectric and the contact pads, but not the passivation layer 224.

[0047] In one embodiment, a buffer layer 250 is disposed on the die active surface of the die. For example, the buffer layer covers the die active surface having contact pads and a passivation layer. In the case where the die active surface does not include the passivation layer, the buffer layer 250 covers the die active surface and the contact pads. For example, the buffer layer 250 may be referred to as a wafer-level buffer layer. For example, before performing the wafer dicing process, the buffer layer 250 may be disposed on the wafer active surface having a plurality of dies.

[0048] The buffer layer 250 prevents or reduces breakage and chipping in the BEOL dielectric during the dicing process. The mechanical properties of the buffer layer are also important for reducing or preventing cracking of the BEOL dielectric during wafer dicing. In particular, the Young's Modulus and Breaking Strength of the buffer layer are important for reducing or preventing breakage and chipping during wafer dicing.

[0049] In one embodiment, the buffer layer 250 is transparent. A non-transparent buffer layer may also be provided. In some cases, the material may be configured to be transparent or opaque. In one embodiment, the buffer layer is non-photoimageable. For example, the buffer layer 250 is non-photosensitive. Patterning of the buffer layer 250 can be achieved by techniques such as laser etching, mask, and etch, or a combination thereof.

[0050] In one embodiment, the buffer layer 250 is a tunable buffer layer. For example, the Young's Modulus and Breaking Strength of the buffer layer 250 are tunable. The Young's Modulus and Breaking Strength of the buffer layer 250 can be adjusted to prevent cracking of the BEOL dielectric. In one embodiment, the Young's Modulus is about 10,000 - 25,000 MPa. In other embodiments, the Young's Modulus is about 14,000 - 25,000 MPa. In other embodiments, the Young's Modulus is about 15,000 - 25,000 MPa. In another embodiment, the Young's Modulus is about 16,000 - 25,000 MPa. In another embodiment, the Young's Modulus is about 15,000 - 20,000 MPa. In other embodiments, the Young's Modulus is about 20,000 - 25,000 MPa.

[0051] The breaking strength can be about 45–150 MPa. In other embodiments, the breaking strength is about 70–150 MPa. In another embodiment, the breaking strength is about 70–120 MPa. In another embodiment, the breaking strength is about 70–105 MPa. In another embodiment, the breaking strength of the buffer layer 250 is about 80–120 MPa. In yet another embodiment, the breaking strength of the buffer layer 250 is about 90–120 MPa. The coefficient of thermal expansion (CTE) of the buffer layer can be, for example, about 6-20 ppm / K. The buffer layer 250 can have temperature stability in the range of minus (-) 65 to plus (+) 300 degrees Celsius (°C).

[0052] In one embodiment, the tunable buffer layer is a tunable composite buffer layer. The tunable composite buffer layer includes a vibration damping composition or a damping agent. For example, the vibration damping composition includes a base layer containing fillers or granules to reduce vibration during the cutting process.

[0053] In one embodiment, the base buffer layer of the tunable composite buffer layer is an organic polymer matrix material. Various types of polymers can be used for the base buffer layer. For example, the polymers can include thermosetting plastics or thermoplastics, such as polyimides, epoxy resins, and other types of polymers. In one embodiment, the base buffer layer includes a resin, such as epoxy or cyanate esters. Preferably, the base buffer layer is a low viscosity resin, such as a biphenyl epoxy resin. The thickness of the buffer layer can be about 10–100 micrometers (μm), about 15–100 μm, about 20–100 μm, about 25–100 μm, about 45–100 μm, or about 60–100 μm. The tolerance of the buffer layer can be plus or minus (±) 1–5 μm, depending on the thickness of the buffer layer. Buffer layers with other thicknesses can also be used.

[0054] The filler of the base buffer layer can be organic-based, inorganic-based, or a combination thereof. For example, the filler may include silica (SiO2) filler, amorphous alumina (α-Al2O3) filler, or a combination thereof. Other types of non-conductive fillers are also possible. For example, the filler can be silica, glass beads, sand, or a combination thereof. For example, the filler can be spherical filler. The spherical filler can have a diameter of about 0.5 - 12 micrometers (um). In other embodiments, the spherical filler can have a diameter of about 0.5 - 10 micrometers (um). Fillers of other sizes are also possible, including nano-sized fillers. In addition, the filler can have any shape. Preferably, the filler can be fillers of non-uniform sizes. For example, the fillers of the base buffer layer have different diameters. The fillers of the base buffer layer can also have different shapes. Providing fillers of different sizes can result in a higher filler density in the buffer layer. For example, smaller-sized fillers can fill the gaps between larger-sized fillers.

[0055] The size of the filler can depend on the width of the saw blade used when cutting the wafer. In one embodiment, the size of the filler is smaller than the width of the saw blade used in the cutting. For example, the size of the filler can be less than or equal to about 1 / 2 or about 1 / 3 of the saw blade width. In one embodiment, the size of the filler can be in the range of about 0.5 micrometers (um) to about 1 / 3 of the saw blade width. The saw blade width is typically about 30 - 36 micrometers (um). For example, when the saw blade width is 36 micrometers (um), the size of the filler can be about 0.5 - 10 micrometers (um); or when the saw blade width is 30 micrometers (um), about 0.5 - 12 micrometers (um). In one embodiment, based on the total weight of the composite buffer layer, the filler concentration in the composite buffer layer is about 70 - 90 weight percent (wt%). In another embodiment, the filler concentration in the composite buffer layer is about 80 - 90 weight percent (wt%).

[0056] In one embodiment, the composite buffer layer can be adjusted to have a selected or defined Young's modulus and fracture strength by choosing a suitable base buffer layer material, filler material, filler concentration, or a combination thereof. In addition, these factors may also affect the coefficient of thermal expansion (CTE) and temperature stability.

[0057] In one embodiment, the composite buffer layer is a preformed layer laminated to the wafer or die. For example, the composite buffer layer is preformed into a sheet and then laminated to the wafer. In other embodiments, the composite buffer layer can be formed on the wafer. The composite buffer layer can also have other configurations.

[0058] The buffer layer includes a via opening 252 for exposing the contact pad 242. The via opening 252 can be formed by laser etching. For example, the via opening includes the sidewalls of the via formed by laser etching. Other techniques for forming the via opening are also possible. For example, the via opening can be formed by plasma etching, such as reactive ion etching, using a patterned photoresist mask. In this case, the via opening includes the sidewalls formed by plasma etching. In other embodiments, the via opening is formed using a multi-etch process, such as first performing a high-power laser etch and then a low-power laser etch; or first performing a high-power laser etch and then a plasma etch. For example, the laser is a laser assembly for non-photoimageable patterning. The two-step etch avoids damage to the aluminum pad by the high-power laser etch. The two-step etch process can result in the upper part of the via opening having sidewalls formed by laser etching, while the lower part can be sidewalls formed by laser etching or plasma etching.

[0059] As shown, the bottom of the via opening in the buffer layer is smaller than the pad opening in the passivation layer. For example, the pad opening is formed before the buffer layer, and the via opening is formed after the buffer layer. The bottom of the via opening can be disposed at approximately the center of the pad opening. Alternatively, the bottoms of the via opening and the pad opening have the same size. For example, the via opening and the pad opening are formed approximately simultaneously. In some embodiments, when the buffer layer is formed, the passivation layer does not include the pad opening. The via opening is formed first, and then the pad opening is formed.

[0060] A redistribution layer (RDL) structure 270 is formed on the package. The RDL structure 270 provides interconnections with the contact pad 242. In one embodiment, the RDL structure includes RDL via contacts 274, RDL lines 276, and RDL posts 278. The various components of the RDL structure can be copper or copper alloy RDL components. For example, the RDL via contacts, RDL lines, and RDL posts are formed of copper or copper alloy. Other types of conductive metals are also possible.

[0061] The RDL component can be formed by electroplating using a seed layer 271. For example, the seed layer lines the buffer layer 250, including the sidewalls and bottom of the via openings. The seed layer can be a titanium copper (TiCu) seed layer formed by sputtering. A plating mask, for example, formed by laser direct imaging, can be used to pattern a patterned photoresist layer for electroplating the RDL layer. For example, a dry film photoresist layer is laminated on top of the seed layer, and a laser assembly capable of photosensitive imaging patterning is used to pattern it by laser direct imaging. The patterned photoresist layer includes openings corresponding to the RDL lines, including the via openings. The electroplating process fills the mask openings, including the via openings, with a conductive layer such as copper to form the RDL lines, which are coupled to the contact pads through the RDL via contacts of the via openings. The electroplating process stops at a height slightly lower than that of the patterned photoresist layer. After forming the RDL lines, the patterned photoresist layer can be retained. Another dry film photoresist layer is laminated on the RDL lines and the mask. The photoresist film is patterned by, for example, laser direct imaging to form stud openings at the positions where the RDL studs will be formed on the RDL lines. For example, the patterned resist layer can be a plating mask for selectively forming RDL studs 278 on the RDL lines 276. An electroplating process is used to form the RDL studs 278 in the stud openings, and then the photoresist film is removed.

[0062] The redistribution (RDL) encapsulation layer 246 is disposed above the buffer layer 250 having the RDL structure 270. The RDL encapsulation layer 246 has a first surface that is flush with the surface of the RDL studs. For example, the RDL encapsulation layer fills the gap between the RDL lines 276 and the RDL studs 278, exposing the surface of the RDL studs.

[0063] In one embodiment, the RDL encapsulation layer is an RDL composite encapsulation layer. The RDL composite encapsulation layer 246 can be similar to the composite buffer layer 250. For example, the RDL composite encapsulation layer 246 includes a base RDL encapsulation layer containing fillers or granules. The fillers in the RDL composite encapsulation layer can be larger than those in the composite buffer layer 250.

[0064] For example, the RDL composite encapsulation layer 248 can pre-form an encapsulation sheet and laminate it onto the buffer layer, for example, by film molding, compression molding, vacuum lamination, or roller lamination. Other techniques can also be used to form the RDL composite encapsulation layer. The laminated RDL composite encapsulation layer covers the buffer layer 250 and the RDL structure 270.

[0065] As shown, the surface of the RDL encapsulation layer 246 is flush with the surface of the RDL posts. The flush surface of the RDL encapsulation layer and the RDL posts 278 can be referred to as the first surface, the top surface, or the exposed surface. When forming the RDL encapsulation layer 248, it can cover the top surface of the RDL posts 278. A grinding process or a planarizing process, such as chemical mechanical polish, can be performed to remove the excess redistribution (RDL) encapsulation material, thereby forming a flush surface of the RDL posts 278 and the RDL encapsulation layer 248.

[0066] In one embodiment, the encapsulation contact 279 is disposed on top of the RDL post 278. As shown, the encapsulation contact includes a solder bump. The solder bump can be formed by solder bump technology. For example, the solder bump technology can include solder drop and reflow to form a solder ball. For example, the solder bump can be used for ball grid array packaging. Other types of encapsulation contacts are also possible, such as LGA and QFN packaging. For example, the encapsulation contact can be a metal-plated contact, such as a tin-plated contact. The metal-plated contact can be formed on the RDL post by, for example, a matt plating process. Other techniques that can be used to form the plated contact are also possible.

[0067] As shown in the figure, the RDL structure includes an RDL level. For example, the RDL structure includes an RDL line level, where the RDL lines are coupled to contact pads through RDL via contacts and a final stud level is provided on the RDL line level. In other embodiments, the RDL line level may include multiple line levels (from level 1 to level x), having RDL via contacts, RDL lines, and a final stud level provided on the topmost RDL line level (level i = x). In this case, the RDL encapsulation layer may have multiple RDL encapsulation levels. Except for the last level, the RDL encapsulation layer is formed after each RDL line level is formed. For the topmost line level, the encapsulation layer covers the RDL lines of the topmost RDL line level and the RDL studs of the final stud level.

[0068] As Figure 2a shown, the encapsulation is a fan-in type semiconductor encapsulation 200. For the fan-in type semiconductor encapsulation, the RDL structure includes RDL lines and RDL studs, which are located within the area of the die. The RDL structure and the RDL encapsulation layer are a wafer-level RDL structure and a wafer-level RDL encapsulation layer, respectively. For example, the RDL structure and the RDL encapsulation layer are formed on the wafer before dicing. In this case, the die side surface, the composite buffer layer, and the RDL encapsulation layer are flush or aligned during the dicing process.

[0069] In one embodiment, the inactive die face 212 also provides an inactive or backside protection layer 258. For example, the backside protection layer 258 is provided on the inactive face or the backside of the die. In a preferred embodiment, the backside protection layer is similar to the composite buffer layer 250. For example, the backside protection layer is a composite backside protection layer. The backside protection layer prevents chipping of the wafer backside during the dicing process. Other types of backside protection layers are also possible. Similar to the composite buffer layer 250, the composite backside protection layer is a wafer-level layer. Before dicing, the backside protection layer is applied to the wafer backside. Therefore, the side surface of the backside protection layer is also flush with the die side surface. The thickness of the backside protection layer may be about 25 - 200 micrometers (um), about 25 - 150 um, or about 50 – 120 micrometers (um). Other thicknesses of the backside protection layer are also possible.

[0070] Figure 2b - 2cOther embodiments of the fan-in semiconductor package 200 are shown. In one embodiment, the RDL structure and the RDL encapsulation layer are panel-level RDL structures and encapsulation layers. For example, after the wafer is diced into individual dies and a panel assembly is formed, the RDL structure and the RDL encapsulation layer are formed at the panel level. For example, the panel assembly includes a plurality of dies arranged in a matrix and is encapsulated by a mold layer 290. Accordingly, the RDL encapsulation layer 246 extends beyond the area of the die 210. For example, the sides of the RDL encapsulation do not align with the sides of the die and the buffer layer. As shown, the sides of the die 210 and the buffer layer 250 are recessed compared to the sides of the RDL encapsulation layer.

[0071] The mold layer 290 encapsulates the die. For example, the mold layer is an epoxy mold compound. Other types of mold layers are also possible. For example, the mold layer can be formed from a liquid mold compound. The mold layer covers the sides of the die and is disposed on top of the RDL encapsulation layer 246. The sides of the RDL encapsulation layer and the sides of the mold layer are flush, and the bottom mold layer surface above the top of the RDL encapsulation layer is flush with the bottom surface of the buffer layer.

[0072] As Figure 2b shown, the mold layer covers the top of the die. For example, the top mold layer surface is disposed above the non-active die face 212. Such an encapsulation can be referred to as a six-sided fan-in package, where all six sides of the die are protected. In another embodiment, as Figure 2c shown, the top mold layer surface is flush with the non-active die face. Such an encapsulation can be referred to as a five-sided fan-in package.

[0073] In other embodiments, the encapsulation is a fan-out package, as Figure 2d - 2e shown. For a fan-out semiconductor package, the RDL structure 270, including RDL lines 276 and RDL posts 278, extends beyond the area of the die 210. The RDL structure and the RDL encapsulation layer 246 are respectively a panel-level RDL structure and an RDL encapsulation layer. For example, the RDL structure and the RDL encapsulation layer are formed at the panel level after wafer dicing. In this case, the sides of the RDL encapsulation layer do not align with the sides of the die and the buffer layer.

[0074] The molding layer 290 encapsulates the die. The molding layer covers the side surfaces of the die and is disposed on top of the RDL encapsulation layer 246. The side surfaces of the RDL encapsulation layer and the side surfaces of the molding layer are flush, and the bottom molding layer surface above the top of the encapsulation layer and the bottom surface of the buffer layer are flush. As Figure 2d shown, the molding layer covers the top of the die. For example, the top molding layer surface is disposed above the non-active die surface. This type of encapsulation can be referred to as a six-sided fan-out package. In another embodiment, as Figure 2e shown, the top molding layer surface and the non-active die surface are flush. This type of encapsulation can be referred to as a five-sided fan-out package.

[0075] Figure 2f An image showing a top view of the wafer 201 with the buffer layer 250 in an embodiment is shown. An enlarged view 204 of the buffer layer is also included. As described above, the buffer layer can prevent or reduce breakage and fragmentation in the BEOL dielectric during dicing. The buffer layer includes a vibration damping agent. In one embodiment, the buffer layer has a specific Young's modulus and fracture strength to prevent breakage and fragmentation of the BEOL dielectric during dicing. In one embodiment, the Young's modulus is about 10,000 - 25,000 MPa. In other embodiments, the Young's modulus is about 14,000 - 25,000 MPa. In other embodiments, the Young's modulus is about 15,000 - 25,000 MPa. In another embodiment, the Young's modulus is about 16,000 - 25,000 MPa. In another embodiment, the Young's modulus is about 15,000 - 20,000 MPa. In other embodiments, the Young's modulus is about 20,000 - 25,000 MPa.

[0076] In one embodiment, the fracture strength of the buffer layer is about 45 - 150 MPa. In other embodiments, the fracture strength is about 70 - 150 MPa. In another embodiment, the fracture strength is about 70 - 120 MPa. In another embodiment, the fracture strength is about 70 - 105 MPa. In another embodiment, the fracture strength of the buffer layer is about 80 - 120 MPa. In another embodiment, the fracture strength of the buffer layer is about 90 - 120 MPa. The coefficient of thermal expansion (CTE) of the buffer layer can be, for example, about 6 - 20 ppm / K. The buffer layer can have temperature stability in the range of minus (-) 65 to plus (+) 300 degrees Celsius (°C).

[0077] The thickness of the buffer layer can be about 10–100 micrometers (um), 15–100 micrometers (um), 20–100 micrometers (um), 25–100 micrometers (um), 45–100 micrometers (um), or 60–100 micrometers (um). The tolerance of the buffer layer can be plus or minus (±) 1-5 micrometers (um), depending on the thickness of the buffer layer. Buffer layers with other thicknesses can also be provided.

[0078] In one embodiment, the buffer layer is a composite buffer layer having a base buffer layer 291 that includes a filler or particles 292. In one embodiment, the base buffer layer is a transparent base buffer layer, such as a transparent polymer base buffer layer. Various types of polymers can be used for the base buffer layer. The polymer base buffer layer can be a thermosetting plastic or a thermoplastic, such as polyimide or resins. In one embodiment, the base buffer layer includes a resin, such as epoxy or cyanate esters. Preferably, the base buffer layer is a low viscosity resin, such as biphenyl epoxy resin.

[0079] The filler can be organic-based, inorganic-based, or a combination thereof. For example, the filler can include silica (SiO2) filler, amorphous alumina (α-Al2O3) filler, or a combination thereof. Other types of non-conductive fillers can also be used. For example, the filler can be silica, glass beads, sand, or a combination thereof. For example, the filler can be spherical filler. Fillers of other shapes can also be used. Preferably, the diameter of the filler is about 0.5–12 micrometers (um).

[0080] The size of the filler can depend on the width of the saw blade used when cutting the wafer. In one embodiment, the size of the filler is less than the width of the saw blade used in the cutting. For example, the size of the filler can be less than or equal to about 1 / 2 or about 1 / 3 of the width of the saw blade. In one embodiment, the size of the filler can be from about 0.5 micrometers (um) to about 1 / 3 of the width of the saw blade. The width of the saw blade is typically about 30–36 micrometers (um). For example, when the width of the saw blade is 36 micrometers (um), the size of the filler can be about 0.5–10 micrometers (um); or when the width of the saw blade is 30 micrometers (um), the size of the filler can be about 0.5–12 micrometers (um). In one embodiment, based on the total weight of the composite buffer layer, the concentration of the filler in the composite buffer layer is about 70–90 weight percent (wt%). In another embodiment, the concentration of the filler in the composite buffer layer is about 80–90 weight percent (wt%).

[0081] To form a buffer layer, components can be combined and applied to the wafer in a flowable form. For example, a liquid including an epoxy resin and additives (hardener) is combined or mixed with a filler (particles). The liquid mixture with the filler is applied to the wafer. After application, the wafer is cured to harden the buffer layer with the filler. For example, such techniques can include spin-coating onto the wafer, or slit die or printing onto the wafer.

[0082] Figure 2g Illustrate forming a buffer layer by spin-coating. As shown, a spin coater 221 includes a rotatable table 222 on which a wafer 201 is mounted. For example, the wafer can be mounted to the rotatable table by a vacuum chuck. A dispenser 226 dispenses a flowable buffer layer composition (resin, filler, and hardener) onto the wafer for coating. After coating, the wafer is heated to cure the buffer layer with the filler.

[0083] Figure 2h Illustrates forming a buffer layer by slit die or printing. As shown, a slit die printer 230 includes a platform 232 on which a wafer 201 is mounted. The wafer can be mounted to the platform by, for example, a vacuum press. An elongated slit die coater 234 is disposed above the platform in the y direction. A container tank 236 supplies the flowable buffer layer to the slit die coater. The slit die coater is configured to translate along the platform in, for example, the x direction. As it translates across the wafer, a coating head on the slit die coater coats the wafer surface with a buffer layer 250. After coating, the wafer is heated to cure the buffer layer with the filler.

[0084] Other techniques that can form a buffer layer on the wafer are also possible. In one embodiment, the buffer layer can be formed by compression molding. For example, a liquid solution of the buffer layer (resin, additives, and fillers) is injected into a compression molding tool carrying the wafer. In other embodiments, the buffer layer can be laminated onto the wafer by vacuum type or roller type lamination. For example, the buffer layer can be prefabricated into a sheet. It can be cut and laminated onto the wafer surface using vacuum type lamination. Alternatively, the prefabricated sheet can be rolled into a roller and laminated onto the wafer surface using roller type lamination. The sheet is pressed onto the wafer and cured to form a buffer layer on the wafer.

[0085] The present disclosure finds that Young's modulus and fracture strength are important for reducing the cracking of BEOL dielectrics during cutting. Young's modulus is defined as the ratio of stress to the corresponding strain and is defined as follows:

[0086] Young's modulus = stress / strain.

[0087] Figure 3a An example of a general stress / strain curve for any material is shown. The curve includes two parts. The first or initial part represents the modulus of resilience of the material; the second or final part represents the modulus of toughness of the material.

[0088] The modulus of resilience is the maximum energy that a material per unit volume can absorb and still return to its original shape. This is the elastic stage of the material. For example, the initial part of the stress / strain curve describes the ability of the material to resist elastic deformation under load (strain). It shows the tendency of the material to maintain its shape even when deformed, such as being stretched, pulled, twisted, or compressed. The limit of the elastic stage is the yield point or elastic limit. The yield point represents the limit before the material undergoes permanent deformation if the force is continued to be applied.

[0089] The modulus of toughness represents the ability of a material to absorb energy during plastic deformation. It is the strain energy density that a material can absorb before fracture. This is the plastic stage of the material. The plastic stage includes the strain hardening part, from the yield point to the ultimate strength point of the material, and the necking part, from the ultimate strength point to the fracture point of the material.

[0090] The stress / strain curve of a material can be used to determine its properties. For example, a stiffer material exhibits a steeper slope in the elastic stage, a brittle material lacks a plastic region, and a stronger material shows a higher ultimate tensile strength.

[0091] In one embodiment, we found that the buffer layer as described above has a Young's modulus of about 10,000 - 25,000 MPa, 14,000 - 25,000 MPa, 15,000 - 25,000 MPa, 16,000 - 25,000 MPa, 15,000 - 20,000 MPa or 20,000 - 25,000 MPa, which can effectively prevent cracks from occurring on the brittle low-k BEOL dielectric during wafer dicing. In addition, the buffer layer can have a fracture strength of about 45 - 150 MPa, 70 - 150 MPa, 70 - 120 MPa, 70 - 105 MPa, 80 - 120 MPa or 90 - 100 MPa. The coefficient of thermal expansion (CTE) of the buffer layer can be, for example, approximately 6–20 ppm / K. The buffer layer can have temperature stability in the range of negative (-) 65–positive (+) 300 degrees Celsius (°C).

[0092] Without being bound by any theory, the buffer layer exhibits good tensile strength, elastic properties, and stiffness. For example, the base buffer layer provides good elastic performance, while the filler provides stiffness and good tensile strength, resulting in a higher fracture strength, such as about 50 - 100 MPa, 70 - 100 MPa or 80 - 100 MPa.

[0093] By providing a buffer layer on the low-k dielectric, the initial contact point of the saw blade is the buffer layer rather than the low-k BEOL dielectric.Figure 3b - 3c A simplified side view or cross-sectional view 300 of a wafer 301 is shown to illustrate this. Refer to Figure 3b , a wafer 301 with a low-k BEOL dielectric 330 is provided on a dicing tape 322. For example, the top of the BEOL dielectric includes a passivation layer with openings to expose die contact pads (not shown). The passivation layer is removed from the dicing streets to expose the BEOL dielectric. A buffer layer 350 is disposed over the wafer, for example covering the BEOL dielectric, the passivation layer, and the contact pads. In particular, the buffer layer 350 covers the BEOL dielectric located in the dicing streets of the wafer.

[0094] When a rotating saw blade 377 with diamond grits 379 descends to cut the wafer, the initial contact point of the saw blade is on the buffer layer. The rotating saw blade vibrates at the initial contact point of the wafer, and the generated force is absorbed by the buffer layer. This is different from conventional cutting processes where the brittle low-k dielectric is the initial contact point, resulting in the formation of microcracks. As Figure 3c shown, when the saw blade continues to cut the wafer, by using the buffer layer to suppress cutting vibrations, the formation of microcracks in the low-k BEOL dielectric can be avoided. The buffer layer not only absorbs the vibrations but also dissipates the vibrations through the layer to prevent the formation of microcracks.

[0095] To reduce the vibration of the saw blade during cutting, the buffer layer can be a sawblade guide during the cutting process. Figure 3d - 3e A simplified cross-sectional view 300 of a wafer 301 through a dicing street 320 is shown.

[0096] Refer to Figure 3d , a conventional wafer is shown. For example, the wafer 301 has circuit elements and a low-k BEOL dielectric 330 thereon. For example, the top of the BEOL dielectric includes a passivation layer 344 with openings to expose the underlying contact pads 342. The passivation layer is removed from the dicing streets to expose the BEOL dielectric therein. As shown, during cutting, a rotating saw blade 376 descends onto the wafer as shown by arrow D. The saw blade rotates about axis A. However, there may be some clearance or movement of the saw blade relative to the axis of rotation as shown by the arrows. For example, such clearance or movement can cause excessive freedom of the saw blade, resulting in vibrations during cutting. Therefore, the vibrations can cause microcracks to appear in the low-k BEOL dielectric.

[0097] In contrast, Figure 3eFigure 301 is shown, having a composite buffer layer 350 disposed on a low-k BEOL dielectric 330. In addition to absorbing and dissipating vibrations from the saw blade 376 during dicing, the composite buffer layer 350 can also act as a saw blade guide. For example, when the saw blade descends, as shown by arrow D, the composite buffer layer accommodates the saw blade, preventing it from having excessive degrees of freedom. For example, the degrees of freedom of the saw blade are limited to the direction in which the saw blade descends. This reduces the vibration of the saw blade during the dicing process, thereby preventing the formation of microcracks in the low-k BEOL dielectric.

[0098] Another important aspect of the buffer layer 350 is the size of the filler. Figure 3f Figure 300 shows a cross-sectional view of a wafer, illustrating problems associated with over-sized fillers 392. As shown, a buffer layer 350 is formed on the wafer, above a low-k BEOL dielectric and a passivation layer 344 having an opening for exposing a contact pad 342. As shown, the buffer layer 350 includes fillers 392 that exceed the width of the (rotating) saw blade 377. As shown, the over-sized fillers 392 are wider than the saw blade. The over-sized fillers can be disposed in the buffer layer 350 along the dicing lanes 320 of the wafer. When the rotating saw blade descends onto the wafer, as shown by arrow D, it will contact the over-sized fillers. The fillers have a higher tensile strength than the resin of the base buffer layer. When the saw blade contacts the over-sized fillers, it will cause excessive vibration, generating microcracks 397 in the base buffer layer, which extend into the passivation layer and the underlying low-k BEOL dielectric. This can significantly affect the reliability of the device.

[0099] However, providing fillers from about 0.5 micrometers (um) to less than the width of the saw blade, such as 1 / 2 or 1 / 3 of the saw blade width, can avoid this problem. When the saw blade cuts the base buffer layer and contacts the fillers, they can be easily removed. In addition, the base buffer layer can absorb the vibration of the saw blade contacting the fillers. This can avoid excessive vibration, thereby preventing the formation of microcracks.

[0100] Figure 4a Figure 401 shows a simplified top view of an embodiment of a semiconductor wafer having a buffer layer. The wafer can include a bare wafer. The bare wafer can be a lightly doped p-type silicon wafer. Other types of wafers can also be used. For example, the wafer can be a silicon (Si), silicon carbide (SiC) wafer, gallium nitride (GaN) wafer, gallium arsenide (GaAs) wafer, or indium phosphide (InP) wafer. Other types of wafers are also possible.

[0101] The crystal grains 410 are formed on the active surface 402 of the wafer. For example, the active surface can be the top surface of the wafer, and the non-active surface can be the bottom surface. The devices are arranged in rows along the first (x) direction and in columns along the second (y) direction. A composite buffer layer is provided on the surface of the wafer, above the devices. After the processing of the wafer is completed, the wafer is cut along the cutting lines 449 in the x and y directions to divide the devices into individual crystal grains.

[0102] Figure 4b A top view showing a portion of the wafer 401 along the scribe lane 420 between two adjacent crystal grains 410a - b. Figure 4c 、 4e And 4g show simplified cross-sectional views of portions of various embodiments of the processed wafer, while Figure 4d 、 4f And 4h show Figure 4c 、 4e And simplified cross-sectional views of the crystal grains of the wafer in 4g.

[0103] Referring to Figure 4b 、 4c 、4e and 4g, a portion of the wafer including parts of two adjacent crystal grains 410a - b is separated by the scribe lane or cutting channel 420. As shown, a bare wafer 401 with an active surface 402 and a non-active surface 403 is provided. The active and non-active surfaces are opposite surfaces. For example, the wafer is a semiconductor wafer, such as a silicon wafer. Other types of wafers, such as silicon carbide (SiC), gallium nitride ((GaN), gallium arsenide (GaAs), or indium phosphide (InP).

[0104] The circuit components (not shown) of the device are formed on the active surface 402 of the wafer. The circuit components can include active and passive circuit elements. The active components can include, for example, transistors, diodes, and triodes, while the passive elements include voltage elements, capacitors, resistors, and inductors. Other types of active and passive elements can also be included. The circuit components can be formed using front-end-of-line (FEOL) processing. For example, by using doping (such as implantation or diffusion), deposition (such as oxidation, chemical vapor deposition (CVD), plating, and sputtering), and patterning (such as lithography and etching). Other techniques can also be used to form the circuit components.

[0105] A back-end-of-line (BEOL) dielectric 430 with interconnects (not shown) is formed on the active surface of the wafer. For example, the BEOL dielectric may cover the circuit components and the scribe lines of the device, and the interconnects are configured to interconnect the circuit components and provide external access. The BEOL dielectric may include multiple interconnect levels. For example, metal lines coupled to the via contacts may be provided in different BEOL dielectric layers or levels. The BEOL dielectric layers may include low-k dielectrics, ultra-low-k dielectrics, and GaN and germanium (Ge) coating materials. The wire and the via contacts may be formed of copper (Cu) or its alloy (copper alloy) and are formed by damascene techniques, such as dual damascene or single damascene techniques. Other techniques, such as reactive ion etching (RIE), and other types of conductive materials may also be used to form the wires and the contacts. Regarding the first contact level, where the contacts are formed to connect to the circuit components, they may be tungsten contacts.

[0106] The top interconnect level may be a pad level with die contact pads 442 for providing external connections. For example, the contact pads or die pads are aluminum (Al) pads. Other types of contact pads are also possible. For example, the contact pads may be copper (Cu), nickel (Ni), palladium (Pd), gold (Au), chromium (Cr), and aluminum (Al) or their alloys, such as Al-Cu. The pad level may include a die seal ring 443. The die seal ring surrounds, for example, the die active area. The die seal ring separates the scribe lines from the die active area.

[0107] A passivation layer 444 can be provided. For example, the passivation layer 444 can be disposed on top of the BEOL dielectric. The passivation layer can be a passivation stack. The passivation stack can include a combination of dielectric layers, such as silicon oxide and silicon nitride layers. Other types of dielectric layers are also possible. The passivation layer covers the contact pads and the die seal ring. As shown, the passivation layer 444 includes a pad opening 448 to expose the contact pads. In one embodiment, a mask and an etching process are used to pattern the pad opening. For example, an anisotropic etch, such as reactive ion etching (RIE), is used to etch the passivation layer with a patterned photoresist mask to form the pad opening. Thus, the pad opening of the passivation layer includes anisotropically etched sidewalls, such as the sidewalls of plasma or dry anisotropic etching. Other techniques can also be used to form the pad opening, such as using isotropic etch (wet or dry) or laser drilling. Different techniques can result in different shapes of sidewall profiles. For example, anisotropic etched sidewalls, wet isotropic etched sidewalls, wet isotropic etched sidewalls, and laser etched sidewalls have different profiles.

[0108] In one embodiment, the passivation layer 444 includes a saw street opening in the saw street between adjacent rows and columns of the device. The saw street opening can be formed in the same process as forming the pad opening. Alternatively, the saw street opening can be formed separately. The saw street opening exposes the low-k dielectric in the saw street of the wafer. As shown, the saw street can include dummy metal structures 441. The dummy metal structures can reduce cracks generated due to wafer dicing. The width of the dummy metal structures 441 can be narrower or wider than the saw blade width.

[0109] A wafer prepared with circuit components, BEOL dielectric, passivation layer, and saw street opening can be referred to as a processed wafer, where the passivation layer has a pad opening for exposing the contact pads. For example, the processed wafer can be an incoming processed wafer from an external supplier. For example, a packaging supplier can accept the processed wafer. In some cases, the incoming processed wafer may be an internally processed wafer rather than from an external customer. The processed wafer can be further processed. For example, the next step of processing can be performed on the processed wafer.

[0110] In one embodiment, the next process includes forming a composite buffer layer 450 on the wafer. For example, the composite buffer layer is disposed on a processed or incoming wafer. As shown, the composite buffer layer is disposed on top of the BEOL dielectric having contact pads 442 and the patterned passivation layer 444 having pad openings 448 for exposing the contact pads and the scribe lanes 420. In other embodiments, the processed wafer may not have a passivation layer. In this case, the composite buffer layer can be the passivation layer.

[0111] As described above, the composite buffer layer 450 prevents the BEOL dielectric from cracking and chipping during dicing. The buffer layer 450 has a Young's modulus and a fracture strength to prevent the BEOL dielectric from cracking and chipping during dicing. In one embodiment, the Young's modulus is about 10,000 - 25,000 MPa. In other embodiments, the Young's modulus is about 14,000 - 25,000 MPa. In other embodiments, the Young's modulus is about 15,000 - 25,000 MPa. In another embodiment, the Young's modulus is about 16,000 - 25,000 MPa. In another embodiment, the Young's modulus is about 15,000 - 20,000. In other embodiments, the Young's modulus is about 20,000 - 25,000 MPa.

[0112] In one embodiment, the fracture strength of the buffer layer is about 45–150 MPa. In other embodiments, the fracture strength is about 70–150 MPa. In another embodiment, the fracture strength is about 70–120 MPa. In another embodiment, the fracture strength is about 70–105 MPa. In another embodiment, the fracture strength of the buffer layer is about 80–120 MPa. In yet another embodiment, the fracture strength of the buffer layer is about 90–120 MPa. For example, the coefficient of thermal expansion (CTE) of the buffer layer can be about 6–20 ppm / K. The buffer layer has temperature stability in the range of negative (-) 65–positive (+) 300 degrees Celsius (°C).

[0113] The thickness of the buffer layer can be about 10–100 micrometers (μm), 15 - 100 micrometers (μm), 20–100 micrometers (μm), 25–100 micrometers (μm), 45–100 micrometers (μm) or 60–100 micrometers (μm). The tolerance of the buffer layer can be plus or minus (±) 1 - 5 micrometers (μm), depending on the thickness of the buffer layer. Buffer layers with other thicknesses can also be provided.

[0114] In one embodiment, the composite buffer layer 450 includes a base buffer layer having fillers or particles. In one embodiment, the base buffer layer is a transparent base buffer layer, such as a transparent polymer base buffer layer. Various types of polymers can be used for the base buffer layer. The polymer base buffer layer can be a thermosetting plastic or a thermoplastic, such as polyimide or resin. In one embodiment, the base buffer layer includes a resin, such as epoxy resin or cyanate ester. Preferably, the substrate buffer layer is a low-viscosity resin, such as biphenyl epoxy resin.

[0115] The fillers can be organic-based, inorganic-based, or a combination thereof. For example, the fillers can include silica (SiO2) fillers, amorphous alumina (α-Al2O3) fillers, or a combination thereof. Other types of non-conductive fillers are also possible. For example, the fillers can be silica, glass beads, sand, or a combination thereof. For example, the fillers can be spherical fillers. Other shaped fillers are also possible.

[0116] The fillers can be fillers of non-uniform size. For example, the fillers of the base buffer layer have different diameters. The fillers of the base buffer layer can also have different shapes. Providing fillers of different sizes enables the buffer layer to contain a higher density of fillers. For example, smaller-sized fillers are nested in the voids between larger-sized fillers, thereby providing a higher filler loading for the buffer layer.

[0117] The size of the fillers can depend on the width of the saw blade used when cutting the wafer. In one embodiment, the size of the fillers is less than the width of the saw blade used in the cutting. For example, the size of the fillers can be less than or equal to about 1 / 2 or about 1 / 3 of the saw blade width. In one embodiment, the size of the fillers can be about 0.5 micrometers (um) to about 1 / 3 of the saw blade width. The saw blade width is typically about 30–36 micrometers (um). For example, when the saw blade width is 36 micrometers (um), the size of the fillers can be about 0.5–10 micrometers (um); or when the saw blade width is 30 micrometers (um), about 0.5–12 micrometers (um).

[0118] In one embodiment, the concentration of the filler in the base buffer layer is selected to adjust the Young's modulus of the buffer layer to about 10,000 - 25,000 MPa, 14,000 - 25,000 MPa, 15,000 - 25,000 MPa, 16,000 - 25,000 MPa, 15,000 - 20,000 MPa, or 20,000–25,000 MPa; and the fracture strength to about 45 - 150 MPa, 70 - 150 MPa, 70 - 120 MPa, 70 - 105 MPa, 80 - 120 MPa, or 90 - 100 MPa. In one embodiment, based on the total weight of the composite buffer layer, the concentration of the filler in the composite buffer layer is about 70 - 90 weight percent (wt%). In another embodiment, the concentration of the filler in the composite buffer layer is about 80 - 90 weight percent (wt%).

[0119] To form the buffer layer, the components can be combined and applied to the wafer in a flowable form. For example, a liquid including an epoxy resin and additives (a hardener) is combined or mixed with a filler (particles). The liquid mixture with the filler is applied to the wafer. After application, the wafer is cured to harden the buffer layer with the filler. For example, such techniques can include spin-coating onto the wafer, or slit die or printing onto the wafer. Other techniques for forming the buffer layer on the wafer are also possible. For example, compression molding or lamination, such as vacuum or roller lamination, can also be used to form the composite buffer layer on the processed wafer.

[0120] As Figure 4c shown, the processing of the wafer is completed at the wafer level. Then the wafer is diced to divide the wafer into individual die 410, as Figure 4d shown.

[0121] As shown, the passivation layer includes pad openings to expose bond pads. Alternatively, the passivation layer does not include pad openings. In other embodiments, as discussed, no passivation layer is provided.

[0122] In some embodiments, as Figure 4eAs shown, before performing the wafer dicing process, the buffer layer 450 is patterned to form via openings 452 to expose the contact pads 442. The via openings may be configured with slanted or tapered sidewall profiles. In one embodiment, the via openings are configured such that the ratio of the bottom surface area of the via openings to the top surface area of the via openings is about 60 - 90%. Other ratios, such as about 70 - 80%, are also possible. As shown, the via openings are smaller than the contact pads. In one embodiment, the bottom of the via openings is smaller than the pad openings in the passivation layer. In a preferred embodiment, the bottom of the via openings is positioned approximately or as close as possible to the central portion of the contact pads. Other configurations of the via openings are also possible.

[0123] In one embodiment, the via openings are formed using a laser etching process. For example, the vias in the buffer layer have laser-etched sidewalls. Other processes for forming the via openings are also possible. In a preferred embodiment, the etching process for forming the via openings is configured to prevent damage to the contact pads. In one embodiment, the via openings in the buffer layer are formed by a multi-etch process to prevent damage to the contact pads. In one embodiment, the etching process includes a high power laser etch process for forming the upper portion of the via openings, and a RIE or inductively coupled plasma-RIE process is used to form the lower portion of the via openings. In another embodiment, a high power laser etching process can be used to form the upper portion of the via openings, and a low power laser etching process can be used to form the lower portion of the via openings. The etching process or the process for forming the via openings may be masked or maskless. Other configurations of the etching process for forming the via openings, such as other numbers of etching steps or combinations of masked or maskless etching, are also possible.

[0124] Optionally, in the case where the passivation layer does not include pad openings, the via openings are formed and then the passivation layer is etched to expose the contact pads. In other cases, no passivation layer is provided. Thus, the via openings expose the contact pads.

[0125] In one embodiment, as Figure 4e shown, the processing of the wafer is completed at the wafer level. Then the wafer is cut to dice the wafer into individual die 410, as Figure 4f shown.

[0126] In another embodiment, as Figure 4gAs shown, after forming the via opening in the composite buffer layer 450, the wafer is continued with the next processing step. The wafer processing forms a redistribution layer (RDL) structure. For example, the RDL structure is formed at the wafer level. In one embodiment, the RDL structure includes conductive via contacts 474 (RDL via contacts), patterned wires 476 (RDL lines), and pillars (RDL pillars) 478 on the buffer layer 450. The RDL lines 476 may have a thickness of about 10–100 micrometers (um), while the RDL pillars 478 may be about 15–100 micrometers (um). Other thicknesses are also possible. As for the RDL via contacts, their height may be approximately equal to the thickness of the passivation layer.

[0127] The RDL via contacts and RDL lines can be formed in a single process. For example, a conductive layer, such as copper or a copper alloy, can be formed on the buffer layer. In one embodiment, the conductive layer can be formed by electroplating. In this case, a seed layer (not shown) is lined on the composite buffer layer, including the via opening. The seed layer can be formed by sputtering. A plating mask (not shown) is used for electroplating the conductive layer, such as a patterned dry film photoresist laminated on the composite buffer layer with the seed layer. The photoresist is patterned by laser direct imaging (LDI). The patterned photoresist layer includes openings corresponding to the RDL lines, including the via opening. The electroplating process forms a conductive layer such as copper or a copper alloy, filling the mask openings, including the via opening, to form the RDL lines 476, which are coupled to the contact pads through the RDL via contacts 474 in the via opening. The electroplating process pauses slightly below the height of the patterned photoresist layer. Another dry film photoresist is laminated on top of the RDL lines 476 and the resist mask. The photoresist is patterned by, for example, LDI to form pillar openings on the RDL lines where the RDL pillars are to be formed. For example, the patterned resist layer can be a plating mask for selectively forming the RDL pillars on the RDL lines 476. An electroplating process is used to form the RDL pillars 478 in the pillar openings, and then the resist film is removed. Other techniques for forming the RDL structure are also possible.

[0128] The RDL encapsulation layer 446 is disposed on the buffer layer having the RDL structure. The RDL encapsulation layer is, for example, a wafer-level RDL encapsulation layer. In one embodiment, the RDL encapsulation layer is an RDL composite encapsulation layer. The RDL composite encapsulation layer may be similar to the composite buffer layer 450. For example, the RDL composite encapsulation layer includes a base RDL encapsulation layer containing fillers or particles.

[0129] The RDL encapsulation layer 446 can be pre-formed into an encapsulation sheet and laminated onto the buffer layer, for example, by compression molding or vacuum lamination. Other techniques for forming the RDL encapsulation layer are also possible. Laminating the RDL encapsulation layer covers the buffer layer and the RDL structure. A grinding process is used to remove the excess encapsulation material to expose the RDL pillars. For example, the grinding process can create a flush surface between the RDL pillars and the RDL encapsulation layer. In one embodiment, the flush surface can be referred to as the first encapsulation layer surface, and the opposite surface in contact with the buffer layer can be referred to as the second encapsulation layer surface.

[0130] In one embodiment, as Figure 4g shown, further processing of the wafer is completed at the wafer level. For example, after forming the RDL structure with the RDL encapsulation layer, the post processing of the wafer is completed. Then the wafer is diced to divide the wafer into individual die 410, as Figure 4h shown. In some embodiments, encapsulation contacts (not shown) can be formed before dividing the wafer into individual die.

[0131] Optionally, before the dicing process, the inactive wafer face 403 can be provided with an inactive or backside wafer face protection layer (not shown). For example, a wafer backside protection layer is formed on the inactive or backside wafer face. In a preferred embodiment, the backside protection layer is similar to the composite buffer layer 450. For example, the backside protection layer is a composite backside protection layer. The backside protection layer prevents wafer chipping on the backside of the wafer during the dicing process. Other types of backside protection layers are also possible. After forming the backside protection layer, the wafer is divided into individual die 410.

[0132] Figure 5a A simplified embodiment of a general process flow 500 for processing a wafer is shown, such as an incoming or processed wafer. For example, an incoming wafer is similar to the incoming wafer 401 described in Figure 4a and 4b . The general process considers various options, including forming fan-in or fan-out packages, performing backgrinding or dicing before backgrinding, and forming a backside protection layer for processing the wafer.

[0133] At 505, the process begins. For example, the process of processing an incoming wafer begins. For example, a processed wafer can be a processed wafer provided by an external supplier.

[0134] For example, a wafer includes circuit components of a device formed on its active or top surface. In one embodiment, BEOL dielectrics with interconnects are formed on the active surface of the wafer, covering the circuit components of the device and the scribe lines. The interconnects of the BEOL dielectrics interconnect the circuit components and provide external access. The BEOL dielectrics may include multiple interconnect levels. For example, metal lines coupled to via contacts may be provided in different BEOL dielectric layers or levels. The BEOL dielectric layers may include low-k dielectric layers. The uppermost interconnect level may be a pad level with contact pads to provide external connections. For example, the pad level may be the top of the BEOL. In one embodiment, a passivation layer may be provided above the pad level, having pad openings to expose the contact pads. Alternatively, a foreign or processed wafer may not include a passivation layer or a passivation layer without pad openings.

[0135] At 510, the process forms a buffer layer on the wafer. In one embodiment, the process forms a composite buffer layer on the active wafer surface. For example, a composite buffer layer is formed on the wafer, covering the contact pads and the passivation layer. In some embodiments, the composite buffer layer is formed on the contact pads without a passivation layer.

[0136] In one embodiment, the composite buffer layer includes a base buffer layer containing fillers or particles. For example, the base buffer layer may be a transparent polymer base buffer layer, and the fillers may be organic, inorganic, or a combination thereof. For example, the size of the fillers may be about 0.5–12 micrometers (μm) or about 0.5–10 micrometers (μm).

[0137] The size of the fillers may depend on the width of the saw blade used when cutting the wafer. In one embodiment, the size of the fillers is less than the width of the saw blade used in the cutting. For example, the size of the fillers may be less than or equal to about 1 / 2 or about 1 / 3 of the width of the saw blade used for cutting. In one embodiment, the size of the fillers may be from about 0.5 micrometers (μm) to about 1 / 3 of the width of the saw blade. The width of the saw blade is typically about 30–36 micrometers (μm). For example, when the width of the saw blade is 36 micrometers (μm), the size of the fillers may be about 0.5–10 micrometers (μm); or when the width of the saw blade is 30 micrometers (μm), about 0.5–12 micrometers (μm). In one embodiment, based on the total weight of the composite buffer layer, the concentration of the fillers in the buffer layer is about 70-90 weight percent (wt%). In another embodiment, the concentration of the fillers in the composite buffer layer is about 80-90 weight percent (wt%).

[0138] As described above, the composite buffer layer prevents or reduces breakage and fragmentation in the BEOL dielectric during cutting. The composite base buffer layer, in one embodiment, has a Young's modulus and a fracture strength that prevent breakage and fragmentation of the BEOL dielectric during cutting. In one embodiment, the Young's modulus is about 10,000 - 25,000 MPa, 14,000 - 25,000 MPa, 15,000 - 25,000 MPa, 16,000 - 25,000 MPa, 15,000 - 20,000 MPa or 20,000–25,000 MPa and the fracture strength is up to about 45 - 150 MPa, about 70 - 150 MPa, about 70 - 120 MPa, about 70 - 105 MPa, about 80 - 120 MPa or about 90 - 100 MPa. For example, the coefficient of thermal expansion (CTE) of the buffer layer can be about 6–20 ppm / K. The buffer layer has temperature stability in the range of negative (-) 65–positive (+) 300 degrees Celsius (°C). The thickness of the buffer layer can be about 10–100 micrometers (μm), 15–100 micrometers (μm), 20–100 micrometers (μm), 25–100 micrometers (μm), 45–100 micrometers (μm) or 60–100 micrometers (μm). The tolerance of the buffer layer can be plus or minus (±) 1 - 5 micrometers (μm), depending on the thickness of the buffer layer. Buffer layers with other thicknesses can also be provided.

[0139] The composite buffer layer can be formed by compression molding or lamination, such as vacuum type or roller type lamination. Other techniques for forming the composite buffer layer can also be used. For example, the composite buffer layer can be formed by spin - coating, slit - die coating, or printing, or other types of printing techniques.

[0140] At 520, the process determines whether to form a via opening in the buffer layer. If no via opening is to be formed, the process continues to 530. On the other hand, if a via is to be formed, the process continues to 522. At 522, a via opening is formed in the buffer layer, exposing the contact pads of the foreign wafer. For example, the via opening includes tapered sidewalls. Various techniques can be used to form the via opening. For example, a laser etching process or a mask and etching process can be used to form the via opening. In some embodiments, a multiple etching process can be used to prevent damage to the contact pads. Other techniques for forming the via opening can also be used. As discussed, the via opening can be formed with a passivation layer, with or without a pad opening, or without a passivation layer.

[0141] After forming the vias openings, the process proceeds to 530. At 530, the process determines whether to form an RDL structure for each die of the wafer. If the RDL structure is not formed, the process continues to 535. If the RDL structure is to be formed, the process continues to 532.

[0142] In one embodiment, the RDL structure is used for a fan-in package without a molding compound. To form the RDL structure, in one embodiment, a seed layer can be formed on the wafer surface. For example, the seed layer coats the surface of the composite buffer layer having the via openings. For example, the seed layer is a titanium-copper (Ti-Cu) seed layer formed by sputtering.

[0143] In one embodiment, a plating mask is formed over the buffer layer having the seed layer. For example, a dry film photoresist is laminated onto the buffer layer having the via openings. The photoresist is patterned by LDI to form a patterned resist film, which can be the plating mask. For example, the patterned resist film includes openings corresponding to the RDL lines having the via openings. An electroplating process is performed to fill the mask openings and the via openings in the buffer layer, forming RDL lines coupled to the contact pads via the RDL via contacts. Other techniques for forming the RDL lines are also possible.

[0144] After forming the RDL lines, a dry film photoresist is laminated over the RDL lines and the plating mask. The dry film photoresist is patterned to form via openings in the RDL lines at the locations where the RDL posts will be formed. For example, the patterned photoresist can be the plating mask for selectively forming RDL posts on the RDL lines. An electroplating process is used to form RDL posts in the via openings. Other processes for forming the RDL posts are also possible. The dry photoresist film used for forming the RDL lines and RDL posts is removed.

[0145] An RDL encapsulation layer is disposed over the buffer layer having the RDL structure. The RDL encapsulation layer covers the RDL lines and RDL posts and fills the gap therebetween. The RDL encapsulation layer is, for example, a dielectric layer similar to the composite buffer layer. For example, the RDL encapsulation layer includes a base RDL encapsulation layer having fillers. In one embodiment, the RDL encapsulation layer is laminated onto the wafer surface. Other techniques for forming the RDL encapsulation layer are also possible. The wafer surface is polished to remove the excess RDL encapsulation material, exposing the surface of the RDL posts. This results in a flush surface with the RDL posts and the RDL encapsulation layer.

[0146] In one embodiment, an encapsulation contact is formed. In one embodiment, the encapsulation contact is formed on an RDL post. The encapsulation contact includes solder or an encapsulation bump. The encapsulation bump can be formed by solder bump technology. For example, the solder bump technology can include solder drop and reflow to form solder balls. For example, the solder bump can be used for a ball grid array (BGA) package. Other types of encapsulation contacts are also possible, such as LGA and QFN packages. For example, the encapsulation contact can be a metal-plated contact, such as a tin-plated contact. The electroplated contact can be formed on the post by, for example, a mattplating process. Other techniques, such as ENIG and NiAu electroplating, are also possible. The process proceeds to 535.

[0147] At 535, the process determines whether to perform dicing before grinding (DBG). If DBG is not performed, the process continues to 540. If DBG is performed, the process continues to 542 to start DBG. At 542, the wafer is partially diced. In one embodiment, the wafer is diced along the dicing line to a depth approximately equal to the final thickness of a singulated die. In some cases, this depth is slightly deeper than the final thickness of a singulated die to account for process variations. This can be 10–30% or 10–20% greater than the final thickness of a singulated die. For example, in the case where the final thickness of the die is approximately 80 micrometers (um), the partial dicing can be approximately 100 micrometers (um). Other depths can also be used for partial dicing.

[0148] After the wafer is partially diced, the process proceeds to 552 to perform backside wafer grinding. For example, the backside of the wafer is ground to thin the wafer to the final die thickness. The grinding process divides the wafer into individual dice. After dicing, the process terminates at 590.

[0149] As described above, if DBG is not performed, the process proceeds to 540. At 540, the process determines whether to perform backside wafer grinding. If backside wafer grinding is not performed, the process proceeds to 560. If backside wafer grinding is required, the process proceeds to 550. At 550, the backside of the wafer is ground. For example, backgrinding is performed to reduce the wafer thickness. The amount of wafer removed results in the wafer having the final wafer thickness. For example, the final thickness of the wafer can be approximately equal to the final thickness of the die. For example, the final thickness of the die does not take into account a possible backside protection layer that may subsequently be formed on the backside of the wafer. After backside grinding is completed, the process continues to 560.

[0150] At 560, the process determines whether to apply a backside protection layer on the backside of the wafer (e.g., the non-active wafer surface). If the backside protection layer is not formed, 580 is performed. On the other hand, if the backside protection layer is formed, 570 is performed. At 570, a backside protection layer is formed on the non-active wafer surface. For example, the backside protection layer is the same as or similar to the composite buffer layer formed at 510. The backside protection layer may include a backside base protection layer with fillers, formed by lamination. The process proceeds to 580 where wafer dicing is performed. After the wafer is divided into individual dies, the process terminates at 590.

[0151] Figure 5b An embodiment of process flow 500 is shown for processing a wafer, such as an incoming or processed wafer, to form a fan-in package without a molding layer. For example, using this process flow, a BGA package is formed. At 505, the process starts. For example, processing of an incoming wafer begins. For example, a processed wafer can be an incoming processed wafer from an external supplier.

[0152] For example, the wafer includes an active surface with contact pads. In some embodiments, a passivation layer may be provided with pad openings to expose the contact pads. At 510, the process forms a composite buffer layer on the active surface of the wafer. For example, a composite buffer layer is formed on the wafer, covering the contact pads or covering the top of the BEOL dielectric, the contact pads, and the passivation layer. The composite buffer layer includes a base buffer layer containing fillers or particles. The composite buffer layer can prevent breakage and fragmentation of the BEOL dielectric during the dicing process. The composite buffer layer can be formed by compression molding or lamination. Other techniques for forming the composite buffer layer are also possible.

[0153] At 520, the process forms a via opening in the buffer layer to expose the contact pads of the incoming wafer. For example, the via opening includes tapered sidewalls. In one embodiment, the via opening is formed by laser etching. Other techniques for forming the via opening are also possible.

[0154] After the via opening is formed, the process proceeds to 530. At 530, the process forms an RDL structure on the buffer layer. The RDL structure can be formed as described above. For example, an RDL structure including RDL via contacts, RDL lines, and RDL posts can be formed as described above. Other techniques for forming the RDL structure are also possible.

[0155] At 540, an RDL encapsulation layer is disposed over a buffer layer having an RDL structure. The RDL encapsulation layer covers the RDL lines and RDL posts and fills the gap therebetween. In one embodiment, the RDL encapsulation layer is the same as or similar to the composite buffer layer. The RDL encapsulation layer may be laminated over the wafer surface. Other techniques for forming the RDL encapsulation layer are also possible. The wafer surface is polished to remove excess RDL encapsulation material to expose the surface of the RDL posts. This will make the RDL posts and the RDL encapsulation layer coplanar.

[0156] In one embodiment, at 550, an encapsulation contact is formed. In one embodiment, the encapsulation contact is formed on the RDL posts. The encapsulation contact includes a solder bump or an encapsulation bump. The encapsulation bump may be formed by solder bump technology (SBT). Other types or techniques for forming the encapsulation contact are also possible.

[0157] After forming the encapsulation contact, at 560, the backside of the wafer is polished to thin the wafer to a final wafer thickness. For example, the final wafer thickness may be equal to the final thickness of the diced die without a backside protection layer. Other final wafer thicknesses are also possible. After the backside polishing is completed, proceed to 570.

[0158] At 570, a backside protection layer is formed. For example, the backside protection layer is the same as or similar to the composite buffer layer formed at 510. The backside protection layer is formed by lamination and may include a base backside protection layer having a filler. The process proceeds to 580 where the wafer is diced into individual packages. The process terminates at 590.

[0159] Figure 5c An embodiment of a process flow 500 for processing a wafer is shown, such as a virgin or processed wafer. In particular, the process flow forms a processed wafer having a composite buffer layer. At 505, the process begins. For example, processing a virgin wafer begins. For example, the processed wafer may be a virgin processed wafer from an external supplier.

[0160] For example, a wafer includes an active surface having contact pads. In some embodiments, a passivation layer may be provided with pad openings to expose the contact pads. Alternatively, the passivation layer may not include pad openings. In other embodiments, there is no passivation layer. At 510, the process forms a composite buffer layer on the active surface of the wafer. The composite buffer layer includes a base buffer layer containing fillers or particles. The composite buffer layer is configured to prevent BEOL dielectric breakage and fragmentation during dicing. The composite buffer layer may be formed by compression molding or lamination. Other techniques for forming the composite buffer layer are also possible.

[0161] At 520, the process forms a via opening in the buffer layer to expose the contact pads of the foreign wafer. For example, the via opening includes tapered sidewalls. In one embodiment, the via opening is formed by laser etching. Other techniques for forming the via opening are also possible. After forming the via opening, the process terminates at 530. For example, the processed wafer having the composite buffer layer and the via opening may then be processed in parallel with other processed wafers on a wafer carrier.

[0162] In some embodiments, skipping the step of forming the via opening in the composite buffer layer results in a processed wafer having the composite buffer layer without a via opening. When the wafers on the wafer carrier are subsequently processed in parallel, the via opening may be formed.

[0163] Figure 6a A top view of an embodiment of process 600 for processing wafers in parallel on a wafer carrier or panel is shown; while Figure 6b - 6j A cross-sectional view of an embodiment of process 600 for processing wafers in parallel on a wafer panel is shown. For example, processing wafers in parallel on a wafer panel is described in the U.S. patent application (USSN 16703887) titled "Packaging Method, Panel Assembly, Wafer Package and Chip Package" filed on December 5, 2019, which is incorporated herein by reference for all purposes.

[0164] Reference Figure 6a - 6b, a wafer carrier or panel 670 is provided, which has a panel adhesive layer 674 on its main surface. For example, the panel adhesive layer 674 is disposed on the processing surface or the top surface of the wafer panel 670. The wafer panel 670 should have sufficient rigidity to enable the wafer 601 attached thereto to be processed. Preferably, the wafer panel 670 can be held by magnetic force during processing. In one embodiment, the wafer panel 670 is metallic. Other types of panels are also possible, such as glass. For non-metallic panels, other techniques can be used to hold them firmly during processing, such as by vacuum pressure. In one embodiment, the panel adhesive layer 674 is a heat release adhesive layer. For example, the panel adhesive layer 674 is a heat release tape. Heat treatment of the panel enables the wafer to be separated or released from the panel. Other types of adhesives that can temporarily hold the wafer in place during processing are also possible. The panel adhesive layer 674 can be laminated to the processing surface of the wafer panel 670. Other techniques, such as printing, spraying, and coating, can also be used to form the panel adhesive layer 674 on the processing surface.

[0165] As shown in the figure, the wafer panel 670 can have a rectangular shape. As shown, the wafer panel 670 holds four wafers 601 for parallel processing. For example, the wafer panel 670 holds four 12-inch wafers 601. It is also possible to provide a wafer panel that holds other numbers of wafers. For example, the wafer panel 670 can be designed to hold nine 8-inch wafers. Other configurations of the wafer panel are also possible.

[0166] A wafer cavity mold layer 660 is disposed on the processing surface. For example, the cavity mold layer 660 is disposed on the adhesive layer 674. The cavity mold layer 660 includes a cavity mold opening for accommodating the wafer 601. For example, each cavity mold opening can accommodate one wafer 601. The shape of the cavity mold opening should be substantially the same as the shape of the wafer 601, but slightly larger in size. When the wafer 601 is mounted on the wafer panel 670, a gap 676 is left between the cavity mold layer 660 and the wafer 601. The cavity mold layer 660 can be a glass reinforced epoxy layer, such as FR-4, or a thin metal sheet, such as copper foil. Other types of materials can also be used for the cavity mold layer. The cavity mold layer 660 can be laminated onto the wafer panel 670. For example, the cavity mold layer 660 includes openings before lamination. The wafer panel 670 can also include wafer alignment marks or components (not shown) for aligning the wafer 601 with the openings of the cavity mold layer 660.

[0167] In one embodiment, the wafer 601 is attached to the wafer panel 670. For example, the wafer is attached to the panel adhesive layer 674. A wafer is installed in each cavity mold opening of the cavity mold layer 660, and a gap 676 is left between the cavity mold layer 660 and the wafer 601. Alignment members (not shown) on the wafer panel can assist in mounting the wafer on the wafer panel. For example, the wafer 601 is a processed wafer having a composite buffer layer 650, and the composite buffer layer 650 has a via opening 652, as Figure 5c described. Alternatively, the processed wafer includes a composite buffer layer 650 without a via opening.

[0168] In Figure 6c , a wafer locking member 678 is formed in the gap between the cavity mold opening and the wafer 601. For example, the wafer locking member 678 is formed in the gap between the cavity mold layer 660 and the wafer 601. For example, the wafer locking member 678 can be an adhesive, such as a UV adhesive. For example, the adhesive is dispensed into the gap between the wafer 601 and the cavity mold layer 660. After dispensing, the adhesive is cured and hardened by exposure to UV radiation or heat. For example, this will form a wafer panel assembly having the wafer 601 above the wafer panel 670.

[0169] As shown, the composite buffer layer 650 on the wafer includes a via opening 652 to expose the contact pad. In some embodiments, the composite buffer layer 650 does not include a via opening. In this case, the process forms a via opening 652 in the composite buffer layer 650 to expose the contact pad. For example, laser etching can be used to form the via opening 652. Other techniques for forming the via opening are also possible, such as plasma etching using a resist mask. In some cases, a multiple etching process is also possible, such as plasma etching after high-power laser etching or low-power laser etching after high-power laser etching, with or without a mask. In the case where the passivation layer does not include a pad opening, the process of forming the via opening 652 also includes forming a pad opening to expose the contact pad.

[0170] Referring to Figure 6d, a process of starting to form an RDL structure on a wafer panel assembly. In one embodiment, a seed layer, such as copper-titanium (Cu-Ti), is formed. The seed layer connects the buffer layer to the via openings. An electroplating mask 692 is formed on the assembly. In one embodiment, the electroplating mask is a patterned dry film photoresist. The patterned dry film photoresist is formed using, for example, LDI, thereby forming openings corresponding to the RDL lines. The openings also expose the via openings in the buffer layer of the assembly. An electroplating process is performed to form an RDL layer, such as copper (Cu) or a copper alloy, filling the mask openings, including the via openings. This forms the RDL line 656 coupled to the pad through the RDL via contact 654.

[0171] In Figure 6e , the RDL stud 658 is formed on the RDL line 656. To form the RDL stud 658, a dry film photoresist 694 is laminated on the RDL line 656 and the electroplating mask 692. The photoresist film is patterned, for example, using LDI to form stud openings, exposing the RDL line 656 at the location where the RDL stud will be formed. For example, the patterned photoresist layer 694 can be an electroplating mask for selectively forming the RDL stud 658 on the RDL line 656. An electroplating process is used to form the RDL stud 658 in the stud openings. After forming the RDL stud 658, the electroplating mask 692 and the dry film photoresist 694 are removed. For the die of the wafer, the RDL via contact 654, the RDL line 656, and the RDL stud 658 form the RDL structure 653.

[0172] Referring to Figure 6f , an RDL encapsulation layer 646 is formed on the wafer panel assembly, covering the RDL structure 653 located above the composite buffer layer 650. For example, the RDL encapsulation layer 646 covers the RDL line 656 and the RDL stud 658 and fills the gap between them. The RDL encapsulation layer 646 is, for example, a dielectric layer similar to the composite buffer layer 650. For example, the RDL encapsulation layer includes a base RDL encapsulation layer with a filler. In one embodiment, the RDL encapsulation layer is laminated onto the wafer surface. Other techniques for forming the RDL encapsulation layer are also possible. As shown, the top surface (exposed surface) of the RDL encapsulation layer is disposed above the RDL structure 653.

[0173] As Figure 6gAs shown, the wafer panel assembly having the wafer 601 is released from the wafer panel and the panel adhesive layer. In one embodiment, the wafer panel assembly having the cavity mold layer, the wafer locking member, and the wafer is released from the adhesion tape on the wafer panel. To release the wafer panel assembly, heat treatment is required, for example, below 200 degrees Celsius (°C). After separation, the wafer panel assembly is divided into individual wafers 601. For example, the wafer panel assembly is laser cut to divide the wafer panel assembly into individual wafers. The laser can cut the glue (locking member) to release the wafer.

[0174] Referring to Figure 6h , the excess RDL encapsulation layer 646 above the RDL structure 653 is removed. In one embodiment, the excess RDL encapsulation layer is removed by grinding. A flat top surface of the RDL encapsulation layer 646 is formed to expose the RDL posts 658. For example, the top surface of the RDL posts 658 and the top surface of the RDL encapsulation layer 646 are coplanar.

[0175] In one embodiment, as Figure 6i shown, the package contacts 679 are formed on the exposed surfaces of the RDL posts 658. The package contacts 679 may include solder bumps or package bumps. The package bumps can be formed by solder bump technology (SBT). For example, solder bumps can be used for ball grid array (BGA) packaging. Other types of package contacts are also possible. For example, the package contacts can be metal-plated contacts, such as tin-plated contacts. The electroplated contacts can be formed on the RDL posts by, for example, matt plating process. Other techniques for forming electroplated contacts are also possible.

[0176] After forming the package contacts 679, the backside of the wafer 601 is ground. For example, the backside of the wafer is ground to reduce the thickness of the wafer. Removing a portion of the wafer can make the wafer have the final wafer thickness T D .

[0177] In one embodiment, as Figure 6j shown, a backside protection layer 681 is formed on the non-active surface of the wafer. For example, the backside protection layer 681 can be the same as or similar to the composite buffer layer 650. The backside protection layer may include a substrate backside protection layer having fillers and is formed by lamination. Other types or techniques for forming the backside protection layer are also possible. The thickness of the backside protection layer can be, for example, about 25–200 micrometers (μm), about 25–150 micrometers (μm), or about 50–120 micrometers (μm). Other thicknesses of the backside protection layer are also possible.

[0178] After forming the backside protection layer, the wafer is cut to form individual packages. The backside protection layer prevents or reduces debris generation on the backside of the wafer when cutting the wafer, asFigure 2a as shown. For example, the package is a fan-in type package.

[0179] Figure 7 An embodiment of a process flow 700 for processing wafers is shown, such as foreign or processed wafers. In particular, the process flow can produce individual die having a composite buffer layer. The die are subsequently processed to form packages having a molding layer. For example, the die are processed to form 6-sided or 5-sided fan-in or fan-out packages. At 705, the process begins. For example, processing of a foreign wafer is started. For example, the processed wafer can be a foreign processed wafer from an external supplier.

[0180] For example, the wafer includes an active surface having contact pads. In some embodiments, a passivation layer may be provided with pad openings to expose the contact pads. At 710, the process forms a composite buffer layer on the active surface of the wafer. For example, a composite buffer layer is formed on the wafer, covering the contact pads; or covering the top of the BEOL dielectric, the contact pads, and the passivation layer. The composite buffer layer includes a base buffer layer containing fillers or particles, as described above. The composite buffer layer can prevent or reduce breakage and fragmentation of the BEOL dielectric during the dicing process. The composite buffer layer can be formed by compression molding or lamination. Other techniques for forming the composite buffer layer are also possible.

[0181] At 720, the process forms a via opening in the buffer layer to expose the contact pads of the foreign wafer. For example, the via opening includes tapered sidewalls. In one embodiment, the via opening is formed by laser etching. Other techniques for forming the via opening are also possible, such as a multiple etching process.

[0182] After forming the via opening, the process proceeds to 730. At 730, the process continues with DBG processing on the wafer. For example, the wafer is partially diced. In one embodiment, the wafer is diced along a dicing line until a depth is approximately equal to the final thickness of an individual die. In some cases, the depth is slightly deeper than the final thickness of an individual die to account for process variations. It can be approximately 10–30% or approximately 10–20% deeper than the final thickness of an individual die.

[0183] After partially dicing the wafer, the process continues to 740 for backside wafer grinding. For example, the backside of the wafer is ground to thin the wafer to the final die thickness without a composite backside protection layer. The grinding process divides the wafer into individual die. For example, an individual die can be similar to the die described in Figure 4f In some cases, the composite buffer layer may not include a via opening. In such a case, the die are similar to those in Figure 4dis similar to the grains described in. After segmentation, the process terminates at 750.

[0184] Figure 8a FIG. shows a top view of an embodiment of process 800 for processing chips in parallel on a chip carrier or panel; while Figure 8b - 8j FIG. shows a cross-sectional view of an embodiment of process 800 for processing chips in parallel on a chip carrier or panel. For example, the parallel processing of chips on a chip panel is described in the U.S. patent application (USSN 17 / 346,310) titled "Method of Packaging Chip and Chip Package Structure" filed on June 14, 2021, which is incorporated herein by reference for all purposes.

[0185] Reference Figure 8a - 8b , shows a chip carrier or panel 801. In one embodiment, the chip panel is configured to accommodate a plurality of chips 810 to be processed. For example, the chips can be processed with a composite buffer layer 850. The composite buffer layer can include via openings as described in Figure 4f or without via openings as described in Figure 4d . As shown, the composite buffer layer 850 includes via openings 852. For example, the process for processing a wafer to produce a single chip with a composite buffer layer is described in Figure 7 . Other processes can also be used to process wafers to produce single chips with a composite buffer layer.

[0186] The chip panel 801 should be rigid enough to be able to process the chips 810 attached thereto. In one embodiment, the chip panel can be made of a material with a low coefficient of thermal expansion (CTE). For example, the CTE of the panel can be equal to or less than 8 ppm / K. For example, low thermal expansion coefficient materials can include Alloy 42 (thermal expansion coefficient 3 - 4.5 ppm / K) or Alloy 46 (thermal expansion coefficient 7 - 8 ppm / K). Preferably, the chip panel 801 can be magnetically fixed, such as a metal panel, so that the panel can be firmly fixed. Other types of panels are also possible, such as glass.

[0187] The panel adhesion layer 805 is formed on its main surface. For example, the panel adhesion layer 805 is disposed on the processing surface or the top surface of the die panel 801. The adhesion layer 805 can be used to hold the dies located on the processing surface of the die panel. In one embodiment, the panel adhesion layer 805 is a heat release adhesion layer. For example, the adhesion layer is a heat release tape. After the panel undergoes heat treatment, it enables the die panel assembly or the reconstructed wafer 860 to be separated or released from the die panel 801. During the processing of forming the die panel assembly, other types of adhesives that can temporarily hold the dies in place are also possible. The adhesion layer 805 can be laminated to the processing surface of the die panel. Other techniques, such as printing or spray coating, can also be used to form the adhesion layer on the processing surface.

[0188] As shown in the figure, the die panel 801 is a rectangular panel. Other shapes are also possible. The dies 810 are attached to the die panel 801. In one embodiment, with the assistance of the adhesion layer, the dies 801 are bonded face - down on the processing surface of the die panel 801. For example, the die active surface of the die 810 faces the die panel 801, while the die non - active surface 812 is away from the die panel. A die bonder can be used to pick up and bond the dies on the die panel. Alignment marks can be included to assist in accurately positioning the dies on the die panel. For example, the die region for bonding the dies can include local alignment. Other techniques for aligning the dies to the die region are also possible.

[0189] In one embodiment, the dies 810 are arranged in a die matrix having rows and columns of dies 810. In one embodiment, the dies 810 are divided into four die modules or die matrices 806 1-4 . The dies 810 on the die panel 801 can have other configurations. For example, the dies 810 on the panel 801 can be configured with other numbers of modules, including 1 module. Preferably, when the panel 801 includes more than 1 module, the number of modules is even. Dividing the dies into blocks can process more dies simultaneously while reducing the position error of the dies. This improves the accuracy of the die positions during processing.

[0190] After the 810 plane of the die is face - down mounted on the die panel 801, a molding process can be performed to encapsulate the die with a mold compound or a mold layer 890. As shown in the figure, the mold layer 890 also fills the gaps between the dies and covers the inactive surface 812 of the die 810 while encapsulating the die 810. The molding process can be, for example, a compression molding process. Other types of molding processes are also possible, such as a high - temperature molding process. The die 810 with the mold layer 890 forms a die panel assembly or a reconstructed wafer 860. The exposed surface 892 of the mold layer 890 can be referred to as an inactive mold layer or the bottom surface of the mold layer. The opposite surface of the mold layer can be referred to as the active surface of the mold layer or the top surface 891 of the mold layer.

[0191] After the die panel assembly 860 is formed, it is separated from the die panel 801. For example, the die panel with the die panel assembly is heat - treated, causing the adhesive layer to lose its adhesive properties. The die panel 801 can be separated from the die panel assembly 860.

[0192] In some embodiments, before the die panel assembly 860 is released from the die panel 801, a grinding process is performed to reduce the height of the mold layer 890 to a final height. In one embodiment, as shown in the figure, the final height of the mold layer is above the inactive surface 812 of the die 810. In other embodiments, the grinding process removes the excess mold layer 890 above the inactive surface 812 of the die 810. For example, the grinding process removes the excess mold material, exposing the inactive surface 812 of the die 810.

[0193] In Figure 8c the die panel assembly 860 is mounted on the component carrier 802. As shown in the figure, the inactive surface 892 of the mold layer is mounted on the component carrier 802. A component carrier adhesive layer 806 is formed on the processing surface of the component carrier 802 to assist in the temporary mounting of the die panel assembly 860. The carrier adhesive layer 806 is, for example, a thermally - separable adhesive layer, similar to the adhesive layer for attaching the die to the die panel. The active surface 891 of the mold layer and the active surface of the die 810 are exposed or face away from the component carrier 802.

[0194] When the composite buffer layer 850 does not include a through hole, a through hole is formed in the composite buffer layer 850. For example, a laser etching can be used to form a through hole in the composite buffer layer 850 to expose the die contact pad. Other techniques can also be used, such as a multiple etching technique. The multiple etching technique can include high-power laser etching followed by low-power laser etching. In other embodiments, the multiple etching technique can include high-power laser etching followed by plasma etching. In the case where the passivation layer does not include a pad opening, the process of forming the through hole further includes forming a pad opening in the passivation layer.

[0195] As Figure 8d to 8e shown, the process continues to form RDL lines 876 and RDL via contacts 874. The RDL lines 876 and RDL via contacts 874 can be formed by an electroplating process as described above. For example, the electroplating process includes forming a seed layer on the buffer layer 850, laminating a dry film photoresist 894, and patterning it by LDI to form openings corresponding to the RDL lines and via openings. The electroplating process forms a conductive layer that fills the mask opening and the via opening, forms the RDL lines 876, and couples to the contact pad through the RDL via contacts 874 in the via opening. As Figure 8e shown, the RDL lines 876 are patterned and disposed within the die area. In one embodiment, the RDL lines 876 are used for fan-in packaging. Fan-out packaging can also be formed. In this case, the RDL lines 876 can extend beyond the die area but still remain within the die package area.

[0196] In one embodiment, RDL posts 878 are formed on the RDL lines 876, as Figure 8f shown. The RDL posts 878 are formed by laminating a dry film photoresist 896 on the RDL lines 876 and patterning the dry film photoresist 894. The photoresist film 894 is patterned by, for example, LDI to form openings, and the RDL lines 876 can be exposed at the positions where the RDL posts are about to be formed. An electroplating process is used to form the RDL posts 878 in the post openings, and then the patterned photoresist films 894, 896 are removed. The RDL via contacts 874, RDL lines 876, and posts 878 form the RDL structure 873 of the die.

[0197] Referring to Figure 8g, an RDL encapsulation layer 846 is formed on the die panel assembly 860. As shown, the RDL encapsulation layer 846 covers the RDL structure 873 above the composite buffer layer 850. For example, the RDL encapsulation layer 846 covers the RDL lines 876 and the RDL pillars 878 and fills the gap therebetween. The RDL encapsulation layer 846 can be similar to the dielectric layer of the composite buffer layer 850. For example, the RDL encapsulation layer 846 includes a base RDL encapsulation layer with fillers. The encapsulation layer can be an epoxy mold compound layer. In one embodiment, the RDL encapsulation layer may include 20–60 micrometers (um) of fillers. Other sizes of fillers are also possible.

[0198] In one embodiment, the RDL encapsulation layer 846 is laminated onto the wafer surface. Other techniques for forming the RDL encapsulation layer 846 are also possible. For example, the RDL encapsulation layer 846 can be formed by film molding. Other techniques for forming the RDL encapsulation layer are also possible. As shown, the top surface (exposed surface) of the RDL encapsulation layer 846 is disposed above the RDL structure 873.

[0199] The die panel assembly 860 includes a module or matrix of multiple dies and can be released from the die panel. For example, the die panel assembly is heat-treated to release the die panel assembly 860 from the component carrier 802. Then the die panel assembly 860 is processed to cut it into individual modules of dies 810. For example, the die panel assembly 860 is cut into individual block panel assemblies. Laser cutting can be used to divide the die panel assembly into block panel assemblies. Alternatively, the die panel assembly 860 can be cut by a saw blade. Other techniques for dividing the die panel assembly 860 into block panel assemblies are also possible. Then the block panel assemblies are attached to a block panel carrier using a block panel adhesion layer such as a thermal separation adhesive layer. In the case where the die panel assembly includes only one module, it is not necessary to release the die panel assembly 860 from the component carrier 802.

[0200] As Figure 8hAs shown, the processed die panel assembly 860 has the excess RDL encapsulation layer 846 removed above the RDL structure 873. For example, when the panel assembly is cut into block assemblies, the die panel assembly 860 can be a block panel assembly. In one embodiment, the excess RDL encapsulation layer 846 is removed by grinding. This forms a flat top surface of the RDL encapsulation layer 846, exposing the RDL pillars 878. For example, the top surface of the RDL pillars 878 and the top surface of the RDL encapsulation layer 846 are coplanar.

[0201] In one embodiment, as Figure 8i shown, the encapsulation contacts 879 are formed on the exposed surfaces of the RDL pillars 878. The encapsulation contacts 879 can include solder bumps or encapsulation bumps. The encapsulation bumps can be formed by solder bump technology (SBT). For example, solder bumps can be used for chip-scale packaging (CSP). Other types of encapsulation contacts can also be formed.

[0202] After the encapsulation contacts 879 are formed, the die panel assembly 860 is released from the panel carrier. As Figure 8j shown, the die panel assembly is segmented to produce individual packages 811. For example, the individual package is a chip-scale package (CSP) with 6-sided wall protection.

[0203] In an alternative embodiment, the process can be configured to form a fan-out package. For example, as Figure 8d described, the RDL layer can be patterned to form RDL lines 876 that can extend beyond the area of the die 810. The process can continue as described above.

[0204] In one embodiment, encapsulation contacts can be formed as Figure 8i described. For example, the process forms encapsulation bumps for ball grid array (BGA) packaging. Alternatively, the encapsulation contacts can include electroplated contacts on the pillar surfaces. The electroplated contacts can be formed by matt tin plating. For example, electroplated contacts are used to form LGA or QFN packages. After the encapsulation contacts are formed, the process continues by releasing the die panel assembly from the panel carrier and segmenting the die panel assembly to produce individual packages 811. As described above, the process forms a 6-sided protected fan-out package. A 6-sided protected fan-in package can also be formed.

[0205] As described above, the RDL structure includes a line level. For example, the RDL structure includes a rewiring level that includes RDL lines 876. An RDL structure having multiple rewiring levels may also be formed.

[0206] Figure 9 An embodiment of a process flow 900 for forming an RDL structure is shown. This process flow can be applied to a single wafer on a carrier, multiple wafers on a wafer carrier, such as Figure 6a - 6j ; or a die panel assembly, such as Figure 8a - 8j . The process begins at 910. For example, the process begins to form an RDL structure.

[0207] In the case where the composite buffer layer includes a via opening, the process continues to 920 to form an RDL layer. If the composite buffer layer does not include a via opening, a via opening is formed in the composite buffer layer to expose the contact pads of the die. The via opening can be formed by laser etching (with or without a mask) or plasma etching using a resist mask. In other embodiments, a multiple etch process can be used to form the via opening. The via opening exposes the contact pads of the die. After forming the via opening, the process proceeds to 920.

[0208] At 920, a rewiring layer of the RDL structure is formed. For example, the first rewiring layer (i = 1) of the RDL structure is formed. The RDL structure can have x rewiring layers, where x is an integer greater than or equal to 1. Generally, the RDL structure can have 1 - 5 rewiring layers.

[0209] The rewiring layer can be, for example, a copper (Cu) or copper alloy layer. In one embodiment, the rewiring layer is formed by electroplating. Before electroplating, a seed layer such as titanium copper (Ti - Cu) can be formed on the panel assembly to form a lining for the composite buffer layer and the via opening. The seed layer can be formed by sputtering. After forming the seed layer, a patterned mask layer can be formed. For example, a dry film photoresist is formed by LDI lamination and patterning to form openings corresponding to the RDL lines, including the via opening. For example, the patterned resist film can be the electroplating mask for the i-th rewiring layer.

[0210] At 930, a conductive rewiring layer such as copper (Cu) or copper alloy is electroplated to fill the mask openings and via openings in the buffer layer. Through the RDL via contacts in the via openings of the composite buffer layer of the die, RDL lines are formed that are coupled to the contact pads of the die. For example, the RDL conductive line is the conductive line of the first rewiring level (x = 1). The RDL lines can be fan - in or fan - out RDL lines. After forming the RDL lines, the process proceeds to 940.

[0211] At 940, the process can determine whether more redistribution layers need to be formed. If more redistribution layers need to be formed, proceed to 950. For example, if i≠x, proceed to 950. On the other hand, if i = x, it indicates that no more redistribution layers are needed, and the process proceeds to 955.

[0212] At 950, when there are more redistribution layers or levels, remove the electroplating mask for the i-th redistribution layer. Form an RDL encapsulation layer. For example, form the i-th encapsulation layer corresponding to the i-th redistribution layer. For example, the encapsulation layer can be a dielectric layer similar to the composite buffer layer. For example, the RDL encapsulation layer includes a base encapsulation layer with fillers. The filler size of the RDL encapsulation layer can be 20–60 micrometers (um). Other filler sizes are also possible. Other types of RDL encapsulation layers are also possible, such as pre-formed RDL encapsulation layers or epoxy mold compound layers. The RDL encapsulation layer covers the conductive lines of the redistribution layer. The thickness of the encapsulation layer takes into account covering the RDL conductive lines and the next redistribution layer (i = i + 1) where the RDL through-hole contacts will be subsequently formed.

[0213] In one embodiment, the RDL encapsulation layer is laminated onto the wafer surface. Other techniques for forming the RDL encapsulation layer are also possible. For example, the RDL encapsulation layer can be formed by thin-film molding.

[0214] At 960, form a via opening in the RDL encapsulation layer, exposing a portion of the conductive line below at the location where the via contact will be formed. The via opening can be formed by laser drilling. For example, the laser used is configured to drill a non-photoimageable layer. Other techniques for forming the via opening are also possible.

[0215] At 970, the next (i = i+1) redistribution layer of the RDL structure is formed. For example, the redistribution layer can be a copper (Cu) or copper alloy layer formed by electroplating. Other types of conductive redistribution layers are also possible. In one embodiment, a seed layer such as copper titanium (Cu-Ti) is formed to line the encapsulation layer and the via openings. A patterned mask layer is formed on the seed layer. For example, a dry film photoresist is laminated and patterned through an LDI to form openings corresponding to the RDL lines, including the via openings. For example, the patterned photoresist film can serve as the electroplating mask for the i+1th redistribution layer. An electroplating process is performed to form a conductive redistribution layer, such as copper or copper alloy. The redistribution layer fills the mask openings and the via openings of the encapsulation layer. The (i+1)th RDL line coupled to the ith RDL line is formed through the RDL via contacts in the via openings of the encapsulation layer. The process returns to 940 to determine whether more redistribution layers need to be formed. The process continues and repeats until all the redistribution layers are formed. For example, i = x, where x is the number of redistribution layers or the number of levels of the RDL structure.

[0216] If no more redistribution layers need to be formed, the process proceeds to 955 to form the RDL pillars. In one embodiment, the RDL pillars are selectively formed by electroplating. To form the RDL pillars, a patterned mask, such as a patterned dry film photoresist, is used. For example, the dry film photoresist is laminated and patterned through an LDI to form openings that expose the RDL lines at the locations where the RDL pillars are to be formed. An electroplating process is used to form the RDL pillars in the pillar openings, and then the electroplating mask is removed.

[0217] The process proceeds to 965 to form the RDL encapsulation layer. The encapsulation layer is similar to that described in 950. For example, the RDL encapsulation layer is a composite RDL encapsulation layer with fillers. Other types of RDL encapsulation layers are also possible. The RDL encapsulation layer covers the RDL lines and the pillars.

[0218] In one embodiment, the RDL encapsulation layer is laminated onto the wafer surface. Other techniques for forming the RDL encapsulation layer are also possible. For example, the RDL encapsulation layer can be formed by thin film molding. Other techniques for forming the RDL encapsulation layer are also possible.

[0219] After the final RDL encapsulation layer is formed, the carrier is released from the wafer assembly or the die panel assembly. After the carrier is released, the wafers are diced in the case of multiple wafers. In one embodiment, when the panel assembly has multiple modules, it can be diced into individual modules.

[0220] The process proceeds to 975. At 975, the final RDL encapsulation layer is polished to remove excess encapsulation material, thereby exposing the conductive RDL pillars. At 980, encapsulation contacts are formed on the exposed RDL pillars. The encapsulation contacts can be solder bumps for CSP packages or electroplated contacts for LGA / QFN packages. After forming the encapsulation contacts, the process terminates at 990.

[0221] Depending on whether the RDL structure is formed on a wafer or on a panel assembly, different downstream processes can be carried out. For example, in the case of a wafer, the backside of the wafer can be polished to thin the wafer. A backside protection layer can be formed on the non-active surface of the wafer, and then the wafer is diced to form individual packages. In the case of a panel assembly, it can be divided to form individual packages.

[0222] Experimental data

[0223] Experiments were conducted to test the effectiveness of the composite buffer layer in preventing cracks and chipping during wafer dicing. The experiments were carried out on two 12-inch wafers with low-k BEOL dielectrics, one with a composite buffer layer and the other without. Wafer 1 (without the composite buffer layer) and Wafer 2 (with the composite buffer layer) are described in Table 1 below:

[0224] Table 1

[0225]

[0226] The composite buffer layer is configured according to Table 2 below:

[0227] Table 2

[0228]

[0229]

[0230] Figure 10a Images of Wafer 1 and Wafer 2 at the X and Y saw streets before dicing are shown. Wafer 1 is directly sawed from the front side, and Wafer 2 is diced before grind. Figure 10b Images of Wafer 1 and Wafer 2 on the X and Y saw streets after dicing are shown. For Wafer 1, debris with a size exceeding 50 microns was observed. On the other hand, no debris was observed on Wafer 2. For example, debris less than 3 microns was observed, which is negligible. Figure 10cImages of the back sides of wafer 1 and wafer 2 on the X and Y saw streets are shown. For wafer 1, debris over 80 microns was observed. For wafer 2, debris less than 5 microns was observed, which is negligible. Providing a composite buffer layer on the back side of the wafer can further reduce the debris on the back side of the wafer. The experimental results show that the composite buffer layer of the present invention can effectively reduce or prevent chipping caused by the wafer dicing process.

[0231] Another experiment was conducted using wafers similar to wafer 2 in Table 1. However, 3 composite buffer layers with different Young's moduli and fracture strengths were used. Composite buffer layer 1, composite buffer layer 2, and composite buffer layer 3 are described in Table 3 below:

[0232] Table 3

[0233]

[0234] Dice before grind was used to cut the wafers. Debris on the saw streets was observed on the wafers with composite buffer layer 1. As for composite buffer layer 2 and composite buffer layer 3, no debris was observed. The experimental results show that a composite buffer layer with a higher Young's modulus (e.g., 10 - 25 GPa) and a higher fracture strength (e.g., 50 - 100 MPa) can effectively reduce debris generated during wafer dicing.

[0235] Without departing from the spirit or essential characteristics of the present disclosure, the present disclosure may be embodied in other specific forms. Therefore, the foregoing embodiments are to be considered in all respects as illustrative and not restrictive of the invention described herein. Accordingly, the scope of the present invention is determined by the appended claims rather than the foregoing description, and all changes within the meaning and range of equivalents of the claims are intended to be embraced therein.

Claims

1. A semiconductor package, comprising: A die, having an active surface and an inactive surface, wherein the active surface includes die pads on a BEOL dielectric in a back end; A buffer layer, disposed on the active surface of the die, wherein the buffer layer includes a damping composition for preventing the BEOL dielectric in the back end from cracking during wafer dicing; A plurality of via openings, located in the buffer layer for exposing the die pads; And A plurality of via contacts, disposed on the via openings for providing electrical connection to the die pads, Wherein the Young's modulus of the buffer layer is 10,000 - 25,000 Mpa, and the fracture strength of the buffer layer is 50 - 150 Mpa, The buffer layer includes a composite buffer layer, and the composite buffer layer further includes: a base buffer layer; and fillers disposed within the base buffer layer, The size range of the fillers is from 0.5 microns to 1 / 3 of the width of the saw blade used in the wafer dicing process.

2. The semiconductor package according to claim 1, further comprising a redistribution RDL structure, which further includes: A plurality of via contacts; A plurality of patterned wires, connected to the plurality of via contacts; And A redistribution RDL encapsulation layer, covering the redistribution RDL structure, wherein the redistribution RDL structure is disposed within the area of the die.

3. The semiconductor package according to claim 2, wherein the semiconductor package includes a package area with a size equal to the area of the die.

4. The semiconductor package according to claim 2, wherein the semiconductor package includes a backside protection layer, disposed on the inactive surface of the die, and the backside protection layer can prevent the die from cracking.

5. The semiconductor package according to claim 2, wherein the semiconductor package includes: An encapsulation layer, covering and surrounding the die; And The redistribution RDL encapsulation layer has the same size as the encapsulation layer.

6. The semiconductor package according to claim 2, wherein the semiconductor package includes: An encapsulation layer, covering and surrounding the die, having a top encapsulation layer surface flush with the inactive surface of the die; And The redistribution RDL encapsulation layer has the same area as the encapsulation layer.

7. The semiconductor package according to claim 1, further comprising a redistribution RDL structure, which further includes: A plurality of via contacts; A plurality of patterned wires, connected to the plurality of via contacts; And A redistribution RDL encapsulation layer, covering the redistribution RDL structure, wherein the redistribution RDL structure is disposed outside the area of the die.

8. The semiconductor package according to claim 7, wherein the semiconductor package includes: An encapsulation layer, covering and surrounding the die; And The redistribution RDL encapsulation layer has the same area as the encapsulation layer.

9. The semiconductor package according to claim 2, wherein the semiconductor package includes: An encapsulation layer, covering and surrounding the die, having a top encapsulation layer surface flush with the inactive surface of the die; And The redistribution RDL encapsulation layer has the same area as the encapsulation layer.

10. The semiconductor package as claimed in claim 1, wherein the base buffer layer comprises a polymer-based base buffer layer.

11. The semiconductor package as claimed in claim 1, wherein the filler in the composite buffer layer comprises an organic filler, an inorganic filler, or a combination thereof.

12. The semiconductor package as claimed in claim 1, wherein the thickness of the composite buffer layer is 10 - 100 micrometers.

13. The semiconductor package as claimed in claim 1, wherein the composite buffer layer comprises a prefabricated composite buffer layer.

14. A semiconductor package, comprising: a die having an active surface and an inactive surface, wherein the active surface comprises die pads on a back-end BEOL dielectric; a buffer layer disposed on the active surface of the die for preventing the back-end BEOL dielectric from cracking during wafer dicing; a plurality of via openings located in the buffer layer for exposing the die pads; and a plurality of via contacts disposed on the via openings for providing electrical connection to the die pads, wherein the buffer layer has a Young's modulus of 10,000 - 25,000 Mpa and a fracture strength of 50 - 150 Mpa, the buffer layer comprises a composite buffer layer, and the composite buffer layer further comprises: a base buffer layer; and a filler disposed within the base buffer layer, the size range of the filler is from 0.5 micrometers to 1 / 3 of the width of the saw blade used in the wafer dicing process.

15. A method of processing a semiconductor wafer, comprising: providing a semiconductor wafer having an active surface, wherein the active surface is processed to have a plurality of dies, and the top die surface of the plurality of dies comprises die pads on a back-end BEOL dielectric; and forming a buffer layer on the semiconductor wafer to cover the top die surface, wherein the buffer layer comprises a vibration damping composition for preventing the back-end BEOL dielectric from cracking during wafer dicing, wherein the buffer layer has a Young's modulus of 10,000 - 25,000 Mpa and a fracture strength of 50 - 150 Mpa, the buffer layer comprises a composite buffer layer, and the composite buffer layer further comprises: a base buffer layer; and a filler disposed within the base buffer layer, the size range of the filler is from 0.5 micrometers to 1 / 3 of the width of the saw blade used in the wafer dicing process.

16. The method as claimed in claim 15, wherein the fracture strength is 50 - 100 MPa.

Images