Semiconductor device

Abstract

In a semiconductor device having an IGBT region (1a) having an IGBT element and an FWD region (1b) having an FWD element formed on a common semiconductor substrate (10), a carrier-inhibiting region (19) of a second conductivity type having a lower impurity concentration than a contact region (18a) is formed to be exposed from one surface (10a) of the semiconductor substrate (10) in the IGBT region (1a). Furthermore, a first electrode (21) is Schottky-joined to the carrier-inhibiting region (19).

Description

[0001] Cross-referencing of related applications

[0002] This application is based on Japanese Patent Application No. 2020-41275, filed on March 10, 2020, the contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device having an insulated gate bipolar transistor (hereinafter referred to as IGBT) element and a freewheeling diode (hereinafter referred to as FWD) element having an insulated gate structure formed on a common semiconductor substrate. Background Technology

[0004] Conventionally, as switching elements used, for example in inverters, semiconductor devices have been proposed in which an IGBT region having an IGBT element and an FWD region having an FWD element are formed on a common semiconductor substrate (see, for example, Patent Document 1).

[0005] Specifically, in this semiconductor device, when N is constituting － A base layer is formed on one side of a semiconductor substrate with a drift layer, and multiple trenches are formed through the base layer. Each trench extends along a direction that is the length direction of the semiconductor substrate. Furthermore, a gate insulating film and a gate electrode are sequentially formed in each trench.

[0006] Additionally, N is formed on the surface of the base layer in a manner that connects with the trench. + The emitter region is of the type [type], and has a P [type] impurity concentration higher than that of the base layer. + A type of contact area. A P-type contact area is formed on the other side of the semiconductor substrate. + Type-type collector layer and N + The cathode layer is of this type. Furthermore, in this semiconductor device, on one side of the semiconductor substrate, a trench contact is formed between adjacent trenches, extending through the emitter region and the contact region to reach the base layer.

[0007] Furthermore, on one side of the semiconductor substrate, an upper electrode is embedded in a trench contact in a manner that electrically connects to the emitter region, the contact region, and the base layer. On the other side of the semiconductor substrate, a lower electrode is formed that is electrically connected to the collector layer and the cathode layer.

[0008] In this semiconductor device, on the other side of the semiconductor substrate, the region where the collector layer is formed is designated as the IGBT region, and the region where the cathode layer is formed is designated as the FWD region. Furthermore, in the FWD region, by employing the above structure, an FWD element with a PN junction is constructed using an N-type cathode layer, a drift layer, and a P-type base layer.

[0009] Furthermore, in the aforementioned semiconductor device, when the FWD element is in the on state and operates as a diode, compared to the case where the upper electrode is only connected to the emitter region and the contact region, since the upper electrode is also connected to the base layer, hole injection in the IGBT region is suppressed. Therefore, when the FWD element is in the recovery state, recovery current can be suppressed, thereby reducing recovery losses.

[0010] Existing technical documents

[0011] Patent documents

[0012] Patent Document 1: Japanese Patent No. 5034461 Summary of the Invention

[0013] However, in the aforementioned semiconductor device, since trench contacts are formed between adjacent trenches, it is difficult to narrow the spacing between adjacent trenches. Therefore, in the aforementioned semiconductor device, there is a possibility that the on-state voltage may rise when the IGBT element operates.

[0014] The purpose of this disclosure is to provide a semiconductor device capable of reducing recovery loss and narrowing the spacing between adjacent trenches.

[0015] According to one aspect of this disclosure, a semiconductor device comprises: a semiconductor substrate having an IGBT region and an FWD region, and including a drift layer of a first conductivity type, a base layer of a second conductivity type formed on the drift layer, a collector layer of the second conductivity type formed in the drift layer in the IGBT region on a side opposite to the base layer side, and a cathode layer of the first conductivity type formed in the drift layer in the FWD region on a side opposite to the base layer side, wherein the semiconductor substrate has one side facing the base layer and the other side facing the collector layer and cathode layer; and a gate insulating film formed in the IGBT region through the base layer to reach... The IGBT includes a drift layer and the walls of multiple trenches extending in one direction along its length; a gate electrode disposed on a gate insulating film; an emitter region of a first conductivity type, which is the surface portion of the base layer in the IGBT region and is formed to connect with the trenches, having a higher impurity concentration than the drift layer; a contact region of a second conductivity type, which is formed on the surface portion of the base layer in the IGBT region, having a higher impurity concentration than the base layer; a first electrode disposed on one side of the semiconductor substrate and electrically connected to the base layer and the emitter region; and a second electrode disposed on the other side of the semiconductor substrate and electrically connected to the collector layer and the cathode layer. Furthermore, a carrier suppression region of a second conductivity type, exposed from one side of the semiconductor substrate and having a lower impurity concentration than the contact region, is formed in the IGBT region, and the first electrode is Schottky-bonded to the carrier suppression region.

[0016] Accordingly, a carrier suppression region is formed that exposes one side of the semiconductor substrate, and the first electrode is Schottky-bonded to the carrier suppression region. Therefore, when the FWD element is in the on state, carrier injection from the first electrode into the surface portion of the IGBT region can be suppressed. Consequently, recovery current and recovery losses can be reduced.

[0017] Furthermore, since the carrier suppression region is exposed from one side of the semiconductor substrate, it is not necessary to form trench contacts to connect the carrier suppression region to the upper electrode. Therefore, the spacing between adjacent trenches can be narrowed, and the high on-state voltage of the IGBT element can be suppressed.

[0018] In addition, the bracketed reference numerals used to indicate each constituent element, etc., represent an example of the correspondence between the constituent element, etc., and the specific constituent elements, etc., described in the embodiments described later. Attached Figure Description

[0019] Figure 1 This is a perspective cross-sectional view of the semiconductor device in the first embodiment.

[0020] Figure 2 It is a top view of the area between adjacent trenches on one side of a semiconductor substrate.

[0021] Figure 3A This is the energy band diagram of the first contact area and the upper electrode.

[0022] Figure 3B This is the band structure diagram of the hole suppression region and the upper electrode.

[0023] Figure 4A This is a graph showing the simulation results related to electron concentration in a semiconductor device where the FWD element is in the on state without a hole suppression region.

[0024] Figure 4B This is a graph showing the simulation results related to electron concentration in a semiconductor device with the FWD element in the on state when the length of the hole suppression region is set to 0.7 μm.

[0025] Figure 4C This is a graph showing the simulation results related to electron concentration in a semiconductor device with the FWD element in the on state, where the length of the hole suppression region is set to the limit.

[0026] Figure 5 This is a graph showing the electron concentration when the FWD element is in the on state.

[0027] Figure 6A This is a graph showing the simulation results related to recovery loss at 25°C.

[0028] Figure 6BThis is a graph showing the simulation results related to the recovery loss at 150°C.

[0029] Figure 7 This is a circuit diagram of the IGBT element in the first embodiment.

[0030] Figure 8 This is a graph showing the simulation results related to the relationship between the length of the hole suppression region and the collector current.

[0031] Figure 9 This is a graph showing the simulation results relating the length of the hole suppression region to the base-emitter voltage of the parasitic NPN transistor.

[0032] Figure 10 This is a graph showing the simulation results related to the relationship between the height of the Schottky barrier of the upper electrode and the recovery loss.

[0033] Figure 11 This is a perspective cross-sectional view of the semiconductor device in the second embodiment.

[0034] Figure 12 This is a perspective cross-sectional view of the semiconductor device in the third embodiment. Detailed Implementation

[0035] Hereinafter, embodiments of the present disclosure will be described based on the accompanying drawings. Furthermore, in each of the following embodiments, the same reference numerals will be used to describe parts that are identical or equivalent to each other.

[0036] (First Implementation)

[0037] The first embodiment will be described with reference to the accompanying drawings. Furthermore, the semiconductor device of this embodiment is preferably used as a power switching element in power supply circuits such as inverters and DC / DC converters.

[0038] like Figure 1 As shown, the semiconductor device in this embodiment is configured such that an RC (Reverse Conducting)-IGBT is formed on a common semiconductor substrate 10, comprising an IGBT region 1a having IGBT elements and an FWD region 1b having FWD elements. Furthermore, in this embodiment, a portion of the collector layer 23 (described later) is designated as the IGBT region 1a, and a portion of the cathode layer 24 (described later) is designated as the FWD region 1b, which will be explained in detail later.

[0039] Semiconductor devices have N －The semiconductor substrate 10 has a drift layer 11. Furthermore, the semiconductor substrate 10 in this embodiment is made of silicon and has a thickness of approximately 110 μm. A base layer 12 is formed on the drift layer 11. That is, the base layer 12 is formed on one side 10a of the semiconductor substrate 10.

[0040] In this embodiment, the base layer 12 is configured to have a lower base layer 12a, a first upper base layer 12b, and a second upper base layer 12c. Specifically, the lower base layer 12a is set to P. － The type is disposed on the drift layer 11. Moreover, a carrier storage layer (hereinafter also referred to as the CS layer) 13 with a higher impurity concentration than the drift layer 11 is formed on the lower base layer 12a. In addition, the lower base layer 12a and the CS layer 13 are formed in the IGBT region 1a and the FWD region 1b.

[0041] The first upper base layer 12b is disposed in the IGBT region 1a of the upper part of the CS layer 13, and has a higher impurity concentration compared to the lower base layer 12a. The second upper base layer 12c is disposed in the FWD region 1b of the upper part of the CS layer 13, and has a lower impurity concentration compared to the lower base layer 12a.

[0042] That is, in this embodiment, the base layer 12 is divided by the CS layer 13 into a lower base layer 12a located on the drift layer 11 side and a first upper base layer 12b and a second upper base layer 12c located on one side 10a of the semiconductor substrate 10. In addition, the first upper base layer 12b and the second upper base layer 12c in this embodiment are separated by the boundary between the IGBT region 1a and the FWD region 1b.

[0043] Furthermore, the impurity concentration of the lower base layer 12a is set based on the required withstand voltage, for example, 5.0 × 10⁻⁶. 16 cm －3 The impurity concentration of the first upper base layer 12b is set based on the threshold voltage Vth in the required insulating gate structure (described later), for example, set to 1.0 to 3.0 × 10⁻⁶. 17 cm －3 The impurity concentration of the second upper base layer 12c is set based on the required forward voltage Vf when the FWD device is in the on-state, for example, 2.0 × 10⁻⁶. 16 cm －3 Left and right. That is, in this embodiment, the lower base layer 12a, the first upper base layer 12b, and the second upper base layer 12c are each set with impurity concentrations in a manner that satisfies the required conditions. In addition, although the second upper base layer 12c is set based on the forward voltage Vf when the FWD element is in the on state, more specifically, it is also set considering the impurity concentration and area of ​​the second contact region 18b, which will be described later.

[0044] Furthermore, a plurality of trenches 14 are formed on the semiconductor substrate 10, extending from one side 10a through the base layer 12 and the CS layer 13 to the drift layer 11. Thus, the base layer 12 and the CS layer 13 are separated into multiple layers by the trenches 14. In this embodiment, the plurality of trenches 14 are formed in the IGBT region 1a and the FWD region 1b, respectively, and their depth from one side 10a of the semiconductor substrate 10 is set to approximately 5 μm. Additionally, in this embodiment, the plurality of trenches 14 are formed in a stripe-like pattern, with one direction intersecting the arrangement direction of the IGBT region 1a and the FWD region 1b as the length direction.

[0045] Each trench 14 is filled with a gate insulating film 15 formed covering the wall surface of each trench 14 and a gate electrode 16 made of polysilicon or the like formed on the gate insulating film 15. Thus, a trench gate structure is formed.

[0046] In the surface portion of the first upper base layer 12b in IGBT region 1a, N₂ has a higher impurity concentration compared to the drift layer 11. + The emitter region 17 of the type and the P-type base layer 12b have a high impurity concentration compared to the first upper base layer 12b. + The first contact area 18a of the type.

[0047] Specifically, the emitter region 17 and the first contact region 18a are respectively formed to expose one side 10a of the semiconductor substrate 10. Furthermore, in this embodiment, the emitter region 17 and the first contact region 18a are as follows... Figure 1 as well as Figure 2 As shown, they are alternately formed along the length of the groove 14 and are formed to connect with the adjacent groove 14 respectively.

[0048] Furthermore, a hole suppression region 19 is formed within the first contact region 18a, exposed from one side 10a of the semiconductor substrate 10. That is, the hole suppression region 19 is formed on one side 10a of the semiconductor substrate 10, separated from the emitter region 17. The hole suppression region 19 has a lower impurity concentration than the first contact region 18a, and in this embodiment, it is formed by exposing the first upper base layer 12b from one side 10a of the semiconductor substrate 10. In other words, the hole suppression region 19 in this embodiment is formed from a portion of the first upper base layer 12b. Additionally, in this embodiment, the hole suppression region 19 corresponds to a carrier suppression region.

[0049] In the surface portion of the second upper base layer 12c in FWD region 1b, a P layer with a higher impurity concentration than the second upper base layer 12c is formed. + The second contact area 18b of the type.

[0050] Additionally, although not specifically limited, the impurity concentration in the first contact region 18a and the second contact region 18b is set to 1.0 × 10⁻⁶. 18 ~5.0×10 19 cm －3 about.

[0051] An interlayer insulating film 20, composed of BPSG (short for Borophosphosilicate Glass), is formed on one side 10a of the semiconductor substrate 10. Within the interlayer insulating film 20, in the IGBT region 1a of one side 10a of the semiconductor substrate 10, a first contact hole 20a is formed, exposing the emitter region 17, the first contact region 18a, and the hole suppression region 19 located between adjacent trenches 14. Furthermore, within the interlayer insulating film 20, in the FWD region 1b of one side 10a of the semiconductor substrate 10, a second contact hole 20b is formed, exposing the second upper base layer 12c and the second contact region 18b.

[0052] In this embodiment, the first contact hole 20a and the second contact hole 20b are formed along the length direction of the trench 14. Furthermore, the first contact hole 20a is formed such that portions between adjacent trenches 14 are alternately exposed in a direction along the surface direction of one surface 10a of the semiconductor substrate 10, and in a direction orthogonal to the length direction of the trench 14. That is, the IGBT element in this embodiment has an intermittent structure. Hereinafter, the direction along the surface direction of one surface 10a of the semiconductor substrate 10, and in a direction orthogonal to the length direction of the trench 14, will sometimes be simply referred to as the direction orthogonal to the length direction of the trench 14.

[0053] In addition, Figure 1 In this diagram, for ease of understanding of the structure of one side 10a of the semi-semiconductor substrate 10, the interlayer insulating film 20 and a portion of the upper electrode 21 (described later) are omitted. Furthermore, in Figure 1 In the diagram, the area exposed from the first contact hole 20a is represented by a dashed line as region A, and the area exposed from the second contact hole 20b is represented by a dashed line as region B.

[0054] Furthermore, an upper electrode 21 is formed on the interlayer insulating film 20. The upper electrode 21 is electrically connected to the emitter region 17 and the first contact region 18a in an ohmic junction state through the first contact hole 20a formed on the interlayer insulating film 20. In addition, the upper electrode 21 is electrically connected to the hole suppression region 19 in a Schottky junction state through the first contact hole 20a formed on the interlayer insulating film 20. That is, a P-type Schottky barrier diode (hereinafter also referred to as SBD) including the hole suppression region 19 and the upper electrode 21 is formed in the IGBT region 1a.

[0055] In addition, the upper electrode 21 is electrically connected to the second upper base layer 12c and the second contact region 18b through the second contact hole 20b formed in the interlayer insulating film 20.

[0056] That is, an upper electrode 21 is formed on the interlayer insulating film 20, which functions as the emitter electrode in the IGBT region 1a and as the anode electrode in the FWD region 1b. Furthermore, in this embodiment, the upper electrode 21 corresponds to the first electrode. In this embodiment, the upper electrode 21, as described later, is composed of titanium silicide or the like, with a Schottky barrier height φB of approximately 0.61 eV relative to silicon, which is conceived as the semiconductor substrate 10.

[0057] An N-type field stop layer (hereinafter referred to as FS layer) 22 with a higher impurity concentration than the base layer 12 is formed on the side of the drift layer 11 opposite to the base layer 12. That is, the FS layer 22 is formed on the other side 10b of the semiconductor substrate 10.

[0058] Furthermore, in IGBT region 1a, P is formed on the side opposite to the drift layer 11, separated by FS layer 22. + The current collector layer 23 of the type is formed in the FWD region 1b, on the side opposite to the drift layer 11, separated by the FS layer 22, with N + The cathode layer 24 is of the type 23. That is, on the side opposite to the drift layer 11 and separated from the FS layer 22, the collector layer 23 and the cathode layer 24 are formed adjacent to each other. Moreover, the IGBT region 1a and the FWD region 1b are divided according to whether the layer formed on the other side 10b of the semiconductor substrate 10 is the collector layer 23 or the cathode layer 24. That is, in this embodiment, the portion on the collector layer 23 is the IGBT region 1a, and the portion on the cathode layer 24 is the FWD region 1b.

[0059] A lower electrode 25, electrically connected to the collector layer 23 and the cathode layer 24, is formed on the side opposite to the drift layer 11, separated by the collector layer 23 and the cathode layer 24. That is, a lower electrode 25 is formed that functions as a collector electrode in the IGBT region 1a and as a cathode electrode in the FWD region 1b. In this embodiment, the lower electrode 25 corresponds to the second electrode.

[0060] The semiconductor device of this embodiment is configured such that, in the IGBT region 1a, an IGBT element is formed with the base layer 12 as the base, the emitter region 17 as the emitter, and the collector layer 23 as the collector. Furthermore, in the FWD region 1b, an FWD element is formed with the base layer as the anode and the drift layer 11, FS layer 22, and cathode layer 24 PN-connected as the cathode.

[0061] The above describes the configuration of the semiconductor device in this embodiment. In this embodiment, an IGBT region 1a and an FWD region 1b are thus formed on a common semiconductor substrate 10. Furthermore, in this embodiment, N-type, N... + Type, N － Type P is equivalent to the first conductivity type, P-type, P-type + This type is equivalent to the second conductivity type. Furthermore, by the configuration described above, the semiconductor substrate 10 is configured to have a drift layer 11, a base layer 12, a CS layer 13, an emitter region 17, a first contact region 18a, a second contact region 18b, a hole suppression region 19, an FS layer 22, a collector layer 23, and a cathode layer 24.

[0062] Next, the operation and effects of the aforementioned semiconductor device will be explained.

[0063] First, if a higher voltage than the upper electrode 21 is applied to the lower electrode 25 of the semiconductor device, the PN junction formed between the base layer 12 and the drift layer 11 becomes reverse-conductive and forms a depletion layer. Furthermore, when a low level (e.g., 0V) voltage less than the threshold voltage Vth of the insulating gate structure is applied to the gate electrode 16, no current flows between the upper electrode 21 and the lower electrode 25.

[0064] To enable the IGBT element to conduct, with a higher voltage applied to the lower electrode 25 than to the upper electrode 21, a high-level voltage above the threshold voltage Vth of the insulating gate structure is applied to the gate electrode 16. Consequently, a reversal layer is formed in the portion of the base layer 12 that connects to the trench 14 where the gate electrode 16 is disposed. Furthermore, regarding the IGBT element, electrons are supplied from the emitter region 17 to the drift layer 11 via the reversal layer, and holes are supplied from the collector layer 23 to the drift layer 11. Through conductivity modulation, the resistance of the drift layer 11 decreases, thus enabling it to conduct.

[0065] Furthermore, when the IGBT element is in the off state and the FWD element is in the on state (i.e., the FWD element is diode-operated), the voltage applied to the upper electrode 21 and the lower electrode 25 is switched, and a forward voltage is applied to the upper electrode 21 with a higher voltage than that applied to the lower electrode 25. As a result, holes are supplied to the base layer 12 and electrons are supplied to the cathode layer 24, thereby enabling the FWD element to operate as a diode.

[0066] In this embodiment, a hole suppression region 19 is formed in the IGBT region 1a. Furthermore, the hole suppression region 19 and the upper electrode 21 are Schottky-bonded to form an SBD. Therefore, when the FWD element is in the on state, hole injection into the second upper base layer 12c of the IGBT region 1a can be suppressed.

[0067] Specifically, such as Figure 3A As shown, between the first contact region 18a and the upper electrode 21, electrons and holes recombine, thereby creating a state in which holes can be injected from the upper electrode 21 into the first contact region 18a. On the other hand, as... Figure 3B As shown, between the hole suppression region 19 and the upper electrode 21, the hole suppression region 19 and the upper electrode 21 are Schottky bonded, making it difficult to inject holes from the upper electrode 21 into the hole suppression region 19. Furthermore, even in the presence of electrons mixed in from the cathode layer 24 to the base layer 12 of the IGBT region 1a, they are not easily discharged to the upper electrode 21 as a drift current due to recombination current with holes. Additionally, Figure 3A as well as Figure 3B This is the energy band diagram with the forward voltage Vf between the cathode and anode set to approximately 2.5V.

[0068] Furthermore, the inventors simulated the carrier concentration distribution when the FWD element is in the on state and obtained... Figures 4A to 4C The electron concentration distribution is shown. Furthermore, since it is in a conductive state, the electron concentration corresponds to the hole concentration. That is, Figures 4A to 4C The simulation results related to electron concentration distribution and hole concentration distribution are roughly the same. Therefore, the carrier concentration distribution will be described below using electron concentration distribution as an example. Furthermore, the lengths of the emitter region 17, the first contact region 18a, and the hole suppression region 19 along the extension direction of trench 14 will be described below as their respective lengths. Moreover, as follows... Figure 2 As shown, the length of the emitter region 17 is taken as length L1 and the length of the hole suppression region 19 is taken as length L2.

[0069] like Figure 4A As shown, even without the hole suppression region 19 formed, a region D with increased electron concentration was identified in the surface portion of the IGBT region 1a on the FWD region 1b side. That is, even without the hole suppression region 19 formed, a region with increased hole concentration was identified in the surface portion of the IGBT region 1a on the FWD region 1b side. On the other hand, as... Figure 4B As shown, with the hole suppression region 19 formed, it was confirmed that region D becomes smaller in IGBT region 1a. Furthermore, as... Figure 4C As shown, when the length of the hole suppression region 19 is taken as the limit, it is confirmed that in the IGBT region 1a, there is no region D on the surface layer on the side of the FWD region 1b.

[0070] In addition, Figure 4CIn the simulation, the limit of the length L2 of the hole suppression region 19 means that the length of the first contact region 18a is 0, and the first contact region 18a is not formed. That is, making Figure 4C The limit of the length L2 of the hole suppression region 19 in the simulation refers to a state in which the emitter region 17 and the hole suppression region 19 are alternately arranged along the length direction of the trench 14. Furthermore, the same applies to the case where the length L2 of the hole suppression region 19 is the limit.

[0071] Moreover, such as Figure 5 As shown, it was confirmed that in IGBT region 1a, by forming the hole suppression region 19, the electron concentration (i.e., hole concentration) decreased compared to the case where the hole suppression region 19 was not formed. Furthermore, since a longer length L2 of the hole suppression region 19 makes hole injection more difficult, it was confirmed that the electron concentration (i.e., hole concentration) decreased. Figure 5 This represents the electron concentration of a portion 10 μm deep from one side 10a of the semiconductor substrate 10, and also represents the electron concentration of the portion of the drift layer 11 closer to the lower electrode 25 than the portion reached by the trench 14.

[0072] Subsequently, when the FWD element is switched from the on state to the off state, a reverse voltage is applied to the lower electrode 25, which is higher than the upper electrode 21. That is, when the forward current flowing through the FWD element is cut off, a reverse voltage is applied to the lower electrode 25, which is higher than the upper electrode 21. As a result, the FWD element enters the recovery state. Furthermore, holes in the base layer 12 are attracted to the upper electrode 21 side, and electrons in the drift layer 11 are attracted to the lower electrode 25 side, thereby generating a recovery current.

[0073] At this time, in IGBT region 1a, as described above, hole injection is suppressed when the FWD element is in the on state. Therefore, in the semiconductor device of this embodiment, the recovery current can be reduced, and the recovery loss Err can be reduced.

[0074] Specifically, such as Figure 6A as well as Figure 6B As shown, by forming the hole suppression region 19, the recovery loss Err can be reduced. Moreover, as mentioned above, since the longer the length L2 of the hole suppression region 19 is, the more hole injection is suppressed, the longer the length L2 of the hole suppression region 19 is, the smaller the recovery loss Err is.

[0075] Here, the semiconductor device of this embodiment has a hole suppression region 19 formed as described above, thus reducing recovery loss Err. However, the IGBT element in such a semiconductor device is prone to latch-up due to the formation of the hole suppression region 19.

[0076] Therefore, in this embodiment, the hole suppression region 19 is formed separately from the emitter region 17. As a result, compared with the case where the hole suppression region 19 is formed in connection with the emitter region 17, it is possible to suppress the flow of holes from the hole suppression region 19 to the emitter region 17, and to suppress latch-up.

[0077] Furthermore, in this embodiment, the hole suppression region 19 is configured as follows. First, the IGBT element in the aforementioned semiconductor device is composed of... Figure 7 The equivalent circuit representation is shown. Additionally, in Figure 7 In the text, for ease of understanding, CS layer 13 is removed.

[0078] like Figure 7 As shown, the IGBT device is configured with an NMOS 100, a PNP transistor 101, and a parasitic NPN transistor (hereinafter also simply referred to as the parasitic transistor) 102. If the parasitic transistor 102 is activated, latch-up occurs. In addition, the parasitic transistor 102 includes an emitter region 17, a base layer 12, and a drift layer 11.

[0079] Furthermore, the IGBT element is configured such that an emitter resistor 110 (serving as the internal resistance of the emitter region 17), a contact resistor 111 (serving as the internal resistance of the first contact region 18a), and an SBD 112 are connected in parallel on the emitter E. The emitter E is the upper electrode 21, and the SBD 112 includes a hole suppression region 19 and the upper electrode 21. Moreover, the anodes of the contact resistor 111 and the SBD 112 are connected to the base of the parasitic transistor 102 via a base resistor 113 (serving as the internal resistance of the base layer 12).

[0080] In this case, the operation of the parasitic transistor 102 is suppressed when the potential on the contact resistance 111 side of the base resistor 113 is low. However, if the SBD 112 is configured by forming the hole suppression region 19, the potential on the contact resistance 111 side of the base resistor 113 becomes high. Furthermore, the longer the length L2 of the hole suppression region 19, the shorter the length of the first contact region 18a, resulting in a higher potential on the contact resistance 111 side of the base resistor 113. Moreover, if the potential on the contact resistance 111 side of the base resistor 113 is too high, latch-up that cannot be controlled by the NMOS 100 occurs due to the operation of the parasitic transistor 102.

[0081] More specifically, the hole quasi-Fermi level E of base layer 12 fp With the electron quasi-Fermi level E in emitter region 17 fn The difference is equal to the base-emitter voltage V of the parasitic transistor 102. BE Moreover, without the hole-quasi-Fermi level E fp With the electron quasi-Fermi level E fn The difference is V BE =0, no base current flows due to holes, and parasitic transistor 102 does not operate. Therefore, no latch-up occurs.

[0082] However, if the hole quasi-Fermi level E fp With the electron quasi-Fermi level E fn There is a difference, the base-emitter voltage V BE If the value increases, the parasitic transistor 102 will operate. In this case, a latch-up condition that cannot be controlled by the NMOS 100 will occur.

[0083] Therefore, the inventors conducted an in-depth study on the length L2 of the hole suppression region 19 and obtained... Figure 8 as well as Figure 9 The results are shown. Additionally, in Figure 8 as well as Figure 9 In, such as Figure 2 As shown, the center-to-center spacing (i.e., pitch) L of adjacent emitter regions 17 along the extension direction of the trench 14 is set to 6 μm, and the length L1 of each emitter region 17 is set to 1.2 μm. Furthermore, Figure 8 as well as Figure 9 These are simulation results under the condition of a fixed spacing and a varying length L2 of the hole suppression region 19. That is, Figure 8 as well as Figure 9 The simulation results are based on the condition that the sum of the lengths of the first contact region 18a and the hole suppression region 19 is 3.6 μm, and the ratio (i.e., the area ratio) of the lengths of the hole suppression region 19 to the lengths of the first contact region 18a is varied. However, in Figure 8 as well as Figure 9 In this context, half the length of L2 in the hole suppression region 19 is represented as the unidirectional length. For example... Figure 8 The unidirectional length of the hole suppression region 19 is 0.1 μm, which means that the length L2 of the hole suppression region 19 is 0.2 μm.

[0084] First, such as Figure 8As shown, without the hole suppression region 19, the collector current Ice when the IGBT element is in the on state becomes constant (i.e., saturation current) because the collector-emitter voltage Vce becomes a predetermined voltage. Furthermore, with the hole suppression region 19, the longer the unidirectional length (i.e., length L2) of the hole suppression region 19, the easier it is for the collector current Ice to latch up, and the larger the saturation current becomes. However, when the length L2 of the hole suppression region 19 is the limit, the collector current Ice does not saturate due to latch-up and becomes linear. Additionally, Figure 8 These are simulation results when the gate-emitter voltage Vge is 15V.

[0085] Moreover, such as Figure 9 As shown, it was confirmed that if the unidirectional length of the hole suppression region 19 is set to 1.2 μm or more, the base-emitter voltage V of the parasitic transistor 102 will be reduced. BE It increases dramatically. That is, it was confirmed that if the length L2 of the hole suppression region 19 is set to 2.4 μm or more, the base-emitter voltage V of the parasitic transistor 102 will increase dramatically. BE The length of the first contact region 18a increases dramatically. Furthermore, in this embodiment, as described above, the sum of the lengths of the first contact region 18a and the hole suppression region 19 is set to 3.6 μm. Therefore, if the area ratio (i.e., length ratio) of the first contact region 18a to the hole suppression region 19 is 1:2 or higher, the base-emitter voltage V of the parasitic transistor 102 will increase dramatically. BE It is prone to becoming large. That is, latch-up is easily generated due to the parasitic transistor 102. Therefore, in this embodiment, the first contact region 18a and the hole suppression region 19 are formed with an area ratio of 1:2 or less. In other words, the area of ​​the hole suppression region 19 is set to be less than twice the area of ​​the first contact region 18a. Thus, in the semiconductor device of this embodiment, even if the hole suppression region 19 is formed, latch-up can be suppressed. In addition, Figure 9 This is a graph showing the simulation results when a large current of 2000A flows through it.

[0086] The above describes the main operation of the semiconductor device in this embodiment.

[0087] Moreover, in this embodiment, it is also based on Figure 10 The Schottky barrier height φB of the upper electrode 21 is specified. Additionally, Figure 10 The impurity concentration in hole suppression region 19 is set to 1.0 × 10⁻⁶. 17 cm －3 The simulation results under the given conditions.

[0088] like Figure 10As shown, the larger the Schottky barrier height φB of the upper electrode 21, the easier it is for holes to be injected, and therefore the recovery loss Err tends to increase. Specifically, when the impurity concentration of the hole suppression region 19 is set to 1.0 × 10⁻⁶, the hole is suppressed further. 17 cm －3 In the case where the Schottky barrier height φB is greater than 0.8 eV, the recovery loss Err increases sharply. Therefore, the upper electrode 21 in this embodiment is made of a material with a Schottky barrier height φB of 0.8 eV or less, such as titanium silicide.

[0089] As explained above, in this embodiment, a hole suppression region 19 is formed that exposes one side 10a of the semiconductor substrate 10, and the upper electrode 21 is Schottky-bonded to the hole suppression region 19. Therefore, when the FWD element is in the on state, hole injection into the surface layer of the IGBT region 1a can be suppressed. Consequently, the recovery current can be reduced, and the recovery loss Err can be reduced.

[0090] Furthermore, the hole suppression region 19 is exposed from one side 10a of the semiconductor substrate 10. Therefore, it is not necessary to form a trench contact for connecting the hole suppression region 19 to the upper electrode 21. Consequently, the spacing between adjacent trenches can be narrowed, and the high on-state voltage of the IGBT element can be suppressed.

[0091] Furthermore, the emitter region 17 and the first contact region 18a are formed along the length direction of the trench 14. Therefore, compared with the case where the emitter region 17 and the first contact region 18a are formed in a direction orthogonal to the length direction of the trench 14, the spacing between adjacent trenches 14 can be further narrowed.

[0092] Furthermore, the hole suppression region 19 is formed not to be connected to the emitter region 17. Therefore, compared with the case where the hole suppression region 19 is connected to the emitter region 17, latch-up of the IGBT element can be suppressed.

[0093] Furthermore, the area ratio of the first contact region 18a to the hole suppression region 19 is 1:2 or less. Therefore, latch-up of the IGBT element can be further suppressed.

[0094] Furthermore, in this embodiment, a CS layer 13 is formed. Therefore, when the IGBT element is in the on state, the holes supplied to the drift layer 11 are suppressed from escaping from the upper electrode 21 by the CS layer 13, thereby reducing the on-state voltage.

[0095] Furthermore, in this embodiment, the base layer 12 is configured to have a lower base layer 12a, a first upper base layer 12b, and a second upper base layer 12c. The impurity concentration of the lower base layer 12a is set based on a required breakdown voltage. The impurity concentration of the first upper base layer 12b is set based on the required threshold voltage Vth of the insulating gate structure. The impurity concentration of the second upper base layer 12c is set based on the required forward voltage Vf when the FWD element is in the on-state. Thus, the impurity concentrations of the lower base layer 12a, the first upper base layer 12b, and the second upper base layer 12c are set in a manner that satisfies the required conditions, thereby enabling improvements in the characteristics of the semiconductor device.

[0096] (Second Implementation)

[0097] The second embodiment will be described. This embodiment differs from the first embodiment in that it does not include the CS layer 13. Everything else is the same as the first embodiment, therefore, the description is omitted here.

[0098] In this embodiment, such as Figure 11 As shown, the CS layer 13 is not formed on the semiconductor substrate 10, and the base layer 12 is not segmented along the depth direction. Furthermore, the impurity concentration of the base layer 12 is constant in both the IGBT region 1a and the FWD region 1b. In this configuration, it is preferable to form a P layer in the FWD region 1b with an impurity concentration lower than that of the base layer 12. － The adjustment area 26 is used to adjust the forward voltage Vf of the FWD element.

[0099] This semiconductor device can also achieve the same effect as the first embodiment described above by forming a hole suppression region 19 in the IGBT region 1a.

[0100] (Third Implementation)

[0101] The third embodiment will be described. This embodiment differs from the first embodiment in that it modifies the portion forming the hole suppression region 19. Everything else is the same as the first embodiment, therefore, descriptions are omitted here.

[0102] In this embodiment, such as Figure 12 As shown, the hole suppression region 19 is formed only on the boundary side of the IGBT region 1a that is opposite to the FWD region 1b. That is, the hole suppression region 19 is not formed on the portion located across the boundary on the side opposite to the FWD region 1b. In other words, for example, when the IGBT regions 1a and FWD regions 1b are arranged alternately, the hole suppression region 19 is not formed on the inner edge of the IGBT region 1a in the arrangement direction of the IGBT regions 1a and FWD regions 1b.

[0103] In this semiconductor device, a hole suppression region 19 is configured only in the IGBT region 1a, which is a portion that easily affects the recovery loss Err. Therefore, it is possible to suppress the decrease in latch-up tolerance and reduce the recovery loss Err.

[0104] (Other implementation methods)

[0105] This disclosure has been described based on embodiments, but it should be understood that this disclosure is not limited to these embodiments and structures. This disclosure also includes various modifications and variations within the same range. Furthermore, various combinations and forms, and even combinations and forms containing only one element, or more or less thereof, also fall within the scope and spirit of this disclosure.

[0106] For example, in the above embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0107] Furthermore, the configurations of the IGBT region 1a and the FWD region 1b can be appropriately modified in the above embodiments. For example, in the first embodiment described above, the lower base layer 12a and the first upper base layer 12b of the IGBT region 1a can also be set to the same impurity concentration. Similarly, the lower base layer 12a and the second upper base layer 12c of the FWD region 1b can also be set to the same impurity concentration. In addition, when the lower base layer 12a and the second upper base layer 12c in the FWD region 1b are set to the same impurity concentration, it is preferable to form a P layer with a lower impurity concentration than the base layer 12. － The adjustment area 26 is used to adjust the forward voltage Vf of the FWD element.

[0108] Furthermore, in the above embodiments, the hole suppression region 19 may have a different configuration than the first upper base layer 12b, or it may have a different impurity concentration than the first upper base layer 12b.

[0109] Furthermore, in the above embodiments, in the IGBT region 1a, the first contact hole 20a may be formed on the interlayer insulating film 20 in such a way that the portions between adjacent trenches 14 are exposed. That is, the IGBT region 1a may not be configured with a spacing structure.

[0110] Furthermore, in the above embodiments, the emitter region 17 and the first contact region 18a may be formed sequentially in a direction orthogonal to the length direction of the trench 14. Additionally, the hole suppression region 19 may also contact the emitter region 17. Such a semiconductor device can also reduce recovery loss Err by forming the hole suppression region 19.

Claims

1. A semiconductor device comprising an IGBT region having IGBT elements and an FWD region having FWD elements formed on a common semiconductor substrate, characterized in that, have: The semiconductor substrate has the IGBT region and the FWD region, and includes: a drift layer of a first conductivity type; a base layer of a second conductivity type formed on the drift layer; a collector layer of the second conductivity type formed in the IGBT region on the side of the drift layer opposite to the base layer side; and a cathode layer of the first conductivity type formed in the FWD region on the side of the drift layer opposite to the base layer side, wherein the semiconductor substrate has the base layer side as one side and the collector layer and cathode layer side as the other side; A gate insulating film is formed on the walls of a plurality of trenches that penetrate the base layer in the IGBT region to reach the drift layer and are extended in one direction as the length direction. Gate electrode disposed on the gate insulating film; The emitter region of the first conductivity type is the surface portion of the base layer in the IGBT region and is formed to be in contact with the trench, and the impurity concentration is higher than that of the drift layer; The contact region of the second conductivity type is formed in the surface portion of the base layer in the IGBT region, and the impurity concentration is higher than that of the base layer; A first electrode is disposed on one side of the semiconductor substrate and is electrically connected to the base layer and the emitter region; as well as The second electrode is disposed on the other side of the semiconductor substrate and is electrically connected to the collector layer and the cathode layer. A second conductivity type carrier suppression region is formed in the IGBT region, which is exposed from one side of the semiconductor substrate and has a lower impurity concentration than the contact region. The first electrode is Schottky-junctioned with the carrier suppression region.

2. The semiconductor device according to claim 1, characterized in that, In the IGBT region, the base layer is divided into a lower base layer on the drift layer side and an upper base layer on one side of the semiconductor substrate by a carrier storage layer with a higher impurity concentration than the drift layer. The impurity concentration of the lower base layer is different from that of the upper base layer.

3. The semiconductor device according to claim 1 or 2, characterized in that, In the IGBT region, the emitter region and the contact region are alternately formed along the length of the trench.

4. The semiconductor device according to claim 3, characterized in that, The carrier suppression region is formed within the contact region and is separated from the emitter region.

5. The semiconductor device according to claim 4, characterized in that, The contact region and the carrier suppression region are configured such that the area ratio of the contact region to the carrier suppression region is 1:2 or less.

Images