Systems and methods for retransmitting erroneously received data

Abstract

The present disclosure provides a method and system for retransmitting only information bits. A transmitter sends a first signal to a receiver, where the first signal includes a first bit sequence of length M1, and the first bit sequence includes N1 information bits and (M1 – N1) redundant bits; if the receiver incorrectly receives the first bit sequence, the receiver sends a retransmission request (Negative Acknowledge, NACK) back to the transmitter. The transmitter sends a second signal including a second bit sequence as a response, where the second bit sequence includes N2 of the N1 information bits of the first bit sequence, but does not include any redundant bits, where 1 ≤ N2 ≤ N1.

Description

Technical Field

[0001] In some embodiments, the present disclosure relates to a communication system configured to send digital data from a transmitter to a receiver. More specifically, but not limited thereto, the present disclosure relates to a system and method for retransmitting erroneously received data, i.e., data detected or decoded erroneously by the receiver. Background Art

[0002] In a communication system, the Automatic Repeat Request (ARQ) protocol is a known error correction protocol, in which, if a transmitted packet is decoded erroneously by the receiver, the receiver discards the erroneous data carried in the received packet (as well as any intermediate results generated during the processing of the packet), and the transmitter retransmits the packet to the receiver. Then, the receiver attempts to decode the retransmitted packet that is independent of the previously erroneously received packet. Hybrid Automatic Repeat Request (HARQ) is a more complex method that combines Forward Error Correction (FEC) codes and ARQ error control. In HARQ, soft combining (or combining of equalized symbols) of the Log Likelihood Ratio (LLR) metrics of different retransmission / transmission versions of the same data is performed by the receiver. This means that the LLR metrics (or equalized symbols) corresponding to the erroneously decoded packet are stored in the receiver's memory and combined with the LLR metrics extracted from the retransmission of the same information, thereby increasing the likelihood of correctly detecting the data (after retransmission).

[0003] (After combination) The performance improvement results in higher throughput and less latency (due to fewer retransmissions) and / or higher spectral efficiency (due to a higher Modulation and Coding Scheme (MCS) level being used). Summary of the Invention

[0004] An object of the present disclosure is to describe a system and method for HARQ in which only the information bits in the erroneously received data are retransmitted without sending the accompanying redundant (or parity) bits that were appended to the information bits during the first transmission of the data.

[0005] The above and other objects are achieved by the features of the independent claims. Other implementations are apparent from the dependent claims, the description, and the drawings.

[0006] In a first aspect, the present disclosure relates to a method of sending information from a transmitter to a receiver. The method includes:

[0007] The transmitter transmits a first signal, where the first signal carries a first symbol sequence, the first symbol sequence represents a first bit sequence of length M1, the first bit sequence includes N1 information bits and (M1 - N1) redundant bits, where 1 < N1 < M1, and the N1 information bits represent a piece of information;

[0008] The receiver receives the first signal;

[0009] The receiver demodulates the received first signal to generate a reconstructed first symbol sequence;

[0010] By generating one or more log-likelihood ratio (LLR) metrics for each symbol in the reconstructed first symbol sequence, the receiver generates a first LLR metric sequence of length M1;

[0011] The receiver generates a reconstructed first bit sequence of length M1 based on the first LLR metric sequence;

[0012] The receiver determines that the reconstructed first bit sequence is invalid;

[0013] The receiver sends a request;

[0014] The transmitter receives the request;

[0015] The transmitter, in response to the received request, transmits a second signal, where the second signal carries a second symbol sequence, the second symbol sequence represents a second bit sequence of length N2, the second bit sequence includes N2 of the N1 information bits of the first bit sequence but does not include any redundant bits, where 1 ≤ N2 ≤ N1;

[0016] The receiver receives the second signal;

[0017] The receiver demodulates the received second signal to generate a reconstructed second symbol sequence;

[0018] By generating one or more LLR metrics for each symbol in the reconstructed second symbol sequence, the receiver generates a second LLR metric sequence of length N2;

[0019] The receiver generates an integrated LLR metric sequence of length M1, where generating the integrated LLR metric sequence includes: combining the first LLR metric sequence and the second LLR metric sequence; and

[0020] The receiver generates a second reconstructed first bit sequence of length M1 based on the integrated LLR metric sequence.

[0021] According to the first aspect, in the first possible implementation manner of the method, the second bit sequence includes all information bits in the first bit sequence.

[0022] According to the first aspect, in the second possible implementation manner of the method, the second bit sequence includes fewer information bits than all information bits in the first bit sequence.

[0023] According to any of the foregoing implementation manners, in the third possible implementation manner of the method, determining that the reconstructed first bit sequence is invalid includes or consists of: determining that the syndrome of the reconstructed first bit sequence is an error correction syndrome.

[0024] According to any of the foregoing implementation manners, in the fourth possible implementation manner of the method, the first bit sequence is a codeword of a forward error correction (FEC) code.

[0025] According to the fourth implementation manner, in the fifth possible implementation manner of the method, determining that the reconstructed first bit sequence is invalid includes or consists of: determining that the reconstructed first bit sequence is not a valid codeword of the FEC code.

[0026] According to any of the foregoing implementation manners, in the sixth possible implementation manner of the method, generating the integrated LLR metric sequence includes: adding the value of one of the N2 metrics in the second LLR metric sequence to each of the N2 metrics in the M1 metrics of the first LLR metric sequence.

[0027] According to any of the foregoing implementation manners, in the seventh possible implementation manner of the method, the integrated LLR metric sequence is a first integrated LLR metric sequence, and the method further includes:

[0028] the receiver determines that the second reconstructed first bit sequence is invalid;

[0029] the receiver sends a second request;

[0030] the transmitter receives the second request;

[0031] the transmitter sends a third signal in response to the received second request, where the third signal carries a third symbol sequence, the third symbol sequence represents a third bit sequence of length M3, and the third bit sequence includes M3 bits in the first bit sequence, where 1 ≤ M3 ≤ M1;

[0032] the receiver receives the third signal;

[0033] the receiver demodulates the received third signal to generate a reconstructed third symbol sequence;

[0034] The receiver generates a third LLR metric sequence of length M3 by generating one or more LLR metrics for each symbol in the reconstructed third symbol sequence;

[0035] The receiver generates a second integrated LLR metric sequence of length M1, where generating the second integrated LLR metric sequence includes: combining the first LLR metric sequence, the second LLR metric sequence, and the third LLR metric sequence, or combining the first integrated LLR metric sequence and the third LLR metric sequence;

[0036] The receiver generates a third reconstructed first bit sequence of length M1 based on the second integrated LLR metric sequence.

[0037] According to the seventh implementation, in the eighth possible implementation of the method, one or more bits in the first bit sequence are included in only one of the second bit sequence and the third bit sequence.

[0038] According to the seventh or eighth implementation, in the ninth possible implementation of the method, the third bit sequence includes N3 information bits of the N1 information bits of the first bit sequence but does not include any redundant bits, where 1 ≤ N3 ≤ N1.

[0039] According to the seventh, eighth, or ninth implementation, in the tenth possible implementation of the method, determining that the reconstructed second bit sequence is invalid includes: determining that the syndrome of the reconstructed second bit sequence is a failure syndrome.

[0040] According to the seventh, eighth, or ninth implementation, in the eleventh possible implementation of the method, the second bit sequence is a codeword of a forward error correction (FEC) code, and determining that the reconstructed second bit sequence is invalid includes: determining that the reconstructed second bit sequence is not a valid codeword of the FEC code.

[0041] According to the first aspect, in the twelfth possible implementation of the method, a method for transmitting multiple pieces of information from a transmitter to a receiver includes:

[0042] By executing an instance of the method according to any of the foregoing possible implementations of the method according to the first aspect, each piece of information in the multiple pieces of information is transmitted from the transmitter to the receiver, where, for each piece of information, N2 bits in the second bit sequence are selected from the first bit sequence according to a bit selection pattern applied to the first bit sequence, and the bit selection pattern is the same for each piece of information in the multiple pieces of information.

[0043] In a second aspect, the present disclosure relates to a method of transmitting information from a transmitter to a receiver, the method comprising operating the transmitter to perform the following steps:

[0044] Transmit a first signal to the receiver, wherein the first signal carries a first symbol sequence that represents a first bit sequence of length M1, the first bit sequence comprising N1 information bits and (M1 - N1) redundant bits, where 1 < N1 < M1;

[0045] Receive a request from the receiver; and

[0046] In response to the received request, transmit a second signal to the receiver, wherein the second signal carries a second symbol sequence that represents a second bit sequence of length N2, the second bit sequence comprising N2 of the N1 information bits of the first bit sequence but no redundant bits, where 1 ≤ N2 ≤ N1.

[0047] In a third aspect, the present disclosure relates to a method of receiving information from a transmitter at a receiver side, the method comprising operating the receiver to perform the following steps:

[0048] Receive a first signal from the transmitter, wherein the first signal carries a first symbol sequence that represents a first bit sequence of length M1, the first bit sequence comprising N1 information bits and (M1 - N1) redundant bits;

[0049] Generate a reconstructed first symbol sequence by demodulating the received first signal;

[0050] Generate a first LLR metric sequence of length M1 by generating one or more log-likelihood ratio (LLR) metrics for each symbol in the reconstructed first symbol sequence;

[0051] Generate a reconstructed first bit sequence of length M1 based on the first LLR metric sequence;

[0052] Determine that the reconstructed first bit sequence is invalid;

[0053] Send a request to the transmitter;

[0054] Receive a second signal from the transmitter, wherein the second signal carries a second symbol sequence that represents a second bit sequence of length N2, the second bit sequence comprising N2 of the N1 information bits of the first bit sequence but no redundant bits, where 1 ≤ N2 ≤ N1;

[0055] Generate a reconstructed second symbol sequence by demodulating the received second signal;

[0056] Generate a second LLR metric sequence of length N2 by generating one or more LLR metrics for each symbol in the reconstructed second symbol sequence;

[0057] Generate an integrated LLR metric sequence of length M1, where generating the integrated LLR metric sequence includes: combining the first LLR metric sequence and the second LLR metric sequence;

[0058] Generate a second reconstructed first bit sequence of length M1 based on the integrated LLR metric sequence.

[0059] In a fourth aspect, the present disclosure relates to a transmitter for:

[0060] Transmit a first signal to a receiver, where the first signal carries a first symbol sequence representing a first bit sequence of length M1, the first bit sequence including N1 information bits and (M1 - N1) redundant bits, where 1 ≤ N1 ≤ M1;

[0061] Receive a request from the receiver;

[0062] Transmit a second signal in response to the received request, where the second signal carries a second symbol sequence representing a second bit sequence of length N2, the second bit sequence including N2 of the N1 information bits of the first bit sequence but not including any redundant bits, where 1 ≤ N2 ≤ N1.

[0063] In a fifth aspect, the present disclosure relates to a receiver for:

[0064] Receive a first signal from a transmitter, where the first signal carries a first symbol sequence representing a first bit sequence of length M1, the first bit sequence including N1 information bits and (M1 - N1) redundant bits;

[0065] Generate a reconstructed first symbol sequence by demodulating the received first signal;

[0066] Generate a first LLR metric sequence by generating one or more log-likelihood ratio (LLR) metrics for each symbol in the reconstructed first symbol sequence;

[0067] Generate a reconstructed first bit sequence of length M1 based on the first LLR metric sequence;

[0068] If the reconstructed first bit sequence is invalid, send a request to the transmitter;

[0069] Receive a second signal from the transmitter, where the second signal carries a second symbol sequence, the second symbol sequence representing a second bit sequence of length N2, the second bit sequence including N2 of the N1 information bits of the first bit sequence but not including any redundant bits, where 1 ≤ N2 ≤ N1;

[0070] Generate a reconstructed second symbol sequence by demodulating the received second signal;

[0071] Generate a second LLR metric sequence of length N2 by generating one or more LLR metrics for each symbol in the reconstructed second symbol sequence;

[0072] Generate an integrated LLR metric sequence of length M1, where generating the integrated LLR metric sequence includes: combining the first LLR metric sequence and the second LLR metric sequence; and

[0073] Generate a second reconstructed first bit sequence of length M1 based on the integrated LLR metric sequence.

[0074] Unless otherwise defined, all technical and / or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of embodiments of this disclosure, exemplary methods and / or materials are described below. In case of conflict, the patent specification including the definitions shall prevail. In addition, these materials, methods, and examples are illustrative only and not necessarily restrictive. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Some embodiments of the present disclosure are described herein only by way of example in conjunction with the drawings. Now, specifically in conjunction with the drawings, it should be emphasized that the details shown are by way of example and for the purpose of providing an illustrative discussion of the embodiments of the present disclosure. Thus, it will be apparent to those skilled in the art how to practice the embodiments of the present disclosure based on the description of the drawings.

[0076] In the drawings,

[0077] Figure 1 Schematically shows a system provided by some embodiments of the present disclosure;

[0078] Figure 2 Schematically shows an example of a bit sequence stream of an FEC codeword transmitted by a transmitter provided by some embodiments of the present disclosure;

[0079] Figure 3Schematically illustrates a method for retransmitting only information bits provided by some embodiments of the present disclosure;

[0080] Figure 4 Schematically illustrates an example of retransmitting information bits in a second signal that are fewer than the information bits in a first signal when the bit sequence is an FEC codeword, provided by some embodiments of the present disclosure;

[0081] Figure 5 Schematically illustrates a comparison diagram of the packet error rate (PER) and the signal to noise ratio (SNR) of different HARQ schemes provided by some embodiments of the present disclosure. The different HARQ schemes include a scheme for retransmitting only information bits; and

[0082] Figure 6A and Figure 6B Schematically illustrates a comparison of the throughput of different HARQ schemes provided by some embodiments of the present disclosure. The different HARQ schemes include a scheme for retransmitting only information bits. Detailed implementation manners

[0083] In some embodiments, the present disclosure relates to a system and method for retransmitting erroneously received data. More specifically, but not limited thereto, the present disclosure relates to a system and method for retransmitting erroneously received data, wherein only the information bits in the erroneously received data are retransmitted. The erroneously received data may be simply referred to as "error data" herein.

[0084] In a communication system, a transmitter (Tx) is a device that sends signals, which transmits signals carrying data to a receiver (Rx), i.e., a device that receives signals. The signals include a sequence of modulated symbols. A symbol represents a bitstream including a pair of sequences or multiple such pairs of sequences, and a pair of sequences is an information bit sequence and a redundant bit sequence (redundant bits are also referred to as parity bits). When the signal is received at the receiver side, the signal is demodulated to reconstruct the symbol sequence. The reconstructed symbol sequence is demapped to LLR metrics (also referred to as soft bits, or simply LLRs), and then these metrics are decoded to detect the data transmitted by the transmitter. Once the signal is correctly decoded, the receiver can send an Acknowledgement (ACK) message to the transmitter according to some embodiments of the present disclosure, indicating that the data has been correctly received. Sometimes the data cannot be correctly decoded, and in this case, the receiver sends a Negative Acknowledgement (NACK) message to the transmitter, indicating that the data has been received in error. The NACK message is actually a request to retransmit the erroneously received data, hereinafter simply referred to as ReTX-request. In response to the ReTX-request, the transmitter retransmits the signal carrying the erroneously received data to the receiver. In the ARQ method, the receiver discards the erroneously received signal and the results obtained by processing the erroneously received signal, and once the transmitter retransmits the data again, a new detection process is performed. On the other hand, in the HARQ method, soft combining (or combining of equalized symbols) of the log-likelihood ratio (LLR) metrics of different retransmission / transmission signals that may carry the same data is performed by the receiver. This means that the LLR metrics corresponding to one or more previously erroneously received signals are stored in the receiver's memory and combined with the LLR metrics extracted from the retransmission signals carrying the same information, thereby increasing the likelihood of correctly receiving the data (after retransmission). However, the retransmission signal is usually constructed by one of two known methods: the first method is called Chase Combining (CC), in which the same signal as the original signal is retransmitted using the same modulated symbols or the same bitstream as a whole, and the modulated symbols or bitstream includes an information bit sequence and a redundant bit sequence, the same as in the first transmission signal; the second method is called Incremental Redundancy (IR), in which the redundant bit sequence retransmitted is different from the redundant bit sequence carried by the first transmission signal. There is a need to provide a method and system for retransmitting only information bits. According to some embodiments of the present disclosure, a system and method are provided for retransmitting only an information bit sequence or a subset of the information bit sequence without retransmitting any redundant bits, thereby improving the efficiency and throughput of the system and also simplifying the system design.

[0085] The computer-readable program instructions for performing the operations of the present disclosure may be assembly instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state-setting data, or source code or object code written in any combination of one or more programming languages. The programming languages include object-oriented programming languages (e.g., Smalltalk or C++) and conventional procedural programming languages (e.g., the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network connection, including a local area network (LAN) or a wide area network (WAN), and may also be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, electronic circuits, including programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), etc., may execute the computer-readable program instructions by using the state information of the computer-readable program instructions to personalize the electronic circuits to perform various aspects of the present disclosure.

[0086] Aspects of the present disclosure are described herein in connection with the flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0087] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing apparatus create a module for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium, which may direct a computer, a programmable data processing apparatus, and / or other devices to work in a particular manner, such that the computer-readable storage medium storing the instructions includes an article of manufacture containing instructions for implementing various aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0088] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices, causing a series of operational steps to be performed on the computer, other programmable apparatus, or other devices, thereby generating a computer-implemented process such that the instructions executed on the computer, other programmable apparatus, or other devices implement the functions / actions specified in the flowchart and / or block diagram.

[0089] The flowcharts and block diagrams in the figures illustrate the structure, functions, and operations of the possible implementations of the systems, methods, and computer program products provided by various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions that includes one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may not be performed in the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by a system based on dedicated hardware that performs the specified functions or actions, or by a combination of dedicated hardware and computer instructions.

[0090] Now refer to Figure 1 , Figure 1Schematically shows a system provided by some embodiments of the present disclosure. System 100 includes a transmitter 101 and a receiver 102. Transmitter 101 includes a memory 111 and a processor 112. Receiver 102 includes a memory 113 and a processor 114. Transmitter 101 may include processing circuitry for performing or causing the transmission-side operations described in this application. The processing circuitry may include hardware and software. The hardware may include analog circuitry or digital circuitry, or both analog and digital circuitry. The analog circuitry may include radio frequency (RF) signal generation and processing means, such as voltage-controlled oscillators, amplifiers, and mixers. The digital circuitry may include components such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or general-purpose processors. In some embodiments, the processing circuitry includes one or more processors and a non-transitory memory connected to the one or more processors. The non-transitory memory may carry executable program code. When executed by the one or more processors, the executable program code causes transmitter 101 to perform the operations or methods described herein. Receiver 102 may include processing circuitry for performing or causing the transmission-side operations described in this application. The processing circuitry may include hardware and software. The hardware may include analog circuitry or digital circuitry, or both analog and digital circuitry. The analog circuitry may include radio frequency (RF) signal generation and processing means, such as voltage-controlled oscillators, amplifiers, and mixers. The digital circuitry may include components such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or general-purpose processors. In one embodiment, the processing circuitry includes one or more processors and a non-volatile memory connected to the one or more processors. The non-transitory memory may carry executable program code. When executed by the one or more processors, the executable program code causes receiver 102 to perform the operations or methods described herein.

[0091] Transmitter 101 transmits a first signal carrying a first symbol sequence. The first symbol sequence represents a first bit sequence of length M1 through Quadrature Amplitude Modulation (QAM) or the like. The first bit sequence includes an information bit sequence of length N1 and a dependent redundant bit sequence of length R1 = M1 - N1, where 1 < N1 < M1; here, the N1 information bits represent a piece of information and are regarded as the entire independent data unit to be sent to the receiver, and the R1 redundant bits accompanying the N1 information bits are generated from the N1 information bits according to a predefined coding scheme, which is also known to receiver 102. Receiver 102 receives the first signal and demodulates the received first signal to attempt to reconstruct the first symbol sequence. Then, by generating one or more Log-Likelihood Ratio (LLR) metrics for each reconstructed symbol, processor 113 of the receiver generates a first LLR metric sequence of length M1 associated with the M1 bits in the first bit sequence. The LLR metrics are stored in memory 114 of the receiver. Then, on the receiver side, processor 113 generates a reconstructed first bit sequence of length M1 based on the first LLR metric sequence. If receiver 102 determines that the reconstructed first bit sequence is invalid, indicating that the reconstructed first bit sequence is received in error, then receiver 102 sends a ReTX-request message (NACK) to transmitter 101. Transmitter 101 receives the ReTX-request and, according to some embodiments of the present disclosure, transmits a second signal carrying a second symbol sequence as a response. The second symbol sequence represents a sequence of only N2 information bits in the sequence of N1 information bits, where 1 ≤ N2 ≤ N1, that is, any bits in the sequence excluding the R1 redundant bits are not included. This improves system efficiency.

[0092] According to some embodiments of the present disclosure, the transmitter 101 transmits a second signal such that the second signal carries all the information bits in the first bit sequence, and at this time, N2 = N1. According to some other embodiments of the present disclosure, the transmitter 101 transmits a second signal such that the second signal carries fewer information bits than all the information bits in the first bit sequence, that is, 1 ≤ N2 < N1. Therefore, the retransmitted information bit sequence includes N2 bits, where N2 is equal to or less than N1. The receiver 102 receives the second signal and generates a reconstructed second symbol sequence by demodulating the received second signal. By generating one or more LLR metrics for each symbol in the reconstructed second symbol sequence, the processor 114 of the receiver generates a second LLR metric sequence of length N2. Then, the receiver 102 generates an integrated sequence of M1 LLR metrics, which includes the combination of the first sequence of M1 LLR metrics and the second sequence of N2 LLR metrics. This means that the receiver combines the LLR metric sequence generated from the first signal and the LLR sequence generated from the second signal into an integrated LLR metric sequence. Finally, the receiver 102 generates a reconstructed bit sequence of length M1 based on the integrated sequence of M1 LLR metrics.

[0093] According to some embodiments of the present disclosure, the combining of the LLR metric sequences into an integrated LLR metric sequence is performed by adding the value of one of the N2 metrics in the second LLR metric sequence to each of the N2 metrics in the M1 metrics of the first LLR metric sequence.

[0094] According to some embodiments of the present disclosure, the receiver determines whether the reconstructed first bit sequence is valid in the following manner: encoding (or re - encoding) the N1 information bits in the reconstructed first bit sequence using the same encoding scheme as that used by the transmitter to generate the R1 redundant bits in the first bit sequence, and comparing the resulting R1 additional bits with the corresponding R1 bits in the reconstructed first bit sequence; an exact match of these two bit sequences of length R1 indicates that the reconstructed first bit sequence is valid and enables the receiver to determine that a piece of information including N1 information bits is correctly received, while any difference between the two sequences indicates that the reconstructed first bit sequence is invalid and thus the decoding of this piece of information is in error.

[0095] According to some embodiments, determining whether the reconstructed first bit sequence is valid can be efficiently accomplished by a method called syndrome check using a parity - check matrix: if the result of multiplying the reconstructed first bit sequence (regarded as a vector over a binary number field) by the parity - check matrix is 0, the receiver determines that the reconstructed first bit sequence is valid; if the result of the multiplication is not 0 (i.e., a "syndrome" is generated), the receiver considers the reconstructed first bit sequence to be invalid.

[0096] According to some embodiments of the present disclosure, a transmitter transmits a codeword of a forward error correction (FEC) code as a bit sequence. The FEC code can be, for example, a Low-Density Parity Check (LDPC) code. In some embodiments of the present disclosure, when the reconstructed first bit sequence is not a valid codeword of the FEC code, the receiver determines that the reconstructed first bit sequence is invalid. If the transmitter transmits a codeword of the FEC code and the receiver determines that the received codeword is invalid, the receiver sends a ReTX-request to the transmitter, and the transmitter only sends the information bits of the indicated invalid codeword as a response without sending redundant bits.

[0097] Figure 2 An example of a signal including a stream of FEC codewords transmitted by a transmitter is schematically shown. In stream 201, codewords #1 to #11 are transmitted from the transmitter to the receiver. Each codeword includes a sequence of information bits and a sequence of redundant (parity) bits. Codeword #3 includes a sequence of information bits 210 (where N1 = 911) and an accompanying sequence of parity bits 211 (where, R1 = M1 - N1 = 911), such that the FEC code rate is N1 / M1 = 1 / 2 in this example. Similarly, codeword #5 includes a sequence of information bits 212 (where N1 = 911) and an accompanying sequence of parity bits 213 (where, R1 = M1 - N1 = 911). In this example, codewords #3 and #5 are received in error, which means that the receiver determines that codewords #3 and #5 are invalid when receiving the transmission from the transmitter. The receiver sends a NACK message to the transmitter, which includes a request to retransmit the erroneously received codewords #3 and #5. The transmitter retransmits bit stream 202 as a response according to some embodiments of the present disclosure. Bit stream 202 includes a sequence of information bits 210 of codeword #3 (where N2 = 911) and a sequence of information bits 212 of codeword #5 (where N2 = 911), but does not include the sequences of redundant bits 211 and 213.

[0098] Now refer to Figure 3 , Figure 3A flowchart is schematically shown that presents a method for retransmitting only the information bits of erroneously received data provided by some embodiments of the present disclosure. In 301, a transmitter sends a first signal carrying a first symbol sequence. The first symbol sequence represents a first bit sequence of length M1. The first bit sequence includes N1 information bits and (M1 - N1) redundant bits, where 1 < N1 < M1. The N1 information bits represent a piece of information. In 302, the receiver receives the first signal and generates a reconstructed first symbol sequence by demodulating the received first signal. In 303, by generating one or more log-likelihood ratio (LLR) metrics for each symbol in the reconstructed first symbol sequence, a processor of the receiver generates a first log-likelihood ratio (LLR) metric sequence of length M1. In 304, the processor of the receiver generates a reconstructed first bit sequence of length M1 based on the first LLR metric sequence. In 305, the receiver determines that the reconstructed first bit sequence is invalid (i.e., the reconstructed first bit sequence is erroneously received or decoded). Then, in 306, the receiver sends a ReTX request to the transmitter. In 307, the transmitter receives the ReTX request. In 308, the transmitter sends a second signal as a response to the receiver. The second signal carries a second symbol sequence, and the second symbol sequence represents a second bit sequence that includes N2 information bits out of the N1 information bits of the first bit sequence but does not include any redundant bits, where 1 ≤ N2 ≤ N1. In 309, the receiver receives the second signal and generates a reconstructed second symbol sequence by demodulating the received second signal. In 310, by generating one or more LLR metrics for each symbol, the processor of the receiver generates a second LLR metric sequence of length N2 based on the reconstructed second symbol sequence. In 311, by combining the first LLR metric sequence and the second LLR metric sequence, the processor of the receiver generates an integrated LLR metric sequence of length M1. Finally, in 312, the processor of the receiver generates a second reconstructed first bit sequence of length M1 based on the integrated LLR metric sequence. Extracting the N1 information bits from the second reconstructed first bit sequence to represent a candidate piece of information that the transmitter attempts to send to the receiver increases the likelihood of correctly receiving this piece of information. In addition, when considering the overhead generated during the retransmission process, compared with the retransmission schemes in the prior art, since the second signal carries fewer bits, the transmission efficiency and throughput are improved. Since the first LLR metric sequence (corresponding to the first bit sequence) can be combined with the (shorter) second LLR metric sequence (corresponding to the second bit sequence) for use, making the likelihood of correctly decoding the first bit sequence higher, it is beneficial to retransmit only the information bits.

[0099] According to some embodiments of the present disclosure, the transmitter indicates to the receiver that a bit sequence including only information bits that was received in error is being retransmitted. For example, in a Wi-Fi communication system based on an IEEE 802.11 standard variant, the signaling may include bits in the SIG-A or SIG-B field of the physical layer (PHY) preamble of the transmission frame.

[0100] According to some embodiments of the present disclosure, the transmitter transmits N2 information bits in a second signal, including all N1 information bits in a first signal, such that the relationship N2 = N1 holds. According to some other embodiments of the present disclosure, the transmitter transmits N2 information bits in the second signal, which is less than all N1 information bits in the first signal, where 1 < N2 < N1. An example of transmitting fewer information bits in the second signal may be that the transmitter deploys an Orthogonal Frequency Division Multiplexing (OFDM)-based modulation scheme to generate the second signal. In this case, according to some embodiments of the present disclosure, the number of information bits transmitted in the second signal is set such that after modulation, the data fully occupies an integer number of OFDM symbols. Therefore, the number of information bits retransmitted in the second signal can be less than the number of information bits transmitted in the first signal in order to reduce the duration of the second signal, thereby improving the efficiency of the retransmission scheme.

[0101] According to some embodiments of the present disclosure, generating an integrated LLR metric sequence is accomplished by adding the value of one of the N2 metrics in a second LLR metric sequence to each of the N2 metrics in the M1 metrics of the first LLR metric sequence.

[0102] According to some other embodiments of the present disclosure, when the transmission of the second signal is not sufficient for the receiver to correctly reconstruct the first bit sequence, the receiver sends an additional ReTX-request to the transmitter to retransmit the data carried by the first signal. The transmitter sends a third signal in response, and the third signal carries a third symbol sequence, and the third symbol sequence represents a third bit sequence of length M3, and the third bit sequence includes M3 bits in the first bit sequence, where 1≤M3≤M1. In this case, the M3 bits can be information bits and / or redundant bits. The receiver receives the third signal and generates a reconstructed third symbol sequence by demodulating the received third signal. Then, the processor of the receiver generates a third LLR metric sequence of length M3 by generating one or more LLR metrics for each symbol in the reconstructed third symbol sequence. Then, the processor of the receiver generates a second integrated LLR metric sequence of length M1 by combining the first LLR metric sequence, the second LLR metric sequence, and the third LLR metric sequence, or by combining the first integrated LLR metric sequence and the third LLR metric sequence. Finally, the processor of the receiver generates a third reconstructed first bit sequence of length M1 according to the second integrated LLR metric sequence. According to some embodiments of the present disclosure, in this case, one or more bits in the first bit sequence are included in only one of the second bit sequence and the third bit sequence.

[0103] According to some embodiments of the present disclosure, the third bit sequence includes N3 information bits out of N1 information bits of the first bit sequence but does not include any redundant bits, where 1≤N3≤N1.

[0104] According to some embodiments of the present disclosure, if the receiver determines that the third reconstructed first bit sequence is invalid, the above process of reconstructing the third integrated first bit sequence is repeated again. This process is continuously repeated to construct a fourth integrated first bit sequence, and so on for n times (where n is a predefined number), or until the receiver determines that the reconstructed first bit sequence is valid.

[0105] According to some embodiments of the present disclosure, when the transmitter sends the second bit sequence to the receiver, the selection of N2 bits from the N1 information bits of the first bit sequence does not depend on a piece of information. Additionally, the selection of bits from the first bit sequence does not depend on which bits in the first bit sequence were not correctly received when the first bit sequence was sent. This means that for each piece of information, i.e., for each instance of sending the second bit sequence, the second bit sequence is constructed in the same way. The selection of bits from the first bit sequence is done according to a bit selection pattern that is also known to the receiver (predefined or indicated by the transmitter to the receiver), and the same pattern is applied to each piece of information sent from the transmitter to the receiver. This enables a simple implementation of the method disclosed herein. According to some embodiments of the present disclosure, the bit selection pattern for selecting the bits to be retransmitted depends on one or both of the first bit sequence and the lengths M1 and N1 of the information bits therein, but does not depend on the values of the bits included in the first bit sequence. According to some other embodiments of the present disclosure, the bit selection pattern depends on the retransmission attempt index. For example, a third bit sequence can be constructed from the first bit sequence using a pattern different from the pattern used to construct the second bit sequence from the first bit sequence.

[0106] According to some embodiments of the present disclosure, the receiver determines that the reconstructed second bit sequence is invalid by determining that the syndrome of the reconstructed second bit sequence is a faulty syndrome.

[0107] According to some embodiments of the present disclosure, when the first bit sequence is a codeword of a forward error correction (FEC) code, determining that the reconstructed second bit sequence is invalid consists of determining that the reconstructed second bit sequence is not a valid codeword of the FEC code.

[0108] Figure 4Schematically shows an example of retransmitting fewer information bits in a second signal than the information bits in a first signal when the bit sequence is an FEC codeword. A signal 410 including 11 codewords is transmitted from a transmitter to a receiver. Each codeword includes information bits and redundant (parity) bits. Codeword #3 includes information bits 403 and redundant bits 404, where the number of information bits is N1 = 911 and the number of redundant bits is R1 = M1 - N1 = 911. Similarly, codeword #5 includes information bits 405 and redundant bits 406, where the number of information bits is N1 = 911 and the number of redundant bits R1 = M1 - N1 = 911. In this example, codewords #3 and #5 are erroneously received by the receiver. The receiver sends a ReTX-request for codewords #3 and #5, and the transmitter sends information bits 410 (where N2 is equal to 800 of the 911 information bits 403 of codeword #3) and information bits 412 (N2 is equal to 800 of the 911 information bits 405 of codeword #5) as a response, but does not send any redundant bits 404 and 406. The information bits 413 of codeword #3 (where N2 = 800) and the information bits 415 of codeword #5 (where N2 = 800) together form the retransmission bit stream 402.

[0109] According to some embodiments of the present disclosure, when the second bit sequence is shorter than the first bit sequence (i.e., N2 < N1), that is, not all N1 information bits are included in the second bit sequence, the transmitter uses a data set mapping. The data set mapping is used to identify which of the N1 information bits are transmitted as the retransmitted N2 information bits in the second bit sequence.

[0110] According to some embodiments of the present disclosure, the receiver uses a data set mapping that matches the data set mapping used by the transmitter. When generating an integrated LLR metric sequence, the data set mapping used by the receiver identifies which N2 LLR metrics in the second LLR metric sequence are to be combined with which N2 LLR metrics in the M1 LLR metrics of the first LLR metric sequence. The data set mapping used by the receiver matches the data set mapping used by the transmitter through a predefined handshake process or signaling from the transmitter to the receiver.

[0111] According to some embodiments of the present disclosure, a transmitter deploys a multi-carrier modulation scheme, such as OFDM, to generate a first signal, and symbols transmitted in the first signal are interleaved according to predefined rules before being mapped to sub-carriers. According to some embodiments of the present disclosure, the transmitter interleaves symbols of a second signal according to possibly different predefined rules before the symbols are mapped to carriers that are the same as or different from the carriers to which the symbols are mapped when generating the first signal. A receiver that receives the first signal and the second signal can use the interleaving and sub-carrier mapping rules, and a processor of the receiver uses these rules when receiving and decoding the first signal and the second signal.

[0112] According to some embodiments of the present disclosure, when the transmitter transmits N2 information bits in the second signal and N2 < N1 (i.e., the number of information bits in the second signal is less than the number of information bits in the first signal), the number of information bits N2 transmitted is negotiated between the transmitter and the receiver through a predefined handshake process or signaling from the transmitter to the receiver.

[0113] Now refer to Figure 5 , Figure 5 , which shows a comparison schematic diagram of the packet error rate (PER) versus the signal-to-noise ratio (SNR). These are evaluation results obtained from simulations of a standard IEEE 802.11ax communication link, but several modulation and coding schemes (MCS) use different retransmission schemes respectively. The scenario considered is a 2×2 multi-input multi-output (MIMO) antenna configuration, using a TGn-D non-line-of-sight (NLOS) channel model under a 20 MHz channel bandwidth, and the receiver uses perfect channel estimation and a minimum mean square error (MMSE) demodulator. The retransmission schemes considered are:

[0114] · No HARQ;

[0115] · HARQ and Chase combining (retransmit the entire codeword when a failure occurs); and

[0116] · HARQ and retransmit only the information bits, where, according to some embodiments of the present disclosure, only the information bits are retransmitted when the receiver decoding fails.

[0117] It can be seen that the retransmission scheme of information bits only provides better results than the "no HARQ" scheme (lower PER corresponding to a given SNR). The Chase combining scheme of retransmitting the entire codeword shows the best PER performance among the three comparison schemes, but has a large overhead, and its impact is considered in the throughput discussion in the following Figure 6A and Figure 6B .

[0118] Figure 6A and Figure 6B shows the simulation results of link throughput comparison in the same scenario considered in Figure 5 , considering all overheads (preamble, Short Interframe Space (SIFS), ACK message duration, etc.), where two MCS selection schemes are deployed. In Figure 6A , the optimal MCS selection is deployed, i.e., the MCS that generates the highest throughput for any given SNR is selected. Figure 6B shows the results when a sub-optimal (simulating the actual) MCS selection is deployed. For no HARQ, the MCS that generates the highest throughput for any given SNR is selected only when the PER of the first transmission is less than 10%; for the two HARQ schemes, the MCS that generates the highest throughput is selected only when the PER of the first transmission is less than 20%.

[0119] In both cases, in the optimal and sub-optimal MCS selection strategies, according to some embodiments of the present disclosure, retransmitting the codeword including only information bits results in extreme performance, and it can be seen that retransmitting the codeword including only information bits is the best retransmission scheme in all cases.

[0120] The description of various embodiments of the present disclosure is for illustrative purposes only and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are chosen to best explain the principles, practical applications, or technological advancements of the embodiments, or to enable other ordinary skilled in the art to understand the embodiments disclosed herein compared to the technologies available in the market.

[0121] It is expected that during the effective period of the patent maturing from this application, many related models for retransmitting only information bits will be developed, and the scope of the term "model for retransmitting only information bits" is intended to include all such new technologies a priori.

[0122] The term "about" as used herein means ±10%.

[0123] The terms "comprising", "having", and their variations mean "including but not limited to". This term includes the terms "consisting of" and "consisting essentially of".

[0124] The phrase "consisting essentially of" means that the composition or method may include additional components and / or steps, provided that the additional components and / or steps do not substantially change the basic and novel characteristics of the claimed composition or method.

[0125] Unless the context clearly indicates otherwise, as used herein, the singular forms "a", "an", and "the" include plural referents. For example, the term "a complex" or "at least one complex" can include a plurality of complexes, including mixtures thereof.

[0126] As used herein, the term "exemplary" means "serving as an example, instance, or illustration". Any embodiment described as "exemplary" is not necessarily to be construed as preferred or more advantageous than other embodiments, and / or excludes combinations of features of other embodiments.

[0127] As used herein, the term "optionally" means "provided in some embodiments and not provided in other embodiments". Any particular embodiment of the present disclosure may include a plurality of "optional" features, unless these features are mutually contradictory.

[0128] In this application, various embodiments of the present disclosure may be presented in a range format. It should be understood that the description in range format is only for convenience and brevity and should not be construed as a fixed limitation on the scope of the present disclosure. Thus, a description of a range should be considered to have specifically disclosed all possible sub-ranges as well as individual numerical values within that range. For example, a description of a range such as from 1 to 6 should be considered to have specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as individual numbers within that range, e.g., 1, 2, 3, 4, 5, and 6. This applies regardless of how broad the range is.

[0129] When a numerical range is indicated herein, it includes any recited number (fractional or integral) within the indicated range. The phrases "a range between a first indicated number and a second indicated number" and "a range from a first indicated number to a second indicated number" are used interchangeably herein and mean to include the first and second indicated numbers and all fractional and integral numbers therebetween.

[0130] It should be understood that, for the sake of brevity of description, certain features of the present disclosure that are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, for the sake of brevity of description, the various features of the present disclosure that are described in the context of a single embodiment may also be provided separately or in any suitable sub-combination or as any suitable other embodiment of the present disclosure. Certain features described in the context of various embodiments should not be considered essential features of those embodiments unless the embodiment is inoperable without those elements.

[0131] Although the present disclosure has been described in connection with specific embodiments thereof, it will be apparent to those skilled in the art that many alternatives, modifications, and variations will be obvious. Accordingly, the present disclosure is intended to cover all such alternatives, modifications, and variations that fall within the spirit and broad scope of the appended claims.

[0132] Herein, all publications, patents, and patent applications mentioned in this specification are incorporated herein by reference, and, similarly, each individual publication, patent, or patent application is specifically and individually incorporated herein. In addition, the citation or identification of any reference to this application should not be taken as allowing such reference to be prior art to the present disclosure. With respect to the use of section headings, the section headings should not be construed as necessarily limiting. Additionally, the entire contents of any one or more priority documents of this application are incorporated herein by reference.

Claims

1. A method for sending multiple pieces of information from a transmitter (101) to a receiver (102), characterized in that, The method includes: The transmitter (101) transmits a first signal, where the first signal carries a first symbol sequence, and the first symbol sequence represents a first bit sequence of length , the first bit sequence includes information bits and redundant bits, where , the information bits represent a piece of information; The receiver (102) receives the first signal; The receiver (102) generates a reconstructed first symbol sequence by demodulating the received first signal; The receiver (102) generates a first sequence of LLR metrics of length by generating one or more log-likelihood ratio (LLR) metrics for each symbol in the reconstructed first symbol sequence; The receiver (102) generates a reconstructed first bit sequence of length based on the first LLR metric sequence; The receiver (102) determines that the reconstructed first bit sequence is invalid; The receiver (102) sends a request; The transmitter (101) receives the request; The transmitter (101) transmits a second signal in response to a received request, wherein the second signal carries a second symbol sequence, and the second symbol sequence represents a second bit sequence of length , and the second bit sequence includes information bits among the information bits of the first bit sequence but does not include any redundant bits, wherein ; The receiver (102) receives the second signal; The receiver (102) generates a reconstructed second symbol sequence by demodulating the received second signal; By generating one or more LLR metrics for each symbol in the reconstructed second symbol sequence, the receiver (102) generates a second LLR metric sequence of length ; The receiver (102) generates an integrated LLR metric sequence having a length of , wherein generating the integrated LLR metric sequence includes: combining the first LLR metric sequence and the second LLR metric sequence; and The receiver (102) generates a first bit sequence of a second reconstruction having a length based on the integrated LLR metric sequence ; Wherein, the second bit sequence includes fewer information bits than all the information bits in the first bit sequence; and, the bits in the second bit sequence are selected from the first bit sequence according to a bit selection pattern applied to the first bit sequence, and the bit selection pattern is the same for each of the plurality of pieces of information.

2. The method according to claim 1, characterized in that, Determining that the reconstructed first bit sequence is invalid includes or consists of: determining that the syndrome of the reconstructed first bit sequence is a fault syndrome.

3. The method according to claim 1, wherein The first bit sequence is a codeword of a forward error correction FEC code.

4. The method according to claim 3, wherein Determining that the reconstructed first bit sequence is invalid includes or consists of: determining that the reconstructed first bit sequence is not a valid codeword of the FEC code.

5. The method according to any one of claims 1 to 4, characterized in that Generating the integrated LLR metric sequence includes: adding the value of one of the metrics in the second LLR metric sequence to each of the metrics in the first LLR metric sequence respectively. ​ 6. The method according to any one of claims 1 to 4, characterized in that The integrated LLR metric sequence is a first integrated LLR metric sequence, and the method further includes: The receiver (102) determines that the second reconstructed first bit sequence is invalid; The receiver (102) sends a second request; The transmitter (101) receives the second request; The transmitter (101) transmits a third signal in response to the received second request, wherein the third signal carries a third symbol sequence, and the third symbol sequence represents a third bit sequence of length The third bit sequence includes bits in the first bit sequence, where ; The receiver (102) receives the third signal; The receiver (102) generates a reconstructed third symbol sequence by demodulating the received third signal; By generating one or more LLR metrics for each symbol in the reconstructed third symbol sequence, the receiver (102) generates a third LLR metric sequence of length ; The receiver (102) generates a second integrated LLR metric sequence having a length of , wherein generating the second integrated LLR metric sequence includes: combining the first LLR metric sequence, the second LLR metric sequence, and the third LLR metric sequence, or combining the first integrated LLR metric sequence and the third LLR metric sequence; The receiver (102) generates a third reconstructed first bit sequence of length based on the second integrated LLR metric sequence.

7. The method according to claim 6, wherein One or more bits in the first bit sequence are included in only one of the second bit sequence and the third bit sequence.

8. The method according to claim 6, characterized in that, The third bit sequence includes the information bits of the first bit sequence, but does not include any redundant bits, where .

9. A method for receiving multiple messages from a transmitter (101) on the receiver (102) side, characterized in that, The method includes operating the receiver (102) to perform the following steps: Receiving a first signal from the transmitter (101), wherein the first signal carries a first symbol sequence, and the first symbol sequence represents a first bit sequence of length , the first bit sequence includes information bits and redundant bits; Generate a reconstructed first symbol sequence by demodulating the received first signal; Generating a first LLR metric sequence of length by generating one or more log-likelihood ratio (LLR) metrics for each symbol in the reconstructed first symbol sequence; Generate a reconstructed first bit sequence of length based on the first LLR metric sequence; Determine that the reconstructed first bit sequence is invalid; Send a request to the transmitter (101); Receiving a second signal from the transmitter (101), wherein the second signal carries a second symbol sequence, the second symbol sequence representing a second bit sequence of length , the second bit sequence including information bits of the first bit sequence information bits but not including any redundant bits, wherein ; Generate a reconstructed second symbol sequence by demodulating the received second signal; Generating a second LLR metric sequence of length by generating one or more LLR metrics for each symbol in the reconstructed second symbol sequence; Generate an integrated LLR metric sequence with a length of , wherein generating the integrated LLR metric sequence includes: combining the first LLR metric sequence and the second LLR metric sequence; and Generate a first bit sequence of a second reconstruction with a length of ; Wherein, the second bit sequence includes fewer information bits than all the information bits in the first bit sequence; and, the bits in the second bit sequence are selected from the first bit sequence according to a bit selection pattern applied to the first bit sequence, and the bit selection pattern is the same for each of the plurality of pieces of information. bits are selected from the first bit sequence according to a bit selection pattern applied to the first bit sequence, and the bit selection pattern is the same for each of the plurality of pieces of information.

10. A transmitter (101) for sending multiple messages, characterized in that, The transmitter (101) is configured to: Send a first signal to a receiver (102), wherein the first signal carries a first symbol sequence, and the first symbol sequence represents a first bit sequence of length , the first bit sequence includes information bits and redundant bits, wherein ; Receive a request from the receiver (102); Sending a second signal in response to the received request, wherein the second signal carries a second symbol sequence, and the second symbol sequence represents a second bit sequence of length , the second bit sequence includes information bits of the first bit sequence and does not include any redundant bits, wherein ; ; Wherein, the second bit sequence includes fewer information bits than all the information bits in the first bit sequence; and, the bits in the second bit sequence are selected from the first bit sequence according to a bit selection pattern applied to the first bit sequence, and the bit selection pattern is the same for each of the plurality of pieces of information.

11. A receiver (102) for receiving multiple messages, characterized in that, The receiver (102) is configured to: Receiving a first signal from a transmitter (101), wherein the first signal carries a first symbol sequence, the first symbol sequence representing a first bit sequence of length , the first bit sequence including information bits and redundant bits; Generate a reconstructed first symbol sequence by demodulating the received first signal; Generate a first LLR metric sequence by generating one or more log-likelihood ratio LLR metrics for each symbol in the reconstructed first symbol sequence; Generate a reconstructed first bit sequence of length based on the first LLR metric sequence; If the reconstructed first bit sequence is invalid, send a request to the transmitter (101); Receiving a second signal from the transmitter (101), wherein the second signal carries a second symbol sequence representing a second bit sequence of length , the second bit sequence including information bits of the first bit sequence but not including any redundant bits, where ; ; Generate a reconstructed second symbol sequence by demodulating the received second signal; Generating a second LLR metric sequence of length by generating one or more LLR metrics for each symbol in the reconstructed second symbol sequence; Generate an integrated LLR metric sequence of length , wherein generating the integrated LLR metric sequence includes: combining the first LLR metric sequence and the second LLR metric sequence; and Generate a first bit sequence of a second reconstruction with a length of ; Wherein, the second bit sequence includes fewer information bits than all the information bits in the first bit sequence; and, the bits in the second bit sequence are selected from the first bit sequence according to a bit selection pattern applied to the first bit sequence, and the bit selection pattern is the same for each of the plurality of pieces of information.

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